Ethernet transmission of image data for autonomous and semi-autonomous systems and applications

Abstract

The invention discloses Ethernet transfer of image data for autonomous and semi-autonomous systems and applications. Embodiments of the present disclosure relate to systems and methods for transferring image data via Ethernet. The system may include a memory for storing frame data that may be received via Ethernet packets. In particular, an Ethernet packet may include a payload, which may include one or more segments and a header. The header may include a sequence number field that indicates a respective sequence number corresponding to a respective segment and a byte offset field that may indicate a respective byte offset that may be applied to the segment. Further, the system may include hardware, which may be configured to perform packet analysis operations including determining whether a previously transmitted segment is lost. The system may also include a processing system to perform data processing operations including storing the segments at respective memory locations based on respective byte offsets included in the Ethernet packet.

Description

Background Art

[0001] Many systems, such as many modern vehicles, include one or more components that send and receive large amounts of data. For example, autonomous and semi-autonomous vehicles or machines include many electronically connected components that communicate data, such as sensor data, deep learning models, image data, control commands, map data, and other data that can be transmitted between components, systems, subsystems, etc. of the machine. The data can be transmitted to manipulate the data, perform calculations, perform one or more other operations corresponding to the data and / or the vehicle, and / or perform one or more control operations, such as braking, acceleration, steering, notification of an object, etc.

[0002] In many cases, the electrically connected components may include one or more electronic control units (ECUs). One or more ECUs include one or more controllers, microcontrollers, devices, systems, embedded systems, modules, etc., which can control one or more specific functions corresponding to the vehicle. In many cases, one or more ECUs are interconnected to collaborate and perform various tasks, such as managing engine control, transmission control, braking systems, and other subsystems. In many cases, the faster data is transmitted between one or more ECUs, the better, assuming that the data can be used to evaluate the environment corresponding to vehicle operation in real time or near real time to allow decisions to be made based on the environment.

[0003] Additionally or alternatively, vehicles typically include one or more image sensors (e.g., cameras) for obtaining information about the environment in which the vehicle may be located. Image data obtained using the cameras can be sent to a processing system for analysis and processing. The processing of the image data can be used for any number of operations, such as perception, planning, actuation (e.g., braking, acceleration, steering), notification of objects, etc. Furthermore, as with ECU-to-ECU communication, the image data can be transmitted and processed to analyze the vehicle's environment as quickly as possible.

[0004] In many cases, the amount of data transferred between systems increases with increasing system complexity, the number of sensors corresponding to the systems, map data detail and complexity, etc. Accordingly, the amount of bandwidth used to transfer data has increased and continues to increase.

[0005] In response to the increase in bandwidth for data communication, many systems have resorted to utilizing Ethernet protocols for communication. Ethernet is often used because it has the ability to handle higher bandwidths than other protocols. Traditional protocols used in automotive / robotic environments to communicate data to corresponding processing systems include the Gigabit Multimedia Serial Link (GMSL) communication interface, which can be used to communicate large amounts of data between components, devices, systems, and the like. However, this approach can require the use of extensive proprietary wiring and multiple serializers and deserializers.

[0006] Additionally or alternatively, other conventional methods of Ethernet data transmission require extensive data processing using one or more processing units, such as one or more central processing units (CPUs). In some cases, the number of processing units required may depend on the amount of data being transmitted and / or communicated. As the amount of data that can be transmitted over Ethernet increases, the number of processing units required to process the data being transmitted may also increase. Furthermore, using processing units for data transmission occupies processing units that could be used for different tasks. Summary of the Invention

[0007] According to one or more embodiments of the present disclosure, the system may be configured to perform one or more operations corresponding to data transmitted via Ethernet. In some embodiments, the system may include a memory that may be configured to store data, wherein the data may be received via an Ethernet packet. In some embodiments, the data may be divided into data segments that may be sorted according to sequence order, wherein one or more Ethernet packets may include a payload and a header, respectively. In some embodiments, the payload may include a corresponding data segment. In some embodiments, the header may include a sequence number field that may indicate a corresponding sequence number that may correspond to a corresponding data segment within a sequence. In addition, in some embodiments, the header may include a byte offset field that may indicate a corresponding byte offset that may be applied to the data segment.

[0008] Additionally, in some embodiments, the system may include hardware configured to perform one or more packet analysis operations. The packet analysis operations may include determining whether a previously transmitted data segment is lost based on a first sequence number that may correspond to the first data segment and a second sequence number that may correspond to a second data segment that was received before the first data segment.

[0009] In some embodiments, the system may further include a processing system for performing one or more data processing operations on the Ethernet packet. The data processing operations may include causing each data segment to be stored at a corresponding memory location included in the memory based on a corresponding byte offset that may have been included in the Ethernet packet. In some embodiments, the corresponding memory location may be derived using data and / or information included in one or more header fields.

[0010] Embodiments of the present disclosure may help reduce the amount of processing resources that may be used compared to other mechanisms for transmitting sensor data. Additionally or alternatively, one or more embodiments described in the present disclosure may help facilitate and / or expedite one or more processing operations corresponding to the transmitted sensor data compared to other conventional methods of transmitting sensor data. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present disclosure describes in detail the present system and method for Ethernet data transmission with reference to the accompanying drawings, wherein:

[0012] Figure 1A is a diagram illustrating an example environment related to sending and receiving data according to one or more embodiments of the present disclosure;

[0013] Figure 1B It represents the one or more embodiments of the present disclosure corresponding to Figure 1A An example diagram of a modified header of a packet with conventional header modifications;

[0014] Figure 1C An example diagram showing grouping information according to one or more embodiments of the present disclosure is shown;

[0015] Figure 2A is a diagram illustrating an example environment related to transmitting and receiving image data according to one or more embodiments of the present disclosure;

[0016] Figure 2B It represents one or more embodiments of the present disclosure. Figure 2A An example diagram of a modified header corresponding to image data and / or packets;

[0017] Figure 3 is a flowchart illustrating a method for processing data transmitted via Ethernet according to one or more embodiments of the present disclosure;

[0018] Figure 4A is an illustration of an example autonomous vehicle according to some embodiments of the present disclosure;

[0019] Figure 4B According to some embodiments of the present disclosure Figure 4AExamples of camera positions and fields of view for autonomous vehicles;

[0020] Figure 4C According to some embodiments of the present disclosure Figure 4A a block diagram of an example system architecture for an example autonomous vehicle;

[0021] Figure 4D is a cloud-based server and Figure 4A System diagram of an example of communication between autonomous vehicles;

[0022] Figure 5 is a block diagram of an example computing device suitable for implementing some embodiments of the present disclosure; and

[0023] Figure 6 is a block diagram of an example data center suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] One or more embodiments of the present disclosure may relate to transmitting data via one or more communication protocols. For example, the communication protocol may include one or more Ethernet protocols, which can communicate a large amount of data between one or more components corresponding to the system in a shorter period of time compared to various other protocols. In particular, the communication protocol may include adding and / or modifying header fields and corresponding data, which can allow reducing the processing traditionally performed using one or more processing units (e.g., one or more CPUs). In the present disclosure, the new header fields and / or corresponding new header data filled in these fields can generally be referred to as "new headers" or "modified headers." Although this document is primarily described with respect to Ethernet, this is not intended to be limiting, and other communication protocols can use the systems and methods described herein without departing from the scope of the present disclosure.

[0025] For example, in some embodiments, a set of data (also referred to as a "data frame") may be divided into multiple data segments (also commonly referred to as "segments"), which are each transmitted via a respective Ethernet packet (also commonly referred to as a "packet"). In some embodiments, a segment may be included in a corresponding payload corresponding to a corresponding packet. In some examples of the present disclosure, a reference to a specific payload may be synonymous with a reference to a specific segment. Additionally or alternatively, a reference to a specific payload may include a specific segment and other data; for example, one or more reserved bits.

[0026] In some embodiments, the segments may be ordered sequentially according to a sequence. For example, the sensor data may be organized in a particular way before being divided into segments, and the ordering of the sequence may reflect this organization.

[0027] In some embodiments, by contrast, the sensor data may not be organized in a particular manner before being divided into particular segments. Instead, the segments may include a set amount of data therein, such that the sensor data may be divided into segments based on the set amount of data. For example, a data frame may include ten (10) kilobytes of data, and the segments corresponding to the data frame may each include one (1) kilobyte of such data. Continuing with this example, the first kilobyte of data in the data frame may correspond to the first segment, the second kilobyte of data in the data frame may correspond to the second data frame, and so on.

[0028] In some embodiments, the new header may include a sequence number field. The sequence number field may indicate a corresponding sequence number within a sequence that corresponds to a corresponding segment included in a payload of the corresponding packet. In some embodiments, without limitation, the sequence numbers may be integers, starting at zero "0" and moving upward incrementally in increments of 1. Continuing with the above example, where the data frame includes ten (10) kilobytes, the first sequence number field corresponding to the first segment may include a first sequence number of zero (0), the second sequence number field corresponding to the second segment may include a second sequence number of one (1), and so on.

[0029] Additionally or alternatively, the new header may include a byte offset field. The byte offset field may indicate a corresponding byte offset to be applied to a corresponding segment included in the payload of the corresponding packet. The byte offset may indicate how many bytes away from a base memory location that may be allocated to the corresponding data frame the corresponding segment will be stored. The base memory location may include a starting memory address ("base address") for storing the data frame. In some embodiments, the base address may include a pointer that may indicate a specific location in memory for storing the data frame. Thus, in some embodiments, the byte offset may indicate an offset from the base address where the corresponding segment corresponding to a particular data frame will be stored.

[0030] In some embodiments, the receiving system can use the new header to direct the storage of segments to their corresponding memory addresses. For example, the receiving hardware of the receiving system can be configured to read the byte offset included in the byte offset field of the corresponding packet. Based on the byte offset and the base memory address, the receiving hardware can be configured to direct the storage of the segments of the corresponding packet to the corresponding memory location.

[0031] Additionally or alternatively, in some embodiments, the new header may be used to determine whether all segments associated with a particular data frame have been received. In some embodiments, a sequence number included in a sequence number field of the new header may be used to make such a determination.

[0032] In some embodiments, the receiving hardware can be configured to report to the processing system that the received sequence number does not follow the sequence, which can indicate that a particular packet carrying a particular segment was lost somewhere during transmission. In these or other embodiments, the processing system can be configured to request retransmission of the data frame in response to one or more segments being lost. Additionally or alternatively, the processing system can request retransmission of the lost segments.

[0033] In some embodiments, the receiving hardware can be configured to detect that one or more segments corresponding to data received in real time or near real time (e.g., image data, sensor data, and other real-time data) may not have been sent in a particular transmission. In some embodiments, in response to detecting and / or determining that one or more segments may be missing from a particular transmission of real-time (or near real-time) data, the one or more processing systems can delete, remove, or otherwise not store data corresponding to data frames associated with the missing one or more segments.

[0034] In some embodiments, segments received after a lost segment can be stored in their designated memory locations even when a particular packet including the corresponding segment may be lost. In these or other embodiments, the receiving hardware can be configured to write segments received after the lost segment to their correct memory locations due to the byte offset included in the byte offset field. The byte offset can enable the receiving hardware to determine the memory location of each segment individually, rather than basing the memory location corresponding to a particular segment on the memory location of a previously received segment.

[0035] In contrast, implementations of conventional data transmission protocols may copy segments to sequential memory locations even in situations where segments may be lost, thereby storing specific data in a memory location that is different from the memory location that may have been designated for that specific data. Furthermore, in such situations, conventional data transmission protocols may require additional processing to reshuffle the data so that it is stored in the originally designated location. In contrast, embodiments of the present disclosure may include one or more modifications to existing communication protocols that may help reduce the amount of processing and / or memory resources used for data transmission.

[0036] In many cases, as the capabilities, technologies, and processes associated with autonomous or semi-autonomous vehicles continue to develop, the amount of bandwidth used, for example, for ECU-to-ECU communications, increases accordingly. Currently, for example, inter-ECU communications utilize approximately fifty (50) gigabits per second (gbps) for data communications. To handle the increase in communication data, the vehicle and various subsystems corresponding to the vehicle utilize one or more processing units (e.g., CPUs). However, in some cases, ten (10) gbps of bandwidth usage typically utilizes one (1) CPU core, and, as data communications increase, the number of CPU cores and corresponding processing power increases accordingly. Furthermore, the additional processing power that could be used to perform one or more other functions is instead used for data communications and storage.

[0037] One or more embodiments of the present disclosure can help reduce the number of CPU cores and / or the amount of processing power used to process data and / or store data in memory. In some embodiments, one or more new and / or modified headers can include information that allows one or more other hardware components to write one or more segments to the correct data storage location. In addition, the new header can include information so that the processing unit is notified only in certain circumstances (e.g., the start of a data frame, the end of a data frame, missing data, etc.). Thus, the embodiments described herein can reduce the processing power and resources dedicated to ECU-to-ECU transmissions while accurately storing and processing data transmitted between components.

[0038] In addition to ECU to ECU data transmission, embodiments of the present disclosure may also involve communicating image data within one or more systems (e.g., autonomous and / or semi-autonomous vehicles). In some cases, with advancements in autonomous driving, the communication of image data from one or more image sensors is a key component of vehicle operation. For example, in a given automobile chassis, there may be several cameras and / or image sensors (e.g., twenty (20) or more) that can capture image data corresponding to various angles associated with the environment in which the vehicle may be located. The image sensors generate image data that can be transmitted to one or more systems within the vehicle for driver assistance, autonomous driving systems, perception systems, etc. In many cases, the image data can be used to generate control or actuation actions corresponding to steering, acceleration, braking, route information, etc. In order to determine accurate control actions, the image data is transmitted as quickly and accurately as possible, and the faster the image data can be accurately transmitted, the better the vehicle can operate in real time or near real time.

[0039] One or more existing solutions for transmitting image data to, for example, one or more processing systems is by using the Camera Serial Interface (CSI) protocol. In many cases, the communication of large amounts of image data is accompanied by a lot of proprietary wiring and serializers / deserializers.

[0040] In contrast, the communication protocol of the present disclosure may include modifications to the existing IEEE 1722 standard (the "1722 standard"). Generally, the 1722 standard includes a link layer protocol that has been established for transmitting media and control data over time-sensitive Ethernet-based networks. Therefore, the communication protocol of the present disclosure takes advantage of building on an already established communication protocol that is configured for high-speed data communication in time-sensitive applications. In addition, the modifications to the 1722 standard described in the present disclosure may help improve the 1722 standard by reducing the amount of processing and / or memory resources that can be used for image data communication as compared to using the currently established 1722 standard. In these or other embodiments, the 1722 standard may include, for example, the existing IEEE 1722b, 1722c, and other IEEE standards corresponding to transmitting data over Ethernet.

[0041] In particular, the modification to the 1722 standard includes adding header fields and corresponding header data to an Ethernet packet header corresponding to the 1722 standard ("1722 header"). The new header fields may include fields and corresponding data that allow for a reduction in processing that is traditionally performed using a processing unit (e.g., by software running on a CPU).

[0042] One or more embodiments disclosed herein may involve data transmission via an Ethernet protocol, which may be performed using one or more self-machines, which may include any applicable machine or system capable of performing one or more autonomous and / or semi-autonomous operations. Example self-machines may include, but are not limited to, vehicles (land, sea, space, and / or air), robots, robotic platforms, and the like. For example, a self-machine computing application may include one or more applications executable by an autonomous vehicle or semi-autonomous vehicle, such as, for example, a vehicle that can be used to perform a task. Figures 4A-4D An example autonomous or semi-autonomous vehicle or machine 400 (alternatively, referred to herein as "vehicle 400" or "ego-machine 400") is depicted. Throughout this disclosure, references to an "autonomous vehicle" or "semi-autonomous vehicle" may include any vehicle that can be configured to perform one or more autonomous or semi-autonomous navigation or driving operations. Thus, such vehicles may also include vehicles in which an operator is required or available to perform such operations.

[0043] The systems and methods described herein may be used by, but are not limited to, non-autonomous vehicles or machines, semi-autonomous vehicles or machines (e.g., in one or more adaptive driver assistance systems (ADAS)), autonomous vehicles or machines, driverless and driverless robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles coupled to one or more trailers, airships, boats, shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, aircraft, engineering vehicles, submarines, drones, and / or other vehicle types. Further, the systems and methods described herein may be used for various purposes, including, by way of example and not limitation, for machine control, machine motion, machine driving, synthetic data generation, model training, perception, augmented reality, virtual reality, mixed reality, robotics, safety and surveillance, simulation and digital twins, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, object or actor simulation and / or digital twins, data center processing, conversational AI, light transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation for 3D assets, cloud computing, and / or any other suitable application.

[0044] The disclosed embodiments may be included in a variety of different systems, such as automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aerial systems, medical systems, boating systems, smart area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems for performing digital twin operations, systems implemented using edge devices, systems including one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least in part in a data center, systems for performing conversational AI operations, systems implementing one or more language models, such as one or more large language models (LLMs) that process text, audio, images, sensors, and / or other data types to generate one or more outputs, systems for hosting real-time streaming applications, systems for presenting one or more of virtual reality content, augmented reality content, or mixed reality content, systems for performing light transport simulations, systems for performing collaborative content creation of 3D assets, systems implemented at least in part using cloud computing resources, and / or other types of systems.

[0045] These and other embodiments of the present disclosure will be explained with reference to the accompanying drawings. It should be understood that these drawings are diagrammatic and schematic representations of such example embodiments and are not restrictive and are not necessarily drawn to scale. In the drawings, unless otherwise indicated, features with the same number indicate the same structure and function.

[0046] Now refer to Figure 1A , Figure 1Ais a diagram illustrating an example environment 100 related to sending and receiving data 102 according to one or more embodiments of the present disclosure. In some embodiments, data 102 may be packaged and sent using a sending system 104 and received and / or stored using a receiving system 110.

[0047] Data 102 may include one or more bits and / or bytes of data. In some embodiments, data 102 may include any data and / or information that can be communicated between systems, subsystems, components within a system, and the like. In some embodiments, data 102 may include data that is communicated between two locations (e.g., from one part, component, feature, etc. of the autonomous vehicle to another part, component, feature, etc. using one or more cables). In particular, data 102 may include any data that can be transmitted and / or communicated between ECUs.

[0048] In some embodiments, data 102 may include data that may be generated using one or more sensors. In some embodiments, data 102 may include data and / or information corresponding to an environment in which one or more sensors (e.g., a temperature sensor, an image sensor, a velocity sensor, an accelerometer, a RADAR sensor, a LiDAR sensor, a proximity sensor, a pressure sensor, etc.) may be located. For example, a camera may generate image data corresponding to a portion of a particular environment at a particular time, where the image data may be included in data 102.

[0049] In some embodiments, data 102 may include data that may have been previously collected. For example, data 102 may include publicly available temperature data corresponding to a particular environment. Similar to data 102 that has been collected and / or generated in real time or near real time, one or more systems (e.g., sending system 104 and / or receiving system 110) may similarly be used to package, process, use, transmit, etc., publicly available temperature data.

[0050] Additionally or alternatively, data 102 may include data that may not have been generated using one or more sensors. For example, data 102 may include map data corresponding to a map, and / or any other type of data generated, obtained, received, or otherwise used by a system performing data communication. Continuing with this example, one or more systems may be configured to retrieve and / or otherwise obtain map data from one or more other systems, servers, web locations, etc.

[0051] In some embodiments, data 102 can be divided and / or organized into one or more data frames. As used in the present disclosure, a data frame can refer to a grouping or collection of data 102. In some embodiments, data 102 can be entirely included in one data frame. Additionally or alternatively, data 102 can be subdivided and included in more than one data frame. In some embodiments, a data frame can include a specific amount of data 102. For example, data 102 can include one hundred (100) kilobytes of data. Continuing with this example, data 102 can be subdivided into one hundred data frames, each data frame including 1 kilobyte of data 102.

[0052] In some embodiments, a data frame may include data 102 corresponding to one or more sensors. Additionally or alternatively, a data frame may include data 102 corresponding to a specific sensor. For example, data 102 may include data corresponding to both a LiDAR sensor and a pressure sensor at a specific time.

[0053] In some embodiments, a data frame may include data 102 generated using a particular sensor at a particular timestamp. For example, in the context of a camera or other image sensor, the camera may generate image data (e.g., data 102) corresponding to a particular environment from time t0 to time t2. Furthermore, data 102 may be subdivided into three (3) data frames, with a first data frame including data 102 generated using the camera at time t0, a second data frame including data 102 generated using the camera at time t1, and a third data frame including data 102 generated using the camera at time t2.

[0054] In some embodiments, one or more systems (e.g., transmitting system 104) may be used to generate, extract, retrieve, and / or otherwise obtain data 102. Transmitting system 104 may include one or more systems, modules, control units, etc. that may be configured to perform one or more operations on data 102. In some embodiments, transmitting system 104 may include one or more electronic control units ("ECUs") corresponding to a larger system. For example, transmitting system 104 may include an ECU corresponding to an autonomous vehicle or a semi-autonomous vehicle, where the ECU may include one or more computing systems, embedded systems, devices, controllers, microcontrollers, etc. that may be configured to receive data 102 and / or perform one or more operations based on data 102.

[0055] In some embodiments, the transmission system 104 may include one or more hardware components and / or software components that may be configured to perform one or more operations on the data 102. In some embodiments, the transmission system 104 may include one or more hardware units. The hardware units include, for example, counters, arithmetic logic units (ALUs), adders, logic circuits, etc. Additionally or alternatively, the transmission system 104 may include one or more modules, such as a packetization module 106, that may be configured to work in conjunction with the hardware units to organize the data 102 for transmission by partitioning, packaging, and / or organizing the data 102.

[0056] In some embodiments, the grouping module 106 may include code and routines configured to allow the computing system to perform one or more operations. Additionally or alternatively, the grouping module 106 may be implemented using hardware including one or more processors, CPUs, graphics processing units (GPUs), data processing units (DPUs), parallel processing units (PPUs), microprocessors (e.g., for performing one or more operations controlling the execution of one or more operations), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), accelerators (e.g., deep learning accelerators (DLAs)), and / or other processor types. In these and other embodiments, the grouping module 106 may be implemented using a combination of hardware and software. In the present disclosure, operations described as being performed by the grouping module 106 may include operations that the grouping module 106 may instruct the corresponding computing system to perform. In these or other embodiments, the grouping module 106 may be implemented by one or more computing devices, such as with respect to Figures 4A-4D 、 Figure 5 and / or Figure 6 A computing device is described in further detail.

[0057] In some embodiments, the grouping module 106 can be configured to assign data frames to a specific queue of data frames. As used in the present disclosure, a queue can refer to a data structure that can be used to organize data frames and corresponding segments and packets 108 to facilitate efficient data transmission. For example, a specific queue can be used to organize the transmission of four (4) data frames. Continuing with this example, the byte offsets associated with the four (4) data frames can each be included in the queue so that the packets 108 transmitting the corresponding segments corresponding to the four (4) data frames can include the correct byte offsets associated with the corresponding segments and be transmitted to one or more other systems (e.g., a receiving system 110).

[0058] In some embodiments, the grouping module 106 can be configured to subdivide and / or organize the data 102 into one or more sets or groups. In particular, one or more data frames can be subdivided into one or more segments. In some embodiments, one or more segments can include one or more corresponding portions of the data 102. In some embodiments, a segment can include all of the data 102 associated with one or more data frames. Additionally or alternatively, a segment can include a subset of the data 102 included in an individual data frame. For example, a data frame can include one (1) megabyte of data, and the data 102 included in the data frame can be subdivided into one thousand (1000) segments, where each segment includes one (1) kilobyte of data. In some embodiments, the size of a segment (e.g., the amount of data included in a segment) can be determined based on the size of one or more payloads that can be carried by a corresponding packet (e.g., packet 108). For example, the Ethernet protocol can define a specific payload size of 64 bytes corresponding to a particular packet. Continuing with this example, in response to the defined payload size of 64 bytes, the data 102 can be subdivided into one or more segments, where the segments include 64 bytes or less of data 102.

[0059] In some embodiments, a sequence number may be assigned to each segment that may correspond to a particular data frame. For example, each segment may be given a sequence number based on a sequence. In some embodiments, the sequence numbers may be integers, starting at zero (0) and incrementally moving upward in increments of one (1). Additionally or alternatively, the sequence numbering may include one or more other sequences that begin with one or more other values ​​and incrementally move upward using one or more other increments (e.g., 2, 3, 4, etc.).

[0060] In some embodiments, sequence numbers corresponding to segments in a particular data frame may be initialized using grouping module 106 and / or one or more other processing units and / or software corresponding to grouping module 106. For example, a first sequence number may be assigned to a first segment using grouping module 106. In some embodiments, one or more hardware elements (e.g., hardware elements associated with transmitting system 104) may be used to assign corresponding sequence numbers to the remaining segments corresponding to the particular data frame based on the first sequence number.

[0061] In some embodiments, the sequence number may be additionally stored in one or more registers, where the registers may include data storage structures configured to store readily accessible data 102. For example, one or more processing units (e.g., packet module 106) and / or hardware units (e.g., one or more components of transmission system 104) may write sequence numbers corresponding to segments in a data frame into one or more registers. The one or more registers may be used to track sequence numbers and segments corresponding to sequence numbers during communication of the segments. Furthermore, the one or more registers may be configured to include data and / or information linking segments to corresponding sequence numbers. By storing the sequence numbers, segments, and data and / or information linking segments to corresponding sequence numbers in the one or more registers, the packet 108 corresponding to the sequence number may be identified by the packet module 106. In some embodiments, in response to one or more packets 108 being lost or otherwise damaged during transmission, the lost or damaged packets 108 may be retransmitted.

[0062] For example, a data frame may include ten (10) segments. Continuing with this example, the grouping module 106 may assign a first sequence number of zero (0) to the first segment. Upon assigning the first segment, one or more hardware elements may be used to assign subsequent sequence numbers to the remaining segments by incrementing the sequence number by one (1), such that subsequent segments are assigned sequence numbers 1, 2, 3, 4, and so on. In some embodiments, using hardware elements in this manner may reduce the amount of overall processing power used to specify segment storage locations in memory.

[0063] In some embodiments, the packet module 106 can be configured to generate individual packets 108. In some embodiments, the packet module 106 can be configured to transmit and / or otherwise communicate one or more segments corresponding to the data 102 using the packets 108.

[0064] In some embodiments, packet 108 may refer to a specific data packet, structure, format, etc. that may be used to transport segments corresponding to data 102. In some embodiments, individual packets 108 may include one or more fields that may be defined by one or more protocols used to transport data. In particular, packets 108 may be organized as one or more Ethernet packets. Thus, packets 108 may be organized and defined according to one or more Ethernet protocols associated with Ethernet packets.

[0065] In some embodiments, the one or more fields corresponding to a packet 108 may refer to a specific portion or section of the packet 108 that carries specific information. In some embodiments, the one or more fields associated with a particular packet 108 may include a payload field and / or one or more header fields.

[0066] In some embodiments, the payload field may be populated with data 102 that may be carried using a particular packet 108. In some embodiments, the payload field may carry a portion of the data 102 being transmitted, e.g., from a transmitting system 104 to a receiving system 110. More specifically, the payload field may be populated with a subset of the data 102—e.g., the payload may be populated with segments corresponding to the data 102. In these or other embodiments, the payload corresponding to a respective packet 108 may be populated with respective segments corresponding to the data 102. As used in this disclosure, "payload" may refer to a payload field corresponding to a particular packet 108. Additionally or alternatively, "payload" may refer to the data 102 that may be included in the payload field corresponding to a particular packet 108.

[0067] For example, data 102 may be organized into a data frame, which may be subdivided into a first segment and a second segment. Continuing with this example, a first payload corresponding to first packet 108 may include the first segment, and a second payload corresponding to second packet 108 may include the second segment. The first segment and the second segment may be carried as respective payloads of first packet 108 and second packet 108, respectively.

[0068] In some embodiments, one or more header fields (also referred to herein as "headers") may include one or more data fields included in a corresponding packet 108, which may include information associated with the transmission and storage of the corresponding packet 108 (e.g., a source address of the sender, a destination address corresponding to the intended recipient of the payload, etc.). Additionally or alternatively, the header may include information describing the payload. For example, the header may include the data type of the data 102 included in the payload, the length of the payload, the length of the header, one or more checksums corresponding to the header and / or the payload, etc. Furthermore, the header may include information indicating one or more storage locations corresponding to the data 102 included in the payload.

[0069] You can refer to Figure 1B To describe an example implementation of the header, Figure 1B FIG. 1 shows an example diagram illustrating a modified header 175b modified from a conventional header 175a according to one or more embodiments of the present disclosure. Figure 1BAs shown, the numbered and bolded portions of the legacy header 175a may be modified to include the bolded portions of the modified header 175b to include data and / or information that may be sent and / or received using one or more packets 108. In some embodiments, the legacy header 175a may include one or more fields that may include fields traditionally labeled as an Ethernet header, an Internet Protocol (IP) header, and / or a User Datagram Protocol (UDP) header. Additionally, the modified header 175b may include one or more fields that may have been modified and / or changed from the legacy header 175a to include fields in an Ethernet header, an IP header, and / or a UDP header.

[0070] like Figure 1B As shown, the VLAN ID field 152a included in the traditional header 175a can be changed so that the modified header 175b can instead include the VLAN field 152b for bulk transmission. Additionally or alternatively, the fragment offset field 154a included in the traditional header 175a can be changed so that the modified header 175b can instead include the SSN field 154b, the queue number field 154c, and / or the flag field 154d. Additionally or alternatively, the source IP address 156a included in the traditional header 175a can be changed so that the modified header 175b can instead include the ISN field 156b, the IBO field 156c, the frame number field 156d, and / or the byte offset field 156e. Additionally or alternatively, the UDP source port 158a included in the legacy header 175a may be changed such that the modified header 175b may instead include a sequence number field 158b.

[0071] The VLAN ID field 152a may include bits and / or bytes of data that may indicate a virtual local area network (VLAN) to which the packet 108 corresponding to the VLAN ID field 152a may belong. In some embodiments, the VLAN ID 152a may be the same for the packets 108 included in a particular data frame. For example, a particular data frame may include three (3) different segments that may correspond to three (3) different payloads corresponding to three (3) respective packets 108. Continuing with this example, the VLAN ID field 152a corresponding to each of the three (3) data packets 108 may include the same VLAN ID or VLAN tag.

[0072] In some embodiments, the legacy header 175a may be altered and / or modified to include a VLAN ID field 152b for block data transmission instead of the VLAN ID field 152a. In some embodiments, the VLAN ID field 152b for block data transmission may include data that may indicate different VLANs to which the packet 108 may belong. In some embodiments, VLAN configurations and network settings may be altered and otherwise modified in preparation for block data transmission. For example, the VLAN configuration may be altered to prioritize block data transmission over other, less time-sensitive traffic. For example, a priority ("PRIO") field may be used to indicate priority sorting. For example, a code of "0" corresponding to the PRIO field may indicate the lowest priority or best effort, while a code of "111" corresponding to the PRIO field may indicate the highest priority. In some embodiments, one or more bandwidth allocation settings and traffic shaping settings may be modified to allocate sufficient resources based on the amount of data being transmitted. In some embodiments, in response to the VLAN being modified to allocate sufficient resources and bandwidth for block data transmission, the VLAN ID field 152b for block data transmission may include a VAN ID, which may be different from the VLAN ID included in the VLAN ID field 152a.

[0073] A fragment offset field 154a, which may be included in a legacy header 175a (e.g., as part of an IP header corresponding to a particular packet 108), may indicate a fragment or portion of data included in the packet 108. In some embodiments, the fragment offset field 154a may be modified, changed, or otherwise manipulated to include one or more other fields in a modified header 175b (e.g., a starting value of a sequence number ("SSN") field 154b, a queue number field 154c, and / or a flags field 154d).

[0074] The SSN field 154b may include data and / or information that may indicate to one or more processing units and / or systems that a local sequence number register may be initialized with the value provided in 158b. For example, the SSN field 154b may be populated with zeros "0" or ones "1." Continuing with this example, a "1" may indicate that one or more hardware components may use a sequence number included in the header, such as the sequence number corresponding to the sequence number field 158b. In contrast, a "0" populated in the SSN field 154b may indicate to one or more hardware components that a sequence number may be incremented from one or more sequence numbers corresponding to one or more previous packets 108, for example, using one or more counters.

[0075] In some embodiments, the modified header 175b may additionally include a queue number field 154c that may indicate a particular queue to which the data 102 included in the particular packet 108 may correspond. In some embodiments, a plurality of different queues may be used to transmit the data 102, for example, four (4) different queues. In some embodiments, the segments included in the payload of the particular packet 108 may also be associated with a particular data frame. For example, each of the segments corresponding to the particular data frame may include the same queue number included in each of their corresponding queue number fields 154c.

[0076] The flag field 154d may include data and / or information that may provide information corresponding to the data 102 included in the particular packet 108. In some embodiments, the value included in the flag field 154d may indicate that the segment included in the payload may be the first segment corresponding to a data frame. In some embodiments, the flag field 154d may include one or more values ​​that may indicate that the second segment included in the second payload of the second packet 108 may be the last segment corresponding to the data frame. In some embodiments, the flag field 154d may include one or more values ​​that may indicate that the particular packet 108 may include data 102 corresponding to a segment that may not be the first segment or the last segment included in the data frame.

[0077] In some embodiments, the flags field 154d may include one or more values ​​that may indicate that one or more errors may have occurred corresponding to segments included in the payload of the corresponding packet 108. For example, one or more errors may have occurred in the collection or transmission of segments included in the corresponding payload of the corresponding packet 108, which may be indicated in the flags field 154d.

[0078] In some embodiments, the flag field 154d may indicate that the packet 108 may have been successfully transmitted. Additionally or alternatively, the flag field 154d may indicate that the packet 108 may have been lost. Furthermore, the flag field 154d may include information indicating that more than one packet 108 corresponding to a particular data frame may have been lost or more than one packet 108 corresponding to a particular data frame may not have been transmitted.

[0079] In some embodiments, the flags field 154d may indicate that a particular packet 108 should be sent and / or transmitted to one or more processing units (e.g., one or more CPUs). The one or more processing units may be configured to determine one or more operations to be performed based on the information included in the flags field 154d. For example, the flags field 154d may include information indicating that one or more errors may have occurred, e.g., one or more packets 108 corresponding to a particular data frame may not have been sent or may have been lost. In response to the information included in the flags field 154d, the one or more processing units may be configured to request retransmission of lost packets 108 and / or request retransmission of data 102 corresponding to the data frame.

[0080] In some embodiments, in response to a lost packet 108 corresponding to real-time or near real-time sensor data, one or more processing units may be configured to delete or otherwise remove data 102 corresponding to the data frame corresponding to the lost packet 108. Additionally or alternatively, information indicating additional information corresponding to the sensor data 102 (e.g., image data) may be included in the tag field 154d, as described in this disclosure, for example, with respect to Figure 2B Further described.

[0081] Examples of possible data included in the flags field 154d of the corresponding packet 108 may be further illustrated and / or explained with respect to Table 1:

[0082] Table 1

[0083]

[0084] Table 1 shows an example of a flag field 154d, which may include 8 bits indicated using an indicator [7:0] indicating the range of bits within the bit field. Using this notation, the numbers before and after the colon (:) represent the most significant bit and least significant bit of the field, respectively.

[0085] The first three bits (denoted as [2:0] in the second row of Table 1) are used to convey information corresponding to the payload included in the packet 108. For example, if the first three bits include "000," the segment carried by the packet 108 may include data 102 corresponding to the middle of a data frame. Continuing with this example, "001" may indicate that the segment carried by the packet 108 may include data 102 corresponding to the beginning of a data frame, and "010" may indicate that the segment may include data 102 that may correspond to the end of a data frame. Furthermore, as shown in Table 1, the remaining bit combinations corresponding to the first three bits ("011," "100," "101," "110," and "111") in the flag field 154d may be reserved to indicate information in subsequent iterations or versions of the flag field 154d corresponding to the corresponding packet 108.

[0086] The fourth bit (denoted as [3] in the third row of Table 1) is used to communicate whether one or more processing systems need to be used to process the data packet 108. For example, in this disclosure, for example, Figure 1A Instances where the fourth bit may include a "1" may indicate that one or more processing systems may be used to send and / or process packet 108. Conversely, instances where the fourth bit may include a "0" may indicate that packet 108 and / or corresponding data 102 that may be carried by packet 108 may not be sent and / or processed using one or more processing systems.

[0087] The fifth bit (denoted as [4] in the fourth row of Table 1) may be used to convey information corresponding to resetting a discontinuity state associated with a particular data frame. For example, a positive discontinuity state may indicate that more than one data packet 108 carrying a segment of data 102 corresponding to the particular data frame may have been lost in transmission. Continuing with this example, in response to the positive discontinuity state, the processing system may request retransmission of the entire data frame corresponding to the more than one data packet 108 that may have been lost. In some embodiments, when retransmitting packets 108 corresponding to the data frame, the fifth bit may include a "1" to indicate resetting of the excessive discontinuity state associated with the particular data frame.

[0088] The last three bits represented in the fourth row of Table 1 can indicate a specific data type associated with the data 102 populated in the payload field corresponding to a particular packet 108. In some embodiments, the data type can refer to different kinds of data, such as integers, characters, floating points, strings, etc. Additionally or alternatively, the data type can refer to one or more other distinctions between data. For example, the data type can indicate that the data populated in the payload field corresponding to the packet 108 can include data corresponding to a particular sensor; for example, image data corresponding to a particular camera, temperature data corresponding to a temperature sensor, data corresponding to a particular accelerometer, etc. In some embodiments, the data type can indicate that the data can include ECU-to-ECU data, map data, etc. Table 1 shows a number of bit combinations that can be reserved to indicate information in subsequent iterations or versions of the flags field 154d corresponding to the corresponding packet 108.

[0089] Reference again Figure 1B , a source Internet Protocol (IP) address field 156a in the legacy header 175a may include a source IP address associated with the packet 108. In some embodiments, the IP address field 156a may be modified, changed, replaced, or otherwise manipulated to include an ISN frame 156b, an IBO frame 156c, a frame number field 156d, and / or a byte offset in frame field 156e.

[0090] The ISN field 156b may include an indicator that may signal or otherwise instruct one or more hardware components to determine and enter a sequence number corresponding to a segment included in the payload of a particular packet 108. For example, the data included in the ISN field 156b may instruct a hardware component to insert a sequence number corresponding to the particular packet 108. In response to the instruction using the data included in the ISN field 156b, the one or more hardware components may insert a sequence-based sequence number and one or more sequence numbers corresponding to one or more other packets 108 that include other data 102 associated with the same data frame.

[0091] Insert byte offset (IBO) field 156c may include an indicator that may signal one or more hardware components to provide and / or insert a byte offset corresponding to packet 108 in byte offset field 156e in the frame. In some embodiments, one or more processing units may determine whether to insert the current byte offset. In response to a determination made by one or more processing units, IBO field 156c may reflect the determination with a corresponding indicator (e.g., "0" to reflect not inserting the byte offset; or "1" to reflect inserting the byte offset).

[0092] Frame number field 156d may include one or more values ​​that may indicate a specific data frame corresponding to a segment included in the payload. In some embodiments, frame number field 156d may indicate a specific buffer in which data 102 corresponding to the specific data frame may be stored. In some embodiments, data and / or information corresponding to frame number field 156d may be used to select one or more base addresses that may be selected and to which a byte offset may be added to determine an address at which a specific segment corresponding to a specific payload may be stored. In these or other embodiments, both the queue number included in queue number field 122 and the frame number included in frame number field 156d may be used to determine, for example, a base address corresponding to a segment included in packet 108.

[0093] For example, four (4) data frames may be included in a particular queue. The four (4) data frames may be indicated using a 2-bit indicator in the frame number field 128, e.g., 00, 01, 10, and 11. Continuing with this example, a 2-bit indicator may correspond to each of the four (4) frames corresponding to the queue, e.g., a first frame indicated using the indicator "00," a second frame indicated using the indicator "01," a third frame indicated using the indicator "10," and a fourth frame indicated using the indicator "11." Additionally, a base address corresponding to each of the four (4) data frames may be selected and / or determined based on the frame number, which may be indicated using the data and / or information included in the frame number field 156d.

[0094] Byte offset field 156e may include a byte offset corresponding to a segment included in the payload of packet 108. In some embodiments, the byte offset may indicate a designated storage location associated with the segment in terms of the number of bytes away from the beginning of the data frame to which the segment corresponds. In some embodiments, the byte offset may indicate how many bytes away from a base memory location associated with a data frame (e.g., a data frame indicated using information corresponding to frame number field 156d) the corresponding segment is to be stored. The base memory location may include a base address for storing a set of data 102 corresponding to the data frame. Thus, in some embodiments, the byte offset may indicate an offset from the base address at which the corresponding segment is to be stored. For example, a particular memory address for a particular segment may be the base address plus the corresponding byte offset.

[0095] In some embodiments, the corresponding byte offset corresponding to the byte offset field 156e can be based on the amount of data 102 used to store one or more segments corresponding to a sequence number preceding the sequence number corresponding to the corresponding byte offset in the packet 108. For example, the packets 108 can include a first packet 108, a second packet 108, and a third packet 108, wherein each packet 108 includes a corresponding payload containing 500 bytes of data. The first packet 108 can include a first sequence number of zero (0), the second packet 108 can correspond to a second sequence number of one (1), and the third packet 108 can correspond to a third sequence number of two (2). Continuing with this example, each of the first packet 108, the second packet 108, and the third packet 108 can additionally correspond to a corresponding byte offset that can correspond to a number of bytes in the corresponding payload. The first packet 108 corresponds to a first byte offset of zero (0), the second packet 108 corresponds to a second byte offset of five hundred (500), and the third packet 108 corresponds to a third byte offset of one thousand (1000). In these or other embodiments, the byte offset field 156e may include a value that may be used and / or otherwise communicated to, for example, Figure 1C Data and / or information for further describing and / or illustrating the processing system.

[0096] In some embodiments, a User Datagram Protocol (UDP) source port field 158a included in the UDP header portion of the legacy header 175a may include information corresponding to a port number of a sending application, system, module, etc. In some embodiments, the UDP source port field 158a may be changed, replaced, modified, and / or otherwise manipulated to instead include a sequence number field 158b.

[0097] Sequence number field 158b may include a sequence number corresponding to a segment included in the payload of packet 108. In some embodiments, sequence number field 158b may include an I6b sequence number, which may be assigned, determined, and / or inserted using one or more hardware components in response to an indicator associated with ISN field 156b. In some embodiments, the sequence number may be entered using one or more hardware components based on a previous sequence number corresponding to a segment associated with the same data frame.

[0098] Without departing from the scope of this disclosure, Figure 1BThe conventional header 175a and / or the modified Ethernet header 175b may include one or more header fields in addition to those shown and discussed herein. The details presented and discussed are intended to help provide an explanation and understanding of the concepts of the present disclosure and are not meant to be limiting.

[0099] Return to Figure 1A , one or more packets 108, corresponding headers, and corresponding payloads may be transmitted to a receiving system 110. In some embodiments, the receiving system 110 may include one or more systems, modules, control units, etc., which may be configured to perform one or more operations using the data 102 included in the packets 108. In some embodiments, the receiving system 110 may include one or more electronic control units ("ECUs") corresponding to a larger system. For example, the receiving system 110 may include an ECU corresponding to an autonomous vehicle or a semi-autonomous vehicle, where the ECU may include one or more computing systems, embedded systems, devices, controllers, microcontrollers, etc., which may be configured to receive the packets 108, store the data 102 included in the payload corresponding to the corresponding packets 108 in a memory 116, and / or perform one or more other operations using the data 102 included in the packets 108.

[0100] In some embodiments, the receiving system 110 may include one or more modules and / or systems that may be configured to perform one or more operations using the data 102 included in the packets 108. In some embodiments, the receiving system 110 may include receiving hardware 112 and / or a processing system 114 that may be configured to extract the data 102 corresponding to the corresponding payload of the corresponding packet 108 and / or store the extracted data 102 in a memory 116 corresponding to the receiving system 110.

[0101] Memory 116 may include one or more components corresponding to receiving system 110 that are configured to store data 102 corresponding to packets 108. In some embodiments, memory 116 may include one or more forms of volatile or non-volatile memory, such as random access memory (RAM), dynamic random access memory (DRAM), flash memory, cache memory, buffer memory, secondary storage, and / or other forms of memory that may be configured to store data 102 corresponding to packets 108. In some embodiments, memory 116 may be included in receiving system 110. Additionally or alternatively, memory 116 may be included in one or more other systems, devices, etc. that may be associated with receiving system 110.

[0102] The receive hardware 112 may include one or more hardware units that may use the data 102 corresponding to the packet 108 to perform one or more operations without using one or more processing units, such as one or more CPUs. The receive hardware 112 may include one or more counters, comparators, arithmetic logic units (ALUs), adders, logic circuits, and / or other hardware units configured to perform the one or more operations without using a processing unit and / or using a reduced amount of processing power and / or resources compared to one or more other Ethernet protocols in which one or more processing units designate a storage location in a memory 116 for the packet 108.

[0103] In some embodiments, the receive hardware 112 can be configured to direct the storage of the segments to their corresponding memory locations in the memory 116. For example, the receive hardware 112 of the receiving system 110 can be configured to read the byte offset included in the byte offset field of the corresponding packet 108. Based on the byte offset and the base memory address, the receive hardware 112 can be configured to direct the storage of the segments of the corresponding packet 108 to the corresponding memory location. For example, the receive hardware 112 can add the base memory address to a particular byte offset included in a particular packet 108 to determine a particular memory address for a particular segment included in the payload of the particular packet 108. In these and other embodiments, the receive hardware 112 can direct that a particular segment be stored at a particular memory address in the memory 116.

[0104] In some embodiments, the receive hardware 112 can be configured to determine whether the order of the sequence numbers follows an expected sequence, for example, the receive hardware 112 can be configured to determine whether the sequence numbers incrementally increase as packets 108 corresponding to data 102 corresponding to a particular data frame are received. In these and other embodiments, the receive hardware 112 can be configured to report to the processing system 114 instances where received sequence numbers do not follow the sequence, which can indicate that a particular packet 108 carrying a particular segment was lost during transmission.

[0105] For example, the receiving hardware 112 may include at least a counter and a comparator. The counter may be configured to increment a value contained in a local register, which may be used to store one or more sequence numbers corresponding to one or more received packets 108. In some embodiments, the sequence number corresponding to a packet 108 successfully received before the current sequence number corresponding to the most recently received packet 108 may be referred to herein as the last good sequence number. In some embodiments, the comparator may be configured to compare the last good sequence number plus one (+1) with the current sequence number. If the sequence numbers do not match, the comparison may indicate a packet loss. For example, in the context of a first packet 108 corresponding to a first sequence number of "0," a second packet 108 corresponding to a second sequence number of "1," and a third packet 108 corresponding to a third sequence number of "2," continuing with this example, the last good sequence number may be zero, while the current sequence number may be 2, indicating that the first and third packets may have been received. Furthermore, the counter may be configured to increment the last good sequence number in the local register by one, and the comparator may be configured to compare the current sequence number with the last good sequence number + 1. In this example, the last good sequence number + 1 equals 1, and the current sequence number is 2, 2 ≠ 1. Therefore, the comparison can indicate that the second packet was lost or otherwise not sent. In response, the receiving hardware 112 can indicate that information corresponding to the packet 108 can be sent or otherwise communicated to the processing system 114.

[0106] In some embodiments, the receiving hardware 112 can be configured to read the flag data included in the header to determine additional information about the segment. For example, the receiving hardware 112 can be configured to identify whether the corresponding segment is the beginning or end of a particular data frame. The receiving hardware 112 can use such an indication to determine whether to reset a sequence counter associated with verifying that all segments of the corresponding set of data 102 corresponding to the data frame have been received. In some embodiments, in response to the flag data indicating that the segment corresponding to a particular packet 108 may include data 102 corresponding to the beginning of a data frame or the end of a data frame, the receiving hardware 112 can also be configured to mark the particular packet 108 for review by the processing system 114.

[0107] In some embodiments, the receiving hardware may be configured to generate packet information 118 corresponding to one or more packets 108. Furthermore, in some embodiments, the receiving hardware 112 may be configured to transmit the packet information 118 to the processing system 114.

[0108] In some embodiments, packet information 118 may include data corresponding to one or more packets 108 that may be transmitted to processing system 114. In some embodiments, the information transmitted to processing system 114 may include data and / or information derived using information corresponding to one or more header fields (e.g., one or more header fields corresponding to modified header 175b). Additionally or alternatively, packet information 118 may include information generated based on data corresponding to respective packets 108. For example, receiving system 110 may include one or more descriptors that may generate and / or otherwise determine information associated with respective packets 108 that may be transmitted to processing system 114.

[0109] Figure 1C An example diagram representing packet information 118 is shown, in accordance with one or more embodiments of the present disclosure. The packet information 118 may include one or more fields representing information that may be communicated to the processing system 114.

[0110] In some embodiments, the packet information 118 may include one or more fields that may include data and / or information corresponding to the packet 108, a payload corresponding to the packet 108, and / or data 102 corresponding to the payload. In some embodiments, the one or more fields may include, for example, a sequence number field 120, a queue number field 122, one or more reserved fields 124, a flag field 126, a frame number field 130, a byte offset field 132, a header pointer field 134, and a last good sequence number field 138.

[0111] The sequence number field 120 may indicate a corresponding sequence number assigned to a corresponding segment included in the payload of the corresponding packet 108. In some embodiments, the sequence number may be the same as that included in the present disclosure, for example, regarding Figure 1B The serial number in the serial number field 158b further described and / or shown is the same.

[0112] The queue number field 122 may indicate a particular queue to which a data frame may correspond. In some embodiments, a segment included in the payload of a particular packet 108 may also be associated with a particular data frame. For example, each of a plurality of segments corresponding to a particular data frame may include the same queue number included in each of its corresponding queue number fields 122. In these or other embodiments, the queue number field 122 may include information described in this disclosure, for example, regarding Figure 1B The data and / or information included in the queue number field 175b is further described and / or illustrated.

[0113] In some embodiments, one or more reserved fields 124 may be included in the packet information 118. In some embodiments, the one or more reserved fields 124 may include one or more data bits, for example, one or more zeros (0). In some embodiments, the one or more reserved fields 124 may serve as placeholders for future use and may be intentionally left blank and / or undefined. In some embodiments, the one or more reserved fields 124 may provide flexibility in standardizing the number of bits and / or bytes that may be included in the packet information 118.

[0114] The flags field 126 may include one or more values ​​that may indicate a status corresponding to the packet 108 and / or a segment included in the payload corresponding to the packet 108. For example, the data included in the flags field 126 may indicate whether the segment included in the payload corresponding to the packet 108 is data 102 corresponding to the beginning of a data frame, the end of a data frame, or data 102 included in the middle of a data frame. In some embodiments, the data included in the flags field 126 may indicate one or more errors and / or discontinuities associated with the data 102 included in the payload of the corresponding packet 108. For example, the data included in the flags field 126 may indicate that one or more packets 108 may not have been sent, which may indicate one or more errors corresponding to the data 102 included in the payload. In these or other embodiments, the data and / or information included in the flags field 126 may be related to information included in the present disclosure, for example, regarding Figure 1B and / or the data or information in the flag field 154d further described and / or shown in Table 1 are the same and / or similar.

[0115] The frame number field 130 may include data indicating a frame number corresponding to a segment included in a payload corresponding to a particular packet 108. In some embodiments, a 2-bit encoding may be used to indicate the frame number, for example, 00, 01, 10, or 11 indicating a frame number corresponding to a particular queue. In these or other embodiments, the frame number field may be similar to that described in the present disclosure, for example, with respect to Figure 1BThe frame number field 156d further described and illustrated is the same and / or similar.

[0116] The byte offset field 132 may include a corresponding byte offset to be applied to a corresponding segment included in the payload of the corresponding packet 108. In some embodiments, the byte offset may indicate a designated storage location associated with the segment in the form of a number of bytes away from the beginning of the data frame to which the segment corresponds. The byte offset field 132 may include a byte offset to be applied to a corresponding segment included in the payload of the corresponding packet 108. In some embodiments, the byte offset may indicate a designated storage location associated with the segment in the form of a number of bytes away from the beginning of the data frame to which the segment corresponds. Figure 1B The byte offset included in the byte offset field 156e is further described and / or illustrated.

[0117] The header pointer field 134 may include a pointer that may indicate a storage memory location where header information may be stored. In some embodiments, the pointer included in the header pointer field 134 may be sequentially incremented so that the number of successfully stored packets 108 may be determined. For example, determining the difference between the header pointers included in the respective header pointer fields 134 of respective packets 108 may be used to determine the number of packets 108 that may have been successfully received. Furthermore, the pointer included in the header pointer field may be used by one or more hardware components (e.g., receiving hardware 112) or processing system 114 to store header information corresponding to a particular packet 108.

[0118] The last good sequence number field 138 may include a sequence number corresponding to a packet 108 that has been received prior to the current packet 108. For example, a first packet 108 corresponding to a first sequence number of "0" may have been successfully received. Continuing with this example, a second packet 108 corresponding to a second sequence number of "1" may include a sequence number of "0" in the last good sequence number field 138.

[0119] Without departing from the scope of this disclosure, Figure 1C Modifications, additions, or omissions may be made. For example, the amount of data included in one or more fields corresponding to the packet information 118 and / or the number of reserved fields 124 may vary. The details presented and discussed are intended to assist in providing an explanation and understanding of the concepts of the present disclosure and are not meant to be limiting.

[0120] return Figure 1A In response to receiving packet information 118, processing system 114 may be configured to perform one or more operations and / or instruct one or more corresponding systems to perform one or more operations. For example, in response to an indication that one or more packets 108 were lost during transmission, processing system 114 may be configured to request retransmission of one or more segments corresponding to the lost packets 108. Furthermore, due to byte offsets, segments received after the missing segments may be stored in their designated memory locations corresponding to memory 116.

[0121] In some embodiments, the processing system 114 may include code and routines configured to allow the computing system to perform one or more operations. Additionally or alternatively, the processing system 114 may be implemented using hardware including one or more processors, CPUs, GPUs, DPUs, PPUs, microprocessors (e.g., for performing or controlling the performance of one or more operations), FPGAs, ASICs, accelerators (e.g., DLAs), and / or other processor types. In these or other embodiments, the processing system 114 may be implemented using a combination of hardware and software. In this disclosure, operations described as being performed by the processing system 114 may include operations that the processing system 114 may instruct the corresponding computing system to perform. In these or other embodiments, the processing system 114 may be implemented by one or more computing devices, such as with respect to Figures 4A-4D 、 Figure 5 and / or Figure 6 those described in further detail.

[0122] In these and other embodiments, for example, the packet information 118 can be used to notify the processing system 114 that a new set of data 102 corresponding to a new data frame can be received using the receiving hardware 112. Additionally or alternatively, the processing system 114 can be notified that a specific set of data 102 corresponding to a specific data frame has been received based on the flag data. The processing system 114 can be configured to perform one or more operations accordingly. For example, the processing system 114 can determine a new base address for the next set of data 102 corresponding to the specific data frame in response to an indication that the current set of data 102 corresponding to the specific data frame has been fully received and / or in response to an indication that a new set of data 102 corresponding to a new data frame is being received.

[0123] In some embodiments, in response to receiving hardware 112 notifying processing system 114 that one or more packets 108 may not have been received, processing system 114 and / or receiving system 110 may be configured to transmit information corresponding to lost packet 108 information to transmitting system 104. For example, receiving hardware 112 may receive a first packet 108 including a first sequence number of zero (0) and a second packet 108 including a second sequence number of two (2). Receiving hardware 112 may be configured to recognize that packet 108 having a corresponding lost sequence number of one (1) is lost. Continuing with this example, processing system 114 may transmit the lost packet 108 by transmitting sequence numbers zero (0) and two (2) and requesting transmission or retransmission of segments included in the lost packet 108.

[0124] In some embodiments, processing system 114 may receive notification from receiving hardware 112, e.g., via packet information 118, that more than one packet 108 may be lost. In response to such notification, processing system 114 may be configured to request retransmission of a group of packets 108. For example, transmitting system 104 may transmit a group of packets 108 corresponding to a data frame. Continuing with this example, receiving hardware 112 may notify processing system 114 that multiple packets 108 may be lost in transmission. In response, processing system 114 may request retransmission of all packets 108 corresponding to the data frame. In some embodiments, in response to notification that an individual packet 108 may be lost in transmission, processing system 114 may be configured to request retransmission of the entire data frame corresponding to the lost individual packets 108.

[0125] In contrast to other protocols and systems that may use one or more processing units to determine the storage location corresponding to each segment included in one or more packets 108, embodiments described herein may use processing system 114 in selective circumstances, such as when receiving hardware 112 encounters one or more lost packets 108 and / or when receiving hardware 112 encounters one or more flags corresponding to a flag field in a corresponding packet 108. In some embodiments, selectively using processing system 114 in this manner may reduce the amount of processing resources available to store the corresponding segments corresponding to the corresponding packets 108 in memory 116.

[0126] Without departing from the scope of this disclosure, Figure 1A 10. The present invention also provides a method for implementing ...

[0127] Figure 2A 2 is a diagram illustrating an example environment 200 associated with sending and receiving image frames 206 according to one or more embodiments of the present disclosure. In some embodiments, the example environment 200 may be a diagram of an example environment 200 associated with sending and receiving image frames 206 according to one or more embodiments of the present disclosure. Figure 1A An example implementation of environment 100 is further described. In some embodiments, example environment 200 may include one or more camera sensors 204 , which may be configured to generate and / or otherwise collect image frames 206 .

[0128] In some embodiments, camera sensor 204 may include one or more types of image sensors, such as a charge coupled device ("CCD"), a complementary metal oxide semiconductor ("CMOS") sensor, and the like. In some embodiments, CCD and CMOS sensors may be used in conjunction with one or more cameras to capture and / or generate image data corresponding to one or more captured images. In some embodiments, camera sensor 204 may be an example of a plurality of camera sensors 204 that may be configured to capture image data included in one or more image frames 206 corresponding to an environment in which each camera sensor 204 may be located.

[0129] In some embodiments, the camera sensor 204 can be configured to generate image data associated with one or more image frames 206 corresponding to an environment in which the camera sensor 204 may be located. In some embodiments, the camera sensor 204 can additionally be configured to generate other data corresponding to the image frames 206. For example, the camera sensor 204 can generate metadata corresponding to the image frames 206, such as a timestamp, sensor type, location information, etc. Continuing with this example, the camera sensor 204 can be configured to communicate and / or indicate that one or more errors occurred during data generation and / or when transmitting image data corresponding to the one or more image frames 206 to the transmitting system 202.

[0130] In some embodiments, the camera sensors 204 can be configured to assign image frames 206 to one or more channels over which the image frames 206 can be transmitted. For example, the image frames 206 can correspond to the first camera sensor 204 and the second camera sensor 204. Continuing with this example, the image frames 206 corresponding to the first camera sensor 204 can be assigned to and transmitted via the first channel, and the image frames 206 corresponding to the second camera sensor 204 can be assigned to and transmitted via the second channel.

[0131] In some embodiments, the image frame 206 may correspond to a particular camera sensor 204. For example, the image frame 206 may include image data corresponding to the first camera sensor 204. Additionally or alternatively, the image frame 206 may include data that may correspond to several different camera sensors 204. In some embodiments, the image frame 206 referred to herein may additionally include information including, for example, corresponding metadata, error information, and the like.

[0132] In some embodiments, image data generated using one or more camera sensors 204 may be divided and / or organized into one or more image frames 206. In some embodiments, in the context of an image frame 206 corresponding to an image, an image frame 206 may refer to image data corresponding to a particular image captured at a particular time (e.g., all pixels included in a single image). In some embodiments, an image frame 206 may include one or more rows of image data (referred to herein as "lines"), which may include image data corresponding to a particular row of pixels in the image. In some embodiments, a line may include all pixels spanning the width of a particular image corresponding to an image frame 206. Additionally or alternatively, a line may include a set amount of image data included in a particular image frame 206. In these or other embodiments, an image frame 206 may be a frame that may be used, for example, in the present disclosure with respect to a particular image frame. Figure 1A Examples of data 102 are further described. In some embodiments, image frames 206 may be transmitted, communicated, or otherwise provided to transmitting system 202 .

[0133] The transmitting system 202 may include one or more systems, modules, control units, etc., which may be configured to perform one or more operations on the image frame 206. In some embodiments, the transmitting system 202 may include one or more media access control ("MAC") layers corresponding to larger modules, systems, etc., such as a system on a chip ("SoC"). For example, the transmitting system 202 may include an SoC corresponding to an autonomous vehicle or a semi-autonomous vehicle, wherein the SoC may include one or more computing systems, embedded systems, processing systems, memory, etc., wherein the SoC may be configured to perform one or more operations on the image frame 206.

[0134] In some embodiments, the transmission system 202 may additionally include one or more modules that may be configured to perform one or more operations on the image frames 206. In some embodiments, the transmission system 202 may include a grouping module 208 that may be configured to collect, generate, and / or prepare the image frames 206 for transmission by dividing, packaging, and / or organizing the image frames 206. In these or other embodiments, the transmission system 202 may be an example and / or similar to the examples described in this disclosure, for example, with respect to Figure 1A The transmission system 104 is further described and / or illustrated.

[0135] In some embodiments, the grouping module 208 may include code and routines configured to allow a computing system to perform one or more operations. Additionally or alternatively, the grouping module 208 may be implemented using hardware including one or more processors, CPUs, GPUs, DPUs, PPUs, microprocessors (e.g., for performing or controlling the performance of one or more operations), FPGAs, ASICs, accelerators (e.g., DLAs), and / or other processor types. In these or other embodiments, the grouping module 208 may be implemented using a combination of hardware and software. In the present disclosure, operations described as being performed by the grouping module 208 may include operations that the grouping module 208 may instruct the corresponding computing system to perform. In these or other embodiments, the grouping module 208 may be implemented by one or more computing devices, such as with respect to Figures 4A-4D 、 Figure 5 and / or Figure 6 A computing device is described in further detail.

[0136] In some embodiments, grouping module 208 can be configured to generate one or more checksums corresponding to image data associated with a particular image frame 206. For example, the one or more checksums can include a cyclic redundancy check ("CRC"), a secure hash algorithm, and / or other checksums configured to ensure that an image frame 206 transmitted using transmitting system 202 is the same image frame as an image frame 206 that can be received using, for example, receiving system 212. For example, grouping module 208 can be configured to generate a corresponding sixteen-byte (16B) checksum corresponding to the image data included in the corresponding image frame 206. In some embodiments, grouping module 208 can be configured to transmit the corresponding checksum along with the corresponding image frame 206 using one or more packets 210.

[0137] In some embodiments, the grouping module 208 can be configured to subdivide and / or organize the image data included in one or more image frames 206 into one or more segments. In some embodiments, a segment can include all of the image data included in the image frame 206. In some embodiments, a segment can include all of the data in a row. Additionally or alternatively, a particular segment can include image data corresponding to a portion of a row. In some embodiments, multiple segments can correspond to the same row. In some embodiments, a segment can correspond to image data included in one or more image frames 206, which can be used as payload and transported in corresponding packets 210. In some embodiments, the payload, and therefore the corresponding segment, can include a specific amount of data (e.g., 64 bytes) to maintain uniformity of the payload and data transmission as a whole.

[0138] In some embodiments, the grouping module 208 may be used to determine, assign, and / or identify one or more subframes. As used in the present disclosure, a subframe may indicate a portion of an image frame 206 that, when received using one or more systems, may initiate one or more data processing operations on the image frame 206. In some embodiments, one or more rows of the image frame 206 may be corresponding subframes. In some embodiments, a subframe may include a predetermined amount of image data or a set number of pixels corresponding to an image. In these or other embodiments, the grouping module 208 may be configured to include an indication that particular image data corresponds to the end of a subframe corresponding to a particular image frame 206. This indication may be included in one or more groups 210.

[0139] In some embodiments, each of the segments that may correspond to a particular image frame 206 may be assigned and / or given a sequence number, such as with respect to Figure 1A 、 Figure 1B and / or Figure 1C described.

[0140] In some embodiments, the sequence numbers may be initialized using one or more processing systems that may be included in the sending system 202, the grouping module 208, and / or one or more other associated systems. In some embodiments, after the sequence numbers may have been initialized using the one or more processing systems, the one or more hardware units may be configured to assign subsequent sequence numbers to the corresponding groups 210. For example, the image data corresponding to a particular image frame 206 may be organized into three segments. Continuing with this example, the one or more processing systems may initialize the sequence numbering by assigning a first sequence number (e.g., "0") to the first segment. Continuing with this example, thereafter, the one or more hardware units may be configured to increment the sequence numbers to assign a second sequence number "1" to the second segment and a third sequence number "2" to the third segment.

[0141] In some embodiments, the grouping module 208 can be configured to assign byte offsets to respective segments. In some embodiments, the respective byte offsets can be assigned based on the amount of image data used to store one or more segments corresponding to a sequence number preceding the sequence number corresponding to the respective byte offset in the grouping 210. For example, the image frame 206 can include a first segment, a second segment, and a third segment, each segment including 64 bytes of image data. The first segment can be assigned a first sequence number of zero (0), the second segment can be assigned a second sequence number of one (1), and the third segment can be assigned a third sequence number of (2). Continuing with this example, each of the first segment, the second segment, and the third segment can additionally correspond to a respective byte offset that can correspond to the number of bytes in the respective segment. The first segment can correspond to a first byte offset of zero (0), the second segment can correspond to a second byte offset of sixty-four (64), and the third segment can be assigned a third byte offset of one hundred and twenty-eight (128).

[0142] In some embodiments, the grouping module 208 can be configured to pack the image data corresponding to the image frame 206 into one or more packets 210. The packet 210 may include a payload field that may be populated with image data corresponding to a particular segment of the image frame 206. As used in this disclosure, "payload" may refer to a payload field corresponding to a particular packet 210. Additionally or alternatively, "payload" may refer to image data that may be included in a payload field corresponding to a particular packet 210. More specifically, the payload may be populated with a subset of the image frame 206, for example, the payload may be populated with segments corresponding to the image frame 206. In these or other embodiments, the payload corresponding to the corresponding packet 210 may be populated with the corresponding segments corresponding to the image frame 206. In these or other embodiments, the payload may be, for example, the image data described in this disclosure with respect to Figure 1A 、 Figure 1B and Figure 1C Examples of payloads and / or payload fields are further described and / or shown.

[0143] In some embodiments, the packet 210 may additionally include a corresponding header. In some embodiments, the header may include one or more data fields included in the corresponding packet 210, which may include information associated with the transmission and storage of the corresponding packet 210 (e.g., a source address of the sender, a destination address corresponding to the intended recipient of the payload, etc.). In some embodiments, the header may be modified by adding one or more additional header fields to one or more existing Ethernet protocols (e.g., the 1722 Ethernet protocol). In these or other embodiments, the header may be a header as described in the present disclosure, for example, with respect to Figure 1A 、 Figure 1B and Figure 1CExamples of headers and / or header fields are further described and / or shown.

[0144] You can refer to Figure 2B An example implementation of a header corresponding to one or more packets 210 is described below. Figure 2B is an example diagram showing a modified 1722 header 275 according to one or more embodiments of the present disclosure, the modified header 275 corresponding to Figure 2A The modified 1722 header 275 may include a fixed header field that may have been included in the 1722 IEEE Ethernet protocol standard. In some embodiments, a header field may be added to the 1722 Ethernet header to include, for example, information regarding the present disclosure. Figure 1A and Figure 1B The data and / or information included in the modified header 175b is further described.

[0145] In some embodiments, the modified 1722 header 275 may include one or more fields that may include data and / or information corresponding to the packet 210, a payload corresponding to the packet 210, and / or image data corresponding to the payload. In some embodiments, the one or more fields may include, for example, a sequence number field 254, an error ("E") field 256, a sticky error ("SE") field 258, a frame checksum ("FCV") field 260, a version field 262, a channel number field 268, a flag field 270, a frame number field 272, a frame number reserved field 274, and / or a byte offset field 276.

[0146] The sequence number field 254 may include a sequence number corresponding to the corresponding payload of the corresponding packet 210. In these or other embodiments, the sequence number field 254 may include a sequence number corresponding to the sequence number of the corresponding packet 210. Figure 1B and Figure 1C The same information as and / or similar to the serial number field 120 and / or serial number field 158a is further described and / or shown.

[0147] Error field 256, represented in this figure as "E" 256, may indicate one or more errors corresponding to a segment associated with a particular packet 210. In some embodiments, in response to an error occurring while generating an image frame 206, camera sensor 204 may be configured to assign, report, or otherwise indicate that an error has occurred. In some embodiments, an indication that an error has occurred corresponding to generating image frame 206 may be included in error field 256.

[0148] Sticky error ("SE") field 258 may indicate a specific error corresponding to image frame 206. In some embodiments, in response to the error affecting or potentially affecting the entire image frame 206, SE field 258 may indicate that the error may correspond to all image data included in image frame 206, e.g., image data included in the payloads of plurality of packets 210. SE field 258 may be reset after each image frame 206. In some embodiments, SE field 258 may indicate the presence of an error even in situations where segments may have been lost and / or otherwise corrupted.

[0149] Frame checksum field 260 may include an indication that a checksum (e.g., a cyclic redundancy check (“CRC”), a hash algorithm, and / or some other checksum) may have been determined to be valid. In some embodiments, the indication may include one or more values ​​that may serve as an indicator that the checksum is valid or invalid. In some embodiments, the packet 210 that may include an indication that the checksum is valid may also be a packet 210 that includes image data corresponding to the end of a particular image frame 206. In some embodiments, the frame checksum may be included in the payload of a packet 210 that includes image data corresponding to the end of a particular image frame 206. For example, a payload that includes image data corresponding to the end of a particular image frame 206 may include a 16B CRC corresponding to all image data corresponding to the particular image frame 206. Continuing with this example, in response to the CRC being valid, frame checksum field 260 may indicate the result using a value (e.g., “1”).

[0150] The version field 262 may include the version of the protocol by which the packet 210 and corresponding payload may be sent. In some embodiments, the version field 262 may allow for subsequent versions and / or improvements to the modified 1722 header 275 without confusing the receiving system 212 and / or the sending system 202 as to which version is being used.

[0151] The exposure field 264 may include a value indicating an exposure corresponding to an image frame 206 that may be included in the payload of the corresponding packet 210. In some embodiments, photographic images and movie images may include one or more exposures corresponding to one or more times that a camera shutter may be open to capture an image. The exposure field 264 may include information corresponding to the number and duration of exposures included in the image frame 206.

[0152] In some embodiments, one or more reserved fields 266 may be included in the modified 1722 header 275. In some embodiments, the one or more reserved fields 266 may include one or more data bits, for example, one or more zeros (0). In some embodiments, the one or more reserved fields 266 may be used as placeholders for future use and may be intentionally left blank and / or undefined in the current version of the modified 1722 Ethernet protocol. In some embodiments, the one or more reserved fields 266 may provide flexibility and / or standardize the number of bits and / or bytes that may be included in the modified 1722 header 275 in the modified 1722 protocol design. In these or other embodiments, the one or more reserved fields 266 may be used in conjunction with the present disclosure, for example, with respect to Figure 1C The reserved fields 124 described and / or shown are the same and / or similar.

[0153] Channel number field 268 may include a value indicating the channel corresponding to image frame 206. In some embodiments, the channel number included in channel number field 268 may be used by receiving system 212 to identify a particular camera sensor 204, a base address corresponding to a particular image frame 206, or the like.

[0154] Flag field 270 may include data that may indicate a status corresponding to packet 210 and / or a segment included in a payload corresponding to packet 210. In some embodiments, the data included in flag field 270 may indicate that the segment included in the payload may be the first segment corresponding to image frame 206. In some embodiments, flag field 270 may include data that may indicate that a second segment included in a second payload of second packet 210 may be the final segment corresponding to image frame 206.

[0155] In some embodiments, data included in flag field 270 may indicate that a segment included in the payload may be the first segment corresponding to metadata included in image frame 206. In some embodiments, flag field 270 may include data indicating that a second segment included in the second payload of second packet 210 may be the last segment corresponding to metadata included in image frame 206.

[0156] In some embodiments, flags field 270 may include an indication of the end of a subframe corresponding to a particular image frame 206. In some embodiments, the end of a subframe may indicate that one or more processing operations (e.g., operations performed using image processor 218) may be performed on the image data that may have been transmitted corresponding to image frame 206. In some embodiments, a subframe may include a predefined number of rows or a predefined amount of image data corresponding to image frame 206.

[0157] In some embodiments, the flags field 270 may include data and / or information that may indicate that one or more errors may have occurred corresponding to a segment included in the payload of the corresponding packet 210. For example, one or more errors may have occurred in the collection or transmission of the segments included in the corresponding payload of the corresponding packet 210, which may be indicated in the flags field 270.

[0158] In some embodiments, flags field 270 may indicate that a particular packet 210 should be sent and / or transmitted to one or more processing units (e.g., one or more CPUs). One or more processing units may be configured to determine one or more operations to perform based on the information included in flags field 270. For example, flags field 270 may include information indicating that one or more errors may have occurred, e.g., one or more packets 210 corresponding to a particular image frame 206 may not have been sent or may have been lost. In some embodiments, one or more processing units may be configured to delete, remove, or otherwise not store image frames 206 corresponding to the missing segments.

[0159] Examples of possible data included in the flags field 270 of the corresponding packet 210 may be further illustrated and / or explained with respect to Table 2:

[0160] Table 2

[0161]

[0162] Table 2 shows an example of a flag field 270, which may include 8 bits indicated using an indicator [7:0] indicating the range of bits within the bit field. Using this notation, the digits before and after the colon (:) represent the most significant bit and the least significant bit of the field, respectively. In some embodiments, Table 2 may be used in the present disclosure, for example, with respect to Figure 1A 、 Figure 1B and Table 1 further describe example implementations of the flags field 154d.

[0163] The first three bits (denoted as [2:0] in the second row of Table 1) may be used to convey information corresponding to a payload carried using packet 210. For example, where the first three bits include “000,” the segment carried by packet 210 may include image data corresponding to image frame 206 that is associated with the middle of image frame 206. Continuing with this example, “001” may indicate that the segment carried by packet 210 may include image data at the beginning of image frame 206, and “010” may indicate that the segment may include image data that may be at the end of image frame 206.

[0164] Furthermore, as shown in Table 2, the first three bits may indicate that a segment corresponding to a particular packet may include the beginning and / or end of metadata corresponding to a particular image frame 206. For example, a bit combination of "011" may indicate that a segment carried by a particular packet 210 may include the beginning of metadata corresponding to a particular image frame 206. Additionally or alternatively, a bit combination of "100" may indicate that a segment carried by a particular packet 210 may include the end of metadata corresponding to a particular image frame 206.

[0165] In some embodiments, the first three bits may indicate that the segment carried by a particular packet 210 may include the end of a subframe corresponding to a particular image frame 206. For example, as shown in Table 2, a three-bit combination of "101" may indicate that the segment included in the payload may include data 102 corresponding to the end of a subframe associated with a particular image frame 206.

[0166] As shown in Table 2, the remaining bit combinations corresponding to the first three bits (“110” and “111”) in the flag field 270 may be reserved to indicate information in subsequent iterations or versions of the flag field 270 corresponding to the corresponding packet 210 .

[0167] The fourth bit (denoted as [3] in the third row of Table 2) is used to communicate whether one or more processing systems need to be used to process the data packet 210. For example, in this disclosure, for example, Figure 2A The packet processor 216 is further described and / or illustrated. Instances where the fourth bit may include a "1" may indicate that one or more processing systems may be used to transmit and / or process the packet 210. Conversely, instances where the fourth bit may include a "0" may indicate that the packet 210 and / or corresponding image data that may be carried by the packet 210 may not be transmitted and / or processed using the one or more processing systems.

[0168] The fifth bit (denoted as [4] in the fourth row of Table 1) may indicate that the image data being transported using a particular packet 210 may include image data corresponding to the end of a row. For example, a fourth bit comprising a "1" may indicate that the payload may include image data corresponding to the end of a row associated with a particular image frame 206. Additionally or alternatively, a fourth bit comprising a "0" may indicate that the payload may include image data that may not correspond to the end of a row associated with a particular image frame 206.

[0169] The last three bits in the example flags field 270, as indicated in Table 2, may indicate the type of packet associated with the packet 210. For example, a bit combination of "101" may indicate that the payload of the particular packet 210 may be filled with image data. In contrast, a bit combination of "110" may indicate that the payload of the particular packet 210 may be filled with metadata corresponding to the image frame 206.

[0170] In some embodiments, as shown in Table 2, the last three bits may indicate that the payload may include image data that may be associated with one or more errors, or that the payload may include image data that may have been successfully transmitted. For example, the bit combination "001" may indicate that an error may have occurred while generating image frame 206. As another example, the bit combination "010" may indicate that image frame 206 was successfully received, for example, using an acknowledgement signal ("ACK") used in Inter-Integrated Circuit ("I2C").

[0171] In some embodiments, as shown in Table 2, the last three digits may indicate that the payload may include image data associated with a security event. For example, image frame 206 captured at a particular timestamp may have been generated during one or more security events associated with the system. A security event may include, for example, an incident with a machine associated with camera sensor 204. In some embodiments, the last three digits may indicate that image frame 206 carried by a particular packet 210 may have been associated with a security event.

[0172] Return to Figure 2B , the frame number field 272 may indicate a frame number corresponding to a segment included in a payload corresponding to a particular packet 210. In some embodiments, a 2-bit encoding (e.g., 00, 01, 10, or 11) may be used to indicate a frame number that corresponds to a particular queue. In these or other embodiments, the frame number field may be similar to that described in this disclosure, for example, with respect to Figure 1B and Figure 1C The frame number field 130 and / or frame number field 156c further described and illustrated are the same and / or similar.

[0173] Byte offset field 276 may include a byte offset corresponding to a segment included in the payload of packet 210. In some embodiments, the byte offset may indicate the memory location of the segment in the form of a number of bytes away from the beginning of image frame 206 to which the segment corresponds. For example, byte offset field 276 may include a 28-bit value indicating the memory location where the segment is stored. In these or other embodiments, byte offset field 276 may be similar to the byte offset of the present disclosure, for example, with respect to Figure 1B and Figure 1C The byte offset fields 132 and / or 156d described and shown further are the same and / or similar.

[0174] Without departing from the scope of this disclosure, Figure 2BThe fixed header fields may be modified, added, or omitted. For example, one or more other fields corresponding to the fixed header fields may be changed, modified, and / or amended to include one or more other fields corresponding to existing fields and / or new information. In addition, the amount of data included in one or more fields corresponding to the modified 1722 header 275 may vary. The details presented and discussed are intended to help provide an explanation and understanding of the concepts of the present disclosure and are not meant to be limiting.

[0175] Return to Figure 2A , one or more packets 210, corresponding headers, and corresponding payloads may be transmitted to a receiving system 212. In some embodiments, the receiving system 212 may include one or more systems, modules, SoCs, MAC layers, etc., which may be configured to perform one or more operations on the image data that may be included in the packets 210. For example, the transmitting system 202 may include a SoC corresponding to an autonomous vehicle or a semi-autonomous vehicle, wherein the SoC may include one or more computing systems, embedded systems, processing systems, etc., wherein the SoC may be configured to perform one or more operations on the image data included in the one or more image frames 206 and / or packets 210.

[0176] In some embodiments, the receiving system 212 may include one or more modules and / or systems that may be configured to perform one or more operations on the image data included in the packets 210. In some embodiments, the receiving system 212 may include receiving hardware 214, a packet processor 216, and an image processor 218 that may be configured to extract data corresponding to corresponding payloads of corresponding packets 210 and / or store the extracted data in a memory 220 corresponding to the receiving system 212.

[0177] The memory 220 may include one or more components corresponding to the receiving system 212, which are configured to store data corresponding to the packet 210. In these or other embodiments, the memory 220 may be a component of the present disclosure, such as the one described with respect to FIG. Figure 1A Examples of memory 116 are further described and illustrated.

[0178] The receive hardware 214 may include one or more hardware units that may use the image data corresponding to the packet 210 to perform one or more operations without utilizing one or more processing units, such as one or more CPUs. The receive hardware 214 may include one or more counters, comparators, arithmetic logic units (ALUs), adders, logic circuits, and / or other hardware units configured to perform the one or more operations without utilizing a processing unit and / or using a reduced amount of processing power and / or resources compared to one or more other Ethernet protocols, wherein the one or more processing units designate a storage location in the memory 220 for the packet 210.

[0179] In some embodiments, the receive hardware 214 can be configured to direct the storage of the segments to their corresponding memory locations in the memory 220. For example, the receive hardware 214 of the receiving system 212 can be configured to read the byte offset included in the byte offset field of the corresponding packet 210. Based on the byte offset and the base memory address, the receive hardware 214 can be configured to direct the storage of the segments of the corresponding packet 210 to the corresponding memory location. For example, the receive hardware 214 can add a specific byte offset to the base memory address to determine a specific memory address for a specific segment. In these and other embodiments, the receive hardware 214 can direct that a specific segment be stored at a specific memory address in the memory 220.

[0180] In some embodiments, the receive hardware 214 can be configured to determine whether the order of the sequence numbers follows a sequence, for example, the receive hardware 212 can be configured to determine whether the sequence number increases incrementally as packets 210 corresponding to image data associated with a particular image frame 206 are received. In these and other embodiments, the receive hardware 214 can be configured to report to the packet processor 216 that the received sequence numbers do not follow a sequence, which can indicate that a particular packet 210 carrying a particular segment was lost during transmission. In response, the packet processor 216 can be configured to delete, remove, or otherwise not store the data in the image frame 206 corresponding to the particular segment.

[0181] In these or other embodiments, the receive hardware 214 can be configured to determine additional information associated with the segment based on the flag field 270. For example, the receive hardware 214 can be configured to identify whether the corresponding segment is the beginning segment or the ending segment of a particular image frame 206. The receive hardware 214 can use such an indication to determine whether to reset a sequence counter associated with verifying that all segments of the corresponding set of image data associated with the image frame 206 have been received. In some embodiments, in response to the flag data indicating that the segment corresponding to the particular packet 210 may include data corresponding to the beginning of the image frame 206 or the end of the image frame 206, the receive hardware 214 can also be configured to mark the particular packet 210 for review and / or additional processing using the image processor 218.

[0182] In some embodiments, receive hardware 214 may be configured to use information corresponding to flag field 270 to detect and / or determine that a segment corresponding to a particular packet 210 includes the end of a sub-frame. In some embodiments, in response to detecting that a segment includes image data corresponding to the end of a sub-frame, receive hardware 214 may be configured to mark the particular packet 210 for review and / or additional processing using packet processor 216. Where the flag may indicate the end of a sub-frame or the end of an image frame 206, packet processor 216 may notify image processor 218 to process the image data corresponding to image frame 206 or sub-frame.

[0183] In some embodiments, the receiving hardware 214 may be similar to the hardware described in this disclosure, for example, Figure 1A The receiving hardware 112 further described and / or illustrated is the same as, similar to, and / or an example thereof.

[0184] In some embodiments, the packet processor 216 and / or image processor 218 may include one or more systems, devices, etc., which may be configured to perform one or more processing operations. In some embodiments, the packet processor 216 and / or image processor 218 may be implemented using hardware that includes one or more processors, CPUs, GPUs, DPUs, PPUs, microprocessors (e.g., for performing or controlling the performance of one or more operations), FPGAs, ASICs, accelerators (e.g., DLAs), and / or other processor types. In these or other embodiments, the packet processor 216 and / or image processor 218 may be implemented using a combination of hardware and software. In the present disclosure, operations described as being performed by the packet processor 216 and / or image processor 218 may include operations that the packet processor 216 or image processor 216 may instruct the corresponding computing system to perform. In these or other embodiments, the packet processor 216 and / or image processor 218 may be implemented by one or more computing devices, such as with respect to Figures 4A-4D 、 Figure 5 and / or Figure 6 A computing device is described in further detail.

[0185] In these and other embodiments, the packet processor 216 can be notified that a new image data set corresponding to the new image frame 206 can be received using the receive hardware 214. Additionally or alternatively, the packet processor 216 can be notified that a particular image data set corresponding to the particular image frame 206 has been received based on, for example, flag data included in the flag field 270. The packet processor 216 can be configured to perform one or more operations accordingly. For example, the packet processor 216 can determine a new base address for the next image data set corresponding to the particular image frame 206 in response to an indication that the current image data set corresponding to the particular image frame 206 has been received in its entirety and / or in response to an indication that a new image data set corresponding to the new image frame 206 is being received.

[0186] In some embodiments, in response to receiving hardware 214 notifying packet processor 216 that one or more packets 210 have not been received, packet processor 216 may be configured to delete or remove image data corresponding to image frames 206 associated with segments in lost packets 210 .

[0187] For example, the receiving hardware 214 may receive image data corresponding to the image frame 206, the image frame 206 including a first packet 210 including a first sequence number of zero (0) and a second packet 210 including a second sequence number of two (2). The receiving hardware 214 may be configured to identify that the packet 210 having a corresponding missing sequence number of one (1) is lost. Continuing with this example, the packet processor 216 may be configured to remove segments corresponding to the first packet 210 and the second packet 210 from the memory 220 and / or not store the segments corresponding to the first packet 210 and / or the second packet 210.

[0188] In some embodiments, image processor 218 may include a combination of hardware and software that may be configured to process image frames 206. In some embodiments, image processor 218 may perform one or more operations on image frames 206, such as reconstructing an image corresponding to image frame 206, reducing noise, correcting color, controlling exposure, compressing image frame 206, and the like.

[0189] In some embodiments, image processor 218 may perform one or more operations on image frame 206 based on data corresponding to, for example, flag field 270. In some embodiments, in response to packet processor 216 notifying image processor 218 that a segment corresponding to a particular packet 210 may include image data corresponding to the end of image frame 206, image processor 218 may be configured to perform one or more processing operations on the image data associated with the particular image frame 206.

[0190] In some embodiments, image processor 218 may begin one or more processing operations on image data corresponding to a particular image frame 206 in response to packet processor 216 notifying image processor 218 that a segment corresponding to the particular image frame 206 may correspond to the end of a sub-frame. Image processor 218 may perform the one or more processing operations on the particular image frame 206 before receiving all of the packets 210 and the corresponding image data associated with the entire image frame 206. In doing so, image processor 218 may process all of the image data corresponding to the particular image frame 206 faster than image processor 218 may process the image data corresponding to the entire image frame 206 upon receiving all of the corresponding packets 210.

[0191] In some embodiments, image processor 218 may be configured to write processed image frame 206 to memory 220 .

[0192] Examples of one or more fields included in the modified 1722 Ethernet header of the corresponding packet 210 and subsequent operations performed using information included in the one or more fields may be further illustrated and / or explained with respect to Table 3:

[0193] Table 3

[0194]

[0195] Table 3 shows example values ​​corresponding to additional header fields included in the modified 1722 header 275, including example packet numbers, sequence numbers, frame numbers, byte offsets, and flag values ​​corresponding to twelve (12) individual packets 210. In some embodiments, a receiving system 212 corresponding to the environment 200 can perform one or more operations corresponding to the information included in the modified header. For the example values ​​included in Table 3, one or more example operations can be performed using the receiving system 212, receiving hardware 214, packet processor 216, and / or image processor 218. More specifically, Table 3 indicates a sequence of operations for sending two (2) full image frames 206 using one or more Ethernet protocols. Each packet 210 in the example includes a 1024B payload, and each image frame 206 includes six (6) Ethernet packets 210 and two (2) subframes. The operations performed on the packets 210 and / or the data included in the packets 210 include the following.

[0196] Packet number one (1) shown in the third row of Table 3 is the first packet 210 of the first image frame 206, which is indicated as frame number "0" in the second column. In response to the first packet 210 of the image frame 206, the sequence number assigned to the first packet 210 is "0". In addition, because this is the first packet 210 in the image frame 206, the flag field corresponding to the start of frame (SOF) may be populated with a value indicating that the first packet 210 includes the first segment of the image frame 206. In this case, the value corresponding to the SOF field is "1".

[0197] In some embodiments, for example, image memory may be reserved in memory 220 for image data included in image frames 206 that may be transmitted to receiving system 212. For example, receiving system 212 may reserve approximately eight (8) kB of data to store information corresponding to packets 210 in each image frame 206. In some embodiments, the reserved space may include one or more discrete memory locations; for example, two (2) four (4) kB locations in memory 220 may be reserved for one image frame 206. Additionally or alternatively, one contiguous eight (8) kB location in memory 220 may be reserved for image data included in a particular image frame 206.

[0198] In some embodiments, the receiving system 212, the receiving hardware 214, the packet processor 216, and / or the image processor 218 may be configured to write the segments included in the corresponding packets 210 to the memory 220 using a base address and a corresponding byte offset. For example, the first packet 210 may include a first byte offset of zero "0," which indicates that the memory address corresponding to the segment included in the payload of the first packet 210 is the base memory address.

[0199] The second packet 210 is the second packet 210 in a row. Similar to the first packet 210, the second packet 210 includes a frame number of zero (0). In addition, the second packet 210 includes a sequence number of one (1) and a byte offset that indicates a memory location in the memory 220 where the segment corresponding to the second packet 210 is to be written, the memory location starting at a byte offset from the base address 1024B. The second packet 210 may include a value indicating that the segment corresponding to the second packet 210 is not the beginning of the image frame 206, the end of the image frame 206, and / or the end of a row.

[0200] The third packet 210 is included in the same image frame 206 as the first packet 210 and the second packet 210, indicated using frame number "0". In addition, based on the sequence number corresponding to the segment included in the second packet 210, the sequence number is sequentially increased to two (2). In addition, the byte offset corresponding to the segment in the third packet 210 can indicate that the segment corresponding to the third packet 210 will be written to the storage location in the memory 220 starting from the byte offset from the base address 2048B. The third packet 210 is not the beginning or end of the image frame 206 and therefore includes a zero value. The third packet 210 includes a segment that includes image data corresponding to the end of a row in the image frame 206. The end of a row is indicated using a value of one (1) in the flag field 270.

[0201] In some embodiments, the indication that the third packet includes image data corresponding to the end of a row may also indicate the end of a sub-frame. In this case, receiving hardware 214 may send the packet information to packet processor 216. Packet processor 216 may further indicate to image processor 218 that one or more processing operations may be performed on image frame 206 corresponding to the segments included in the first three packets.

[0202] The remaining packets 210, 4 through 12 include corresponding packet numbers, frame numbers, sequence numbers, byte offsets, start of frame, end of frame, and end of line. In some embodiments, the receiving system 212, receiving hardware 214, packet processor 216, and / or image processor 218 may perform one or more operations on one or more image frames 206 based on information corresponding to fields in the associated header, such as the information included in Table 3.

[0203] Without departing from the scope of this disclosure, Figure 2A206, the number of image frames 206, the number of image frames 206, the number of transmitting systems 202, the grouping module 208, the number of groups 210, the receiving system 212, the receiving hardware 214, the grouping processor 216, the image processor 218, and / or the memory 220 may vary. Furthermore, the operations performed using the grouping module 208, the transmitting system 202, the receiving system 212, the receiving hardware 214, the grouping processor 216, and / or the image processor 218 are meant to be illustrative. The operations may be performed using one or more other systems, modules, devices, hardware, software, etc. The details presented and discussed are intended to help provide an explanation and understanding of the concepts of the present disclosure and are not meant to be limiting.

[0204] Figure 3 300 is a flow chart illustrating a method for processing data transmitted via an Ethernet network according to one or more embodiments of the present disclosure. Method 300 may include one or more blocks 302, 304, and 306. Although illustrated as discrete blocks, operations associated with one or more of the blocks in method 300 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the specific implementation.

[0205] In some embodiments, method 300 may include block 302. At block 302, data may be received via Ethernet packets that may be stored in a memory. In some embodiments, the received data may be divided into one or more segments that may be sequentially ordered according to a sequence. In some embodiments, one or more individual Ethernet packets may include a payload and a header.

[0206] In some embodiments, the payload may include a corresponding segment of one or more segments corresponding to the received data. Additionally or alternatively, the header may include a sequence number field and a byte offset field. In some embodiments, the sequence number field may indicate a corresponding sequence number within a sequence that may correspond to the corresponding segment. The byte offset field may indicate a corresponding byte offset applicable to the segment. One or more example headers corresponding to the received data may be described in the present disclosure, for example, with respect to Figure 1B 、 Figure 1C and Figure 2B further shown and / or described.

[0207] At block 304, one or more packet analysis operations may be performed, where the packet analysis operations may include determining whether a previously transmitted segment is lost. In some embodiments, the previously transmitted segment may be determined to be lost based on at least a first sequence number corresponding to a first segment and at least a second sequence number corresponding to a second segment that may have been received before the first segment. In these or other embodiments, the present disclosure, for example, regarding Figure 1A One or more of the receiving system 110, receiving hardware 112, and / or processing system 114 further described and / or illustrated in the drawings may perform packet analysis operations.

[0208] At block 306, one or more data processing operations may be performed on the one or more Ethernet packets. The one or more data processing operations may include causing the respective segments to be stored at respective memory locations included in the memory based at least on respective byte offsets included in the one or more Ethernet packets. In these or other embodiments, the data processing operations may be performed based on the use of the present disclosure, for example, regarding Figure 1A One or more operations performed by the receiving system 110 , receiving hardware 112 , and / or processing system 114 as further described and / or illustrated may store the one or more packets in the memory 116 .

[0209] Without departing from the scope of the present disclosure, the method 300 and / or one or more operations included in the method 300 may be modified, added to, or omitted. For example, the operations corresponding to the method 300 may be implemented in a different order. Additionally or alternatively, two or more operations may be performed simultaneously. Furthermore, the operations and actions outlined are provided as examples only, and some operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without departing from the essence of the described embodiments.

[0210] Example autonomous vehicle

[0211] Figure 4A4 is an illustration of an example autonomous vehicle 400 according to some embodiments of the present disclosure. Autonomous vehicle 400 (alternatively referred to herein as "vehicle 400") may include, but is not limited to, a passenger vehicle, such as a car, truck, bus, emergency vehicle, shuttle, electric or motorized bicycle, motorcycle, fire truck, police car, ambulance, boat, construction vehicle, underwater vessel, drone, and / or other types of vehicles (e.g., unmanned and / or capable of accommodating one or more passengers). Autonomous vehicles are generally described according to the levels of automation defined by the National Highway Traffic Safety Administration (NHTSA), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (SAE), "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (Standard No. J3016-201506, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and future versions of such standards). The vehicle 400 is capable of implementing functions consistent with one or more of levels 3 to 5 of autonomous driving levels. The vehicle 400 is capable of implementing functions consistent with one or more of levels 1 to 5 of autonomous driving levels. For example, depending on the embodiment, the vehicle 400 is capable of driver assistance (level 1), partial automation (level 2), conditional automation (level 3), high automation (level 4) and / or full automation (level 5). The term "autonomous" as used herein may include any and / or all types of autonomy of 400 or other machines, such as full autonomy, high autonomy, conditional autonomy, partial autonomy, providing assisted autonomy, semi-autonomous, primarily autonomous, or other names.

[0212] Vehicle 400 may include components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. Vehicle 400 may include a propulsion system 450, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. Propulsion system 450 may be connected to a drivetrain of vehicle 400, which may include a transmission, to achieve propulsion of vehicle 400. Propulsion system 450 may be controlled in response to receiving a signal from throttle / accelerator 452.

[0213] A steering system 454, which may include a steering wheel, may be used to steer vehicle 400 (e.g., along a desired path or route) when propulsion system 450 is operating (e.g., when the vehicle is in motion). Steering system 454 may receive signals from steering actuator 456. For fully automated (Level 5) functionality, a steering wheel may be optional.

[0214] Brake sensor system 446 may be used to operate vehicle brakes in response to receiving signals from brake actuator 448 and / or brake sensors.

[0215] May include one or more CPUs, System on Chip (SoC) 404 ( Figure 4C ) and / or one or more GPUs can provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 400. For example, the one or more controllers can send signals to operate the vehicle brakes via one or more brake actuators 448, to operate the steering system 454 via one or more steering actuators 456, and / or to operate the propulsion system 450 via one or more throttles / accelerators 452. The one or more controllers 436 can include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 400. The one or more controllers 436 can include a first controller 436 for autonomous driving functions, a second controller 436 for functional safety functions, a third controller 436 for artificial intelligence functions (e.g., computer vision), a fourth controller 436 for infotainment functions, a fifth controller 436 for redundancy in emergency situations, and / or other controllers. In some examples, a single controller 436 may handle two or more of the above functions, two or more controllers 436 may handle a single function, and / or any combination thereof.

[0216] The one or more controllers 436 may provide signals for controlling one or more components and / or systems of the vehicle 400 in response to sensor data (e.g., sensor inputs) received from one or more sensors. The sensor data may be received from, for example and without limitation, a global navigation satellite system sensor 458 (e.g., a global positioning system sensor), a RADAR sensor 460, an ultrasonic sensor 462, a LIDAR sensor 464, an inertial measurement unit (IMU) sensor 466 (e.g., an accelerometer, a gyroscope, a magnetic compass, a magnetometer, etc.), a microphone 796, a stereo camera 468, a wide-angle camera 470 (e.g., a fisheye camera), an infrared camera 472, a surround camera 474 (e.g., a 360-degree camera), a long-range and / or mid-range camera 498, a speed sensor 444 (e.g., for measuring the velocity of the vehicle 400), a vibration sensor 442, a steering sensor 440, a brake sensor (e.g., as part of a brake sensor system 446), and / or other sensor types.

[0217] One or more of the controllers 436 may receive input (e.g., represented by input data) from the instrument cluster 432 of the vehicle 400 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (HMI) display 434, an audible annunciator, a speaker, and / or via other components of the vehicle 400. These outputs may include information such as vehicle speed, velocity, time, map data (e.g., Figure 4C The HMI display 434 may include information such as the HD map 422 of the vehicle 400 , location data (e.g., the location of the vehicle 400 on the map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and object states as sensed by the controller 436 , and the like. For example, the HMI display 434 may display information about the presence of one or more objects (e.g., street signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that the vehicle has made, is making, or will make (e.g., changing lanes now, leaving 34B in two miles, etc.).

[0218] The vehicle 400 further includes a network interface 424 that can communicate over one or more networks using one or more wireless antennas 426 and / or a modem. For example, the network interface 424 can be capable of communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, etc. The one or more wireless antennas 426 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks such as Bluetooth, Bluetooth LE, Z-wave, ZigBee, etc. and / or one or more low power wide area networks (LPWANs) such as LoRaWAN, SigFox, etc.

[0219] Figure 4B For use according to some embodiments of the present disclosure Figure 4A An example of camera positions and fields of view for autonomous vehicle 400 is shown. The cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, additional and / or alternative cameras may be included and / or located at different locations on vehicle 400.

[0220] The camera type used for the camera may include, but is not limited to, a digital camera that can be suitable for use with components and / or systems of the vehicle 400. The camera may operate under Automotive Safety Integrity Level (ASIL) B and / or under another ASIL. The camera type may have any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. The camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In some examples, the color filter array may include a red-white-white-white (RCCC) color filter array, a red-white-white-blue (RCCB) color filter array, a red-blue-green-white (RBGC) color filter array, a red-green-blue-infrared (RGB-IR) color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In some embodiments, a clear pixel camera such as a camera with an RCCC, RCCB, and / or RBGC color filter array may be used in an effort to improve light sensitivity.

[0221] In some examples, one or more of the cameras can be used to perform advanced driver assistance system (ADAS) functions (e.g., as part of a redundant or fail-safe design). For example, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. One or more of the cameras (e.g., all of the cameras) can simultaneously record and provide image data (e.g., video).

[0222] One or more of the cameras can be mounted in a mounting assembly, such as a custom-designed (3-D printed) assembly, to cut off stray light and reflections from within the car (e.g., reflections from the dashboard reflected in the windshield mirror) that could interfere with the camera's ability to capture image data. With respect to the wing mirror mounting assembly, the wing mirror assembly can be custom 3-D printed so that the camera mounting plate matches the shape of the wing mirror. In some examples, one or more cameras can be integrated into the wing mirror. For side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cab.

[0223] A camera with a field of view that includes a portion of the environment in front of the vehicle 400 (e.g., a front-facing camera) can be used for surround vision to help identify the forward path and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 436 and / or control SoCs. The front-facing camera can be used to perform many of the same ADAS functions as LIDAR, including emergency braking, pedestrian detection, and collision avoidance. The front-facing camera can also be used for ADAS functions and systems, including lane departure warning (LDW), autonomous cruise control (ACC), and / or other functions such as traffic sign recognition.

[0224] A variety of cameras can be used in the front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. Another example could be a wide-angle camera 470, which can be used to sense objects entering the field of view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although Figure 4B The figure shows only one wide-angle camera, but there can be any number of wide-angle cameras 470 on the vehicle 400. In addition, long-range cameras 498 (e.g., a long-view stereo camera pair) can be used for depth-based object detection, especially for objects for which neural networks have not yet been trained. Long-range cameras 498 can also be used for object detection and classification and basic object tracking.

[0225] One or more stereo cameras 468 may also be included in the front configuration. The stereo camera 468 may include an integrated control unit including a scalable processing unit that may provide a multi-core microprocessor and programmable logic (FPGA) with an integrated CAN or Ethernet interface on a single chip. Such a unit may be used to generate a 3-D map of the vehicle environment, including distance estimates for all points in the image. An alternative stereo camera 468 may include a compact stereo vision sensor that may include two camera lenses (one on the left and one on the right) and an image processing chip that may measure the distance from the vehicle to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. Other types of stereo cameras 468 may be used in addition to or alternatively to those described herein.

[0226] Cameras with a field of view that includes portions of the environment to the sides of the vehicle 400 (e.g., side-view cameras) can be used for surround viewing, providing information used to create and update occupancy grids and generate side impact collision warnings. For example, surround cameras 474 (e.g., Figure 4BFour surround cameras 474 (shown in FIG) can be placed on the vehicle 400. The surround cameras 474 can include wide-angle cameras 470, fisheye cameras, 360-degree cameras, and / or the like. For example, four fisheye cameras can be placed on the front, rear, and sides of the vehicle. In an alternative arrangement, the vehicle can use three surround cameras 474 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0227] A camera having a field of view that includes a portion of the environment behind the vehicle 400 (e.g., a rearview camera) can be used to assist with parking, surround view, rear collision warning, and creating and updating occupancy grids. A variety of cameras can be used, including but not limited to cameras that are also suitable as front-facing cameras as described herein (e.g., long-range and / or mid-range cameras 498, stereo cameras 468, infrared cameras 472, etc.).

[0228] Figure 4C For use according to some embodiments of the present disclosure Figure 4A 4. A block diagram of an example system architecture for an example autonomous vehicle 400 is shown. It should be understood that this arrangement and other arrangements described herein are set forth merely as examples. Other arrangements and elements (e.g., machines, interfaces, functions, sequences, functional groupings, etc.) may be used in addition to or in place of those shown, and some elements may be omitted entirely. Further, many of the elements described herein are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, and in any appropriate combination and location. The various functions described herein as being performed by entities may be implemented by hardware, firmware, and / or software. For example, the various functions may be implemented by a processor executing instructions stored in memory.

[0229] Figure 4C Each of the components, features, and systems of vehicle 400 is illustrated as being connected via bus 402. Bus 402 may include a controller area network (CAN) data interface (alternatively, referred to herein as a "CAN bus"). CAN may be a network internal to vehicle 400 that assists in controlling various features and functions of vehicle 400, such as actuation of brakes, acceleration, braking, steering, windshield wipers, and the like. The CAN bus may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). The CAN bus may be read to find steering wheel angle, ground speed, engine revolutions per minute (RPM), button positions, and / or other vehicle status indicators. The CAN bus may be ASIL B compliant.

[0230] Although bus 402 is described here as a CAN bus, this is not intended to be limiting. For example, FlexRay and / or Ethernet may be used in addition to or in lieu of a CAN bus. Furthermore, although bus 402 is represented by a single line, this is not intended to be limiting. For example, there may be any number of buses 402, which may include one or more CAN buses, one or more FlexRay buses, one or more Ethernet buses, and / or one or more other types of buses using different protocols. In some examples, two or more buses 402 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 402 may be used for collision avoidance functionality, and a second bus 402 may be used for drive control. In any example, each bus 402 may communicate with any component of vehicle 400, and two or more buses 402 may communicate with the same component. In some examples, each SoC 404, each controller 436, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors on vehicle 400) and may be connected to a common bus such as a CAN bus.

[0231] The vehicle 400 may include one or more controllers 436, such as those described herein. Figure 4A Controller 436 may be used for a variety of functions. Controller 436 may be coupled to any of the various other components and systems of vehicle 400 and may be used for control of vehicle 400, artificial intelligence of vehicle 400, infotainment for vehicle 400, and / or the like.

[0232] The vehicle 400 may include one or more system-on-chips (SoCs) 404. The SoC 404 may include a CPU 406, a GPU 408, a processor 410, a cache 412, an accelerator 414, a data store 416, and / or other components and features not shown. The SoC 404 may be used to control the vehicle 400 in a variety of platforms and systems. For example, the one or more SoCs 404 may be combined with an HD map 422 in a system (e.g., a system of the vehicle 400), which may be downloaded from one or more servers (e.g., a server) via a network interface 424. Figure 4D one or more servers 478) to obtain map refreshes and / or updates.

[0233] The CPU 406 may include a CPU cluster or CPU complex (alternatively, referred to herein as a "CCPLEX"). The CPU 406 may include multiple cores and / or L2 caches. For example, in some embodiments, the CPU 406 may include eight cores in a coherent multiprocessor configuration. In some embodiments, the CPU 406 may include four dual-core clusters, each of which has a dedicated L2 cache (e.g., a 2MB L2 cache). The CPU 406 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of CPU 406 clusters can be active at any given time.

[0234] The CPU 406 may implement power management capabilities including one or more of the following features: each hardware block may be automatically clock gated when idle to conserve dynamic power; each core clock may be gated when the core is not actively executing instructions due to the execution of WFI / WFE instructions; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. The CPU 406 may further implement an enhanced algorithm for managing power states, in which allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. The processing core may support a simplified power state entry sequence in software, with this work being offloaded to the microcode.

[0235] The GPU 408 may include an integrated GPU (alternatively referred to herein as an "iGPU"). The GPU 408 may be programmable and efficient for parallel workloads. In some examples, the GPU 408 may use an enhanced tensor instruction set. The GPU 408 may include one or more streaming microprocessors, each of which may include an L1 cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more of these streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In some embodiments, the GPU 408 may include at least eight streaming microprocessors. The GPU 408 may use a computing application programming interface (API). In addition, the GPU 408 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0236] In the case of automotive and embedded use, GPU 408 can be power optimized to achieve optimal performance. For example, GPU 408 can be manufactured on fin field effect transistors (FinFETs). However, this is not intended to be limiting, and GPU 408 can be manufactured using other semiconductor manufacturing processes. Each streaming microprocessor can merge several mixed precision processing cores divided into multiple blocks. For example and without limitation, 64 PF32 cores and 32 PF64 cores can be divided into four processing blocks. In such an example, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed precision NVIDIA tensor cores for deep learning matrix arithmetic, L0 instruction cache, warp scheduler, dispatch unit and / or 64KB register file. In addition, the streaming microprocessor may include independent parallel integer and floating point data paths to provide efficient execution of workloads using a mix of computation and addressing calculations. The streaming microprocessor may include independent thread scheduling capabilities to allow for finer-grained synchronization and collaboration between parallel threads. Streaming microprocessors may include a combined L1 data cache and shared memory unit to increase performance while simplifying programming.

[0237] GPU 408 can include high bandwidth memory (HBM) and / or a 16GB HBM2 memory subsystem that provides a peak memory bandwidth of approximately 900 GB / s in some examples. In some examples, synchronous graphics random access memory (SGRAM), such as fifth generation graphics double data rate synchronous random access memory (GDDR5), can be used in addition to or in lieu of HBM memory.

[0238] The GPU 408 may include unified memory technology that includes access counters to allow memory pages to be more accurately migrated to the processor that accesses them most frequently, thereby improving the efficiency of memory ranges shared between processors. In some examples, address translation services (ATS) support may be used to allow the GPU 408 to directly access the CPU 406 page tables. In such an example, when the GPU 408 memory management unit (MMU) experiences a miss, an address translation request may be transmitted to the CPU 406. In response, the CPU 406 may look up the virtual-to-physical mapping for the address in its page table and transmit the translation back to the GPU 408. In this way, unified memory technology may allow a single unified virtual address space to be used for memory of both the CPU 406 and the GPU 408, thereby simplifying GPU 408 programming and porting applications to the GPU 408.

[0239] In addition, GPU 408 can include access counters that can track how often GPU 408 accesses the memory of other processors. The access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses them most frequently.

[0240] SoC 404 may include any number of caches 412, including those described herein. For example, cache 412 may include an L3 cache available to both CPU 406 and GPU 408 (e.g., connected to both CPU 406 and GPU 408). Cache 412 may include a write-back cache that can track the state of lines, for example, using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). Depending on the embodiment, the L3 cache may include 4MB or more, although smaller cache sizes may also be used.

[0241] SoC 404 may include one or more arithmetic logic units (ALUs) that may be used to perform processing for any of a variety of tasks or operations related to vehicle 400, such as processing a DNN. Furthermore, SoC 404 may include a floating point unit (FPU) or other math coprocessor or digital coprocessor type for performing mathematical operations within the system. For example, SoC 404 may include one or more FPUs integrated as execution units within CPU 406 and / or GPU 408.

[0242] SoC 404 may include one or more accelerators 414 (e.g., hardware accelerators, software accelerators, or a combination thereof). For example, SoC 404 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. The large on-chip memory (e.g., 4MB SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. The hardware acceleration cluster may be used to supplement GPU 408 and offload some tasks of GPU 408 (e.g., freeing up more cycles of GPU 408 for performing other tasks). As an example, accelerator 414 may be used for targeted workloads (e.g., perception, convolutional neural networks (CNNs), etc.) that are sufficiently stable to be easily controlled for acceleration. When used herein, the term "CNN" may include all types of CNNs, including region-based or regional convolutional neural networks (RCNNs) and fast RCNNs (e.g., for object detection).

[0243] The accelerator 414 (e.g., a hardware acceleration cluster) may include a deep learning accelerator (DLA). The DLA may include one or more tensor processing units (TPUs) that can be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. The TPU may be an accelerator configured to perform image processing functions (e.g., for CNN, RCNN, etc.) and optimized for performing image processing functions. The DLA may be further optimized for a specific set of neural network types and floating-point operations and reasoning. The design of the DLA may provide higher performance per millimeter than a general-purpose GPU and far exceed the performance of the CPU. The TPU may perform several functions, including a single-instance convolution function, support for INT8, INT16, and FP16 data types for both features and weights, and post-processor functions.

[0244] DLA can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a wide variety of functions, such as, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection and recognition and detection using data from microphones; CNNs for facial recognition and vehicle owner identification using data from camera sensors; and / or CNNs for safety and / or security-related events.

[0245] The DLA can perform any function of the GPU 408, and by using an inference accelerator, for example, the designer can target any function to either the DLA or the GPU 408. For example, the designer can focus the processing of CNNs and floating-point operations on the DLA and leave other functions to the GPU 408 and / or other accelerators 414.

[0246] The accelerator 414 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (PVA), which may be alternatively referred to herein as a computer vision accelerator. The PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (ADAS), autonomous driving, and / or augmented reality (AR) and / or virtual reality (VR) applications. The PVA may provide a balance between performance and flexibility. For example, each PVA may include, for example and without limitation, any number of reduced instruction set computer (RISC) cores, direct memory access (DMA), and / or any number of vector processors.

[0247] The RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and / or the like. Each of these RISC cores can include any amount of memory. Depending on the embodiment, the RISC core can use any of a number of protocols. In some examples, the RISC core can execute a real-time operating system (RTOS). The RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits (ASICs), and / or memory devices. For example, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0248] The DMA can enable components of the PVA to access system memory independently of the CPU 406. The DMA can support any number of features used to provide optimizations for the PVA, including but not limited to support for multi-dimensional addressing and / or circular addressing. In some examples, the DMA can support addressing in up to six or more dimensions, which can include block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0249] A vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In some examples, the PVA can include a PVA core and two vector processing subsystem partitions. The PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. The vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit (VPU), an instruction cache, and / or a vector memory (e.g., VMEM). The VPU core can include a digital signal processor, such as, for example, a single instruction multiple data (SIMD), a very long instruction word (VLIW) digital signal processor. The combination of SIMD and VLIW can enhance throughput and speed.

[0250] Each of the vector processors can include an instruction cache and can be coupled to dedicated memory. As a result, in some examples, each of the vector processors can be configured to execute independently of the other vector processors. In other examples, the vector processors included in a particular PVA can be configured to employ data parallelism. For example, in some embodiments, multiple vector processors included in a single PVA can execute the same computer vision algorithm, but on different regions of an image. In other examples, the vector processors included in a particular PVA can execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequenced images or portions of images. Among other things, any number of PVAs can be included in a hardware acceleration cluster, and any number of vector processors can be included in each of these PVAs. In addition, the PVAs can include additional error correction code (ECC) memory to enhance overall system security.

[0251] The accelerator 414 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and SRAM to provide high bandwidth, low latency SRAM for the accelerator 414. In some examples, the on-chip memory may include at least 4MB of SRAM consisting of, for example and without limitation, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. Each pair of memory blocks may include an advanced peripheral bus (APB) interface, configuration circuitry, a controller, and a multiplexer. Any type of memory may be used. The PVA and DLA may access the memory via a backbone that provides high-speed memory access to the PVA and DLA. The backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using APB).

[0252] The on-chip computer vision network can include an interface that ensures that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. Such an interface can provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transmission. This type of interface can comply with ISO 26262 or IEC 61508 standards, but other standards and protocols can also be used.

[0253] In some examples, SoC 404 may include a real-time ray tracing hardware accelerator, such as that described in U.S. patent application Ser. No. 16 / 101,232, filed on Aug. 10, 2018. The real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visualization simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulations, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses. In some embodiments, one or more tree traversal units (TTUs) may be used to perform one or more ray tracing related operations.

[0254] The accelerator 414 (e.g., a hardware accelerator cluster) has a wide range of uses in autonomous driving. The PVA can be a programmable vision accelerator that can be used in key processing stages in ADAS and autonomous vehicles. The capabilities of the PVA are a good match for algorithmic domains that require predictable processing, low power, and low latency. In other words, the PVA performs well on semi-intensive or intensive rule computations, and even on small data sets that require predictable runtimes with low latency and low power. Therefore, in the context of platforms for autonomous vehicles, the PVA is designed to run classic computer vision algorithms because they are efficient at object detection and integer math operations.

[0255] For example, according to one embodiment of the technology, PVA is used to perform computer stereo vision. In some examples, a semi-global matching-based algorithm can be used, but this is not intended to be limiting. Many applications for Level 3-5 autonomous driving require on-the-fly motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.). PVA can perform computer stereo vision functions on input from two monocular cameras.

[0256] In some examples, PVA can be used to perform dense optical flow, for example by processing raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR. In other examples, PVA is used for time-of-flight depth processing, for example by processing raw time-of-flight data to provide processed time-of-flight data.

[0257] The DLA can be used to run any type of network to enhance control and driving safety, including, for example, a neural network that outputs a confidence measure for each object detection. Such confidence values ​​can be interpreted as probabilities, or as providing a relative "weight" of each detection compared to other detections. This confidence value enables the system to make further decisions about which detections should be considered true positives versus false positives. For example, the system can set a threshold for confidence and only consider detections that exceed the threshold as true positives. In an automatic emergency braking (AEB) system, a false positive detection could cause the vehicle to automatically apply emergency braking, which is clearly undesirable. Therefore, only the most confident detections should be considered triggers for AEB. The DLA can run a neural network to regress the confidence value. This neural network can take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), inertial measurement unit (IMU) sensor 466 output related to the orientation and distance of the vehicle 400, and 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., LIDAR sensor 464 or RADAR sensor 460).

[0258] SoC 404 may include one or more data stores 416 (e.g., memory). Data stores 416 may be on-chip memory of SoC 404 that may store neural networks to be executed on the GPU and / or DLA. In some examples, for redundancy and safety, data stores 416 may be large enough to store multiple instances of the neural network. Data stores 412 may include L2 or L3 cache 412. References to data stores 416 may include references to memory associated with the PVA, DLA, and / or other accelerators 414 as described herein.

[0259] SoC 404 may include one or more processors 410 (e.g., embedded processors). Processor 410 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related safety implementations. The boot and power management processor may be part of the boot sequence of SoC 404 and may provide runtime power management services. The boot power and management processor may provide clock and voltage programming, auxiliary system low power state transitions, SoC 404 thermal and temperature sensor management, and / or SoC 404 power state management. Each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC 404 may use the ring oscillator to detect the temperature of CPU 406, GPU 408, and / or accelerator 414. If it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place SoC 404 in a lower power state and / or place vehicle 400 in a driver safety parking mode (e.g., to safely park vehicle 400).

[0260] Processor 410 may further include a set of embedded processors that can be used as an audio processing engine. The audio processing engine can be an audio subsystem that allows for full hardware support for multi-channel audio through multiple interfaces and a wide range of flexible audio I / O interfaces. In some examples, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0261] The processor 410 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. The always-on processor engine may include a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0262] Processor 410 may further include a safety cluster engine, which includes a dedicated processor subsystem that handles safety management of automotive applications. The safety cluster engine may include two or more processor cores, tightly coupled RAM, supporting peripherals (such as timers, interrupt controllers, etc.), and / or routing logic. In safety mode, the two or more cores can operate in lockstep mode and act as a single core with comparison logic to detect any differences between their operations.

[0263] Processor 410 may further include a real-time camera engine, which may include a dedicated processor subsystem for handling real-time camera management.

[0264] Processor 410 may further include a high dynamic range signal processor, which may include an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0265] The processor 410 may include a video image compositer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by the video playback application to produce the final image for the player window. The video image compositer may perform lens distortion correction for the wide-angle camera 470, the surround camera 474, and / or for the in-cab monitoring camera sensor. The in-cab monitoring camera sensor is preferably monitored by a neural network running on another instance of the advanced SoC, configured to recognize in-cab events and respond accordingly. The in-cab system may perform lip reading to activate mobile phone service and place calls, dictate emails, change vehicle destinations, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. Certain functions are only available to the driver when the vehicle is operating in autonomous mode and are disabled in other circumstances.

[0266] The video image compositer can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in the presence of motion in the video, the noise reduction appropriately weights spatial information and downweights information provided by neighboring frames. In the case where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositer can use information from previous images to reduce noise in the current image.

[0267] The video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. The video image compositor can further be used for user interface composition when the operating system desktop is in use and the GPU 408 does not need to continuously render new surfaces. Even when the GPU 408 is powered on and active for 3D rendering, the video image compositor can be used to offload the GPU 408 to improve performance and responsiveness.

[0268] SoC 404 may further include a mobile industry processor interface (MIPI) camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for camera and related pixel input functions. SoC 404 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0269] SoC 404 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio codecs, power management, and / or other devices. SoC 404 may be used to process data from cameras (connected via Gigabit multimedia serial links and Ethernet), sensors (e.g., LIDAR sensor 464, RADAR sensor 460, etc., which may be connected via Ethernet), data from bus 402 (e.g., vehicle 400 speed, steering wheel position, etc.), and data from GNSS sensor 458 (connected via Ethernet or CAN bus). SoC 404 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free up CPU 406 from routine data management tasks.

[0270] SoC 404 can be an end-to-end platform with a flexible architecture that spans Levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently uses computer vision and ADAS technologies for diversity and redundancy, along with deep learning tools to provide a platform for a flexible and reliable driving software stack. SoC 404 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, when combined with CPU 406, GPU 408, and data storage 416, accelerator 414 can provide a fast and efficient platform for Levels 3-5 autonomous vehicles.

[0271] This technology therefore provides capabilities and functionality that cannot be achieved with conventional systems. For example, computer vision algorithms can be executed on CPUs, which can be configured using high-level programming languages ​​such as the C programming language to execute a wide variety of processing algorithms across a wide variety of visual data. However, CPUs often fail to meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In particular, many CPUs are unable to execute complex object detection algorithms in real time, a requirement for in-vehicle ADAS applications and practical Level 3-5 autonomous vehicles.

[0272] In contrast to conventional systems, by providing a CPU complex, a GPU complex, and a hardware acceleration cluster, the technology described herein allows for multiple neural networks to be executed simultaneously and / or sequentially, and the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, a CNN executed on a DLA or dGPU (e.g., GPU 420) can include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which a neural network has not been specifically trained. The DLA can further include a neural network capable of recognizing, interpreting, and providing semantic understanding of the signs, and passing that semantic understanding to a path planning module running on the CPU complex.

[0273] As another example, as required for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, a warning sign consisting of "Caution: Flashing lights indicate icing conditions" along with a light can be interpreted by several neural networks, either independently or collectively. The sign itself can be identified as a traffic sign by a first neural network deployed (e.g., a trained neural network), and the text "Flashing lights indicate icing conditions" can be interpreted by a second neural network deployed, which informs the vehicle's path planning software (preferably executing on a CPU complex) that icing conditions exist when the flashing lights are detected. The flashing lights can be identified by operating a third neural network deployed over multiple frames, which informs the vehicle's path planning software of the presence (or absence) of the flashing lights. All three neural networks can run simultaneously, for example, within the DLA and / or on GPU 408.

[0274] In some examples, a CNN for facial recognition and owner recognition can use data from a camera sensor to identify the presence of an authorized driver and / or owner of vehicle 400. An always-on sensor processing engine can be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and in security mode, disable the vehicle when the owner leaves the vehicle. In this way, SoC 404 provides security against theft and / or carjacking.

[0275] In another example, a CNN for emergency vehicle detection and identification can use data from microphone 796 to detect and identify emergency vehicle sirens. In contrast to conventional systems that use general classifiers to detect sirens and manually extract features, SoC 404 uses CNNs to classify environmental and urban sounds and to classify visual data. In a preferred embodiment, the CNN running on the DLA is trained to identify the relative closing speed of emergency vehicles (for example, by using the Doppler effect). The CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by the GNSS sensor 458. Thus, for example, when operating in Europe, the CNN will seek to detect European sirens, and when in the United States, the CNN will seek to identify only North American sirens. Once an emergency vehicle is detected, with the assistance of the ultrasonic sensor 462, the control program can be used to execute emergency vehicle safety routines to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0276] The vehicle may include a CPU 418 (e.g., a discrete CPU or dCPU) that may be coupled to the SoC 404 via a high-speed interconnect (e.g., PCIe). The CPU 418 may include, for example, an X86 processor. The CPU 418 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the SoC 404, and / or monitoring the status and health of the controller 436 and / or the infotainment SoC 430.

[0277] The vehicle 400 may include a GPU 420 (e.g., a discrete GPU or dGPU) that may be coupled to the SoC 404 via a high-speed interconnect (e.g., NVIDIA's NVLINK). The GPU 420 may provide additional artificial intelligence functionality, for example, by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based on input (e.g., sensor data) from sensors of the vehicle 400.

[0278] The vehicle 400 may further include a network interface 424, which may include one or more wireless antennas 426 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). The network interface 424 may be used to enable wireless connections to the cloud (e.g., to a server 478 and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device) via the Internet. In order to communicate with other vehicles, a direct link may be established between the two vehicles, and / or an indirect link may be established (e.g., across a network and through the Internet). The direct link may be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link may provide the vehicle 400 with information about vehicles approaching the vehicle 400 (e.g., vehicles in front of, to the side of, and / or behind the vehicle 400). This functionality may be part of the cooperative adaptive cruise control functionality of the vehicle 400.

[0279] The network interface 424 may include a SoC that provides modulation and demodulation functions and enables the controller 436 to communicate over a wireless network. The network interface 424 may include an RF front-end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. The frequency conversion may be performed by a well-known process and / or may be performed using a super-heterodyne process. In some examples, the RF front-end functionality may be provided by a separate chip. The network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0280] The vehicle 400 may further include data storage 428, which may include off-chip storage (e.g., outside the SoC 404). The data storage 428 may include one or more storage elements, including RAM, SRAM, DRAM, VRAM, flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0281] Vehicle 400 may further include a GNSS sensor 458. GNSS sensor 458 (e.g., GPS, assisted GPS sensor, differential GPS (DGPS) sensor, etc.) is used to assist with mapping, perception, occupancy grid generation, and / or path planning functions. Any number of GNSS sensors 458 may be used, including, for example and without limitation, GPS using a USB connector with an Ethernet to serial (RS-232) bridge.

[0282] The vehicle 400 may further include a RADAR sensor 460. The RADAR sensor 460 may be used by the vehicle 400 for remote vehicle detection even in darkness and / or in adverse weather conditions. The RADAR functional safety level may be ASIL B. The RADAR sensor 460 may use CAN and / or bus 402 (e.g., to transmit data generated by the RADAR sensor 460) for control and access to object tracking data, and in some examples access Ethernet to access raw data. A variety of RADAR sensor types may be used. For example and without limitation, the RADAR sensor 460 may be suitable for front, rear, and side RADAR use. In some examples, a pulsed Doppler RADAR sensor is used.

[0283] The RADAR sensor 460 can include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, and so on. In some examples, the long-range RADAR can be used for adaptive cruise control functions. The long-range RADAR system can provide a wide field of view (e.g., within 250m) achieved through two or more independent browsing. The RADAR sensor 460 can help distinguish between static objects and moving objects and can be used by the ADAS system for emergency braking assistance and forward collision warning. The long-range RADAR sensor may include a single-station multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In the example with six antennas, the central four antennas can create a focused beam pattern that is designed to record the surroundings of the vehicle 400 at a higher rate with minimal traffic interference from adjacent lanes. The other two antennas can expand the field of view, making it possible to quickly detect vehicles entering or leaving the lane of the vehicle 400.

[0284] As an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). A short-range RADAR system may include, but is not limited to, a RADAR sensor designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, such a RADAR sensor system can create two beams that continuously monitor the blind spots behind and beside the vehicle.

[0285] Short-range RADAR systems can be used in ADAS systems for blind spot detection and / or lane change assistance.

[0286] Vehicle 400 may further include ultrasonic sensors 462. Ultrasonic sensors 462, which may be located on the front, rear, and / or sides of vehicle 400, may be used for parking assistance and / or for creating and updating an occupancy grid. A variety of ultrasonic sensors 462 may be used, and different ultrasonic sensors 462 may have different detection ranges (e.g., 2.5 m, 4 m). Ultrasonic sensors 462 may operate at functional safety level ASIL B.

[0287] Vehicle 400 may include a LIDAR sensor 464. LIDAR sensor 464 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. LIDAR sensor 464 may be ASIL B functional safety level. In some examples, vehicle 400 may include multiple LIDAR sensors 464 (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0288] In some examples, LIDAR sensor 464 may be capable of providing a list of objects and their distances for a 360-degree field of view. Commercially available LIDAR sensors 464 may have, for example, an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support for 100 Mbps Ethernet connections. In some examples, one or more non-obtrusive LIDAR sensors 464 may be used. In such examples, LIDAR sensor 464 may be implemented as a small device that can be embedded in the front, back, sides, and / or corners of vehicle 400. In such examples, LIDAR sensor 464 may provide a field of view of up to 120 degrees horizontally and 35 degrees vertically, even for low-reflectivity objects, with a range of 200 meters. Front-mounted LIDAR sensor 464 may be configured for a horizontal field of view between 45 and 135 degrees.

[0289] In some examples, LIDAR technologies such as 3D flash LIDAR may also be used. 3D flash LIDAR uses flashes of laser as an emission source to illuminate the vehicle's surroundings up to about 200 m. The flash LIDAR unit includes a receiver that records the laser pulse transmission time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle to the object. Flash LIDAR can allow a highly accurate and distortion-free image of the surrounding environment to be generated with each laser flash. In some examples, four flash LIDAR sensors can be deployed, one on each side of the vehicle 400. Available 3D flash LIDAR systems include solid-state 3D staring array LIDAR cameras (e.g., non-browsing LIDAR devices) with no moving parts other than a fan. The flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data. By using flash LIDAR, and because flash LIDAR is a solid-state device with no moving parts, the LIDAR sensor 464 may be less susceptible to motion blur, vibration, and / or shock.

[0290] The vehicle may further include an IMU sensor 466. In some examples, the IMU sensor 466 may be located at the center of the rear axle of the vehicle 400. The IMU sensor 466 may include, for example and without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other sensor types. In some examples, such as in a six-axis application, the IMU sensor 466 may include an accelerometer and a gyroscope, while in a nine-axis application, the IMU sensor 466 may include an accelerometer, a gyroscope, and a magnetometer.

[0291] In some embodiments, IMU sensor 466 can be implemented as a miniature high-performance GPS-assisted inertial navigation system (GPS / INS) that combines micro-electromechanical system (MEMS) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. Thus, in some examples, IMU sensor 466 can enable vehicle 400 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to IMU sensor 466. In some examples, IMU sensor 466 and GNSS sensor 458 can be combined into a single integrated unit.

[0292] The vehicle may include microphones 496 positioned in and / or around the vehicle 400. The microphones 496 may be used for, among other things, emergency vehicle detection and identification.

[0293] The vehicle may further include any number of camera types, including stereo cameras 468, wide angle cameras 470, infrared cameras 472, surround cameras 474, long and / or medium range cameras 498, and / or other camera types. These cameras may be used to capture image data around the entire periphery of the vehicle 400. The type of camera used depends on the embodiment and the requirements of the vehicle 400, and any combination of camera types may be used to provide the necessary coverage around the vehicle 400. Additionally, the number of cameras may vary depending on the embodiment. For example, the vehicle may include six cameras, seven cameras, ten cameras, twelve cameras, and / or another number of cameras. As an example and not limitation, the cameras may support Gigabit Multimedia Serial Link (GMSL) and / or Gigabit Ethernet. Each of the cameras described herein may include a 10GbE GPIO (100GbE) ... Figure 4A and Figure 4B Described in more detail.

[0294] Vehicle 400 may further include a vibration sensor 442. Vibration sensor 442 can measure vibrations of vehicle components, such as axles. For example, changes in vibration can indicate changes in the road surface. In another example, when two or more vibration sensors 442 are used, the difference between the vibrations can be used to determine friction or slippage of the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0295] Vehicle 400 may include an ADAS system 438. In some examples, ADAS system 438 may include a SoC. ADAS system 438 may include autonomous / adaptive / automatic cruise control (ACC), cooperative adaptive cruise control (CACC), forward collision warning (FCW), automatic emergency braking (AEB), lane departure warning (LDW), lane keeping assist (LKA), blind spot warning (BSW), rear cross traffic warning (RCTW), collision warning system (CWS), lane centering (LC), and / or other features and functions.

[0296] The ACC system may utilize RADAR sensor 460, LIDAR sensor 464, and / or a camera. The ACC system may include longitudinal ACC and / or lateral ACC. Longitudinal ACC monitors and controls the distance to the vehicle immediately in front of vehicle 400, automatically adjusting the vehicle speed to maintain a safe distance from the vehicle in front. Lateral ACC maintains distance and, when necessary, recommends lane changes for vehicle 400. Lateral ACC is related to other ADAS applications such as LCA and CWS.

[0297] CACC uses information from other vehicles, which can be received from other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via the network interface 424 and / or the wireless antenna 426. A direct link can be provided by a vehicle-to-vehicle (V2V) communication link, while an indirect link can be an infrastructure-to-vehicle (I2V) communication link. Typically, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of the vehicle 400 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. The CACC system can include either or both of the I2V and V2V information sources. Given information about the vehicle ahead of the vehicle 400, CACC can be more reliable, and it has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0298] The FCW system is designed to alert the driver to hazards so that the driver can take corrective action. The FCW system uses a front-facing camera and / or RADAR sensor 460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibrating component. The FCW system can provide warnings in the form of, for example, audible, visual warnings, vibrations, and / or rapid brake pulses.

[0299] The AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. The AEB system can use a front-facing camera and / or RADAR sensor 460 coupled to a dedicated processor, DSP, FPGA and / or ASIC. When the AEB system detects a hazard, it typically first alerts the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system can automatically apply the brakes in an effort to prevent or at least mitigate the effects of the predicted collision. The AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0300] The LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 400 crosses a lane marking. When the driver indicates an intention to leave the lane by activating a turn signal, the LDW system is deactivated. The LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to driver feedback such as a display, speaker, and / or vibration components.

[0301] The LKA system is a variation of the LDW system. If vehicle 400 begins to leave its lane, the LKA system provides corrective steering input or braking for vehicle 400. The BSW system detects and warns the driver of vehicles in the car's blind spot. The BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. The system can also provide additional warnings when the driver uses a turn signal. The BSW system may utilize one or more rear-facing cameras and / or one or more RADAR sensors.

[0302] The RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear-mounted camera while the vehicle 400 is in reverse. Some RCTW systems include automatic emergency braking (AEB) to ensure that the vehicle brakes are applied to avoid a collision. The RCTW system can use one or more rear-mounted RADAR sensors 460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0303] Conventional ADAS systems may be prone to false positive results, which may be annoying and distracting to the driver, but are typically not catastrophic because the ADAS system alerts the driver and allows the driver to decide whether a safety condition actually exists and take action accordingly. However, in the autonomous vehicle 400, in the event of conflicting results, the vehicle 400 itself must decide whether to pay attention to the results from the main computer or the auxiliary computer (e.g., the first controller 436 or the second controller 436). For example, in some embodiments, the ADAS system 438 can be a backup and / or auxiliary computer for providing perception information to the backup computer rationality module. The backup computer rationality monitor can run redundant and diverse software on hardware components to detect failures in perception and dynamic driving tasks. The output from the ADAS system 438 can be provided to the supervisory MCU. If the outputs from the main computer and the auxiliary computer conflict, the supervisory MCU must determine how to reconcile the conflict to ensure safe operation.

[0304] In some examples, the primary computer can be configured to provide a confidence score to the supervisory MCU, indicating the primary computer's confidence in the selected result. If the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's direction, regardless of whether the secondary computer provides conflicting or inconsistent results. In the event that the confidence score does not meet the threshold and the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between these computers to determine the appropriate result.

[0305] The supervisory MCU can be configured to run a neural network that is trained and configured to determine, based on outputs from the primary and secondary computers, conditions under which the secondary computer provides a false alarm. Thus, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot. For example, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover that triggers an alarm. Similarly, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to disregard the LDW when a cyclist or pedestrian is present and lane departure is actually the safest strategy. In embodiments that include a neural network running on the supervisory MCU, the supervisory MCU can include at least one of a DLA or a GPU suitable for running the neural network with associated memory. In preferred embodiments, the supervisory MCU can include and / or be included as a component of the SoC 404.

[0306] In other examples, the ADAS system 438 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In this way, the auxiliary computer can use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, safety, and performance. For example, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially with respect to failures caused by software (or software-hardware interface) functions. For example, if there is a software vulnerability or bug in the software running on the main computer and the non-identical software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a substantial error.

[0307] In some examples, the output of ADAS system 438 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, if ADAS system 438 indicates a forward collision warning due to an object immediately ahead, the perception block can use this information when identifying the object. In other examples, the secondary computer can have its own neural network that is trained and thus reduces the risk of false positives as described herein.

[0308] The vehicle 400 may further include an infotainment SoC 430 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, the infotainment system may not be an SoC and may include two or more separate components. The infotainment SoC 430 may include a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., a navigation system, rear parking assistance, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 400. For example, the infotainment SoC 430 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, in-vehicle entertainment, Wi-Fi, steering wheel audio controls, hands-free voice controls, a head-up display (HUD), an HMI display 434, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. The infotainment SoC 430 may further be used to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 438, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0309] The infotainment SoC 430 may include GPU functionality. The infotainment SoC 430 may communicate with other devices, systems, and / or components of the vehicle 400 via a bus 402 (e.g., a CAN bus, Ethernet, etc.). In some examples, the infotainment SoC 430 may be coupled to a supervisory MCU so that in the event of a failure of a primary controller 436 (e.g., a primary and / or backup computer of the vehicle 400), the infotainment system's GPU may perform some self-driving functions. In such an example, the infotainment SoC 430 may place the vehicle 400 in a driver-safe parking mode as described herein.

[0310] The vehicle 400 may further include an instrument cluster 432 (e.g., a digital instrument panel, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 432 may include a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). The instrument cluster 432 may include a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, a seat belt warning light, a parking brake warning light, an engine check light, airbag (SRS) system information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 430 and the instrument cluster 432. In other words, the instrument cluster 432 may be included as part of the infotainment SoC 430, or vice versa.

[0311] Figure 4D For cloud-based servers and Figure 4A 4. System diagram of communication between an example autonomous vehicle 400. System 476 may include a server 478, a network 490, and a vehicle including vehicle 400. Server 478 may include multiple GPUs 484(A)-484(H) (collectively referred to herein as GPUs 484), PCIe switches 482(A)-482(H) (collectively referred to herein as PCIe switches 482), and / or CPUs 480(A)-480(B) (collectively referred to herein as CPUs 480). GPUs 484, CPUs 480, and PCIe switches may be interconnected with a high-speed interconnect and / or PCIe connection 486, such as, for example and without limitation, an NVLink interface 488 developed by NVIDIA. In some examples, GPUs 484 are connected via NVLink and / or NVSwitch SoCs, and GPUs 484 and PCIe switches 482 are connected via a PCIe interconnect. Although eight GPUs 484, two CPUs 480, and two PCIe switches are illustrated, this is not intended to be limiting. Depending on the embodiment, each of the servers 478 can include any number of GPUs 484, CPUs 480, and / or PCIe switches. For example, each of the servers 478 can include eight, sixteen, thirty-two, and / or more GPUs 484.

[0312] Server 478 can receive image data from a vehicle via network 490, the image data representing images showing unexpected or changed road conditions, such as recently begun road construction. Server 478 can transmit neural network 492, updated neural network 492, and / or map information 494, including information about traffic and road conditions, via network 490 and to the vehicle. Updates to map information 494 can include updates to HD map 422, such as information about construction sites, potholes, curves, flooding, or other obstacles. In some examples, neural network 492, updated neural network 492, and / or map information 494 can have been generated from new training and / or data received from any number of vehicles in the environment and / or based on experience from training performed at a data center (e.g., using server 478 and / or other servers).

[0313] Server 478 can be used to train a machine learning model (e.g., a neural network) based on training data. The training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In some examples, the training data is labeled (e.g., in cases where the neural network benefits from supervised learning) and / or undergoes other preprocessing, while in other examples, the training data is not labeled and / or preprocessed (e.g., in cases where the neural network does not require supervised learning). Training can be performed according to any one or more classes of machine learning techniques, including but not limited to the following: supervised training, semi-supervised training, unsupervised training, self-learning, reinforcement learning, federated learning, transfer learning, feature learning (including principal component and cluster analysis), multilinear subspace learning, manifold learning, representation learning (including alternative dictionary learning), rule-based machine learning, anomaly detection, and any variants or combinations thereof. Once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via network 490), and / or the machine learning model can be used by server 478 to remotely monitor the vehicle.

[0314] In some examples, server 478 can receive data from the vehicle and apply the data to the latest real-time neural network for real-time intelligent reasoning. Server 478 can include a deep learning supercomputer and / or a dedicated AI computer powered by GPU 484, such as the DGX and DGX Station machines developed by NVIDIA. However, in some examples, server 478 can include the deep learning infrastructure of a data center using only CPU power.

[0315] The deep learning infrastructure of server 478 may be capable of rapid real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in vehicle 400. For example, the deep learning infrastructure may receive periodic updates from vehicle 400, such as an image sequence and / or objects that vehicle 400 has located in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). The deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 400. If the results do not match and the infrastructure concludes that the AI ​​in vehicle 400 has malfunctioned, server 478 may transmit a signal to vehicle 400 instructing the vehicle's 400 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0316] For inference, server 478 may include a GPU 484 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). The combination of GPU-powered servers and inference acceleration can enable real-time responses. In other examples, such as where performance is less important, CPU, FPGA, and other processor-powered servers can be used for inference.

[0317] Example computing device

[0318] Figure 5 5 is a block diagram of an example computing device 500 suitable for implementing some embodiments of the present disclosure. Computing device 500 may include an interconnect system 502 that directly or indirectly couples the following devices: memory 504, one or more central processing units (CPUs) 506, one or more graphics processing units (GPUs) 508, a communication interface 510, input / output (I / O) ports 512, I / O components 514, a power supply 516, one or more presentation components 518 (e.g., a display), and one or more logic units 520. In at least one embodiment, computing device 500 may include one or more virtual machines (VMs), and / or any of its components may include virtual components (e.g., virtual hardware components). For non-limiting examples, one or more GPUs 508 may include one or more vGPUs, one or more CPUs 506 may include one or more vCPUs, and / or one or more logic units 520 may include one or more virtual logic units. Thus, computing device 500 may include discrete components (eg, a complete GPU dedicated to computing device 500 ), virtual components (eg, a portion of a GPU dedicated to computing device 500 ), or a combination thereof.

[0319] although Figure 5The various blocks of are shown as being connected via an interconnect system 502 having wires, but this is not intended to be limiting and is provided for clarity only. For example, in some embodiments, a presentation component 518 such as a display device may be considered an I / O component 514 (e.g., if the display is a touch screen). As another example, the CPU 506 and / or the GPU 508 may include memory (e.g., the memory 504 may represent a storage device in addition to the memory of the GPU 508, the CPU 506, and / or the other components). In other words, Figure 5 The term computing device is illustrative only. No distinction is made between categories such as "workstation," "server," "laptop," "desktop," "tablet," "client device," "mobile device," "handheld device," "game console," "electronic control unit (ECU)," "virtual reality system," and / or other device or system types, as all are considered within the Figure 5 within the range of computing devices.

[0320] Interconnect system 502 can represent one or more links or buses, such as an address bus, a data bus, a control bus, or a combination thereof. Interconnect system 502 can include one or more links or bus types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standard association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, and / or another type of bus or link. In some embodiments, there is a direct connection between components. As an example, CPU 506 can be directly connected to memory 504. In addition, CPU 506 can be directly connected to GPU 508. In the case of a direct or point-to-point connection between components, interconnect system 502 can include a PCIe link to perform the connection. In these examples, it is not necessary to include a PCI bus in computing device 500.

[0321] Memory 504 may include any of a variety of computer-readable media. Computer-readable media can be any available media that can be accessed by computing device 500. Computer-readable media can include volatile and non-volatile media and removable and non-removable media. By way of example and not limitation, computer-readable media can include computer storage media and communication media.

[0322] Computer storage media may include volatile and non-volatile media and / or removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 504 may store computer-readable instructions (e.g., representing programs and / or program elements, such as an operating system). Computer storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage devices, magnetic cassettes, magnetic tape, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by computing device 500. As used herein, computer storage media does not include signals themselves.

[0323] Computer storage media may embody computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal such as a carrier wave or other transmission mechanism, and include any information delivery media. The term "modulated data signal" may refer to a signal that has one or more of its characteristics set or changed in such a manner as to encode information into the signal. By way of example and not limitation, computer storage media may include wired media such as a wired network or a direct wired connection, and wireless media such as acoustic, RF, infrared, and other wireless media. Any combination of the above should also be included within the scope of computer-readable media.

[0324] The CPU 506 can be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 500 to perform one or more of the methods and / or processes described herein. Each of the CPUs 506 can include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) capable of processing a large number of software threads simultaneously. The CPU 506 can include any type of processor and can include different types of processors, depending on the type of computing device 500 implemented (e.g., a processor with fewer cores for mobile devices and a processor with more cores for servers). For example, depending on the type of computing device 500, the processor can be an Advanced RISC (ARM) processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). The computing device 500 can also include one or more CPUs 506 in addition to one or more microprocessors or supplementary coprocessors such as math coprocessors.

[0325] In addition to or in place of the CPU 506, the GPU 508 may also be configured to execute at least some computer-readable instructions to control one or more components of the computing device 500 to perform one or more of the methods and / or processes described herein. The one or more GPUs 508 may be integrated GPUs (e.g., with the one or more CPUs 506) and / or the one or more GPUs 508 may be discrete GPUs. In embodiments, the one or more GPUs 508 may be coprocessors for the one or more CPUs 506. The computing device 500 may use the GPU 508 to render graphics (e.g., 3D graphics) or perform general-purpose computations. For example, the GPU 508 may be used for general-purpose computing on a GPU (GPGPU). The GPU 508 may include hundreds or thousands of cores capable of processing hundreds or thousands of software threads simultaneously. The GPU 508 may generate pixel data for outputting an image in response to a rendering command (e.g., a rendering command received from the CPU 506 via a host interface). The GPU 508 may include graphics memory, such as display memory, for storing pixel data or any other suitable data (e.g., GPGPU data). Display memory can be included as part of memory 504. GPU 508 can include two or more GPUs operating in parallel (e.g., via a link). The link can connect the GPUs directly (e.g., using NVLINK) or through a switch (e.g., using NVSwitch). When combined, each GPU 508 can generate pixel data or GPGPU data for different portions or different outputs (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU can include its own memory or can share memory with other GPUs.

[0326] In addition to or in lieu of the CPU 506 and / or GPU 508, the logic unit 520 may be configured to execute at least some computer-readable instructions to control one or more components of the computing device 500 to perform one or more methods and / or processes described herein. In embodiments, the CPU 506, GPU 508, and / or logic unit 520 may perform any combination of methods, processes, and / or portions thereof, either separately or in conjunction. The one or more logic units 520 may be part of and / or integrated within the one or more CPUs 506 and / or the one or more GPUs 508 and / or the one or more logic units 520 may be discrete components of or otherwise external to the CPU 506 and / or GPU 508. In embodiments, the one or more logic units 520 may be processors of the one or more CPUs 506 and / or the one or more GPUs 508.

[0327] Examples of logic unit 520 include one or more processing cores and / or components thereof, such as a data processing unit (DPU), a tensor core (TC), a tensor processing unit (TPU), a pixel vision core (PVC), a vision processing unit (VPU), a graphics processing cluster (GPC), a texture processing cluster (TPC), a streaming multiprocessor (SM), a tree traversal unit (TTU), an artificial intelligence accelerator (AIA), a deep learning accelerator (DLA), an arithmetic logic unit (ALU), an application-specific integrated circuit (ASIC), a floating point unit (FPU), an input / output (I / O) element, a peripheral component interconnect (PCI) or a peripheral component interconnect express (PCIe) element, etc.

[0328] The communication interface 510 may include one or more receivers, transmitters, and / or transceivers that enable the computing device 500 to communicate with other computing devices via an electronic communication network, including wired and / or wireless communications. The communication interface 510 may include components and functionality that enable communication over any of a number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communicating over Ethernet or InfiniBand), low-power wide-area networks (e.g., LoRaWAN, SigFox, etc.), and / or the Internet. In one or more embodiments, the logic unit 520 and / or the communication interface 510 may include one or more data processing units (DPUs) to transmit data received over the network and / or through the interconnect system 502 directly to one or more GPUs 508 (e.g., memory in a GPU 508).

[0329] The I / O ports 512 can enable the computing device 500 to be logically coupled to other devices including I / O components 514, presentation components 518, and / or other components, some of which can be built into (e.g., integrated into) the computing device 500. Illustrative I / O components 514 include a microphone, a mouse, a keyboard, a joystick, a game pad, a game controller, a satellite dish, a browser, a printer, a wireless device, and the like. The I / O components 514 can provide a natural user interface (NUI) that processes user-generated mid-air gestures, voice, or other physiological input. In some instances, the input can be transmitted to an appropriate network element for further processing. The NUI can implement any combination of voice recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition on and adjacent to the screen, mid-air gestures, head and eye tracking, and touch recognition associated with the display of the computing device 500 (as described in more detail in this disclosure). The computing device 500 can include a depth camera such as a stereo camera system, an infrared camera system, an RGB camera system, touch screen technology, and combinations thereof for gesture detection and recognition. Additionally, computing device 500 may include an accelerometer or gyroscope to enable motion detection (e.g., as part of an inertial measurement unit (IMU)). In some examples, the output of the accelerometer or gyroscope may be used by computing device 500 to render immersive augmented or virtual reality.

[0330] The power supply 516 may include a hardwired power supply, a battery power supply, or a combination thereof. The power supply 516 may provide power to the computing device 500 to enable the components of the computing device 500 to operate.

[0331] The presentation component 518 may include a display (e.g., a monitor, a touch screen, a television screen, a head-up display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. The presentation component 518 may receive data from other components (e.g., the GPU 508, the CPU 506, the DPU, etc.) and output the data (e.g., as images, video, sound, etc.).

[0332] Sample Data Center

[0333] Figure 6 An example data center 600 is shown, which may be used in at least one embodiment of the present disclosure. The data center 600 may include a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640.

[0334] like Figure 6As shown, the data center infrastructure layer 610 may include a resource coordinator 612, grouped computing resources 614, and node computing resources ("node CRs") 616(1)-616(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 616(1)-616(N) may include, but are not limited to, any number of central processing units (CPUs) or other processors (including DPUs, accelerators, field programmable gate arrays (FPGAs), graphics processors or graphics processing units (GPUs), etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (NW I / O) devices, network switches, virtual machines (VMs), power modules, and cooling modules. In some embodiments, one or more of the node CRs 616(1)-616(N) may correspond to a server having one or more of the above-mentioned computing resources. Furthermore, in some embodiments, node CRs 616 ( 1 )- 616 (N) may include one or more virtual components, such as vGPUs, vCPUs, etc., and / or one or more of node CRs 616 ( 1 )- 616 (N) may correspond to virtual machines (VMs).

[0335] In at least one embodiment, the grouped computing resources 614 can include a separate grouping (not shown) of node CR616 housed in one or more racks, or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CR616 within the grouped computing resources 614 can include computing, network, memory, or storage resources that can be configured or assigned to support groupings of one or more workloads. In at least one embodiment, several node CR616 comprising CPU, GPU, DPU, and / or other processors can be grouped in one or more racks to provide computing resources to support one or more workloads. One or more racks can also include any number of power modules, cooling modules, and / or network switches in any combination.

[0336] Resource coordinator 612 may configure or otherwise control one or more nodes CR 616(1)-616(N) and / or grouped computing resources 614. In at least one embodiment, resource coordinator 612 may comprise a software design infrastructure (SDI) management entity for data center 600. Resource coordinator 612 may comprise hardware, software, or some combination thereof.

[0337] In at least one embodiment, Figure 6As shown, the framework layer 620 may include a job scheduler 633, a configuration manager 634, a resource manager 636, and a distributed file system 638. The framework layer 620 may include a framework that supports the software 632 of the software layer 630 and / or one or more applications 642 of the application layer 640. The software 632 or the application 642 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. The framework layer 620 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize the distributed file system 638 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 633 may include a Spark driver to facilitate scheduling workloads supported by various layers of the data center 600. In at least one embodiment, the configuration manager 634 may be capable of configuring different layers, such as the software layer 630 and the framework layer 620 including Spark and the distributed file system 638 for supporting large-scale data processing. Resource manager 636 can manage clustered or grouped computing resources that are mapped to or allocated to support distributed file system 638 and job scheduler 633. In at least one embodiment, clustered or grouped computing resources can include grouped computing resources 614 at data center infrastructure layer 610. Resource manager 636 can coordinate with resource coordinator 612 to manage these mapped or allocated computing resources.

[0338] In at least one embodiment, the software 632 included in the software layer 630 may include software used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 638 of the framework layer 620. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0339] In at least one embodiment, the one or more applications 642 included in the application layer 640 may include one or more types of applications used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 638 of the framework layer 620. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and / or other machine learning applications used in conjunction with one or more embodiments.

[0340] In at least one embodiment, any of configuration manager 634, resource manager 636, and resource coordinator 612 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. The self-modification actions can relieve a data center operator of data center 600 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0341] The data center 600 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, a machine learning model may be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described herein with respect to the data center 600. In at least one embodiment, using weight parameters calculated using one or more training techniques, the resources described herein with respect to the data center 600 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks, such as but not limited to those described herein.

[0342] In at least one embodiment, the data center 600 may use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, and / or other hardware (or corresponding virtual computing resources) to perform training and / or reasoning using the aforementioned resources. In addition, one or more software and / or hardware resources described in this disclosure may be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0343] Sample network environment

[0344] A network environment suitable for implementing embodiments of the present disclosure may include one or more client devices, servers, network attached storage (NAS), other backend devices, and / or other device types. The client devices, servers, and / or other device types (e.g., each device) may be configured to: Figure 5 The backend device 600 may be implemented on one or more instances of the computing device 500—for example, each device may include similar components, features, and / or functionality of the computing device 500. In addition, in the case of implementing a backend device (e.g., a server, NAS, etc.), the backend device may be included as part of the data center 600, an example of which is described herein with respect to Figure 6 Describe in more detail.

[0345] The components of the network environment can communicate with each other through the network, which can be wired, wireless, or both. The network can include multiple networks, or a network of networks. For example, the network can include one or more wide area networks (WANs), one or more local area networks (LANs), one or more public networks (e.g., the Internet and / or the Public Switched Telephone Network (PSTN)), and / or one or more private networks. In the case where the network includes a wireless telecommunications network, components such as base stations, communication towers, or even access points (and other components) can provide wireless connections.

[0346] Compatible network environments may include one or more peer-to-peer network environments (in which case the server may not be included in the network environment), and one or more client-server network environments (in which case one or more servers may be included in the network environment). In a peer-to-peer network environment, the functionality described herein with respect to the server may be implemented on any number of client devices.

[0347] In at least one embodiment, the network environment may include one or more cloud-based network environments, distributed computing environments, combinations thereof, and the like. The cloud-based network environment may include a framework layer, a job scheduler, a resource manager, and a distributed file system implemented on one or more servers, which may include one or more core network servers and / or edge servers. The framework layer may include a framework for supporting software at the software layer and / or one or more applications at the application layer. The software or application may include network-based service software or application programs, respectively. In an embodiment, one or more client devices may use network-based service software or application programs (e.g., by accessing the service software and / or application programs via one or more application programming interfaces (APIs)). The framework layer may be, but is not limited to, a type of free and open source software network application framework that may, for example, use a distributed file system for large-scale data processing (e.g., "big data").

[0348] A cloud-based network environment can provide cloud computing and / or cloud storage that performs any combination of the computing and / or data storage functions described herein (or one or more portions thereof). Any of these various functions can be distributed across multiple locations from a central or core server (e.g., one or more data centers that can be distributed across a state, region, country, global, etc.). If the connection to the user (e.g., client device) is relatively close to an edge server, the core server can assign at least a portion of the functionality to the edge server. A cloud-based network environment can be private (e.g., limited to a single organization), public (e.g., available to many organizations), and / or a combination thereof (e.g., a hybrid cloud environment).

[0349] Client devices may include Figure 5 The client device 500 may be embodied as a personal computer (PC), a laptop computer, a mobile device, a smartphone, a tablet computer, a smartwatch, a wearable computer, a personal digital assistant (PDA), an MP3 player, a virtual reality head-mounted display, a global positioning system (GPS) or device, a video player, a camera, a surveillance device or system, a vehicle, a watercraft, an aircraft, a virtual machine, a drone, a robot, a handheld communication device, a hospital device, a gaming device or system, an entertainment system, an in-vehicle computer system, an embedded system controller, a remote control, an appliance, a consumer electronic device, a workstation, an edge device, any combination of these described devices, or any other suitable device.

[0350] The present disclosure can be described in the general context of machine-usable instructions or computer code executed by a computer or other machine such as a personal digital assistant or other handheld device, including computer-executable instructions such as program modules. Generally, program modules including routines, programs, objects, components, data structures, etc. refer to code that performs a specific task or implements a specific abstract data type. The present disclosure can be practiced in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, more specialized computing devices, etc. The present disclosure can also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked through a communication network.

[0351] As used herein, the description of "and / or" with respect to two or more elements should be interpreted as referring to only one element or combination of elements. For example, "element A, element B and / or element C" may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B and C. In addition, "at least one of element A or element B" may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, "at least one of element A and element B" may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. In addition, the use of the term "based on" should not be interpreted as "based only on" or "based only on". On the contrary, a first element "based on" a second element includes instances in which the first element is based on the second element but may also be based on one or more additional elements.

[0352] The subject matter of the present disclosure is described in detail herein to meet statutory requirements. However, the description itself is not intended to limit the scope of the present disclosure. On the contrary, the inventors have contemplated that the claimed subject matter may also be embodied in other ways to include steps that are different from the steps described herein in conjunction with other current or future technologies, or combinations of similar steps. Moreover, although the terms "step" and / or "block" may be used herein to imply different elements of the method employed, these terms should not be interpreted as implying any particular order among or between the various steps disclosed herein, unless the order of the steps is explicitly described.

Claims

1. A system comprising: A memory for storing frame data corresponding to an image frame received via a plurality of Ethernet packets, the frame data being divided into a plurality of segments ordered according to a sequence order, one or more individual Ethernet packets respectively comprising: a payload, the payload comprising a corresponding segment of the plurality of segments; and A header, the header comprising: a sequence number field indicating a respective sequence number within the sequence corresponding to the respective segment; and a byte offset field indicating a corresponding byte offset to be applied to the segment; hardware for performing one or more packet analysis operations, the one or more packet analysis operations comprising: determining whether a previously transmitted segment is lost based on at least a first sequence number corresponding to the first segment and a second sequence number corresponding to the second segment; and A processing system is configured to perform one or more data processing operations on the plurality of Ethernet packets, the one or more data processing operations comprising causing respective segments corresponding to the plurality of segments to be stored at respective memory locations included in the memory based at least on the respective byte offsets included in the plurality of Ethernet packets.

2. The system of claim 1, wherein the one or more data processing operations further comprise: The frame data is deleted or not stored in response to a determination made using the hardware that one or more Ethernet packets are lost.

3. The system of claim 1, wherein the sequence number field, the byte offset field, and one or more flag fields are added to a standard header, the standard header including fields satisfying the IEEE 1722 Ethernet standard.

4. The system of claim 1 , wherein the one or more data processing operations further comprise: An image signal processor is caused to begin processing frame data stored in the memory and corresponding to one or more of the segments in response to a particular number of image data rows corresponding to the image frame having been received.

5. The system of claim 1, wherein causing segments corresponding to the plurality of segments to be stored at respective memory locations included in the memory is further based at least on applying the respective byte offsets to a base memory address.

6. The system of claim 4, wherein the one or more data processing operations further comprise determining the base memory address.

7. The system of claim 1, wherein the hardware comprises one or more counters, comparators, arithmetic logic units, adders, or logic circuits.

8. The system according to claim 1, wherein the processing system includes one or more central processing units CPU, graphics processing units GPU, data processing units DPU, parallel processing units PPU, microprocessors, field programmable gate arrays FPGA, application-specific integrated circuits ASIC, accelerators or deep learning accelerators DLA.

9. The system of claim 1 , wherein headers of the one or more individual Ethernet packets respectively include one or more flag fields including flag data therein, the flag data indicating whether the respective segments corresponding to the one or more individual Ethernet packets include: Image data; metadata corresponding to the image frame; The beginning segment of the image data; The end segment of the image data; The end row of the image data; image data corresponding to an end of a subframe of the image frame; the start of said metadata; or The end of the metadata.

10. The system of claim 1, wherein the system comprises at least one of: control systems for autonomous or semi-autonomous machines; Perception systems for autonomous or semi-autonomous machines; A system for performing simulation operations; Systems for performing digital twin operations; A system for performing light transport simulations; A system for performing collaborative content creation of 3D assets; Systems for performing deep learning operations; a system for presenting at least one of augmented reality content, virtual reality content, or mixed reality content; A system for hosting one or more real-time streaming applications; Systems implemented using edge devices; Systems implemented using robots; Systems for performing conversational AI operations; A system implementing one or more large language models (LLMs); Systems for generating synthetic data; A system comprising one or more virtual machines VM; A system implemented at least in part in a data center; or A system implemented at least in part using cloud computing resources.

11. A method comprising: receiving frame data corresponding to an image frame to be stored in a memory, the frame data being divided into a plurality of segments sequentially ordered according to a sequence and received via a plurality of Ethernet packets, one or more individual Ethernet packets respectively comprising: a payload, the payload comprising a corresponding segment of the plurality of segments; and A header, the header comprising: a sequence number field indicating a respective sequence number within the sequence corresponding to the respective segment; and a byte offset field indicating a corresponding byte offset to be applied to the segment; performing one or more packet analysis operations, the one or more packet analysis operations comprising: determining whether a previously transmitted segment is lost based on at least a first sequence number corresponding to a first segment and based on at least a second sequence number corresponding to a second segment received prior to the first segment; and One or more data processing operations are performed on the plurality of Ethernet packets, the one or more data processing operations comprising: causing respective segments corresponding to the plurality of segments to be stored at respective memory locations included in the memory based at least on the respective byte offsets included in the plurality of Ethernet packets.

12. The method of claim 9, wherein the one or more data processing operations further comprise: Retransmission of the frame data is requested in response to a determination by hardware that one or more Ethernet packets are lost.

13. The method of claim 9, wherein the one or more data processing operations further comprise: An image signal processor is caused to begin processing frame data stored in the memory and corresponding to one or more of the segments in response to a particular number of image data rows corresponding to the image frame having been received.

14. The method of claim 9, wherein causing segments corresponding to the plurality of segments to be stored at respective memory locations included in the memory is further based at least on applying the respective byte offsets to a base memory address.

15. The method of claim 12, wherein the one or more data processing operations further comprises determining the base memory address.

16. The method of claim 9, wherein the frame data comprises one or more of image data or metadata.

17. The method of claim 9, wherein headers of the one or more individual Ethernet packets respectively include one or more flag fields including flag data indicating whether the respective segments corresponding to the one or more individual Ethernet packets include: Image data; metadata corresponding to the image frame; The beginning segment of the image data; The end segment of the image data; The end row of the image data; image data corresponding to an end of a subframe of the image frame; the start of said metadata; or The end of the metadata.

18. A processor comprising processing circuitry for performing operations comprising: receiving frame data corresponding to an image frame to be stored in a memory, the frame data being divided into a plurality of segments sequentially ordered according to a sequence and received via a plurality of Ethernet packets, one or more individual Ethernet packets respectively comprising: a payload, the payload comprising a corresponding segment of the plurality of segments; and A header, the header comprising: a sequence number field indicating a respective sequence number within the sequence corresponding to the respective segment; and a byte offset field indicating a corresponding byte offset to be applied to the segment; performing one or more packet analysis operations, the one or more packet analysis operations comprising: determining whether a previously transmitted segment is lost based on at least a first sequence number corresponding to a first segment and based on at least a second sequence number corresponding to a second segment received prior to the first segment; and One or more data processing operations are performed on the plurality of Ethernet packets, the one or more data processing operations comprising: causing respective segments corresponding to the plurality of segments to be stored at respective memory locations included in the memory based at least on the respective byte offsets included in the plurality of Ethernet packets.

19. The processor of claim 16, wherein the one or more data processing operations further comprise: Retransmission of the frame data is requested in response to a determination by hardware that one or more Ethernet packets are lost.

20. The processor of claim 16, wherein the one or more data processing operations further comprise: An image signal processor is caused to begin processing frame data stored in the memory and corresponding to one or more of the segments in response to a particular number of image data rows corresponding to the image frame having been received.

Images