Image scanning method and device, electronic equipment and storage medium

Abstract

The invention provides an image scanning method and device, electronic equipment and a storage medium, correction configuration parameters are obtained before scanning processing, the correction configuration parameters are stored in a programmable logic gate array chip, an original manuscript image is scanned through an image sensor, and after image scanning data are obtained, the original manuscript image is scanned through an image sensor; the analog-to-digital conversion chip is used for carrying out analog-to-digital conversion on image scanning data and outputting a digital signal to the programmable logic gate array chip, then the programmable logic gate array chip is used for carrying out correction processing on the digital signal based on correction configuration parameters, and the corrected digital signal is output to the system-on-chip. Before scanning processing, correction configuration parameters are stored in the programmable logic gate array chip, digital signals corresponding to image scanning data are processed through the programmable logic gate array chip, the number of turns of a read-write memory of the system-on-chip is reduced, the data processing load of the system-on-chip is also reduced, and the data processing efficiency is improved. And the external scanning data input rate is improved.

Description

Technical Field

[0001] The present application relates to the field of image processing, and in particular to an image scanning method, device, electronic device and storage medium. Background Art

[0002] At present, the system-on-chip (SoC) in the printer integrates multiple functional modules and is the core component of the printer. For example, the SoC can perform print engine control, scan timing control, image scan data processing, etc. Among them, image scan data processing can eliminate the uneven brightness and color caused by light source, sensor characteristics, etc. The SoC's processing ability for image scan data will directly affect the printer's scanning speed.

[0003] In the existing printer chip architecture, after the contact image sensor (CIS) scans the original image, it outputs an analog electrical signal to the analog front end (AFE), and the analog front end converts the analog electrical signal into a digital signal and transmits it to the system-level chip. The system-level chip then obtains the correction (shading) processing parameters from the double data rate synchronous dynamic random access memory (DDR SDRAM) and performs correction processing on the digital signal based on the correction processing parameters.

[0004] However, as the image scanning speed increases, the speed of correcting and processing digital signals is also getting faster and faster, and the frequency of the system-level chip accessing the double data rate synchronous dynamic random access memory is also increasing. When the system-level chip's access rate to the double data rate synchronous dynamic random access memory or the speed of performing correction processing cannot keep up with the speed at which the analog-to-digital conversion chip outputs the digital signal to the system-level chip, it is easy to cause data processing errors, thereby causing abnormalities in the scanned image. Summary of the invention

[0005] The present application provides an image scanning method, device, electronic device and storage medium, which are used to solve the problem of abnormal scanned images caused by low system-level chip processing performance.

[0006] In a first aspect, the present application provides an image scanning method, which is applied to an image scanning device, wherein the image scanning device includes a system-level chip, an image sensor, an analog-to-digital conversion chip, and a programmable logic gate array chip, and the method includes:

[0007] Before starting the scanning process, the correction configuration parameters are stored in the programmable logic gate array chip in advance through the system-level chip;

[0008] When the scanning process is started, the image sensor is used to scan the original image to obtain image scanning data;

[0009] Performing analog-to-digital conversion on the image scanning data through the analog-to-digital conversion chip, and outputting digital signals to the programmable logic gate array chip;

[0010] Based on the correction configuration parameters, the digital signal is corrected by the programmable logic gate array chip, and the corrected digital signal is saved in the system-level chip.

[0011] In some embodiments, before the step of scanning the original image by the image sensor to obtain image scan data, the step further includes:

[0012] The system-on-chip distributes corresponding control signals to the programmable logic gate array chip, the image sensor and the analog-to-digital conversion chip respectively.

[0013] In some embodiments, the system-on-chip includes a timing control unit, and the step of allocating a corresponding control signal to the image sensor through the system-on-chip includes:

[0014] Allocating a row synchronous excitation signal and a light source control signal to the image sensor through the timing control unit;

[0015] The image sensor receives a first clock signal sent by the programmable logic gate array chip;

[0016] The line synchronous excitation signal, the light source control signal and the first clock signal constitute a control signal of the image sensor.

[0017] In some embodiments, the step of scanning the manuscript image by the image sensor to obtain image scan data includes:

[0018] Based on the light source control signal, emitting a preset light to the document image through the image sensor;

[0019] The image sensor is used to obtain reflected light of the preset light on the original image, and the image scanning data is generated based on the reflected light.

[0020] In some embodiments, the step of performing analog-to-digital conversion on the image scan data by the analog-to-digital conversion chip and outputting a digital signal to the programmable logic gate array chip includes:

[0021] Performing parameter configuration on the analog-to-digital conversion chip through the system-level chip to obtain analog-to-digital conversion configuration data;

[0022] Based on the analog-to-digital conversion configuration data, the image scanning data is analog-to-digital converted by the analog-to-digital conversion chip to obtain the digital signal;

[0023] Based on a control signal assigned to the analog-to-digital conversion chip, the digital signal is input to the programmable logic gate array chip through the analog-to-digital conversion chip.

[0024] In some embodiments, the analog-to-digital conversion configuration data includes a gain value and / or an offset value, and the step of performing analog-to-digital conversion on the image scan data through the analog-to-digital conversion chip based on the analog-to-digital conversion configuration data to obtain the digital signal includes:

[0025] Based on the control signal assigned to the analog-to-digital conversion chip, the image scanning data is subjected to image sampling processing by the analog-to-digital conversion chip to obtain image sampling data;

[0026] Based on the gain value and / or the offset value, the analog-to-digital conversion chip performs compensation calculation on the image sampling data to obtain analog data;

[0027] The analog data is converted by the analog-to-digital conversion chip to obtain the digital signal.

[0028] In some embodiments, the step of performing correction processing on the digital signal through the programmable logic gate array chip based on the correction configuration parameters, and saving the corrected digital signal to the system-level chip includes:

[0029] Based on the row synchronous excitation signal of the programmable logic gate array chip, the digital signal is sampled by the programmable logic gate array chip to obtain digital sampling data;

[0030] Based on the correction configuration parameters, the digital sampled data is corrected by the programmable logic gate array chip to obtain target correction data;

[0031] Based on a third clock signal, the target correction data is saved to the system-level chip, wherein the line synchronization excitation signal and the third clock signal constitute a control signal of the programmable logic gate array chip.

[0032] In some embodiments, the correction configuration parameters include brightness parameters and / or contrast parameters, the target correction data include brightness correction data and / or contrast correction data, and the step of performing correction processing on the digital sampling data through the programmable logic gate array chip based on the correction configuration parameters to obtain the target correction data includes:

[0033] Based on the brightness parameter, the digital sampling data is subjected to brightness correction processing by the programmable logic gate array chip to obtain the brightness correction data;

[0034] Based on the contrast parameter, the digital sampling data is subjected to contrast correction processing by the programmable logic gate array chip to obtain the contrast correction data.

[0035] In some embodiments, before starting the scanning process, the step of storing the correction configuration parameters in the programmable logic gate array chip in advance through the system-level chip includes:

[0036] Obtaining a correction parameter table from a dynamic random access memory through the system-level chip, wherein the correction parameter table includes a plurality of the correction configuration parameters;

[0037] The correction parameter table is transmitted to the static random access memory of the programmable logic gate array chip through the system-level chip.

[0038] In a second aspect, the present application provides an image scanning device, the device comprising:

[0039] System-on-chip, image sensor, analog-to-digital conversion chip and programmable logic gate array chip;

[0040] The image sensor is connected to the analog-to-digital conversion chip, and the analog-to-digital conversion chip is connected to the programmable logic gate array chip;

[0041] The system-level chip is used to transmit the acquired correction configuration parameters to the programmable logic gate array chip in advance before starting the scanning process;

[0042] The image sensor is used to scan the original image when the scanning process is started, and output the image scanning data to the analog-to-digital conversion chip;

[0043] The analog-to-digital conversion chip is used to perform analog-to-digital conversion on the image scanning data when starting the scanning process, and output a digital signal to the programmable logic gate array chip;

[0044] The programmable logic gate array chip is used to perform correction processing on the digital signal based on the correction configuration parameters when starting the scanning process, and output the corrected digital signal to the system-level chip.

[0045] In some embodiments, when there are at least two image sensors, at least one of the image sensors is connected to the programmable logic gate array chip through the analog-to-digital conversion chip.

[0046] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0047] The memory stores computer-executable instructions;

[0048] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementations of the first aspect.

[0049] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementations of the first aspect.

[0050] The image scanning method, device, electronic device and storage medium provided by the present application obtain correction configuration parameters before scanning processing, store the correction configuration parameters in a programmable logic gate array chip, scan the manuscript image through the image sensor to obtain image scanning data, perform analog-to-digital conversion on the image scanning data through the analog-to-digital conversion chip, output the digital signal to the programmable logic gate array chip, and then perform correction processing on the digital signal through the programmable logic gate array chip based on the correction configuration parameters, and output the corrected digital signal to the system-level chip. The scheme of the present application stores the correction configuration parameters in the programmable logic gate array chip before scanning processing, and processes the digital signal corresponding to the image scanning data through the programmable logic gate array chip, which can not only reduce the number of times the system-level chip reads and writes the memory, but also reduce the data processing load of the system-level chip, thereby increasing the external scanning data input rate and adapting to a higher scanning speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 A flowchart of an image scanning method provided in one embodiment of the present application;

[0053] Figure 2A schematic diagram of the structure of an image scanning device provided in one embodiment of the present application;

[0054] Figure 3 A schematic structural diagram of an image scanning device provided in yet another embodiment of the present application;

[0055] Figure 4 A schematic diagram of the structure of another image scanning device provided in one embodiment of the present application;

[0056] Figure 5 A schematic diagram of the structure of another image scanning device provided in an embodiment of the present application;

[0057] Figure 6 A schematic diagram of the structure of another image scanning device provided in one embodiment of the present application;

[0058] Figure 7 A schematic diagram of the hardware structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] In the prior art, when the speed at which the analog-to-digital conversion chip outputs digital signals to the system-level chip does not match the speed at which the system-level chip corrects and processes the digital signals, it is easy to cause errors in the data processing process of the system-level chip, thereby causing abnormalities in the scanned image.

[0061] To this end, the present application proposes an image scanning method, which stores the correction configuration parameters in the memory in a field-programmable gate array (FPGA) chip before scanning, and eliminates the need for the system-level chip to synchronously read the correction configuration parameters and process the image scanning data during the scanning process. The image scanning data is directly converted and processed based on the correction configuration parameters by the programmable gate array chip during the scanning process, thereby reducing the number of times the system-level chip (SoC) reads the memory and reducing the data processing load of the system-level chip, thereby ensuring that the scanned image is normal.

[0062] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0063] Figure 1 The image scanning method provided by an embodiment of the present application is shown, which is applied to an image scanning device, wherein the image scanning device includes a system-level chip, an image sensor, an analog-to-digital conversion chip, and a programmable logic gate array chip, such as Figure 1 As shown, the image scanning method provided in this embodiment includes:

[0064] S101 . Before starting the scanning process, the correction configuration parameters are stored in advance in the programmable logic gate array chip through the system-level chip.

[0065] In this embodiment, the correction configuration parameters may include a brightness parameter and a contrast parameter. The brightness parameter may include a correction offset value (offset), which is used to adjust the baseline brightness level of the image. By increasing the correction offset value, the brightness of the image can be increased, and by decreasing the correction offset value, the brightness of the image can be reduced. The contrast parameter may include a correction gain value (gain), which is used to adjust the contrast of the image. By increasing the correction gain value, the contrast of the image can be increased, and by decreasing the correction gain value, the contrast of the image can be reduced.

[0066] In some embodiments, before the scanning process, the correction parameter table is obtained from the dynamic random access memory by the system-level chip, and the correction parameter table is stored in the static random access memory (SRAM) of the programmable logic gate array chip through the system-level chip in the SPI (Serial Peripheral Interface) communication mode. In this way, there is no need to wait until the scanning process for the system-level chip to read the correction parameter table from the dynamic random access memory, thereby reducing the processing load of the system-level chip. Among them, the correction parameter table includes several correction configuration parameters. The dynamic random access memory can store more data, so that the configuration parameters of different images can be stored through the dynamic random access memory.

[0067] In some embodiments, the dynamic random access memory may include a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0068] In this embodiment, before the scanning process, the correction configuration parameters are stored in the programmable logic gate array chip, so that the programmable logic gate array chip can directly perform correction processing on the digital signal corresponding to the image scanning data based on the stored correction configuration parameters, thereby reducing the need for the system-level chip to pre-read and write the correction configuration parameters in the memory during the scanning process, thereby reducing the data processing load of the system-level chip.

[0069] S102: When starting the scanning process, the original image is scanned by the image sensor to obtain image scanning data.

[0070] In this embodiment, the original image is scanned and processed by an image sensor to obtain image scanning data in the form of analog electrical signals. The image sensor may include a contact image sensor (CIS) and a non-contact image sensor.

[0071] In some embodiments, the manuscript image may include various types of content, including but not limited to photographs, illustrations, text images, images, technical drawings, etc. Photos may be color images or black and white images taken by a camera; illustrations may include cartoons, sketches, illustrations, etc.; text images may include scanned documents, book pages, handwritten notes, etc.; graphics may include icons, logos, posters, etc.; technical drawings may include engineering drawings, architectural drawings, electronic circuit diagrams, etc.

[0072] In some embodiments, the present application takes a contact image sensor as an example, and the contact image sensor may include a light source array and a photoelectric sensor.

[0073] The light source array may include a plurality of light emitting units. For example, the light source array is an LED (Light Emitting Diode) array of three colors (RGB (red, green, blue)), including a plurality of LED light emitting units.

[0074] There may be multiple photoelectric sensors, each of which corresponds to one pixel. One pixel may include multiple LEDs, for example, at least one R-LED, G-LED, and B-LED. Each photoelectric sensor converts the received light into a corresponding analog electrical signal. Since the light reflected from the original image carries the light intensity information of the original image, each analog electrical signal generated by the photoelectric sensor based on the reflected light also represents the light intensity information of each pixel of the original image.

[0075] In some embodiments, the image sensor further includes a first storage module, and after the image scanning data is generated by the photoelectric sensor in the image sensor, the image scanning data in the form of analog electrical signals can be stored by the first storage module in the image sensor. Storing the analog electrical signals during the scanning process can ensure that the analog electrical signals can be processed and transmitted in an orderly manner. Moreover, during the scanning process, the photoelectric sensor continuously converts the optical signal into an analog electrical signal. If it is not stored, direct transmission may cause the analog electrical signal to be lost. The first storage module can be used as a buffer to ensure that all analog electrical signals can be completely captured and processed during the processing and transmission of the analog electrical signals. The analog-to-digital conversion chip needs time to convert the analog electrical signal into a digital signal. By storing the analog electrical signal, it can be ensured that the analog-to-digital conversion chip has enough time to perform accurate conversion, and information will not be lost due to the continuity of the data stream. For example, the first storage module can be a shift register, a cache, or other types of memory.

[0076] S103, performing analog-to-digital conversion on the image scanning data through an analog-to-digital conversion chip, and outputting a digital signal to a programmable logic gate array chip.

[0077] In this embodiment, before step S102, that is, before starting the scanning process, the analog-to-digital conversion chip (Analog Front End, AFE) is configured with parameters through the system-level chip synchronization to obtain analog-to-digital conversion configuration data, and the analog-to-digital conversion configuration data is saved to the analog-to-digital conversion chip, which can shorten the parameter configuration time and speed up the processing speed. Accordingly, during the scanning process, the image scanning data can be converted into digital signals through the analog-to-digital conversion chip based on the analog-to-digital conversion configuration data, thereby improving the accuracy and quality of the image scanning data.

[0078] In some embodiments, the analog-to-digital conversion configuration data includes preset basic configuration data, gain value, and offset value. Considering that the image sensor may have some fixed offsets, the output is not zero even in the absence of an input signal. This offset may come from the sensor itself, power supply noise, etc. In addition, considering that the amplitude of the analog signal output by the image sensor may be small, direct use may cause the analog signal to be not obvious enough, affecting subsequent processing and analysis. Therefore, based on the gain value and offset value, the image scanning data can be compensated and calculated by the analog-to-digital conversion chip to obtain analog data, and then the analog data can be converted by the analog-to-digital conversion chip to obtain a digital signal, so that the image data is more real and accurate.

[0079] S104 , based on the correction configuration parameters, the digital signal is corrected by a programmable logic gate array chip, and the corrected digital signal is saved in a system-level chip.

[0080] In this embodiment, the programmable logic gate array chip performs correction processing on the digital signal based on the correction configuration parameters, thereby reducing the data processing load of the system-level chip, increasing the external scanning data input rate, and adapting to a higher scanning speed. In addition, since the correction configuration parameters are stored in the programmable logic gate array chip before the scanning process, the programmable logic gate array chip can directly process the digital signal based on the stored correction configuration parameters after receiving the digital signal, thereby reducing the number of times the system-level chip reads the memory.

[0081] In some embodiments, after the digital signal corrected by the programmable logic gate array chip is saved in the system-level chip, the digital signal processed by the programmable logic gate array chip can be post-processed by the system-level chip to ensure the image quality and performance of the final output.

[0082] In some embodiments, the post-processing may include denoising, which removes noise generated during the scanning process to improve the clarity of the image.

[0083] Post-processing can include color correction, which adjusts the color balance of the image to ensure color accuracy and consistency. Color correction can include white balance adjustment, color space conversion, and gamma correction.

[0084] Post-processing can include sharpening, which can enhance the edges and details of the image to make the image appear clearer.

[0085] Post-processing may include image compression, which compresses image data into a smaller file size for easier storage and transmission.

[0086] Post-processing can also include format conversion, which converts image data into the desired output format for use in different devices and applications.

[0087] The image scanning method provided in the embodiment of the present application stores the correction configuration parameters in the programmable logic gate array chip before the scanning process, and corrects the image scanning data through the programmable logic gate array chip during the scanning process, thereby reducing the number of times the system-level chip reads the memory and reducing the data processing load of the system-level chip.

[0088] In an optional implementation, before step S102, the method further includes:

[0089] Corresponding control signals are respectively distributed to the programmable logic gate array chip, the image sensor and the analog-to-digital conversion chip through the system-level chip.

[0090] In this embodiment, the control signal allocated by the system-level chip to the image sensor includes a line synchronization trigger signal (Line Synchronization Trigger Signal), a first clock signal and a light source control signal; the control signal allocated by the system-level chip to the analog-to-digital conversion chip includes a second clock signal and a sampling pulse signal; the control signal allocated by the system-level chip to the programmable logic gate array chip includes a third clock signal and a line synchronization trigger signal, wherein the line synchronization trigger signal allocated to the image sensor is the same as the line synchronization trigger signal allocated to the programmable logic gate array chip.

[0091] It can be understood that the second clock signal is N times the first clock signal, and the third clock signal is 2*N times the first clock signal, where N is an integer greater than 0, and the value of N depends on the output data format of the analog-to-digital conversion chip, ensuring that the programmable logic gate array chip accurately samples the data output by the analog-to-digital conversion chip.

[0092] In some embodiments, the system-on-chip may include an image control module, and the image control module may include a timing control unit. Specifically, the timing control unit in the system-on-chip may distribute the control signals to the programmable logic gate array chip, the image sensor, and the analog-to-digital conversion chip.

[0093] In an optional implementation, the step of “distributing corresponding control signals to the programmable logic gate array chip, the image sensor, and the analog-to-digital conversion chip respectively through the system-level chip” includes the following steps:

[0094] S201, allocating a row synchronous excitation signal and a light source control signal to an image sensor through a timing control unit;

[0095] S202: The image sensor receives a first clock signal sent by a programmable logic gate array chip.

[0096] In this embodiment, the programmable logic gate array chip performs frequency division processing on the third clock signal to generate a first clock signal and sends it to the image sensor. The frequency division processing may be to perform 2*N frequency division on the third clock signal through the programmable logic gate array chip. Specifically, N may be an integer greater than 0.

[0097] In this embodiment, a row synchronous excitation signal and a light source control signal are allocated to the image sensor through a timing control unit, and a third clock signal is allocated to the programmable logic gate array chip through the timing control unit. The programmable logic gate array chip generates a first clock signal for the image sensor based on the third clock signal, thereby reducing the data processing load of the system-level chip.

[0098] In some embodiments, the first clock signal may also be directly distributed to the image sensor through a timing control unit in the system-on-chip.

[0099] In an optional implementation, step S102 includes the following steps:

[0100] S1021, based on the light source control signal, emitting a preset light to the original image through the image sensor;

[0101] S1022. Acquire reflected light of the preset light on the original image through an image sensor, and generate image scanning data based on the reflected light.

[0102] In this embodiment, taking a contact image sensor as an example, the contact image sensor may include a light source array and a photoelectric sensor. Based on a light source control signal, the light source array in the contact image sensor emits a preset light to the original image for scanning, thereby realizing black and white, grayscale or color scanning of the original image. The photoelectric sensor in the contact image sensor obtains the reflected light of the preset light on the original image, and generates image scanning data based on the reflected light.

[0103] And considering that the image scanning data captured by the contact image sensor is usually generated in row or column order, the image scanning data can be transmitted to the analog-to-digital conversion chip in a specific order through shift transmission to ensure the synchronization of data transmission and prevent data loss or errors during transmission.

[0104] In practical applications, after scanning a row of pixels in the original image is completed, the light source array can be turned off, and the next row of pixels can be scanned after the next row synchronous excitation signal arrives.

[0105] In some embodiments, the light reflected from the original image can be converted into an analog electrical signal (i.e., the image scanning data) by the photoelectric sensor in the image sensor. After the next line synchronous excitation signal TR arrives, the analog electrical signal is output to the analog-to-digital conversion chip in sequence through the shift register according to the first clock signal.

[0106] In an optional implementation, step S103 includes the following steps:

[0107] S1031, configuring parameters of the analog-to-digital conversion chip through the system-level chip to obtain analog-to-digital conversion configuration data;

[0108] S1032, based on the analog-to-digital conversion configuration data, performing analog-to-digital conversion on the image scanning data through an analog-to-digital conversion chip to obtain a digital signal;

[0109] S1033. Based on the control signal assigned to the analog-to-digital conversion chip, the digital signal is input into the programmable logic gate array chip through the analog-to-digital conversion chip.

[0110] In this embodiment, the system-level chip obtains the basic configuration data, gain value, and offset value (i.e., the above-mentioned analog-to-digital conversion configuration data) in the analog-to-digital conversion chip before starting the scanning process, and then the system-level chip transmits the basic configuration data, gain value, and offset value to the analog-to-digital conversion chip through the SPI communication interface circuit and saves them in the corresponding registers inside the analog-to-digital conversion chip.

[0111] In some embodiments, the calculated analog data can be converted into a 16-bit digital electrical signal (i.e., the above-mentioned digital signal) through an analog-to-digital conversion chip, and the above-mentioned digital electrical signal can be output to the programmable logic gate array chip in sequence according to the order of the second clock signal provided by the system-level chip.

[0112] In this embodiment, based on the analog-to-digital conversion configuration data, the image scan data can be converted into digital signals through the analog-to-digital conversion chip to improve the accuracy and quality of the image data. Subsequently, based on the second clock signal, the digital signals can be sequentially input into the programmable logic gate array chip through the analog-to-digital conversion chip to facilitate subsequent processing of the digital signals by the programmable logic gate array chip.

[0113] In an optional implementation, the analog-to-digital conversion configuration data includes a gain value and / or an offset value, and the step of “converting the image scan data into analog-to-digital data by an analog-to-digital conversion chip based on the analog-to-digital conversion configuration data to obtain a digital signal” includes the following steps:

[0114] Based on the control signal assigned to the analog-to-digital conversion chip, the image scanning data is subjected to image sampling processing by the analog-to-digital conversion chip to obtain image sampling data;

[0115] Based on the gain value and / or the offset value, the image sampling data is compensated and calculated by an analog-to-digital conversion chip to obtain analog data;

[0116] The analog data is converted and processed by the analog-to-digital conversion chip to obtain a digital signal.

[0117] In this embodiment, the image scanning data can be sampled and processed by the analog-to-digital conversion chip based on the second clock signal and the sampling pulse signal. Specifically, the second clock signal is used to synchronize the entire analog-to-digital conversion process to ensure that data sampling and processing are performed within a fixed time interval, and the sampling pulse signal is used to instruct the analog-to-digital conversion chip to sample the received image scanning data at a fixed time, and the above-mentioned image sampling data can be an analog electrical signal.

[0118] In some embodiments, the above-mentioned compensation calculation can be performed by subtracting a preset offset value from the image scanning data through an analog-to-digital conversion chip to eliminate the fixed offset and obtain a compensated analog signal (i.e., the above-mentioned analog data). The image scanning data can also be multiplied by a preset gain value through the analog-to-digital conversion chip to amplify the amplitude of the analog signal and obtain a compensated analog signal (i.e., the above-mentioned analog data). The compensated analog signal can be more obvious and easier to process in subsequent processing, ensuring that the analog signal has sufficient dynamic range during the analog-to-digital conversion process and improving the availability and processing quality of the analog signal.

[0119] In this embodiment, based on the control signal corresponding to the analog-to-digital conversion chip, the image scanning data is sampled and processed by the analog-to-digital conversion chip. After the image sampling data is obtained, the image scanning data can be compensated and calculated based on the gain value and / or offset value by the analog-to-digital conversion chip to obtain analog data. Then, the analog data is converted and processed by the analog-to-digital conversion chip to obtain a digital signal, thereby making the image data more realistic and accurate.

[0120] In an optional implementation, step S104 includes the following steps:

[0121] S1041, based on the line synchronous excitation signal of the programmable logic gate array chip, sampling the digital signal through the programmable logic gate array chip to obtain digital sampling data;

[0122] S1042, based on the correction configuration parameters, the digital sampling data is corrected by a programmable logic gate array chip to obtain target correction data;

[0123] S1043. Based on the third clock signal, save the target correction data to the system-on-chip.

[0124] In this embodiment, the clock pulse of the third clock signal may be a rising edge or a falling edge of the third clock signal (for example, the rising edge or the falling edge may be configured by the system-level chip).

[0125] In some embodiments, based on the row synchronous excitation signal of the programmable logic gate array chip, a 16-bit digital signal can be sent to the analog-to-digital conversion chip through the programmable logic gate array chip according to the rising edge or falling edge of the above-mentioned third clock signal, and the analog-to-digital conversion chip can be sampled in sequence according to the input order, and the sampled 16-bit digital signal (i.e., the above-mentioned digital sampling data) and the correction configuration parameters are calculated and converted, and the converted 16-bit digital signal (i.e., the target correction data) is output to the system-level chip in sequence according to the rising edge or falling edge of the third clock signal.

[0126] In some embodiments, the first clock signal, the second clock signal, and the third clock signal may use the same clock source to ensure the accuracy of sampling of image scanning data and transmission of processed data.

[0127] In this embodiment, at the clock pulse of the third clock signal, based on the row synchronous excitation signal of the programmable logic gate array chip, the digital signal is sampled by the programmable logic gate array chip to obtain digital sampled data, and then based on the correction configuration parameters, the digital sampled data is processed by the programmable logic gate array chip to obtain target correction data, and then based on the clock pulse of the third clock, the target correction data is sequentially saved to the system-level chip, thereby reducing the data processing load of the system-level chip.

[0128] In an optional implementation, the step of “based on the correction configuration parameters, performing correction processing on the digital sampled data through a programmable logic gate array chip to obtain target correction data” includes at least one of the following steps:

[0129] Based on the brightness parameter, the digital sampling data is subjected to brightness correction processing by a programmable logic gate array chip to obtain brightness correction data;

[0130] Based on the contrast parameter, the digital sampling data is subjected to contrast correction processing by a programmable logic gate array chip to obtain contrast correction data.

[0131] In this embodiment, the target correction data includes brightness correction data and contrast correction data. The brightness correction processing can be to reduce the brightness of the image by subtracting a preset correction offset value from the digital sampled data through the programmable logic gate array chip, or to increase the brightness of the image by adding a preset correction offset value to the digital sampled data through the programmable logic gate array chip, so as to achieve the effect of adjusting the baseline brightness level of the image.

[0132] In this embodiment, the above-mentioned contrast correction processing can multiply the digital sampling data by a preset correction gain value through a programmable logic gate array chip. When the correction gain value is greater than 1, the contrast of the image can be improved. When the correction gain value is less than 1, the contrast of the image can be reduced, thereby achieving the effect of contrast correction of the digital signal through the programmable logic gate array chip.

[0133] In this embodiment, based on the brightness parameter, the digital sampled data is subjected to brightness correction processing by a programmable logic gate array chip, and based on the contrast parameter, the digital sampled data is subjected to contrast correction processing by a programmable logic gate array chip to improve image quality.

[0134] Figure 2 An image scanning device provided by an embodiment of the present application is shown. Figure 2As shown, the image scanning device provided in this embodiment includes:

[0135] The system-on-chip 10, the image sensor 40, the analog-to-digital conversion chip 50 and the programmable logic gate array chip 20, the system-on-chip 10 includes an image control module 101 and a streaming front-end module (Steaming Front End, SFE) 102;

[0136] The image control module 101 is connected to the stream front-end module 102 and the programmable logic gate array chip 20, the image sensor 40 is connected to the analog-to-digital conversion chip 50, and the analog-to-digital conversion chip 50 is connected to the programmable logic gate array chip 20;

[0137] The stream front-end module 102 is used to obtain the calibration configuration parameters before starting the scanning process, and transmit the calibration configuration parameters to the image control module 101;

[0138] The image control module 101 is used to store the correction configuration parameters into the programmable logic gate array chip 20;

[0139] The image sensor 40 is used to scan the original image when the scanning process is started, and output the image scanning data to the analog-to-digital conversion chip 50;

[0140] The analog-to-digital conversion chip 50 is used to perform analog-to-digital conversion on the image scanning data when the scanning process is started, and output the digital signal to the programmable logic gate array chip 20;

[0141] The programmable logic gate array chip 20 is used to perform correction processing on the digital signal based on the correction configuration parameters when starting the scanning process, and output the corrected digital signal to the image control module 101 .

[0142] In the embodiment of the present application, before the scanning process, the correction configuration parameters are obtained through the stream front-end module 102 in the system-level chip 10 and transmitted to the image control module 101. The image control module 101 stores the correction configuration parameters in the programmable logic gate array chip 20, reducing the number of times the system-level chip 10 reads the memory, and the digital signal corresponding to the image scanning data is processed by the programmable logic gate array chip 20 with high-speed signal processing capability, reducing the data processing load of the system-level chip 10, and avoiding the image abnormality problem caused by insufficient processing performance of the system-level chip 10. In addition, by processing the digital signal output by the analog-to-digital conversion chip 50 through the programmable logic gate array chip 20, the input rate of the external scanning data can also be increased to adapt to a higher scanning speed.

[0143] It should be noted that processing the image scan data can make the printed image high-quality, accurate in color, clear in detail, and restore the true information of the original image as much as possible.

[0144] In some embodiments, the image scanning device further includes a dynamic random access memory 30, which interacts with the stream front-end module in the system-level chip 10 to calibrate configuration parameters and communicates in the form of a correction parameter table. Before starting the scanning process, the system-level chip 10 obtains the correction parameter table from the dynamic random access memory 30, and stores the correction parameter table in the static random access memory (SRAM) of the programmable logic gate array chip 20 in an SPI (Serial Peripheral Interface) communication mode.

[0145] In some embodiments, the analog-to-digital conversion chip 50 includes a first communication module and an analog-to-digital conversion module, and the analog-to-digital conversion configuration data configured by the system-level chip 10 can be received through the first communication module, and then the image scanning data can be subjected to image sampling processing through the analog-to-digital conversion module based on the control signal corresponding to the analog-to-digital conversion chip 50 assigned by the system-level chip to obtain image sampling data, and then the image sampling data is subjected to compensation calculation and analog-to-digital conversion processing after the analog-to-digital conversion module is subjected to gain value and / or offset value in the analog-to-digital conversion configuration data to obtain a digital signal. Then, based on the second clock signal in the control signal corresponding to the analog-to-digital conversion chip 50, the digital signal is sequentially output to the programmable logic gate array chip 20 through the analog-to-digital conversion module.

[0146] For example, based on the second clock signal and sampling pulse signal in the control signal corresponding to the analog-to-digital conversion chip 50, the image scanning data can be sampled and processed by the analog-to-digital conversion module. The second clock signal is used to synchronize the entire analog-to-digital conversion process to ensure that data sampling and processing are performed within a fixed time interval. The sampling pulse signal is used to instruct the analog-to-digital conversion module to sample the received image scanning data at a fixed time.

[0147] In some embodiments, the programmable logic gate array chip 20 includes a second communication module, a second storage module and a data processing module. The correction configuration parameters sent by the system-level chip 10 are received through the second communication module in the programmable logic gate array chip 20 and stored in the second storage module; the third clock signal in the control signal assigned by the system-level chip 10 to the programmable logic gate array chip 20 is used to correct the digital signal based on the correction configuration parameters through the data processing module to obtain the target correction data, and the target correction data is stored in the second storage module. Then, based on the third clock signal, the target correction number is sequentially saved to the system-level chip 10 through the second storage module to ensure the accuracy and quality of the digital signal.

[0148] In some embodiments, Figure 3 As shown, Figure 3 and Figure 2 The similarities are as follows: the image scanning device comprises an image sensor 40 and a programmable logic gate array chip 20, wherein the image sensor 40 is connected to the programmable logic gate array chip 20 via an analog-to-digital conversion chip.

[0149] Specifically, Figure 3 In the embodiment, the image control module 101 sends a line synchronous excitation signal and a light source control signal to the image sensor 40. The image control module 101 is also used to send a control signal of the analog-to-digital conversion chip to the analog-to-digital conversion chip 50. The image control module 101 is also used to send a control signal of the programmable logic gate array chip to the programmable logic gate array chip 20. The programmable logic gate array chip 20 sends a first clock signal to the image sensor 40 based on the control signal of the programmable logic gate array chip, and the stream front-end module 102 receives the correction configuration parameters of the dynamic random access memory 30.

[0150] Accordingly, the image sensor 40 can scan the original image based on the line synchronous excitation signal, the light source control signal and the first clock signal, and output the scanned image scan data to the analog-to-digital conversion chip 50 based on the first clock signal; the analog-to-digital conversion chip 50 converts the image scan data into a digital signal based on the control signal of the analog-to-digital conversion chip, and sends the digital signal to the programmable logic gate array chip 20 based on the control signal of the analog-to-digital conversion chip; the programmable logic gate array 20 processes the digital signal based on the control signal of the programmable logic gate array chip, and then the programmable logic gate array 20 sends the corrected digital signal to the image control module 101 based on the control signal of the programmable logic gate array chip; the image control module 101 sends the received digital signal to the streaming front-end module 102, so that the digital signal can be further processed by the streaming front-end module 102.

[0151] Figure 3 and Figure 2 The difference is, Figure 3 The image scanning device further includes a motor driving circuit 71 . The motor driving circuit 71 can enable the image sensor 40 to scan the original image according to the control signal sent by the system-level chip 10 , that is, the image sensor 40 starts to work.

[0152] In some embodiments, the image scanning device further includes a USB (Universal Serial Bus) interface module 72 and a network interface module 73. The interface module 72 is responsible for data exchange between peripherals such as computers and the system-on-chip 10. The network interface may be, for example, an RJ45 interface.

[0153] In some embodiments, the image scanning device further includes a USB host interface module 74 for connecting to peripherals such as a WiFi module and a USB flash drive to perform data exchange with the system-level chip 10 .

[0154] In some embodiments, the image scanning device further includes a flash memory module 60, and the flash memory module 60 mainly stores firmware and the like.

[0155] In some embodiments, the number of image sensors may be several, and multiple image sensors may scan different image areas at the same time to achieve parallel processing to increase the scanning speed. Accordingly, the number of analog-to-digital conversion chips may be several, each analog-to-digital conversion chip is connected to an image sensor, and each analog-to-digital conversion chip may convert the analog electrical signal output by the corresponding image sensor into a digital signal.

[0156] In some embodiments, the image scanning device includes a programmable logic gate array chip, Figure 3 The example shows that an image scanning device includes an image sensor 40 and a programmable logic gate array chip 20, wherein the image sensor 40 is connected to the programmable logic gate array chip 20 via an analog-to-digital conversion chip. The programmable logic gate array chip is connected to an analog-to-digital conversion chip among multiple analog-to-digital conversion chips, and receives the digital signal output by the analog-to-digital conversion chip, and the programmable logic gate array chip can process the received digital signal. Accordingly, the system-level chip may include multiple image control modules and multiple streaming front-end modules, each image control module is connected to a programmable logic gate array chip or an analog-to-digital conversion chip, and each streaming front-end module is connected to an image control module. If the image control module is connected to the programmable logic gate array chip, the corrected digital signal sent by the programmable logic gate array chip can be sent to the streaming front-end module, and the streaming front-end module can further process the digital signal when it receives the digital signal. If the image control module is connected to the analog-to-digital conversion chip, the image data after analog-to-digital conversion can be sent to the streaming front-end module, and the streaming front-end module can process the digital signal output by the analog-to-digital conversion chip when it receives it. Each streaming front-end module can send and store the processed digital signal to the memory.

[0157] For example, Figure 4 As shown, Figure 4 and Figure 3 The difference is that Figure 4 The exemplary image scanning device includes two image sensors and a programmable logic gate array chip, and only one image sensor is connected to the programmable logic gate array chip via an analog-to-digital conversion chip, and the other image sensor is connected to the system-level chip via a mode conversion chip.

[0158] Specifically, Figure 4As shown, the image scanning device includes an image sensor 1, an image sensor 2, an analog-to-digital conversion chip 1, an analog-to-digital conversion chip 2, a programmable logic gate array chip 1 and a system-level chip 10, the programmable logic gate array chip 1 includes a data processing module 1, the system-level chip includes an image control module 1, an image control module 2, a streaming front-end module 1 and a streaming front-end module 2, and the streaming front-end module 2 includes a data processing module 2.

[0159] The image control module 1 sends a control signal of the image sensor 1 to the image sensor 1, wherein the control signal of the image sensor 1 includes a line synchronous excitation signal 1 and a light source control signal 1. The image control module 1 is also used to send a control signal of the analog-to-digital conversion chip 1 to the analog-to-digital conversion chip 1, wherein the control signal of the analog-to-digital conversion chip 1 includes a second clock signal 1 and a sampling pulse signal 1. The image control module 1 is also used to send a control signal of the programmable logic gate array chip to the programmable logic gate array chip 1, wherein the control signal of the programmable logic gate array chip includes a third clock signal 1 and a line synchronous excitation signal 1. The programmable logic gate array chip 1 sends a first clock signal 1 to the image sensor 1 based on the third clock signal 1.

[0160] The image control module 2 sends a control signal of the image sensor 2 to the image sensor 2, wherein the control signal of the image sensor 2 includes a first clock signal 2, a line synchronous excitation signal 2, and a light source control signal 2. The image control module 2 is also used to send a control signal of the analog-to-digital conversion chip 2 to the analog-to-digital conversion chip 2, wherein the control signal of the analog-to-digital conversion chip 2 may include a second clock signal 2 and a sampling pulse signal 2.

[0161] Correspondingly, the image sensor 1 can scan the original image based on the control signal of the image sensor 1 and the first clock signal 1, and output the scanned analog electrical signal 1 to the analog-to-digital conversion chip 1 in sequence based on the first clock signal 1; the analog-to-digital conversion chip 1 converts the analog electrical signal 1 into a digital signal 1 based on the control signal of the analog-to-digital conversion chip 1, and sends the digital signal 1 to the programmable logic gate array chip 1 based on the second clock signal 1; the programmable logic gate array 1 processes the digital signal 1 through the data processing module 1 in the programmable logic gate array 1 based on the control signal 1, and then sends the corrected digital signal to the image control module 1 based on the third clock signal 1; the image control module 1 sends the received digital signal to the streaming front-end module 1, so that the digital signal can be further processed through the streaming front-end module 1.

[0162] The image sensor 2 can scan the original image based on the control signal of the image sensor 2 and the first clock signal 2, and output the scanned analog electrical signal 2 to the analog-to-digital conversion chip 2 in sequence based on the first clock signal 2; the analog-to-digital conversion chip 2 converts the analog electrical signal 2 into a digital signal 2 based on the control signal of the analog-to-digital conversion chip 2, and sends the digital signal 2 to the image control module 2 based on the second clock signal 2; the image control module 2 sends the received digital signal 2 to the streaming front-end module 2, so as to perform correction processing and other further processing through the data processing module 2 in the streaming front-end module 2. In some embodiments, the number of programmable logic gate array chips is multiple, each programmable logic gate array chip is connected to an analog-to-digital conversion chip, and each programmable logic gate array chip can perform correction processing on the received digital signal after receiving the digital signal input by the analog-to-digital conversion chip. Accordingly, the system-level chip can include multiple image control modules and multiple streaming front-end modules, each image control module can be connected to a programmable logic gate array chip, and each streaming front-end module can be connected to an image control module. Each image control module can send the corrected digital signal sent by the corresponding programmable logic gate array chip to the corresponding stream front-end module, and each stream front-end module can perform further processing when receiving the processed digital signal.

[0163] For example, Figure 5 As shown, Figure 5 and Figure 3 The difference is that Figure 5 The image scanning device comprises two image sensors and two programmable logic gate array chips, and each image sensor is connected to a programmable logic gate array chip through an analog-to-digital conversion chip.

[0164] Specifically, Figure 5 In the embodiment, the image scanning device includes an image sensor 1, an image sensor 2, an analog-to-digital conversion chip 1, an analog-to-digital conversion chip 2, a programmable logic gate array chip 1, a programmable logic gate array chip 2 and a system-level chip 10. The system-level chip includes an image control module 1, an image control module 2, a streaming front-end module 1 and a streaming front-end module 2. The programmable logic gate array chip 1 includes a data processing module 1, and the programmable logic gate array chip 2 includes a data processing module 2. The image control module 1 is electrically connected to the streaming front-end module 1, and the image control module 2 is electrically connected to the streaming front-end module 2.

[0165] The image control module 1 sends a control signal of the image sensor 1 to the image sensor 1, wherein the control signal of the image sensor 1 includes a line synchronous excitation signal 1 and a light source control signal 1. The image control module 1 is also used to send a control signal of the analog-to-digital conversion chip 1 to the analog-to-digital conversion chip 1, wherein the control signal of the analog-to-digital conversion chip 1 includes a second clock signal 1 and a sampling pulse signal 1. The image control module 1 is also used to send a control signal of the programmable logic gate array chip 1 to the programmable logic gate array chip 1, wherein the control signal of the programmable logic gate array chip 1 includes a line synchronous excitation signal 1 and a third clock signal 1, and the programmable logic gate array chip 1 sends a first clock signal 1 to the image sensor 1 based on the third clock signal 1.

[0166] The image control module 2 sends a control signal of the image sensor 2 to the image sensor 2, and the control signal of the image sensor 2 includes a line synchronous excitation signal 2 and a light source control signal 2. The image control module 2 is also used to send a control signal of the analog-to-digital conversion chip 2 to the analog-to-digital conversion chip 2, and the control signal of the analog-to-digital conversion chip 2 includes a second clock signal 2 and a sampling pulse signal 2. The image control module 2 is also used to send a control signal of the programmable logic gate array chip 2 to the programmable logic gate array chip 2, and the control signal of the programmable logic gate array chip 2 includes a third clock signal 2 and a line synchronous excitation signal 2. The programmable logic gate array chip 2 sends a first clock signal 2 to the image sensor 2 based on the third clock signal 2.

[0167] Correspondingly, the image sensor 1 can scan the original image based on the control signal of the image sensor 1 and the first clock signal 1, and output the scanned analog electrical signal 1 to the analog-to-digital conversion chip 1 in sequence based on the first clock signal 1; the analog-to-digital conversion chip 1 converts the analog electrical signal 1 into a digital signal 1 based on the control signal of the analog-to-digital conversion chip 1, and sends the digital signal 1 to the programmable logic gate array chip 1 based on the second clock signal 1; the programmable logic gate array 1 corrects the digital signal 1 through the data processing module 1 in the programmable logic gate array chip 1 based on the control signal of the programmable logic gate array chip 1, and then sends the corrected digital signal to the image control module 1 based on the third clock signal 1; the image control module 1 sends the received digital signal to the streaming front-end module 1, so that the digital signal can be further processed through the streaming front-end module 1.

[0168] The image sensor 2 can scan the original image based on the control signal of the image sensor 2 and the first clock signal 2, and output the scanned analog electrical signal 2 to the analog-to-digital conversion chip 2 in sequence based on the first clock signal 2; the analog-to-digital conversion chip 2 converts the analog electrical signal 2 into a digital signal 2 based on the control signal of the analog-to-digital conversion chip 2, and sends the digital signal 2 to the programmable logic gate array chip 2 based on the second clock signal 2; the programmable logic gate array 2 corrects the digital signal 2 through the data processing module 2 in the programmable logic gate array chip 2 based on the control signal of the programmable logic gate array chip 2, and then sends the corrected digital signal to the image control module 2 based on the third clock signal 2; the image control module 2 sends the received digital signal to the streaming front-end module 2, so that the digital signal can be further processed through the streaming front-end module 2.

[0169] In some embodiments, the image scanning device includes a programmable logic gate array chip, which includes multiple data processing modules, each data processing module is connected to an analog-to-digital conversion chip, and each data processing module can process the received data after receiving the data input by the corresponding analog-to-digital conversion chip. Correspondingly, the system-level chip can include multiple image control modules and multiple streaming front-end modules, each image control module can be connected to a data processing module, and each streaming front-end module can be connected to an image control module. Then each image control module can send the processed data sent by the corresponding data processing module to the corresponding streaming front-end module, and each streaming front-end module can perform further processing when receiving the processed data.

[0170] For example, Figure 6 As shown, Figure 6 and Figure 5 The difference is that Figure 6 The image scanning device includes two image sensors and a programmable logic gate array chip, and the two image sensors are connected to the same programmable logic gate array chip through analog-to-digital conversion chips.

[0171] Specifically, Figure 6 In the present invention, the image scanning device includes an image sensor 1, an image sensor 2, an analog-to-digital conversion chip 1, an analog-to-digital conversion chip 2, a programmable logic gate array chip, and a system-level chip 10. The programmable logic gate array chip includes a data processing module 1 and a data processing module 2. The system-level chip includes an image control module 1, an image control module 2, a streaming front-end module 1 and a streaming front-end module 2.

[0172] The image control module 1 sends a control signal of the image sensor 1 to the image sensor 1, and the control signal of the image sensor 1 includes a line synchronous excitation signal 1 and a light source control signal 1. The image control module 1 is also used to send a control signal of the analog-to-digital conversion chip 1 to the analog-to-digital conversion chip 1, and the control signal of the analog-to-digital conversion chip 1 includes a second clock signal 1 and a sampling pulse signal 1. The image control module 1 is also used to send a control signal to the data processing module 1 in the programmable logic gate array chip 1, and the control signal of the programmable logic gate array chip includes a third clock signal 1 and a line synchronous excitation signal 1. The data processing module 1 sends a first clock signal 1 to the image sensor 1 based on the third clock signal 1.

[0173] The image control module 2 sends a control signal of the image sensor 2 to the image sensor 2, and the control signal of the image sensor 2 includes a line synchronous excitation signal 2 and a light source control signal 2. The image control module 2 is also used to send a control signal of the second analog-to-digital conversion chip to the analog-to-digital conversion chip 2, and the control signal of the second analog-to-digital conversion chip includes a second clock signal 2 and a sampling pulse signal 2. The image control module 2 is also used to send a control signal of the programmable logic gate array chip to the data processing module 2, and the control signal of the programmable logic gate array chip includes a third clock signal 2 and a line synchronous excitation signal 2. The data processing module 2 sends a first clock signal 1 to the image sensor 2 based on the third clock signal 2.

[0174] Correspondingly, the image sensor 1 can scan the original image based on the control signal of the image sensor 1 and the first clock signal 1, and output the scanned analog electrical signal 1 to the analog-to-digital conversion chip 1 in sequence based on the first clock signal 1; the analog-to-digital conversion chip 1 converts the analog electrical signal 1 into a digital signal 1 based on the control signal of the analog-to-digital conversion chip 1, and sends the digital signal 1 to the data processing module 1 based on the second clock signal 1; the data processing module 1 corrects the digital signal 1 based on the control signal of the programmable logic gate array chip, and then sends the corrected digital signal to the image control module 1 based on the third clock signal 1; the image control module 1 sends the received digital signal to the streaming front-end module 1, so that the digital signal can be further processed through the streaming front-end module 1.

[0175] The image sensor 2 can scan the original image based on the control signal of the image sensor 2 and the first clock signal 2, and output the scanned analog electrical signal 2 to the analog-to-digital conversion chip 2 in sequence based on the first clock signal 2; the analog-to-digital conversion chip 2 converts the analog electrical signal 1 into a digital signal 2 based on the control signal of the analog-to-digital conversion chip 2, and sends the digital signal 2 to the data processing module 2 based on the second clock signal 2; the data processing module 2 processes the digital signal 2 based on the control signal of the programmable logic gate array chip, and then sends the corrected digital signal to the image control module 2 based on the third clock signal 2; the image control module 2 sends the received digital signal to the streaming front-end module 2, so that the digital signal can be further processed through the streaming front-end module 2.

[0176] For example, further processing of the digital signal by the streaming front-end module may include converting the digital signal into a format required for printing, filtering, etc.

[0177] The image scanning device provided by the present application processes the digital signal output by the analog-to-digital conversion chip by a programmable logic gate array with high-speed processing capability. Before starting the scanning process, the correction configuration parameters are stored in the programmable logic gate array chip, and the digital signal corresponding to the image scanning data is processed by the programmable logic gate array chip, which can not only reduce the number of times the system-level chip reads and writes the memory, but also reduce the data processing load of the system-level chip, thereby increasing the external scanning data input rate, adapting to a higher scanning speed, and avoiding scanning abnormalities caused by insufficient system-level chip processing performance.

[0178] Figure 7 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 7 As shown, the electronic device 90 provided in this embodiment includes: at least one processor 901 and a memory 902. Optionally, the device 90 further includes a communication component 903. The processor 901, the memory 902 and the communication component 903 are connected via a bus 904.

[0179] In a specific implementation process, at least one processor 901 executes the computer execution instructions stored in the memory 902, so that at least one processor 901 executes the above method.

[0180] The specific implementation process of the processor 901 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0181] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0182] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0183] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0184] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0185] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0186] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0187] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0188] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0189] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0190] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0191] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0192] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0193] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An image scanning method, characterized in that: Applied to an image scanning device, the image scanning device includes a system-level chip, an image sensor, an analog-to-digital conversion chip and a programmable logic gate array chip, and the method includes: Before starting the scanning process, the correction configuration parameters are stored in the programmable logic gate array chip in advance through the system-level chip; When the scanning process is started, the image of the original document is scanned by the image sensor to obtain image scanning data; the image scanning data is converted into analog-to-digital by the analog-to-digital conversion chip, and a digital signal is output to the programmable logic gate array chip; Based on the correction configuration parameters, the digital signal is corrected by the programmable logic gate array chip, and the corrected digital signal is saved in the system-level chip.

2. The image scanning method according to claim 1, characterized in that: Before the step of scanning the manuscript image by the image sensor to obtain image scan data, the method further includes: The system-on-chip distributes corresponding control signals to the programmable logic gate array chip, the image sensor and the analog-to-digital conversion chip respectively.

3. The image scanning method according to claim 2, characterized in that: The system-level chip includes a timing control unit, and the step of allocating a corresponding control signal to the image sensor through the system-level chip includes: Allocating a row synchronous excitation signal and a light source control signal to the image sensor through the timing control unit; The image sensor receives a first clock signal sent by the programmable logic gate array chip; The line synchronous excitation signal, the light source control signal and the first clock signal constitute a control signal of the image sensor.

4. The method according to claim 3, characterized in that The step of scanning the manuscript image by the image sensor to obtain image scan data comprises: Based on the light source control signal, emitting a preset light to the document image through the image sensor; The image sensor is used to obtain reflected light of the preset light on the original image, and the image scanning data is generated based on the reflected light.

5. The method according to claim 2, characterized in that: The step of performing analog-to-digital conversion on the image scan data by the analog-to-digital conversion chip and outputting a digital signal to the programmable logic gate array chip comprises: Performing parameter configuration on the analog-to-digital conversion chip through the system-level chip to obtain analog-to-digital conversion configuration data; Based on the analog-to-digital conversion configuration data, the image scanning data is analog-to-digital converted by the analog-to-digital conversion chip to obtain the digital signal; Based on a control signal assigned to the analog-to-digital conversion chip, the digital signal is input to the programmable logic gate array chip through the analog-to-digital conversion chip.

6. The method according to claim 5, characterized in that The analog-to-digital conversion configuration data includes a gain value and / or an offset value. The step of performing analog-to-digital conversion on the image scan data through the analog-to-digital conversion chip based on the analog-to-digital conversion configuration data to obtain the digital signal includes: Based on the control signal assigned to the analog-to-digital conversion chip, the image scanning data is subjected to image sampling processing by the analog-to-digital conversion chip to obtain image sampling data; Based on the gain value and / or the offset value, the analog-to-digital conversion chip performs compensation calculation on the image sampling data to obtain analog data; The analog data is converted by the analog-to-digital conversion chip to obtain the digital signal.

7. The method according to claim 2, characterized in that The step of performing correction processing on the digital signal through the programmable logic gate array chip based on the correction configuration parameters, and saving the corrected digital signal to the system-level chip includes: Based on the row synchronous excitation signal of the programmable logic gate array chip, the digital signal is sampled by the programmable logic gate array chip to obtain digital sampling data; Based on the correction configuration parameters, the digital sampled data is corrected by the programmable logic gate array chip to obtain target correction data; Based on a third clock signal, the target correction data is saved to the system-level chip, wherein the line synchronization excitation signal and the third clock signal constitute a control signal of the programmable logic gate array chip.

8. The method according to claim 7, characterized in that The correction configuration parameters include brightness parameters and / or contrast parameters, the target correction data include brightness correction data and / or contrast correction data, and the step of performing correction processing on the digital sampling data through the programmable logic gate array chip based on the correction configuration parameters to obtain the target correction data includes: Based on the brightness parameter, the digital sampling data is subjected to brightness correction processing by the programmable logic gate array chip to obtain the brightness correction data; Based on the contrast parameter, the digital sampling data is subjected to contrast correction processing by the programmable logic gate array chip to obtain the contrast correction data.

9. The method according to any one of claims 1 to 8, characterized in that: The step of storing the correction configuration parameters in the programmable logic gate array chip in advance through the system-level chip before starting the scanning process includes: Obtaining a correction parameter table from a dynamic random access memory through the system-level chip, wherein the correction parameter table includes a plurality of the correction configuration parameters; The correction parameter table is transmitted to the static random access memory of the programmable logic gate array chip through the system-level chip.

10. An image scanning device, characterized in that: The device comprises: System-on-chip, image sensor, analog-to-digital conversion chip and programmable logic gate array chip; The image sensor is connected to the analog-to-digital conversion chip, and the analog-to-digital conversion chip is connected to the programmable logic gate array chip; The system-level chip is used to transmit the acquired correction configuration parameters to the programmable logic gate array chip in advance before starting the scanning process; and is used to receive the corrected digital signal sent by the programmable logic gate array chip when starting the scanning process; The image sensor is used to scan the original image when the scanning process is started, and output the image scanning data to the analog-to-digital conversion chip; The analog-to-digital conversion chip is used to perform analog-to-digital conversion on the image scanning data when starting the scanning process, and output a digital signal to the programmable logic gate array chip; The programmable logic gate array chip is used to perform correction processing on the digital signal based on the correction configuration parameters when starting the scanning process, and output the corrected digital signal to the system-level chip.

11. The device according to claim 10, characterized in that When there are at least two image sensors, at least one of the image sensors is connected to the programmable logic gate array chip via the analog-to-digital conversion chip.

12. An electronic device, characterized in that: include: processor; Memory; A computer program is stored in the memory, and when the computer program is executed, the electronic device executes the method according to any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 9.

Images