Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; a stacked structure is formed on the substrate, the stacked structure comprises sacrificial parts and initial semiconductor columns which are sequentially and alternately stacked in the thickness direction of the substrate, and the sacrificial parts are adjacent to the substrate; a first preset process is adopted to remove the sacrificial part, an interface layer is formed on the outer surface, extending in the first direction, of the initial semiconductor column, and the remaining initial semiconductor column is used for forming a middle semiconductor column; removing a corrosion layer formed by the interface layer and a part of the middle semiconductor column by adopting a second preset process; wherein the remaining middle semiconductor columns are used for forming target semiconductor columns, the first preset process is different from the second preset process, and the first direction is perpendicular to the thickness direction. According to the method, the crystal quality of the monocrystalline silicon on the surface of the target semiconductor column can be improved, so that the carrier mobility of a channel is improved, the performance of the surrounding type gate device is improved, and meanwhile, the integration level of the device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In integrated circuit manufacturing, as the integration and performance of memory continue to improve, the use of gate all around transistors (GAA transistors) can effectively reduce the size of memory cells. The channel in the gate all around device mainly exists in the nanometer range of the single crystal silicon film and is relatively small in size. Therefore, the overall performance of the device has extremely high requirements on the quality of the single crystal silicon film.

[0003] However, during the preparation of the semiconductor structure, etching of adjacent structures may cause deformation and surface damage of the single-crystal silicon film, which affects the performance and reliability of the surround-gate transistor. Therefore, it is urgent to provide a semiconductor structure and a preparation method thereof to improve the morphology and surface damage of the single-crystal silicon film. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problems of the morphology and surface damage of the single-crystal silicon film, so as to improve the morphology of the single-crystal silicon film used to form the channel and reduce or eliminate its surface damage, thereby improving the overall performance of the surround gate transistor.

[0005] The present application provides a method for preparing a semiconductor structure, comprising: providing a substrate; forming a stacking structure on the substrate, the stacking structure comprising sacrificial parts and initial semiconductor columns alternately stacked in sequence along the thickness direction of the substrate, the sacrificial parts being adjacent to the substrate; using a first preset process to remove the sacrificial parts, an outer surface of the initial semiconductor column extending along a first direction forming an interface layer, and the remaining initial semiconductor columns being used to form intermediate semiconductor columns; using a second preset process to remove the interface layer and a corrosion layer formed by a portion of the intermediate semiconductor columns; wherein the remaining intermediate semiconductor columns are used to form target semiconductor columns, the first preset process is different from the second preset process, and the first direction is perpendicular to the thickness direction.

[0006] In the method for preparing the semiconductor structure, the stacked structure includes sacrificial parts and initial semiconductor columns alternately stacked in sequence along the thickness direction of the substrate, the initial semiconductor column is used to form the channel portion in the wrap-around gate transistor, and the sacrificial part is the portion that needs to be removed by etching later. In the process of removing the sacrificial part, first, after removing the sacrificial part by a first preset process, the outer surface of the initial semiconductor column extending along the first direction will be corroded by the etching reactant in the first preset process, and the morphology will be changed or the surface will be damaged, so that an interface layer will be formed; then, the interface layer is removed by a second preset process, and the size of the intermediate semiconductor column is further adjusted, so that the ultra-high crystal quality single crystal silicon on the surface of the target semiconductor column is exposed to form the channel of the wrap-around gate transistor, which can improve the carrier mobility of the channel and thus improve the performance of the wrap-around gate device. Therefore, since the surface morphology of the target semiconductor column is improved, the diameter of the channel can be further reduced to reduce the dark current; since the initial semiconductor column includes a corrosion layer and a target semiconductor column, and the interface layer is removed, the thickness of the target semiconductor column is less than the thickness of the initial semiconductor column, and the reduced thickness of the target semiconductor column can replace part of the thickness of the sacrificial layer formed at the beginning. Therefore, during the processing of the stacked structure, the thickness of the sacrificial layer can be reduced accordingly while the overall thickness of the single-cycle sacrificial part and the initial semiconductor column remains unchanged. This process method can greatly increase the maximum number of cycles that can be achieved in the stacked structure, thereby increasing the number of 3D stacking layers of the device to improve the device integration. Through the above-mentioned method for preparing the semiconductor structure, the damage and morphological effects on the surface of the initial semiconductor column when etching and removing the sacrificial layer in the related technology can be improved, thereby reducing the impact of the process on the carrier mobility of the device, and can also increase the number of 3D stacking layers of the device structure to improve the device integration.

[0007] In some of the embodiments, the first predetermined process includes a dry etching process, and the second predetermined process includes a quasi-atomic layer wet etching process.

[0008] In some of the embodiments, the second preset process has at least one process cycle to remove the corrosion layer, including: in one process cycle, providing a first etching solution on the interface layer to remove the oxidized surface exposed on the corrosion layer; providing a second etching solution on the corrosion layer to oxidize the remaining corrosion layer; repeating the process cycle until the corrosion layer is completely removed and the thickness of the target semiconductor column reaches a preset channel thickness.

[0009] In some embodiments, the first etching solution includes a buffered oxide etching solution, and the second etching solution includes a hydrogen peroxide solution.

[0010] In some of the embodiments, the initial semiconductor column has a first predetermined thickness; wherein the first predetermined thickness is greater than the predetermined channel thickness.

[0011] In some embodiments, the first preset thickness is greater than or equal to 1nm and less than or equal to 100nm; the thickness of the interface layer is greater than or equal to 1nm; wherein the first preset thickness is the sum of the preset channel thickness and the thickness of the corrosion layer on the two outer surfaces relative to the target semiconductor column along the thickness direction.

[0012] In some of the embodiments, in the dry etching process, an etching selectivity ratio of the sacrificial portion to the initial semiconductor pillar is greater than 100.

[0013] In some embodiments, the material of the sacrificial part includes a silicon-germanium alloy, and the germanium content in the silicon-germanium alloy is 5%-40%.

[0014] In some of the embodiments, a stacked structure is formed on a substrate, including: forming a sacrificial layer and a semiconductor layer alternately stacked in sequence along the thickness direction of the substrate on the substrate, the sacrificial layer being adjacent to the substrate; forming a plurality of stacked structures spaced apart along a second direction based on the sacrificial layer and the semiconductor layer, the sacrificial layer being used to form a sacrificial portion, and the semiconductor layer being used to form an initial semiconductor column; wherein the second direction, the first direction, and the thickness direction are perpendicular to each other.

[0015] In some of the embodiments, after removing the etching layer, the method further includes: performing ion doping on the target semiconductor column to form a first contact region, a channel region, a second contact region and a capacitor region arranged in sequence along a first direction; wherein the first contact region is a source contact region or a drain contact region, and the second contact region is a drain contact region or a source contact region.

[0016] In some embodiments, after forming the first contact region, the method further includes: forming a bit line structure extending along a second direction on a side of the first contact region away from the channel region along the first direction, and the first contact regions arranged in the same column along the second direction share the bit line structure.

[0017] In some embodiments, after forming the bit line structure, the method further includes: forming a word line structure extending along the thickness direction and contacting a portion of the outer surface of the channel region, and the channel regions in the same column arranged along the thickness direction share a word line structure.

[0018] In some of the embodiments, after forming the word line structure, the further step includes: forming a capacitor structure circumferentially surrounding an outer surface of the capacitor region extending along a first direction, wherein the capacitor structure extends along the first direction.

[0019] In some of the embodiments, a capacitor structure is formed, including: forming a first electrode on an outer surface that circumferentially surrounds a capacitor region and extends along a first direction; forming an intermediate dielectric layer on the outer surface of the first electrode that extends along the first direction; forming a second electrode on the outer surface of the intermediate dielectric layer that extends along the first direction, wherein the first electrode, the intermediate dielectric layer, and the second electrode together constitute a capacitor structure.

[0020] On the other hand, the present application further provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in any one of the embodiments of the present application.

[0021] In the above semiconductor structure, the crystal quality of the single crystal silicon on the surface of the target semiconductor column can be improved, and then used to form the channel of the surround gate transistor, which can improve the carrier mobility of the channel, thereby improving the performance of the surround gate device, and can further reduce the diameter of the channel to reduce the dark current. In addition, during the processing of the stacked structure, the thickness of the sacrificial layer can be reduced accordingly while the overall thickness of the single-cycle sacrificial part and the initial semiconductor column remains unchanged. This process method can greatly increase the maximum number of cycles that can be achieved in the stacked structure, thereby increasing the number of 3D stacking layers of the device to improve the device integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, they can also obtain drawings of other embodiments based on these drawings without paying any creative work.

[0023] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present application;

[0024] Figure 2 (a) is a schematic top view of forming a sacrificial layer and a semiconductor layer on a substrate in a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0025] Figure 2 (b) in Figure 2 (a) is a schematic cross-sectional view along the AA' direction;

[0026] Figure 3 (a) is a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 2 A schematic top view of a stacked structure formed on the structure shown in (a);

[0027] Figure 3 (b) in Figure 3 (a) is a schematic cross-sectional view along the AA' direction;

[0028] Figure 4 (a) is a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 3 A schematic top view of forming an interface layer and a target semiconductor column on the structure shown in (a);

[0029] Figure 4 (b) in Figure 4 (a) is a schematic cross-sectional view along the AA' direction;

[0030] Figure 5 (a) is a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 4 A schematic top view of the structure shown in (a) with the interface layer removed;

[0031] Figure 5 (b) in Figure 5 (a) is a schematic cross-sectional view along the AA' direction;

[0032] Figure 6 (a) is a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 5 A schematic top view of a structure shown in (a) in which a first contact region, a channel region, a second contact region and a capacitor region are formed;

[0033] Figure 6 (b) in Figure 6 (a) is a schematic cross-sectional view along the AA' direction;

[0034] Figure 7 (a) is a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 6 A schematic top view of a bit line structure formed on the structure shown in (a);

[0035] Figure 7 (b) in Figure 7 (a) is a schematic cross-sectional view along the AA' direction;

[0036] Figure 8 (a) is a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 7 A schematic top view of a word line structure formed on the structure shown in (a);

[0037] Figure 8 (b) in Figure 8 (a) is a schematic cross-sectional view along the AA' direction;

[0038] Fig. 9 (a) is a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 8 A schematic top view of a capacitor structure formed on the structure shown in (a);

[0039] Fig. 9 (b) in Fig. 9 (a) is a schematic cross-sectional view along the AA' direction;

[0040] Fig.10 (a) is a schematic diagram of a three-dimensional structure of a semiconductor structure provided in one embodiment of the present application;

[0041] Fig.10 (b) in Fig.10 Schematic diagram of the three-dimensional structure of part of the structure in (a).

[0042] Description of reference numerals:

[0043] 10. Substrate; 11. Sacrificial layer; 12. Semiconductor layer; 13. Stacked structure; 131. Sacrificial part; 132. Initial semiconductor column; 1320. Interface layer; 1321. Intermediate semiconductor column; 1321'. Etching layer; 1322. Target semiconductor column; 1322a. First contact area; 1322b. Channel area; 1322c. Second contact area; 1322d. Capacitor area; 14. Bit line structure; 15. Word line structure; 16. Capacitor structure; 161. First electrode; 162. Intermediate dielectric layer; 163. Second electrode; 17. Stacked isolation structure; 18. Bit line isolation structure; 19. Word line isolation structure; 20. Fixed structure; 21. Filling dielectric layer. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the application content of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0047] Spatially relative terms such as "below", "beneath", "below", "beneath", "above", "above", etc., may be used herein to describe the relationship of one element or feature to other elements or features as shown in the figures. It should be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientations shown in the figures.

[0048] When used herein, the singular forms of "a", "an" and " / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. In the case of using "including", "having", and "comprising" described herein, unless clear limiting terms such as "only", "consisting of...", etc. are used, another component may also be added. Unless mentioned to the contrary, terms in the singular form may include plural forms and cannot be understood as having a number of one.

[0049] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques.

[0050] See also Figure 1-Figure 10 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present application. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0051] In integrated circuit manufacturing, with the integration and size reduction of memories such as DRAM (Dynamic Random Access Memory), the density of the circuit structure inside the memory is gradually increasing. With the continuous improvement of the integration and performance of the memory, the use of gate all around transistors (GAA transistors) can effectively reduce the size of the memory unit, which provides the possibility of further reducing the size of the memory while ensuring that the performance of the memory is not reduced. The channel in the gate all around device mainly exists in the nanometer range of the single crystal silicon film and is small in size. Therefore, the overall performance of the device has extremely high requirements on the quality of the single crystal silicon film.

[0052] However, in a DRAM structure with multiple layers of horizontal units based on a stacked structure, single crystal silicon in the stacked structure is used to form a channel and is alternately stacked with a sacrificial layer. In the etching process of the sacrificial layer, the two common etching methods are wet etching and dry etching. The edge morphology of the silicon film changes after wet etching, forming a rounded corner with poor verticality. Dry etching has high selectivity and can obtain a relatively steep edge morphology. However, the plasma used in dry etching will damage the surface of the silicon film, thereby affecting the channel quality and the overall performance of the device.

[0053] Based on the problems of morphology and surface damage of single crystal silicon thin film in wrap-around gate transistor, the following embodiments of the present application provide a semiconductor structure and a preparation method thereof to improve the morphology of single crystal silicon thin film used to form a channel and reduce or eliminate its surface damage, thereby improving the overall performance of the wrap-around gate transistor.

[0054] It should be noted that, in the embodiments of the present application, the thickness direction may be the oy direction, the first direction may be the ox direction, and the second direction may be the oz direction.

[0055] As an example, see Figure 1 , the present application provides a method for preparing a semiconductor structure, comprising:

[0056] Step S2: providing a substrate;

[0057] Step S4: forming a stacked structure on the substrate, the stacked structure comprising sacrificial portions and initial semiconductor columns alternately stacked in sequence along a thickness direction of the substrate, the sacrificial portions being adjacent to the substrate;

[0058] Step S6: using a first preset process to remove the sacrificial portion, forming an interface layer on the outer surface of the initial semiconductor column extending along the first direction, and the remaining initial semiconductor column is used to form an intermediate semiconductor column;

[0059] Step S8: using a second preset process to remove the interface layer and the corrosion layer formed by part of the intermediate semiconductor column; wherein the remaining intermediate semiconductor column is used to form a target semiconductor column, the first preset process is different from the second preset process, and the first direction is perpendicular to the thickness direction.

[0060] In the method for preparing the semiconductor structure, the stacked structure includes sacrificial parts and initial semiconductor columns alternately stacked in sequence along the thickness direction of the substrate, the initial semiconductor column is used to form the channel portion in the wrap-around gate transistor, and the sacrificial part is the portion that needs to be removed by etching later. In the process of removing the sacrificial part, first, after removing the sacrificial part by a first preset process, the outer surface of the initial semiconductor column extending along the first direction will be corroded by the etching reactant in the first preset process, and the morphology will be changed or the surface will be damaged, so that an interface layer will be formed; then, the interface layer is removed by a second preset process, and the size of the intermediate semiconductor column is further adjusted, so that the ultra-high crystal quality single crystal silicon on the surface of the target semiconductor column is exposed to form the channel of the wrap-around gate transistor, which can improve the carrier mobility of the channel and thus improve the performance of the wrap-around gate device. Therefore, since the surface morphology of the target semiconductor column is improved, the diameter of the channel can be further reduced to reduce the dark current; since the initial semiconductor column includes a corrosion layer and a target semiconductor column, and the interface layer is removed, the thickness of the target semiconductor column is less than the thickness of the initial semiconductor column, and the reduced thickness of the target semiconductor column can replace part of the thickness of the sacrificial layer formed at the beginning. Therefore, during the processing of the stacked structure, the thickness of the sacrificial layer can be reduced accordingly while the overall thickness of the single-cycle sacrificial part and the initial semiconductor column remains unchanged. This process method can greatly increase the maximum number of cycles that can be achieved in the stacked structure, thereby increasing the number of 3D stacking layers of the device to improve the device integration. Through the above-mentioned method for preparing the semiconductor structure, the damage and morphological effects on the surface of the initial semiconductor column when etching and removing the sacrificial layer in the related technology can be improved, thereby reducing the impact of the process on the carrier mobility of the device, and can also increase the number of 3D stacking layers of the device structure to improve the device integration.

[0061] As an example, the first preset process includes a dry etching process, and the second preset process includes a quasi-atomic layer wet etching process, namely, a qALE (quasi Atomic Layer Etching) wet process. The dry etching process has a high selectivity, which can make the target semiconductor column after etching have very high conformality, and thus be used to form a high-quality channel region; the quasi-atomic layer wet etching process can utilize its self-limiting and self-saturated adsorption reaction to have surface controllability, and the prepared structure has excellent three-dimensional conformality and large-area uniformity. At the same time, it can also produce a smooth surface morphology to reduce the stress generated by the subsequent deposition process, and can also accurately control the etching thickness, so that the target semiconductor column is controlled within the preset channel thickness and its surface uniformity is improved at the same time.

[0062] As an example, the initial semiconductor column has a first preset thickness, and the target semiconductor column has a preset channel thickness; wherein the first preset thickness is greater than the preset channel thickness. The quasi-atomic layer wet etching process can accurately control the etching thickness, so that the target semiconductor column has a preset channel thickness and improves its surface uniformity at the same time. The thickness of the target semiconductor column is less than the thickness of the initial semiconductor column. The reduced thickness of the target semiconductor column can replace part of the thickness of the sacrificial layer formed at the beginning. Therefore, the thickness of the sacrificial layer can be reduced accordingly when it is formed, and the number of stacking cycles can be further improved.

[0063] As an example, the first preset thickness is greater than or equal to 1nm and less than or equal to 100nm; the thickness of the interface layer is greater than or equal to 1nm; wherein the first preset thickness is the sum of the preset channel thickness and the thickness of the corrosion layer on the two outer surfaces of the target semiconductor column along the thickness direction. Specifically, the first preset thickness can be 1nm, 10nm, 30nm, 50nm or 100nm, etc.; the thickness of the interface layer can be equal to 1nm, 2nm, 5nm or 10nm, etc.

[0064] As an example, see Figure 1 Step S2 in Figure 2In (a) and (b), in step S2, the substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistor formed on the substrate 10, and therefore, the type of substrate 10 should not limit the scope of protection of the present application.

[0065] As an example, see Figure 1 Step S4 in which a stacked structure is formed on a substrate comprises:

[0066] Step S41: forming a sacrificial layer and a semiconductor layer alternately stacked in sequence along the thickness direction of the substrate on the substrate, wherein the sacrificial layer is adjacent to the substrate;

[0067] Step S42: Based on the sacrificial layer and the semiconductor layer, a plurality of stacked structures spaced apart along the second direction are formed, wherein the sacrificial layer is used to form a sacrificial portion, and the semiconductor layer is used to form an initial semiconductor column; wherein the second direction, the first direction, and the thickness direction are perpendicular to each other.

[0068] As an example, in step S41, see Figure 2 In (a) and (b), a sacrificial layer 11 and a semiconductor layer 12 are formed on a substrate 10, which are alternately stacked in the thickness direction (e.g., oy direction) of the substrate 10, and the sacrificial layer 11 is adjacent to the substrate 10; wherein the specific formation process includes but is not limited to reduced pressure chemical vapor deposition (RPCVD), molecular beam epitaxy (MBE) and other processes, and the precursors for preparing the sacrificial layer 11 include but are not limited to materials such as monosilane (SiH4) and germanium hydride (GeH4).

[0069] In the above embodiment, the material of the substrate 10 is single crystal silicon, the material of the sacrificial layer 11 includes a silicon-germanium alloy, the germanium content in the silicon-germanium alloy is 5%-40%, and the thickness of the sacrificial layer 11 is greater than or equal to 1nm and less than or equal to 100nm. Specifically, the germanium content in the silicon-germanium alloy can be 5%, 10%, 20%, 30% or 40%, etc.; the thickness of the sacrificial layer 11 can be 1nm, 10nm, 30nm, 50nm or 100nm, etc.

[0070] As an example, in step S42, see Figure 3 In (a) and (b), a plurality of stacked structures 13 spaced apart along a second direction (e.g., oz direction) are formed based on a sacrificial layer 11 and a semiconductor layer 12, wherein the sacrificial layer 11 is used to form a sacrificial portion 131, and the semiconductor layer 12 is used to form an initial semiconductor column 132, so as to form an active region in the semiconductor structure. Specifically, the active region can be defined by a photolithography process.

[0071] As an example, see Figure 3 In (a) and (b), the step of defining the active area using the photolithography process may include: providing a mask substrate (not shown); coating a layer of photoresist (not shown) on the mask substrate; exposing and developing the photoresist to form a photoresist pattern; transferring the photoresist layer to the sacrificial layer 11 and the semiconductor layer 12 to define the active area; etching the sacrificial layer 11 and the semiconductor layer 12 in the thickness direction (e.g., oy direction) to form a plurality of stacked structures 13 spaced apart along a first direction (e.g., ox direction), the sacrificial layer 11 being used to form a sacrificial portion 131, and the semiconductor layer 12 being used to form an initial semiconductor column 132 to form an active area in the semiconductor structure.

[0072] As an example, see Figure 1 Step S6 in Figure 3 (a), (b), Figure 4 In (a) and (b), in step S6, under the first preset process, the sacrificial portion 131 is removed, and the outer surface of the initial semiconductor column 132 extending along the first direction (for example, the ox direction) forms an interface layer 1320, and the remaining initial semiconductor column 132 is used to form an intermediate semiconductor column 1321. While removing the sacrificial portion 131, due to the participation of plasma in the etching process, the surface crystal structure of the initial semiconductor column 132 is damaged, so that an interface layer 1320 is formed on the outer surface extending along the first direction (for example, the ox direction), and in some embodiments, the thickness of the interface layer 1320 is greater than or equal to 1 nm.

[0073] As an example, see Figure 3 (a), (b), Figure 4In (a) and (b), before removing the sacrificial portion 131, a fixing structure 20 is formed on the outer surface of the stack structure 13 to fix the initial semiconductor column 132 at its original position and provide support for the semiconductor structure in subsequent process steps.

[0074] The above-mentioned step of removing the sacrificial portion 131 under the first preset process can specifically include: first, using photolithography to define the etching area, and then performing dry lateral selective etching to achieve a high selectivity ratio between the sacrificial portion 131 and the initial semiconductor column 132, thereby achieving conformality of the channel formed in the initial semiconductor column 132.

[0075] As an example, in the above dry etching process, the etching selectivity of the sacrificial portion 131 to the initial semiconductor column 132 is greater than 100. Specifically, the etching selectivity of the sacrificial portion 131 to the initial semiconductor column 132 may be 140, 145, 150, 155 or 160, etc.

[0076] As an example, see Figure 1 In step S8, the second preset process has at least one process cycle, and removing the corrosion layer in step S8 includes:

[0077] Step S81: in one process cycle, providing a first etching solution on the corrosion layer to remove the exposed oxidized surface of the corrosion layer;

[0078] Step S82: providing a second etching solution on the corrosion layer to oxidize the remaining corrosion layer;

[0079] Step S83: Repeat the process cycle until the etching layer is completely removed and the thickness of the target semiconductor column reaches a preset channel thickness.

[0080] As an example, in step S81, see Figure 4 (a), (b) and Figure 5 In (a) and (b), the corrosion layer 1321' is the part to be removed in the second preset process. The corrosion layer 1321' is composed of the entire interface layer 1320 and part of the intermediate semiconductor column 1321. After removing the corrosion layer 1321', the remaining intermediate semiconductor column is used to form the target semiconductor column. There is a natural oxide layer on the surface exposed by the corrosion layer 1321'. Therefore, the first etching solution is used to remove the oxidized surface exposed on the corrosion layer 1321'. The first etching solution includes a buffered oxide etching solution. Specifically, the buffered oxide etching solution can be a diluted buffered oxide etching solution, namely dBOE (dilute Buffered Oxide Etch), which can be a mixture of hydrofluoric acid and water or ammonium fluoride and water.

[0081] As an example, in step S82, please continue to refer to Figure 4 (a), (b) and Figure 5 In (a) and (b), a second etching solution is provided on the corrosion layer 1321', and after the first etching solution etches away a portion of the corrosion layer 1321', the remaining corrosion layer 1321' is oxidized. The second etching solution includes a hydrogen peroxide solution. In one process cycle, the corrosion layer 1321' may not be completely removed, and only a portion of the corrosion layer 1321' is removed at a time to protect the surface of the target semiconductor column 1322 from being damaged, thereby obtaining a high-quality crystal surface.

[0082] As an example, after step S81 and / or step S82, a cleaning solution may be used to clean the surface of the structure after the reaction to remove impurities on the surface of the corrosion layer 1321'. The cleaning solution includes deionized water.

[0083] As an example, in step S83, please continue to refer to Figure 4 (a), (b) and Figure 5 In (a) and (b), the quasi-atomic layer wet etching process can accurately control the etching thickness of the etching layer 1321' through multiple etching process cycles, and remove the etching layer 1321' completely through the control of the etching cycle to expose the high-quality surface of the target semiconductor column 1322, that is, the silicon single crystal surface, thereby improving the carrier mobility of the channel. In addition, due to the improvement of the quality of the silicon single crystal surface, a smaller channel width can be achieved under the same device size to reduce leakage; it can also appropriately reduce the thickness of the sacrificial layer 11 under the conditions of the same channel spacing and stacking size, thereby improving the stacking density.

[0084] As an example, the difference between the first preset thickness and the preset channel thickness is greater than or equal to 1 nm and less than or equal to 60 nm. Specifically, the difference between the first preset thickness and the preset channel thickness can be 1 nm, 10 nm, 30 nm, 50 nm or 60 nm, etc.

[0085] As an example, after removing the corrosion layer in step S8, the following steps are further included:

[0086] Step S91: forming a filling dielectric layer between target semiconductor pillars adjacent to each other along the thickness direction and the second direction;

[0087] Step S92: performing ion doping on the target semiconductor column to form a first contact region, a channel region, a second contact region and a capacitor region sequentially arranged along a first direction; wherein the first contact region is a source contact region or a drain contact region, and the second contact region is a drain contact region or a source contact region.

[0088] As an example, in step S92, see Figure 6In (a) and (b), a filling dielectric layer 21 is formed between target semiconductor pillars adjacent to each other in the thickness direction (e.g., the oy direction) and the second direction (e.g., the oz direction) to fill the gap inside the semiconductor structure. Specifically, the material of the filling dielectric layer 21 can be selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0089] As an example, in step S92, please continue to refer to Figure 6 In (a) and (b), the first contact region 1322a, the channel region 1322b, the second contact region 1322c and the capacitor region 1322d are defined by photolithography technology again, and ion doping is performed on the corresponding regions. The first contact region 1322a, the channel region 1322b and the second contact region 1322c in the same target semiconductor column 1322 are used to form the same transistor; specifically, the type of doped ions can be the first doping type or the second doping type. The first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type. The specific photolithography process is a conventional technical means that can be used by those skilled in the art, and will not be repeated here.

[0090] As an example, the P-type impurity ions may include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, indium (In) ions, etc. The N-type impurity ions may include, but are not limited to, one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0091] As an example, after forming the first contact area in step S9, the step further includes:

[0092] Step S10: forming a bit line structure extending along a second direction on a side of the first contact region away from the channel region along the first direction, and the first contact regions arranged in the same column along the second direction share the bit line structure.

[0093] As an example, in step S10, see Figure 7 In (a) and (b), a bit line structure 14 extending along a second direction (e.g., oz direction) is formed on a side of the first contact region 1322a away from the channel region 1322b along a first direction (e.g., ox direction). Specifically, the position of the bit line structure 14 can be defined by a photolithography process, and the first contact region 1322a can be etched by a high aspect ratio dry etching to form a bit line contact plug (not shown) and the bit line structure 14; wherein the first contact region 1322a is connected to the bit line structure 14, and the first contact regions 1322a in the same column arranged along the second direction (e.g., oz direction) share a bit line structure 14.

[0094] As an example, after forming the bit line structure in step S10, the step further includes:

[0095] Step S11: forming a word line structure extending along the thickness direction and contacting a portion of the outer surface of the channel region, wherein the channel regions in the same column arranged along the thickness direction share a word line structure.

[0096] As an example, in step S11, see Figure 8 In (a) and (b), a word line structure 15 extending along the thickness direction (e.g., the oy direction) and contacting a portion of the outer surface of the channel region 1322b is formed, and the channel regions 1322b in the same column arranged along the thickness direction (e.g., the oy direction) share a word line structure 15. Specifically, the position of the word line structure 15 can be defined by a photolithography process first, and the word line structure 15 is formed on a portion of the outer surface of the channel region 1322b and circumferentially surrounds the channel region 1322b, that is, the word line structure 15 at least wraps a portion of the outer surface of the channel region 1322b; the material of the word line structure 15 may include a metal with a high dielectric constant to form a corresponding gate structure.

[0097] As an example, see Fig. 9 In (a) and (b), after the word line structure is formed in step S11, the method further includes:

[0098] Step S12: forming a capacitor structure 16 circumferentially surrounding the outer surface of the capacitor region 1322 d extending along a first direction (eg, ox direction), wherein the capacitor structure 16 extends along the first direction (eg, ox direction).

[0099] As an example, step S12 forms a capacitor structure, including:

[0100] Step S121: forming a first electrode circumferentially surrounding an outer surface of the capacitor region extending along a first direction;

[0101] Step S122: forming an intermediate dielectric layer on the outer surface of the first electrode extending along the first direction;

[0102] Step S123: forming a second electrode on the outer surface of the intermediate dielectric layer extending along the first direction, wherein the first electrode, the intermediate dielectric layer and the second electrode together constitute a capacitor structure.

[0103] As an example, in step S121, please continue to refer to Fig. 9 In (a) and (b), firstly, the position of the capacitor region 1322d is defined by a photolithography process, and a first electrode 161 is formed on an outer surface that circumferentially surrounds the capacitor region 1322d and extends along a first direction (e.g., ox direction). Specifically, the material of the first electrode 161 is selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, knob nitride, and combinations thereof.

[0104] As an example, in step S122, please continue to refer to Fig. 9In (a) and (b), the same photolithography process is used to form an intermediate dielectric layer 162 on the outer surface of the first electrode 161 extending along the first direction (e.g., the ox direction). Specifically, the material of the intermediate dielectric layer 162 is selected from aluminum oxide, zirconium oxide, and a combination thereof. The intermediate dielectric layer 162 may also include other insulating materials with a relatively high dielectric constant (high-k), such as a material with a dielectric constant greater than 3.9.

[0105] As an example, in step S123, a second electrode 163 is formed on the outer surface of the intermediate dielectric layer 162 extending along the first direction (e.g., ox direction), and the first electrode 161, the intermediate dielectric layer 162, and the second electrode 163 together constitute the capacitor structure 16. Specifically, the material of the second electrode 163 is selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, and combinations thereof.

[0106] Although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, the execution of these steps is not strictly limited to the order, and these steps can be executed in other orders. Moreover, although Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution of these sub-steps or stages is not necessarily carried out sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0107] As an example, see Fig. 9 (a) and (b) in the above description, the present application further provides a semiconductor structure, which is prepared by the method for preparing a semiconductor structure described in any one of the embodiments of the present application.

[0108] In the above semiconductor structure, the crystal quality of the single crystal silicon on the surface of the target semiconductor column 1322 can be improved, and then used to form the channel of the surrounding gate transistor, which can improve the carrier mobility of the channel, thereby improving the performance of the surrounding gate device, and can further reduce the length of the channel to reduce the dark current. In addition, when the overall thickness of the stacked structure remains unchanged, the number of stacked layers can be further increased, thereby further increasing the density of the transistor to improve the device integration.

[0109] As an example, see Fig.10 (a) and (b) in Fig.10A 3D DRAM device prepared by the method for preparing a semiconductor structure provided in any embodiment of the present application is formed by a process of stacking a plurality of stacked units, and finally forms a DRAM device in which horizontal units are stacked vertically. The device includes target semiconductor columns 1322 extending along a first direction (e.g., ox direction) and arranged in an array along a thickness direction (e.g., oy direction) and a second direction (e.g., oz direction) of a substrate (not shown), and stacked isolation structures 17 are provided between adjacent target semiconductor columns 1322 along the thickness direction (e.g., oy direction) to insulate and isolate adjacent horizontal units along the thickness direction (e.g., oy direction); the device also includes a bit line structure 14 extending along the second direction (e.g., oz direction) and stacked at intervals along the thickness direction (e.g., oy direction), and bit line isolation structures 18 are provided between adjacent bit line structures 14 along the thickness direction (e.g., oy direction) to insulate and isolate adjacent bit line structures 14. The device further comprises a word line structure 15 extending in the thickness direction (e.g., oy direction) and stacked in a second direction (e.g., oz direction), and a word line isolation structure 19 is provided between adjacent word line structures 15 in the second direction (e.g., oz direction) to insulate and isolate adjacent word line structures 15; the device further comprises a capacitor structure 16 extending in the first direction (e.g., ox direction) and arranged in an array in the thickness direction (e.g., oy direction) and the second direction (e.g., oz direction) of the substrate 10, and the capacitor structure 16 is formed on the corresponding target semiconductor column 1322; in addition, the capacitor structure 16 also has a fixed structure 20 on one side away from the bit line structure 14 in the first direction (e.g., ox direction). The above semiconductor structure can improve the carrier mobility of the channel, thereby improving the performance of the surrounding gate device, and can further reduce the length of the channel to reduce the dark current; and further increase the density of the transistor.

[0110] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0111] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0112] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacking structure on the substrate, the stacking structure comprising sacrificial portions and initial semiconductor columns alternately stacked in sequence along a thickness direction of the substrate, the sacrificial portions being adjacent to the substrate; The sacrificial portion is removed by a first preset process, an outer surface of the initial semiconductor column extending along the first direction forms an interface layer, and the remaining initial semiconductor column is used to form an intermediate semiconductor column; A second preset process is used to remove the interface layer and a portion of the corrosion layer formed by the intermediate semiconductor column; wherein the remaining intermediate semiconductor column is used to form a target semiconductor column, the first preset process is different from the second preset process, and the first direction is perpendicular to the thickness direction.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first preset process includes a dry etching process, and the second preset process includes a quasi-atomic layer wet etching process.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The second preset process has at least one process cycle, and removing the corrosion layer includes: In one of the process cycles, a first etching solution is provided on the interface layer to remove the exposed oxidized surface of the corrosion layer; Providing a second etching solution on the interface layer to oxidize the remaining corrosion layer; The process cycle is repeated until the etching layer is completely removed and the thickness of the target semiconductor column reaches a preset channel thickness.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The first etching solution includes a buffered oxide etching solution, and the second etching solution includes a hydrogen peroxide solution.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The initial semiconductor column has a first preset thickness; wherein the first preset thickness is greater than the preset channel thickness.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The first preset thickness is greater than or equal to 1 nm and less than or equal to 100 nm; the thickness of the interface layer is greater than or equal to 1 nm; The first preset thickness is the sum of the preset channel thickness and the thickness of the etching layer on two outer surfaces of the target semiconductor column along the thickness direction.

7. The method for preparing a semiconductor structure according to any one of claims 2 to 6, characterized in that: In the dry etching process, an etching selectivity ratio between the sacrificial portion and the initial semiconductor column is greater than 100.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The material of the sacrificial part includes a silicon-germanium alloy, and the germanium content in the silicon-germanium alloy is 5%-40%.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: A stacking structure is formed on the substrate, comprising: forming a sacrificial layer and a semiconductor layer alternately stacked in sequence along a thickness direction of the substrate on the substrate, wherein the sacrificial layer is adjacent to the substrate; Based on the sacrificial layer and the semiconductor layer, a plurality of stacked structures are formed and arranged at intervals along the second direction, the sacrificial layer is used to form the sacrificial part, and the semiconductor layer is used to form the initial semiconductor column; wherein the second direction, the first direction, and the thickness direction are perpendicular to each other.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: After removing the corrosion layer, the method further comprises: Ion doping is performed on the target semiconductor column to form a first contact region, a channel region, a second contact region and a capacitor region arranged in sequence along the first direction; wherein the first contact region is a source contact region or a drain contact region, and the second contact region is a drain contact region or a source contact region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: After forming the first contact area, the method further includes: A bit line structure extending along the second direction is formed on a side of the first contact region away from the channel region along the first direction, and the first contact regions in the same column arranged along the second direction share one bit line structure.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: After forming the bit line structure, the method further includes: A word line structure is formed which extends along the thickness direction and contacts a portion of the outer surface of the channel region. The channel regions in the same column arranged along the thickness direction share one word line structure.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: After forming the word line structure, the method further includes: A capacitor structure is formed which circumferentially surrounds an outer surface of the capacitor region extending along the first direction, and the capacitor structure extends along the first direction.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: Forming the capacitor structure includes: Forming a first electrode circumferentially surrounding an outer surface of the capacitor region extending along the first direction; forming an intermediate dielectric layer on an outer surface of the first electrode extending along the first direction; A second electrode is formed on an outer surface of the intermediate dielectric layer extending along the first direction. The first electrode, the intermediate dielectric layer, and the second electrode together constitute the capacitor structure.

15. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 14.

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