Power device and method of manufacturing the same
By introducing a dual resistor and diode structure into the IGBT device, the potential is adjusted, solving the problems of on-state voltage drop and latch-up failure, and achieving more efficient current drive and higher reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JOULWATT TECH INC LTD
- Filing Date
- 2024-06-14
- Publication Date
- 2026-05-12
AI Technical Summary
The on-state voltage drop of existing IGBT devices is difficult to reduce further, and they are prone to latch-up failure under high current conditions, affecting the reliability and efficiency of the devices.
Introducing additional dual resistors and diode structures into IGBT devices reduces the on-state voltage drop and enhances latch-up resistance by adjusting the potential in different regions.
It effectively reduces the on-state voltage drop of IGBT devices, improves the device's anti-latch-up capability, enhances the device's reliability and current drive capability, while reducing the impact of noise and RC delay and improving the utilization rate per unit area.
Smart Images
Figure CN119497421B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor device technology, and more specifically, to a power device and a method for manufacturing the same. Background Technology
[0002] Insulated-gate bipolar transistors (IGBTs) are core devices in power electronic systems for medium to high power applications. As a composite device of field-effect transistors and bipolar transistors, IGBTs feature high input impedance, simple driving, high current capability, and low on-state voltage drop.
[0003] Compared to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), IGBTs exhibit a lower on-state voltage drop, thanks to the conductivity modulation effect within the drift region when the IGBT is turned on. Currently, further reducing the on-state voltage drop of IGBTs, thereby lowering their power consumption, remains a crucial research area in the IGBT field. Summary of the Invention
[0004] In view of the above problems, the purpose of this disclosure is to provide a power device and a method for manufacturing the same, which adjusts the potential of different regions in the power device by setting additional resistors and diodes in the power device, thereby reducing the on-state voltage drop of the power device.
[0005] According to one aspect of the present disclosure, a power device is provided, comprising: a semiconductor layer having opposing first and second surfaces, the semiconductor layer including a first doped region, a second doped region, a well region, and a third doped region sequentially adjacent to each other along a direction from the second surface toward the first surface;
[0006] An isolation portion extends from the first surface of the semiconductor layer into the second doped region and is adjacent to the well region and the third doped region; and
[0007] The gate conductor is located in the isolation section.
[0008] The first doped region and the well region are of a first doping type, and the second doped region and the third doped region are of a second doping type. The first doping type is the opposite of the second doping type.
[0009] The semiconductor device further includes: a first resistor structure, a second resistor structure, and a first diode structure, wherein the first resistor structure constitutes a first resistor, the second resistor structure constitutes a second resistor, and the diode structure constitutes a first diode.
[0010] The first terminal of the first resistor is electrically connected to the third doped region, the second terminal of the first resistor is electrically connected to the cathode of the first diode and the first terminal of the second resistor, the anode of the first diode is electrically connected to the third doped region, and the second terminal of the second resistor is electrically connected to the well region.
[0011] The resistance of the first resistor is less than the resistance of the second resistor.
[0012] Optionally, the first doped region, the second doped region, and the well region are used to form a first transistor.
[0013] The second doped region, the well region, and the third doped region are used to form the second transistor and the third transistor.
[0014] The first transistor is a PNP transistor, the second transistor is an NPN transistor, and the third transistor is an NMOS transistor.
[0015] The emitter of the first transistor is connected to a first potential, the base of the first transistor is connected to the collector of the second transistor and the first current terminal of the third transistor, the collector of the first transistor is connected to the base of the second transistor and the substrate of the third transistor, and the emitter of the second transistor is connected to the second current terminal of the third transistor.
[0016] The anode of the first diode is connected to the emitter of the second transistor, and the cathode of the first diode is connected to the second potential.
[0017] The first resistor is connected in series between the emitter of the second transistor and the second potential.
[0018] The second resistor is connected in series between the base of the second transistor and the second potential.
[0019] Optionally, the semiconductor device further includes a fourth doped region adjacent to the well region, and a second terminal of the second resistor is electrically connected to the fourth doped region.
[0020] The fourth doped region is of the first doping type.
[0021] Optionally, the gate conductor, the first resistor structure, the second resistor structure, and the diode structure are located in the same isolation portion;
[0022] Alternatively, at least one of the gate conductor, the first resistor structure, the second resistor structure, and the diode structure may be located in different isolation portions.
[0023] Optionally, the diode structure includes a first filling portion extending from the surface of the isolation portion into the isolation portion.
[0024] Optionally, the diode structure further includes a fifth doped region extending from the surface of the first filled portion into the first filled portion.
[0025] The fifth doped region is of the first doping type, and the first filling portion is of the second doping type.
[0026] Optionally, the diode structure further includes a metal layer located on the surface of the first filling portion.
[0027] The first filling portion, in contact with the metal layer, constitutes a Schottky diode.
[0028] Optionally, the first filling portion is made of the same material as the gate conductor.
[0029] Optionally, the material of the first filling portion includes polycrystalline silicon or silicon carbide.
[0030] Optionally, the first resistive structure extends from the surface of the isolation portion into the isolation portion, or the first resistive structure is located on the surface of the isolation portion;
[0031] The second resistor structure extends from the surface of the isolation portion into the isolation portion, or the second resistor structure is located on the surface of the isolation portion.
[0032] Optionally, the material of the first resistor structure and / or the second resistor structure is the same as the material of the gate conductor.
[0033] Optionally, the material of the first resistor structure and / or the second resistor structure includes polycrystalline silicon or silicon carbide.
[0034] According to another aspect of the present disclosure, a method for manufacturing a power device is provided, comprising: forming a first doped region, a second doped region, a well region and a third doped region sequentially adjacent to each other in the semiconductor layer along a direction from a second surface toward a first surface;
[0035] An isolation portion is formed in the semiconductor layer, the isolation portion extending from the first surface into the second doped region and adjacent to the well region and the third doped region; and
[0036] A gate conductor is formed in the isolation section.
[0037] The first doped region and the well region are of a first doping type, and the second doped region and the third doped region are of a second doping type. The first doping type is the opposite of the second doping type.
[0038] The manufacturing method further includes: forming a first resistor structure, a second resistor structure, and a diode structure.
[0039] The first resistor structure is used to form a first resistor, the second resistor structure is used to form a second resistor, and the diode structure is used to form a first diode.
[0040] The first end of the first resistor is electrically connected to the third doped region, the second end of the first resistor is electrically connected to the cathode of the first diode and the first end of the second resistor, the anode of the first diode is electrically connected to the third doped region, and the second end of the second resistor is electrically connected to the well region.
[0041] Optionally, the step of forming the diode structure includes: forming a first filling portion in the isolation portion,
[0042] The first filling portion is formed in the same step as the gate conductor.
[0043] Optionally, the first resistive structure and / or the second resistive structure are formed in the same step as the gate conductor.
[0044] Optionally, the method further includes forming a fourth doped region in the semiconductor layer, the fourth doped region extending from the first surface toward the second surface and adjacent to the well region.
[0045] The step of forming the diode structure further includes: forming a fifth doped region in the first filled portion.
[0046] The fourth and fifth doped regions are of the first doping type, and the first filling portion is of the second doping type.
[0047] The fourth doped region is formed in the same step as the fifth doped region.
[0048] One of the above technical solutions has the following beneficial effects:
[0049] By incorporating additional dual resistors and diodes into the power device, the potential in different regions of the power device can be adjusted, thereby reducing the on-state voltage drop and enhancing the anti-latch-up capability of the power device.
[0050] In some embodiments, since no additional carrier storage layer is introduced to increase the doping concentration by forming a dual-resistance structure and / or a diode structure outside the doped region of the semiconductor layer, the breakdown voltage (BV) of the power device is not degraded.
[0051] In some embodiments, the resistor structure and / or diode structure are formed in the isolation section and integrated with the IGBT main circuit in the same device, thereby reducing the adverse effects of external wiring such as noise and RC delay.
[0052] Furthermore, the resistor structure and / or diode structure share the same isolation section with the gate conductor, which can save the space occupied by the isolation section and increase the utilization rate of the device per unit area.
[0053] In some embodiments, the first filling portion and / or resistive structure of the diode structure are made of the same material as the gate conductor and are formed in the same step as the gate conductor, thereby eliminating the need for additional mask design for the first filling portion and / or resistive structure when manufacturing power devices, thus saving manufacturing costs.
[0054] In some embodiments, the fifth doped region of the diode structure and the contact region (fourth doped region) of the well region are formed in the same step, thereby eliminating the need for an additional mask design for the fifth doped region when manufacturing power devices, thus saving manufacturing costs.
[0055] Furthermore, in some embodiments, since the device does not have a floating P-region adjacent to the gate, the gate capacitance is effectively reduced, and the risk of displacement current charging the gate is greatly reduced. Therefore, the power devices of the embodiments of this disclosure also have the ability to resist high dv / dt.
[0056] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description
[0057] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only involve some embodiments of this disclosure, and are not intended to limit this disclosure.
[0058] Figure 1 A three-dimensional structural schematic diagram of a power device according to a first embodiment of the present disclosure is shown.
[0059] Figure 2 It shows along Figure 1 A schematic diagram of the cross-section cut by line AA.
[0060] Figure 3 It shows Figure 2 A schematic diagram of some adjacent cells and the structures between them.
[0061] Figure 4 It shows Figure 3 The circuit structure diagram is shown in the figure.
[0062] Figures 5 to 10A cross-sectional schematic diagram of a portion of the manufacturing process of a power device according to the first embodiment of this disclosure is shown.
[0063] Figure 11 A schematic diagram of the structure of a power device according to a second embodiment of the present disclosure is shown.
[0064] Figure 12 A schematic diagram of the power device according to the third embodiment of this disclosure is shown. Detailed Implementation
[0065] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.
[0066] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.
[0067] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".
[0068] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.
[0069] In related technologies, there are two techniques to reduce the on-state voltage drop of IGBTs: First, increase the channel density, such as using a combination of planar gates and slot gates, to increase the electron current concentration in the drift region, thereby enhancing the conductivity modulation effect; Second, introduce an N-type carrier storage layer with hole blocking effect at the cathode of the IGBT to increase the carrier concentration in the drift region near the cathode, which can also enhance the conductivity modulation effect.
[0070] However, increasing the channel density is limited by critical process dimensions and does not significantly improve the current capability of the device. Introducing an N-type carrier storage layer on the cathode side of the IGBT can lead to a decrease in device BV when the doping concentration of the N-type carrier storage layer is high, and a significant reduction in the current capability improvement when the doping concentration of the N-type carrier storage layer is low. Furthermore, an additional injection is required, increasing the cost.
[0071] In view of the above problems, the purpose of this disclosure is to provide a power device and a method for manufacturing the same, which adjusts the potential of different regions in the power device by setting additional dual resistors and diodes in the power device, thereby reducing the on-state voltage drop of the power device.
[0072] Figure 1 A three-dimensional structural schematic diagram of the power device according to the first embodiment of this disclosure is shown. Figure 2 It shows along Figure 1 A schematic diagram of the cross-section cut by line AA. Figure 3 It shows Figure 2 A schematic diagram of some adjacent cells and the structures between them. Figure 4 It shows Figure 3 The circuit structure diagram is shown in the image. Among them, Figures 1 to 3 The interlayer dielectric layer and wiring layer above the semiconductor layer are omitted to more clearly express the positional relationship between the various structures and regions. Figure 3 Only the connection relationships between each region in the second cell Cell-2 and the first resistor structure 181, the second resistor structure 182, and the diode structure 190 are shown to more clearly illustrate the circuit connection structure. The circuit connections of other cell structures can be referred to the second cell Cell-2.
[0073] like Figures 1 to 4 As shown, the power device of the first embodiment of this disclosure includes: a semiconductor layer 101, an isolation portion 160, a gate conductor 170, a first resistor structure 181, a second resistor structure 182, and a diode structure 190. The semiconductor layer 101 is, for example, a Si, SiC substrate, or a stacked structure composed of a substrate and an epitaxial layer. However, the embodiments of this disclosure are not limited thereto, and those skilled in the art can make other settings regarding the material and number of layers of the semiconductor layer 101 as needed.
[0074] Semiconductor layer 101 has opposing first surfaces 101a and second surfaces 101b. Semiconductor layer 101 includes a first doped region 110, a second doped region 102, a well region 140, a third doped region 151, and a fourth doped region 152. Along the direction from the second surface 101b toward the first surface 101a, the first doped region 110, the second doped region 102, and the well region 140 are sequentially adjacent. The third doped region 151 and the fourth doped region 152 extend from the first surface 101a toward the second surface 101b and are adjacent to the well region 140. The third doped region 151 and the fourth doped region 152 can be adjacent or separated by the well region 140. The first doped region 110, the well region 140, and the fourth doped region 152 represent a first doping type, while the second doped region 102 and the third doped region 151 represent a second doping type, with the first doping type being the opposite of the second doping type. The first doping type is either P-type or N-type, and the second doping type is either P-type or N-type. In the following description, examples will be given with P-type as the first doping type and N-type as the second doping type.
[0075] In this embodiment, the second doped region 102 includes a buffer region 120 and a drift region 130. Optionally, the buffer region 120 may not be provided. The doping concentration of the third doped region 151 is greater than that of the well region 140, thereby serving as the contact region of the well region 140. Optionally, the third doped region 151 may not be provided.
[0076] An isolation portion 160 extends from the first surface 101a of the semiconductor layer 101 into the drift region 130, and the sidewalls of the isolation portion 160 are adjacent to the well region 140 and the third doped region 151. The material of the isolation portion 160 includes, for example, an oxide layer, a nitride layer, or other high-k dielectric layers. A gate conductor 170 is located in the isolation portion 160, wherein the isolation portion 160 located between the gate conductor 170 and the well region 140 serves as a gate dielectric layer.
[0077] The power device of the first embodiment of this disclosure has a multi-cell structure. Figure 2 Only three cell structures are listed: Cell-1, Cell-2, and Cell-3. Cell-1 is mirror-symmetric to Cell-2, and Cell-2 is mirror-symmetric to Cell-3. Each cell structure includes a first doped region 110, a second doped region 102, a well region 140, a third doped region 151, a fourth doped region 152, and a trench gate structure (including a gate conductor 170 and a gate dielectric layer).
[0078] However, the embodiments disclosed herein are not limited thereto, and those skilled in the art can make other settings for the internal structure, quantity, and symmetry relationship of the cell structure as needed.
[0079] In this embodiment, the first resistor structure 181, the second resistor structure 182, and the diode structure 190 are all located in the isolation portion 160 between the second cell Cell-2 and the third cell Cell-3, and between the gate conductor 170 of the second cell Cell-2 and the gate conductor 170 of the third cell Cell-3. The first resistor structure 181, the second resistor structure 182, the diode structure 190, and the gate conductor 170 are all separated from each other by the isolation portion 160. Optionally, the first resistor structure 181 and the second resistor structure 182 are located on opposite sides of the diode structure 190, thereby increasing the symmetry of the power device. Optionally, at least one of the gate conductor 170, the first resistor structure 181, the second resistor structure 182, and the diode structure 190 is located in different isolation portions 160.
[0080] The diode structure 190 includes a first filling portion 191 and a fifth doped region 192. The first filling portion 191 is of the second doping type, and the fifth doped region 192 is of the first doping type, thereby forming a first diode D1. A first resistor structure 181 is used to form a first resistor R1, and a second resistor structure 182 is used to form a second resistor R2. The resistance value of the first resistor R1 is less than the resistance value of the second resistor R2. The resistance values of the first resistor R1 and the second resistor R2 can be adjusted by adjusting the doping concentration of the first resistor structure 181 and the second resistor structure 182, or by adjusting the dimensions of the first resistor structure 181 and the second resistor structure 182.
[0081] In some preferred embodiments, the first filling portion 191, the first resistive structure 181, the second resistive structure 182, and the gate conductor 170 are made of the same material, for example, polycrystalline silicon.
[0082] In some other embodiments, the materials of the first filling portion 191, the first resistive structure 181, and the second resistive structure 182 may also be SiC.
[0083] However, the embodiments disclosed herein are not limited thereto, and those skilled in the art may make other settings for the materials of the first filling portion 191, the first resistive structure 181, and the second resistive structure 182 as needed.
[0084] The first doped region 110, the second doped region 102, and the well region 140 are used to form the first transistor T1. The second doped region 102, the well region 140, and the third doped region 151 are used to form the second transistor T2 and the third transistor T3. The first transistor T1 is a PNP transistor, the second transistor T2 is an NPN transistor, and the third transistor T3 is an NMOS transistor. The first transistor T1, the second transistor T2, and the third transistor T3 constitute the main IGBT circuit 10. A parasitic diode formed by the well region 140 and the third doped region 151 exists between the base and emitter of the second transistor T2.
[0085] The third doped region 151 on the cathode side of the main IGBT circuit 10 (the side of the power device connected to the second potential V2) is connected to the second potential V2 of the entire device through the first resistor R1, and the third doped region 151 is also connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to the second potential V2 of the entire device; the fourth doped region 152 on the cathode side of the main IGBT circuit 10 is connected to the second potential V2 of the entire device through the second resistor R2.
[0086] Specifically, the emitter of the first transistor T1 is connected to a first potential V1, the base of the first transistor T1 is connected to the collector of the second transistor T2 and the first current terminal of the third transistor T3, the collector of the first transistor T1 is connected to the base of the second transistor T2 and the substrate of the third transistor T3, the emitter of the second transistor T2 is connected to the second current terminal of the third transistor T3, the anode of the first diode D1 is connected to the emitter of the second transistor T2, the cathode of the first diode D1 is connected to the second potential V2, the first resistor R1 is connected in series between the emitter of the second transistor T2 and the second potential V2, and the second resistor R2 is connected in series between the base of the second transistor T2 and the second potential V2. The first and second current terminals of the third transistor T3 can be interchanged (i.e., the drain and source of the third transistor T3 can be interchanged). The working principle of the power device according to the first embodiment of this disclosure will be explained below.
[0087] When the power device is in the blocking state, the potentials of the fourth doped region 152 and the third doped region 151 on the cathode side of the main IGBT circuit 10 are the same as the second potential V2, and the insulation breakdown voltage BV of the power device is the same as that of the main IGBT circuit 10.
[0088] When a high level is applied to the gate G of the power device, the power device turns on as the voltage of the first potential V1 increases. Since the resistance of the first resistor R1 is less than that of the second resistor R2, the potential of the fourth doped region 152 on the cathode side of the main IGBT circuit 10 rises faster than the potential of the third doped region 151. This results in a voltage difference between the potential of the fourth doped region 152 and the potential of the third doped region 151, causing the parasitic diode formed by the well region 140 and the third doped region 151 to turn on. At this time, carriers are injected into the drift region 130 through the conducting parasitic diode and the channel formed by the well region 140 near the gate G side surface, thereby enhancing the conductivity modulation effect in the drift region 130 and reducing the turn-on voltage Von of the power device. As the voltage of the first potential V1 further increases, the potential of the third doped region 151 rises to the turn-on voltage of the first diode D1, thereby turning on the first diode D1. At this time, the potential of the third doped region 151 and the potential of the fourth doped region 152 are clamped, and the current of the entire power device reaches saturation. This saturated current is higher than the saturation current of the IGBT device without the first resistor R1, the second resistor R2 and the first diode D1. Therefore, the power device of this embodiment has stronger driving energy.
[0089] When a short circuit occurs in the external circuit of the power device in this embodiment, causing the power device to be subjected to a large current and high voltage condition, the first diode D1 and the parasitic diode formed by the well region 140 and the third doped region 151 are all turned on. However, the power device will not trigger latch-up and fail. This is because the large power in the power device causes the device temperature to rise continuously, and the carrier mobility of the device decreases, resulting in a decrease in the current in the third doped region 151 and the fourth doped region 152 of the main IGBT circuit 10. The potential of the third doped region 151 decreases slowly with the potential of the first diode D1, and the potential of the fourth doped region 152 decreases rapidly with the first resistor R1, causing the parasitic diode formed by the well region 140 and the third doped region 151 to turn off rapidly. Furthermore, the barrier height of the PN junction of the parasitic diode will continue to increase with temperature, making it even more difficult to turn on.
[0090] In some specific embodiments, the power device (hereinafter referred to as "power device A") of this disclosure is connected in series with an external device B. The normal operating mode of an IGBT device generally involves switching between two states: "gate G off, anode (first potential V1) high voltage off state" and "gate G on (i.e., high current flowing through the IGBT device), anode low voltage on state". However, when the external device B is short-circuited, power device A may experience a situation where the gate G is on and the anode is at a high voltage. For example, if power device A is on with a low anode voltage, and the external device B connected in series is off and under voltage, but the external device B suddenly short-circuits, the voltage drop previously withstood by the external device B will be applied to power device A, causing power device A to experience a "short-circuit state". In this state, power device A is easily burned out by the heat accumulation caused by high power. Therefore, in this state, power device A needs to withstand (buffer) for at least a period of time so that other external circuits can provide corresponding feedback to resolve the short-circuit problem of external device B. Because the power device in this embodiment of the present disclosure is equipped with a first resistor R1, a second resistor R2 and a first diode D1, a longer buffer time can be achieved.
[0091] For IGBT devices without the first resistor R1, the second resistor R2, and the first diode D1, the parasitic diode's barrier height gradually decreases as the temperature rises due to the increased intrinsic excited carrier concentration, causing the parasitic diode to turn on and triggering latch-up, leading to device failure. Therefore, the power devices of this disclosure have strong anti-latch-up capability under high current.
[0092] When a low level is applied to the gate G of the power device, the current flowing through the third doped region 151 decreases, the potential of the third doped region 151 decreases, and the potential of the fourth doped region 152 also decreases. The conductivity modulation effect is weakened, and the power device is eventually turned off.
[0093] Figures 5 to 10 A cross-sectional schematic diagram of a portion of the manufacturing process of a power device according to the first embodiment of this disclosure is shown.
[0094] like Figure 5 As shown, along the direction from the second surface 101b of the semiconductor layer 101 toward the first surface 101a, a first doped region 110, a buffer region 120, a drift region 130 and a well region 140 are formed in the semiconductor layer 101 in sequence.
[0095] Furthermore, a groove 103 is formed in the semiconductor layer 101, such as Figure 6 As shown.
[0096] In this step, for example, an etching process is used to etch the semiconductor layer 101 to form a groove 103 that penetrates the well region 140. The etching stops near the drift region 130, so that the bottom surface of the groove 103 is located in the drift region 130.
[0097] Furthermore, an isolation portion 160 is formed in the groove 103, such as... Figure 7 As shown.
[0098] Furthermore, a gate conductor 170, a first resistor structure 181, a second resistor structure 182, and a first filling portion 191 are formed in the isolation portion 160, as follows: Figure 8 As shown.
[0099] In this step, for example, an etching process is used to form multiple trenches in the isolation portion 160, and then a gate conductor 170, a first resistor structure 181, a second resistor structure 182 and a first filling portion 191 are formed in different trenches.
[0100] Optionally, the first resistor structure 181 and the second resistor structure 182 are symmetrically arranged on both sides of the first filling portion 191, and the two gate conductors 170 are symmetrically arranged on both sides of the first filling portion 191, thereby increasing the overall symmetry of the device.
[0101] Optionally, the gate conductor 170, the first resistor structure 181, the second resistor structure 182, and the first filling portion 191 are made of the same material and can be formed in the same step. Therefore, when manufacturing power devices, it is not necessary to design additional photomasks for the first resistor structure 181, the second resistor structure 182, and the first filling portion 191, which is compatible with the original process and saves manufacturing costs.
[0102] Furthermore, a fourth doped region 152 is formed in the well region 130, and a fifth doped region 192 is formed in the first filled portion 191, as follows: Figure 9 As shown.
[0103] In this step, the fourth doped region 152 and the fifth doped region 192 are formed simultaneously, so that when manufacturing power devices, there is no need to design an additional mask for the fifth doped region 192, which is compatible with the original process and saves manufacturing costs.
[0104] Furthermore, a third doped region 151 is formed in the well region 140, such as... Figure 10 As shown. The step of forming the third doped region 151 can be interchanged with the steps of forming the fourth doped region 152 and the fifth doped region 192.
[0105] The power device of the first embodiment of this disclosure adjusts the potential of different regions in the power device by setting additional dual resistors and diodes, thereby reducing the on-state voltage drop of the power device and improving its anti-latch-up capability.
[0106] Furthermore, since no additional carrier storage layer is introduced to increase the doping concentration by forming a dual-resistance structure and / or diode structure outside the doped region of the semiconductor layer, the breakdown voltage BV of the power device will not be degraded.
[0107] Furthermore, the first resistor structure, the second resistor structure, and the diode structure are all formed in the isolation section and integrated with the IGBT main circuit in the same device (integrated in the same semiconductor layer), thereby reducing the adverse effects of noise and RC delay caused by external interconnects.
[0108] Furthermore, the first resistor structure, the second resistor structure, the diode structure, and the gate conductor share the same isolation section, which can save the space occupied by the isolation section and increase the utilization rate of the device per unit area.
[0109] Furthermore, no floating P-type doped region is provided in this embodiment. Because a floating P-type doped region exhibits carrier storage during device switching, leading to local potential changes, this causes gate charging and discharging via displacement current. This displacement current not only reduces the device switching frequency (effectively increasing the gate capacitance area) but also subjectes the device to greater dV / dt stress, thus reducing device reliability. In this embodiment, however, no floating P-type doped region is provided. Instead, the area between the cell trench gate structure is first filled with an isolation portion, and then a resistor and diode structure are fabricated within the isolation portion. This effectively reduces the gate capacitance and significantly lowers the risk of displacement current charging the gate. Therefore, this solution also possesses high resistance to dV / dt stress.
[0110] Figure 11 A schematic diagram of the structure of a power device according to a second embodiment of the present disclosure is shown.
[0111] like Figure 11 As shown, the similarities between the power device of the second embodiment and the first embodiment will not be repeated here, but can be found in the references. Figures 1 to 10 The difference lies in that the diode structure in this embodiment is a Schottky diode formed by the contact between the first filling portion 191 and the metal layer 193, wherein the metal layer 193 is located on the surface of the first filling portion 191.
[0112] Figure 12 A schematic diagram of the power device according to the third embodiment of this disclosure is shown.
[0113] like Figure 12 As shown, the similarities between the power device of the third embodiment and the first embodiment will not be repeated here, but can be found in the references. Figures 1 to 10The difference lies in that, between the third doped region 151 of the two cell structures, the two gate conductors 170 and the diode structure 190 are located in different isolation portions 160. A thin isolation portion 160 is also formed on the first surface of the semiconductor layer 101 between the diode structure 190 and the two gate conductors 170, and the first resistor structure 181 and the second resistor structure 182 are located on the thin isolation portion 160.
[0114] Optionally, the semiconductor layer 101 further includes a sixth doped region 104 located between two adjacent isolation regions 160, wherein the doping type of the sixth doped region 104 may be the same as or opposite to the doping type of the well region 140.
[0115] In some specific embodiments, when the well region 140 is P-type, the sixth doped region 104 is N-type. Since the N-type sixth doped region 104 accumulates fewer net holes during the power device conduction process, the floating region potential rises less, and the gate G displacement current charging is also less, thus enabling the power device to have high resistance to dV / dt stress.
[0116] In some other embodiments, the first diode D2 may be disposed outside the semiconductor layer 101.
[0117] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A power device, comprising: A semiconductor layer having opposing first and second surfaces, the semiconductor layer comprising a first doped region, a second doped region, a well region and a third doped region sequentially adjacent to each other along the direction from the second surface toward the first surface; An isolation region extends from the first surface of the semiconductor layer into the second doped region and is adjacent to the well region and the third doped region; as well as The gate conductor is located in the isolation section. The first doped region and the well region are of a first doping type, and the second doped region and the third doped region are of a second doping type. The first doping type is the opposite of the second doping type. The power device further includes: a first resistor structure, a second resistor structure, and a first diode structure, wherein the first resistor structure constitutes a first resistor, the second resistor structure constitutes a second resistor, and the diode structure constitutes a first diode. The first terminal of the first resistor is electrically connected to the third doped region, the second terminal of the first resistor is electrically connected to the cathode of the first diode and the first terminal of the second resistor, the anode of the first diode is electrically connected to the third doped region, and the second terminal of the second resistor is electrically connected to the well region. The resistance of the first resistor is less than the resistance of the second resistor.
2. The power device according to claim 1, wherein, The first doped region, the second doped region, and the well region are used to form the first transistor. The second doped region, the well region, and the third doped region are used to form the second transistor and the third transistor. The first transistor is a PNP transistor, the second transistor is an NPN transistor, and the third transistor is an NMOS transistor. The emitter of the first transistor is connected to a first potential, the base of the first transistor is connected to the collector of the second transistor and the first current terminal of the third transistor, the collector of the first transistor is connected to the base of the second transistor and the substrate of the third transistor, and the emitter of the second transistor is connected to the second current terminal of the third transistor. The anode of the first diode is connected to the emitter of the second transistor, and the cathode of the first diode is connected to the second potential. The first resistor is connected in series between the emitter of the second transistor and the second potential. The second resistor is connected in series between the base of the second transistor and the second potential.
3. The power device according to claim 1, wherein, The semiconductor layer further includes a fourth doped region adjacent to the well region, and the second terminal of the second resistor is electrically connected to the fourth doped region. The fourth doped region is of the first doping type.
4. The power device according to claim 1, wherein, The gate conductor, the first resistor structure, the second resistor structure, and the diode structure are located in the same isolation section; Alternatively, at least one of the gate conductor, the first resistor structure, the second resistor structure, and the diode structure may be located in different isolation portions.
5. The power device according to claim 1, wherein, The diode structure includes a first filling portion extending from the surface of the isolation portion into the isolation portion.
6. The power device according to claim 5, wherein, The diode structure further includes a fifth doped region extending from the surface of the first filled portion into the first filled portion. The fifth doped region is of the first doping type, and the first filling portion is of the second doping type.
7. The power device according to claim 5, wherein, The diode structure further includes a metal layer located on the surface of the first filling portion. The first filling portion, in contact with the metal layer, constitutes a Schottky diode.
8. The power device according to any one of claims 5 to 7, wherein, The first resistive structure extends from the surface of the isolation portion into the isolation portion, or the first resistive structure is located on the surface of the isolation portion; The second resistor structure extends from the surface of the isolation portion into the isolation portion, or the second resistor structure is located on the surface of the isolation portion.
9. The power device according to claim 8, wherein, The material of the first filling portion and / or the first resistive structure and / or the second resistive structure is the same as the material of the gate conductor.
10. A method for manufacturing a power device, comprising: Along the direction from the second surface of the semiconductor layer toward the first surface, a first doped region, a second doped region, a well region, and a third doped region are formed in the semiconductor layer in sequence. An isolation portion is formed in the semiconductor layer, the isolation portion extending from the first surface into the second doped region and adjacent to the well region and the third doped region; as well as A gate conductor is formed in the isolation section. The first doped region and the well region are of a first doping type, and the second doped region and the third doped region are of a second doping type. The first doping type is the opposite of the second doping type. The manufacturing method further includes: forming a first resistor structure, a second resistor structure, and a diode structure. The first resistor structure is used to form a first resistor, the second resistor structure is used to form a second resistor, and the diode structure is used to form a first diode. The first end of the first resistor is electrically connected to the third doped region, the second end of the first resistor is electrically connected to the cathode of the first diode and the first end of the second resistor, the anode of the first diode is electrically connected to the third doped region, and the second end of the second resistor is electrically connected to the well region.
11. The manufacturing method according to claim 10, wherein, The step of forming the diode structure includes: forming a first filling portion in the isolation portion, The first filling portion is formed in the same step as the gate conductor.
12. The manufacturing method according to claim 10 or 11, wherein, The first resistor structure and / or the second resistor structure are formed in the same step as the gate conductor.
13. The manufacturing method of claim 11, further comprising forming a fourth doped region in the semiconductor layer, the fourth doped region extending from the first surface toward the second surface and adjacent to the well region. The steps for forming the diode structure further include: A fifth doped region is formed in the first filled portion. The fourth and fifth doped regions are of the first doping type, and the first filling portion is of the second doping type. The fourth doped region is formed in the same step as the fifth doped region.