Display device

Abstract

The invention relates to a display device. The display device includes first and second circuit boards connected to a display panel, the display panel defining a display area and a non-display area, and including a first sub-base layer overlapping the display area and the non-display area, a second sub-base layer overlapping the display area and the non-display area, a connection electrode and a pad electrode, and a circuit layer. The second sub-base layer is over the first sub-base layer, the connection electrode is between the first sub-base layer and the second sub-base layer and is electrically connected to the signal line, and the pad electrode is exposed through an opening in the first sub-base layer, is electrically connected to the connection electrode, and includes a first pad electrode and a second pad electrode, the first pad electrode is electrically connected to the first circuit board and extends in a direction, the second pad electrode is electrically connected to the second circuit board, is spaced apart from the first pad electrode in the direction, and extends in an opposite direction, and the circuit layer includes a transistor and at least one signal line connected to the transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display device, a rear surface of which may be coupled to a circuit board. Background Art

[0002] Electronic devices such as smart phones, tablet computers, laptop computers, vehicle navigation systems, and smart TVs have been developed. These electronic devices are equipped with display devices to provide information.

[0003] Various types of display devices have been developed to satisfy user experience (UX) / user interface (UI) of users. Display devices have been developed to provide a wide display area and a narrow non-display area. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device having a reduced non-display area.

[0005] According to one or more embodiments, a display device includes a first circuit board, a second circuit board and a display panel, the display panel is electrically connected to the first circuit board and the second circuit board, defines a display area and a non-display area, and includes a base layer and a circuit layer, the base layer includes a first sub-base layer, a second sub-base layer, a connecting electrode and a pad electrode, the first sub-base layer overlaps the display area and the non-display area, the second sub-base layer is above the first sub-base layer, the connecting electrode is between the first sub-base layer and the second sub-base layer and is electrically connected to the signal line, the pad electrode is exposed through an opening defined in the first sub-base layer, is electrically connected to the connecting electrode, and includes a first pad electrode and a second pad electrode, the first pad electrode is electrically connected to the first circuit board and extends in a first direction, the second pad electrode is electrically connected to the second circuit board, is spaced apart from the first pad electrode in the first direction, and extends in a direction opposite to the first direction, the circuit layer is above the base layer and includes a transistor and at least one signal line connected to the transistor.

[0006] The first circuit board may include a first base film and a first bump electrode over the first base film, wherein the second circuit board includes a second base film and a second bump electrode over the second base film.

[0007] The first circuit board may include a first base film and a first bump electrode over the first base film, wherein the second circuit board includes a second base film and a second bump electrode over the second base film and facing the first bump electrode in the first direction.

[0008] The first pad electrodes may contact the first bump electrodes, respectively, wherein the second pad electrodes contact the second bump electrodes, respectively.

[0009] The first bump electrode may include a first contact portion extending beyond an edge of the first base film, wherein the second bump electrode includes a second contact portion extending beyond an edge of the second base film.

[0010] The display device may also include: a first metal pattern electrically connecting the first bump electrode and the first pad electrode; and a second metal pattern electrically connecting the second bump electrode and the second pad electrode, wherein the first metal pattern contacts the first pad electrode and the first contact portion, and wherein the second metal pattern contacts the second pad electrode and the second contact portion.

[0011] The display device may further include: a first adhesive layer between the first bump electrode and the first pad electrode; and a second adhesive layer between the second bump electrode and the second pad electrode.

[0012] The first pad electrode may include: a first main portion overlapping the first bump electrode in a plane; and a first extension portion not overlapping the first bump electrode in a plane and extending from the first main portion, wherein the second pad electrode includes: a second main portion overlapping the second bump electrode in a plane; and a second extension portion not overlapping the second bump electrode in a plane and extending from the second main portion.

[0013] The first main portion and the second main portion may face each other in a first direction, and may be arranged in a second direction substantially perpendicular to the first direction.

[0014] The first extending portions and the second extending portions may be alternately arranged in the second direction.

[0015] The first extending portion and the second extending portion may partially overlap each other in the second direction.

[0016] Respective widths of the first extension portion and the second extension portion may decrease along the first direction.

[0017] The first circuit board may include a bent portion bent toward a lower side of the display panel, wherein a portion of the first circuit board overlaps the second circuit board in a plane.

[0018] The first pad electrode and the second pad electrode may overlap the non-display area.

[0019] The display device may further include an insulating layer between the pad electrode and the connecting electrode, the pad electrode and the connecting electrode being electrically connected through a contact hole defined by the insulating layer.

[0020] The display device may further include a connection pattern penetrating a portion of the base layer, wherein the signal line is over an upper surface of the second sub base layer and is electrically connected to corresponding ones of the pad electrodes through the connection pattern.

[0021] According to one or more embodiments, a display device includes a display panel and a first circuit board and a second circuit board, the display panel defines a display area and a non-display area, the first circuit board is electrically connected to the display panel, the second circuit board is electrically connected to the display panel and is spaced apart from the first circuit board in a first direction, wherein the display panel includes a base layer and a circuit layer, the base layer includes a first sub-base layer, a second sub-base layer, a connecting electrode and a pad electrode, the first sub-base layer overlaps the display area and the non-display area, the second sub-base layer is above the first sub-base layer, the connecting electrode is between the first sub-base layer and the second sub-base layer and is electrically connected to the signal line, the pad electrode is exposed through an opening defined in the first sub-base layer, is electrically connected to the connecting electrode and includes a first pad electrode and a second pad electrode, the first pad electrode overlaps the first circuit board and does not overlap the second circuit board, the second pad electrode overlaps the second circuit board and does not overlap the first circuit board, at least one of the second pad electrodes faces at least one of the first pad electrodes in a second direction substantially perpendicular to the first direction, and the circuit layer is above the base layer and includes a transistor and at least one signal line connected to the transistor.

[0022] The first pad electrode and the second pad electrode may be spaced apart from each other in the first direction.

[0023] The first pad electrode may include: a first main portion overlapping the first circuit board in a plane; and a first extension portion not overlapping the first circuit board in a plane and extending from the first main portion, wherein the second pad electrode includes: a second main portion overlapping the second circuit board in a plane; and a second extension portion not overlapping the second circuit board in a plane and extending from the second main portion.

[0024] The first extending portions and the second extending portions may be alternately arranged in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0026] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0027] Figure 2 is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0028] Figure 3 It is along Figure 2 A cross-sectional view of the display device taken along line II'.

[0029] Figure 4is a schematic cross-sectional view of a display module according to one or more embodiments of the present disclosure.

[0030] Figure 5 is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0031] Figure 6 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure.

[0032] Fig. 7A is an enlarged view of a portion of a display device according to the present disclosure.

[0033] Figure 7B It is along Fig. 7A A cross-sectional view of the display module taken along line II-II'.

[0034] Fig. 8A is an enlarged view of a portion of a display device according to the present disclosure.

[0035] Figure 8B is an enlarged view of a portion of a display device according to the present disclosure.

[0036] Fig. 9 is an enlarged view of a portion of a display device according to the present disclosure.

[0037] Fig. 10A It is along Fig. 9 2 is a cross-sectional view of the display module taken along line III-III'.

[0038] Fig. 10B It is along Fig. 9 A cross-sectional view of the display module taken along line IV-IV'.

[0039] Fig. 10C yes Fig. 10A Magnified view of area AA'. DETAILED DESCRIPTION

[0040] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for implementing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, processes, elements and techniques that are redundant, irrelevant or unrelated to the description of the embodiments, or are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, in all drawings and written descriptions, the same figure numerals, marks or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0041] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments described herein. The use of "may", "can" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interconnections and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented in association.

[0042] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0043] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shapes illustrated, such as due to manufacturing techniques and / or tolerances, should be expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but should include deviations in shapes such as those caused by manufacturing.

[0044] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0045] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc. can be used in this article to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as "below", "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device can be oriented in addition (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged at the upper or lower side of the second part, without being limited to the upper side of the second part based on the direction of gravity.

[0046] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross section taken by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "not overlap" may include meanings such as "spaced apart from each other" or "offset from each other" or "separated from each other" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "face" and "facing" may mean that the first object may be directly opposite or indirectly opposite to the second object. In the case where a third object is inserted between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0047] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component, or is directly on another component, without the presence of intervening components.

[0048] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" another part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components (such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to...") can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0049] For the purposes of this disclosure, expressions such as "at least one of" or "any of" or "one or more of" when following an element of a list modify the elements of the entire list without modifying the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as, for example, XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases when following an element of a list modify the elements of the entire list without modifying the individual elements of the list.

[0050] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish between elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0051] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0052] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are intended to also include the singular forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0053] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of +5% / -5% of the corresponding value. In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the values ​​and mean within an acceptable deviation range for a particular value determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0055] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0056] Figure 2 is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0057] Figure 3 It is along Figure 2 A cross-sectional view of the display device taken along line II'.

[0058] refer to Figure 1 The electronic device ED according to one or more embodiments of the present disclosure may include a display surface DS defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The electronic device ED may provide an image IM to a user through the display surface DS.

[0059] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may be an area where an image IM is displayed, and the non-display area NDA may be an area where the image IM is not displayed. The non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the shape of the display area DA and the shape of the non-display area NDA may be modified.

[0060] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The third direction DR3 is used as a criterion for distinguishing the front surface and the rear surface of each of the members. In this specification, the wording "on a plan view" may be defined as a state in which the display device DD is observed on the third direction DR3.

[0061] In one or more embodiments of the present disclosure, the electronic device ED may be a foldable electronic device that can be folded around a folding axis. The folding axis may be parallel to the first direction DR1 or the second direction DR2, and the folding area may be defined in a portion of the display area DA. The electronic device ED may be folded inwardly so that the display areas DA face each other, or may be folded outwardly so that the display areas DA are folded away from each other.

[0062] like Figure 2 As shown in FIG. , the electronic device ED may include a display device DD, an electronic module EM, a power supply module PSM and a housing HM. Figure 2 The electronic device ED is briefly shown, and may further include a mechanical structure (eg, a hinge) for controlling the operation (eg, folding or rolling) of the display device DD.

[0063] The display device DD generates an image IM and detects an external input. The display device DD includes a window WM, an upper member UM, a display module DM, a lower member LM, flexible circuit boards FCB1 and FCB2, and driver integrated circuits DIC1 and DIC2. The upper member UM includes a member arranged on the display module DM, and the lower member LM includes a member arranged under the display module DM.

[0064] The window WM provides a front surface of the electronic device ED. The window WM includes a transmissive area TA and a bezel area BZA. Figure 1The display area DA and the non-display area NDA of the display surface DS shown in FIG. 4 may be defined by a transmissive area TA through which an image IM passes, and a bezel area BZA covering a structure / member located under the window WM.

[0065] The display module DM includes corresponding Figure 1 In the present specification, the expression "region / portion and region / portion correspond to each other" means that the region / portion and region / portion overlap each other and are not limited to the same area.

[0066] The pad area PA is located on one side of the non-display area DM-NDA. The pad area PA is an area electrically coupled (or connected) to the flexible circuit boards FCB1 and FCB2 to be described below. In one or more embodiments, the pad area PA is defined on the rear surface of the display module DM.

[0067] The display module DM has a substantially quadrilateral shape. Here, the "substantially quadrilateral shape" includes not only a quadrilateral shape in a mathematical sense, but also a shape similar to a quadrilateral shape that can be recognized as a quadrilateral shape by a user. For example, the substantially quadrilateral shape may include a quadrilateral shape with a rounded corner area. In addition, in the substantially quadrilateral shape, the edge of the display module DM is not limited to a straight shape, and the edge may include a curved area.

[0068] The upper member UM may include a protective film or an optical film. The optical film may include a polarizer and a retarder to reduce the reflection of external light. The lower member LM may include a protective film for protecting the display module DM, a supporting member for supporting the display module DM, a digitizer, etc. The upper member UM and the lower member LM will be described in detail below.

[0069] The flexible circuit boards FCB1 and FCB2 may include a first flexible circuit board (or first circuit board) FCB1 and a second flexible circuit board (or second circuit board) FCB2. The first flexible circuit board FCB1 and the second flexible circuit board FCB2 are located under the display module DM. The first flexible circuit board FCB1 and the second flexible circuit board FCB2 may be coupled to the rear surface of the display module DM. The first flexible circuit board FCB1 electrically connects the display module DM and the first main circuit board MCB1 (see Figure 3 ), and the second flexible circuit board FCB2 is electrically connected to the display module DM and the second main circuit board MCB2 (see Figure 3 ). The first flexible circuit board FCB1 and the second flexible circuit board FCB2 include at least one insulating layer and at least one conductive layer. The conductive layer may include a plurality of signal lines.

[0070] The driver integrated circuits DIC1 and DIC2 may include a first driver integrated circuit DIC1 and a second driver integrated circuit DIC2. The first driver integrated circuit DIC1 may be mounted on a first flexible circuit board FCB1. The second driver integrated circuit DIC2 may be mounted on a second flexible circuit board FCB2. The first driver integrated circuit DIC1 and the second driver integrated circuit DIC2 may include a driving circuit for driving pixels of the display module DM, for example, a data driving circuit. Figure 2 A structure is shown in which the driver integrated circuits DIC1 and DIC2 are mounted on the flexible circuit boards FCB1 and FCB2, but the present disclosure is not limited thereto. For example, the driver integrated circuits DIC1 and DIC2 may be mounted on the display module DM or the main circuit board.

[0071] The electronic module EM may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, etc. The electronic module EM may include a main circuit board, and the module may be mounted on the main circuit board or may be electrically connected to the main circuit board through a flexible circuit board. The electronic module EM is electrically connected to the power supply module PSM.

[0072] In one or more embodiments, the electronic device ED may further include an electro-optical module. The electro-optical module may be an electronic component that outputs or receives an optical signal. The electro-optical module may include a camera module and / or a proximity sensor. The camera module may capture an external image through a portion of the display module DM.

[0073] Figure 2 The housing HM shown in FIG. 1 is coupled to a display device DD (eg, a window WM) to accommodate other modules. The housing HM is shown to have an integral shape, but the present disclosure is not limited thereto. The housing HM may include a plurality of portions (eg, side edge portions and a bottom portion) coupled to each other.

[0074] refer to Figure 3 The window WM may include a base substrate BS and a frame pattern BM located on the lower surface (e.g., below) of the base substrate BS. The base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multi-layer structure. The base substrate BS may include a thin film glass substrate, a protective film located on (e.g., above) the thin film glass substrate, and an adhesive layer bonding the thin film glass substrate and the protective film.

[0075] The frame pattern BM as a colored light shielding film can be formed by, for example, a coating method. The frame pattern BM may include a base material and a dye or pigment mixed with the base material. Figure 1 The non-display area NDA and Figure 2The frame area BZA shown in the figure overlaps. The frame pattern BM may be located on the lower surface of the base substrate BS. When the base substrate BS has a multi-layer structure, the frame pattern BM may be located between interfaces defined by multiple layers. For example, the frame pattern BM may be located between the thin film glass substrate and the protective film. In one or more embodiments, the window WM may also include at least one of a hard coating layer, an anti-fingerprint layer, and an anti-reflection layer on the upper surface of the base substrate BS.

[0076] The upper member UM may include an upper film. The upper film may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, triacetyl cellulose, polymethyl methacrylate, or polyethylene terephthalate.

[0077] The upper film can absorb external impact applied to the front surface of the display device DD. In one or more embodiments of the present disclosure, the display module DM may include a color filter instead of a polarizing film as an anti-reflection member, and thus, the front impact strength of the display device DD may be reduced. The upper film may compensate for the reduced impact strength by applying a color filter.

[0078] The upper member UM overlaps the frame area BZA and the transmission area TA. The upper member UM may overlap only a portion of the frame area BZA. Another portion of the frame pattern BM may be exposed from the upper member UM. In one or more embodiments of the present disclosure, the upper member UM may be omitted. In one or more embodiments of the present disclosure, the upper member UM may be replaced with an optical film including a polarizer and a retarder.

[0079] In one or more embodiments, an adhesive layer bonding the upper member UM and the window WM may be further included between the upper member UM and the window WM. The adhesive layer may be a pressure sensitive adhesive (PSA) film or an optically clear adhesive (OCA) member.

[0080] The display module DM is located under the upper member UM. The display module DM overlaps the frame area BZA and the transmission area TA. The display module DM may completely overlap the upper member UM within the frame area BZA. The side surface of the display module DM may be aligned with the side surface of the upper member UM, and the edge of the display module DM may be aligned with the edge of the upper member UM on a plane.

[0081] The pad area PA of the display module DM within the bezel area BZA may overlap with the upper member UM. A portion of the display module DM corresponding to the pad area PA may be bonded to the lower surface of the upper member UM through an adhesive layer. The pad area PA overlaps with the upper member UM, and a portion of the display module DM overlapping with the pad area PA is coupled to the upper member UM. Therefore, when the flexible circuit boards FCB1 and FCB2 are bonded to the pad area PA, the upper member UM may fully support the pad area PA.

[0082] The lower member LM may include a lower film PF and a cover panel CP. In one or more embodiments of the present disclosure, the lower member LM may further include a support plate and a digitizer.

[0083] The lower film PF may expose or may define the pad area PA of the display module DM. The lower film PF may have a size smaller than that of the display module DM. For example, the lower film PF may overlap only with the display area DM-DA of the display module DM. An opening area PF-OP corresponding to the non-display area DM-NDA may be defined in the lower film PF. Alternatively, the lower film PF may have a size substantially corresponding to the display module DM. In this case, an opening area PF-OP corresponding to the pad area PA may be defined in the lower film PF. The pad area PA may be exposed through the opening area PF-OP.

[0084] The lower film PF may expose the pad area PA. The lower film PF may have an area smaller than that of the display module DM. For example, the lower film PF may overlap only with the display area DA. The lower film PF may have an area substantially the same as that of the display module DM. An opening area PF-OP corresponding to the pad area PA may be defined in the lower film PF. The pad area PA may be exposed through the opening area PF-OP.

[0085] The cover panel CP may be located below the lower film PF. The cover panel CP may increase resistance to compressive forces generated by external pressure. Therefore, the cover panel CP may be used to reduce or prevent deformation of the display module DM. The cover panel CP may include a flexible plastic material such as polyimide or polyethylene terephthalate. In addition, the cover panel CP may be a colored film with low light transmittance. The cover panel CP may absorb light beams input from the outside. For example, the cover panel CP may be a black synthetic resin film. When the display device DD is observed from the front side of the window WM, the components arranged under the cover panel CP may not be visually recognized by the user.

[0086] The support plate may be further located under the cover panel CP. The support plate may include a metal material having relatively high strength. The support plate may also include a reinforced fiber composite material. The support plate may include reinforcing fibers located in the base portion. The reinforcing fibers may be carbon fibers or glass fibers. The base portion may include a polymer resin. The base portion may include a thermoplastic resin. For example, the base portion may include a polyamide-based resin or a polypropylene-based resin. For example, the reinforced fiber composite material may be a carbon fiber reinforced plastic (CFRP) or a glass fiber reinforced plastic (GFRP).

[0087] The first main circuit board MCB1 may be located on the lower surface (e.g., below) of the first flexible circuit board FCB1. The second main circuit board MCB2 may be located on the lower surface of the second flexible circuit board FCB2. Each of the first flexible circuit board FCB1 and the second flexible circuit board FCB2 may include an insulating film and a conductive wiring line mounted on the insulating film. Each of the first main circuit board MCB1 and the second main circuit board MCB2 may include a signal line and an electronic component. The electronic component may be connected to the signal line and electrically connected to the display module DM. The electronic component generates various electrical signals (e.g., a signal for generating an image IM or a signal for detecting an external input), or processes a detected signal. Meanwhile, a single first main circuit board MCB1 and a single second main circuit board MCB2 may be arranged to correspond to each of the electrical signals for generation and processing, and three or more first main circuit boards MCB1 and / or three or more second main circuit boards MCB2 may be arranged, but the present disclosure is not limited thereto.

[0088] In one or more embodiments, the first main circuit board MCB1 may include a first driver integrated circuit DIC1 (see FIG. 1 ) mounted inside the first main circuit board MCB1. Figure 2 ), and the second main circuit board MCB2 may include a second driver integrated circuit DIC2 mounted inside the second main circuit board MCB2 (see Figure 2 ).

[0089] The first flexible circuit board FCB1 may include a bending portion BAP. In detail, the bending portion BAP may be bent toward the lower side of the display module DM around a bending axis parallel to the first direction DR1. By bending the bending portion BAP, the first flexible circuit board FCB1 may overlap a portion of the second flexible circuit board FCB2 on a plane.

[0090] refer to Figure 2 and Figure 3 , the flexible circuit boards FCB1 and FCB2 are bonded to the rear surface of the display module DM (rear surface bonding). Since the non-display area DM-NDA of the display module DM is not bent, defects in the non-display area DM-NDA of the display module DM during bending can be reduced or prevented. In addition, the area of ​​the bezel area BZA of the window WM for covering the non-display area DM-NDA of the display module DM can be reduced.

[0091] Figure 4 is a schematic cross-sectional view of a display module according to one or more embodiments of the present disclosure.

[0092] refer to Figure 4, the display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may include a display area and a non-display area corresponding to a display area DM-DA and a non-display area DM-NDA of the display module DM, respectively. The display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-ED, and an encapsulation layer TFE.

[0093] The circuit layer DP-CL is located on the upper surface (e.g., above) of the base layer BL. The base layer BL may be a flexible substrate that can be bent, folded, and curled. The base layer BL may be a glass substrate, a metal substrate, a polymer substrate, etc. However, one or more embodiments of the present disclosure are not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. Basically, the base layer BL has the same shape as that of the display panel DP.

[0094] The base layer BL may have a multi-layer structure. For example, the base layer BL may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer therebetween. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, but the present disclosure is not limited thereto.

[0095] The circuit layer DP-CL may be located on the base layer BL. The circuit layer DP-CL may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and signal lines. The circuit layer DP-CL may include a driving circuit for a pixel. Hereinafter, unless otherwise specified, when component A and component B are arranged on the same layer, it is understood that component A and component B are formed by the same process and therefore include the same material or have the same stacked structure. Conductive patterns or semiconductor patterns arranged on the same layer may be explained as described above.

[0096] The display element layer DP-ED may be located on the circuit layer DP-CL. The display element layer DP-ED may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro light emitting diode (LED), or a nano LED.

[0097] The encapsulation layer TFE may be located on the display element layer DP-ED. The encapsulation layer TFE may protect the display element layer DP-ED (i.e., the light emitting element) from moisture, oxygen, and foreign matter such as dust particles. The encapsulation layer TFE may include at least one inorganic encapsulation layer. The encapsulation layer TFE may include a stacked structure of a first inorganic encapsulation layer / an organic encapsulation layer / a second inorganic encapsulation layer.

[0098] The input sensing layer ISL may be directly located on the display panel DP. The input sensing layer ISL may detect the user's input using, for example, an electromagnetic induction method or a capacitive method. The display panel DP and the input sensing layer ISL may be formed by a continuous process. Here, the aspect that the input sensing layer ISL is directly located on the display panel DP may mean that a third component is not located between the input sensing layer ISL and the display panel DP. That is, a separate adhesive layer may not be located between the input sensing layer ISL and the display panel DP.

[0099] Figure 5 is a plan view of a display panel according to one or more embodiments of the present disclosure. Figure 6 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure.

[0100] like Figure 5 As shown in FIG. 1 , the display panel DP may include a scan drive circuit SDC, a plurality of signal lines SGL, and a plurality of pixels PX. The plurality of pixels PX are arranged in the display area DM-DA. Each of the pixels PX includes a light emitting element and a pixel drive circuit connected to the light emitting element. The scan drive circuit SDC, the plurality of signal lines SGL, and the pixel drive circuit may include Figure 4 The circuit layer DP-CL is shown in FIG.

[0101] The scan drive circuit SDC may include a gate drive circuit. The gate drive circuit generates a plurality of scan signals and sequentially outputs the plurality of scan signals to a plurality of scan lines GL to be described below. The scan drive circuit SDC may also include a light emitting drive circuit separate from the gate drive circuit. The light emitting drive circuit may output scan signals to scan lines of another group.

[0102] The scan driving circuit SDC may include a plurality of thin film transistors formed by the same process as that of the pixel driving circuit (eg, a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process).

[0103] The plurality of signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the scan lines GL is connected to a corresponding pixel PX among the plurality of pixels PX, and each of the data lines DL is connected to a corresponding pixel PX among the plurality of pixels PX. The power lines PL are connected to the plurality of pixels PX. The data lines DL provide data signals to the pixels PX. The control signal lines CSL may provide control signals to the scan drive circuit SDC.

[0104] A plurality of power lines PL may be provided. For example, the power lines PL may include a first power line receiving a first power voltage and a second power line receiving a second power voltage having a level higher than that of the first power voltage. The first power voltage is provided to the pixel PX through the first power line, and the second power voltage is provided to the pixel PX through the second power line. Figure 5 Although one control signal line CSL is shown in FIG. 1 , a plurality of control signal lines CSL may be provided.

[0105] The scan line GL, the data line DL, and the power line PL may overlap the display area DM-DA and the non-display area DM-NDA, and the control signal line CSL may overlap the non-display area DM-NDA. The distal ends of the plurality of signal lines SGL may be aligned on one side of the non-display area DM-NDA. The plurality of signal lines SGL may have an integral shape, but may include a plurality of parts arranged on different layers. The different parts divided by the insulating layer may be connected by contact holes passing through the insulating layer. For example, the data line DL may include a first part located in the display area DM-DA and a second part located in the non-display area DM-NDA at a layer different from that of the first part. The first part and the second part may include different materials and have different stacked structures.

[0106] The plurality of signal lines SGL may be electrically connected to the pad area PA. Figure 3 The main circuit boards MCB1 and MCB2 are shown in FIG.

[0107] Figure 6 Shows the corresponding Figure 5 FIG. 5 is a cross section of a display module DM of a pixel PX.

[0108] The pixel driving circuit PC driving the light emitting element LD may include a plurality of pixel driving elements. The pixel driving circuit PC may include a plurality of transistors S-TFT and O-TFT and a capacitor Cst. The plurality of transistors S-TFT and O-TFT may include a silicon transistor S-TFT and an oxide transistor O-TFT. Figure 6 A silicon transistor S-TFT and an oxide transistor O-TFT are shown. Figure 6 The pixel driving circuit PC is merely one or more embodiments, and the configuration of the pixel driving circuit PC is not necessarily limited thereto. The pixel driving circuit PC may include only one type of transistor of a silicon transistor S-TFT and an oxide transistor O-TFT.

[0109] refer to Figure 6, the base layer BL is shown as a single layer. The base layer BL may include a synthetic resin such as polyimide. The base layer BL may be formed by coating a working substrate (or a carrier substrate) with a synthetic resin layer. When the display module DM is completed through subsequent processes, the working substrate may be removed.

[0110] refer to Figure 6 , the barrier layer BRL may be located on the base layer BL (as used below, "located on" may mean "above"). The barrier layer BRL reduces or prevents foreign matter from flowing in from the outside. The barrier layer BRL may include at least one inorganic layer. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0111] The barrier layer BRL may include a lower barrier layer BRL1 and an upper barrier layer BRL2. The first shielding electrode BML1 may be located between the lower barrier layer BRL1 and the upper barrier layer BRL2. The first shielding electrode BML1 may correspond to a silicon transistor S-TFT. The first shielding electrode BML1 may include a metal, such as molybdenum.

[0112] The first shielding electrode BML1 may receive a bias voltage. The first shielding electrode BML1 may also receive a first power voltage. The first shielding electrode BML1 may reduce or prevent the possibility of an electric potential due to a polarization phenomenon affecting the silicon transistor S-TFT. The first shielding electrode BML1 may reduce or prevent the possibility of an external light beam reaching the silicon transistor S-TFT. In one or more embodiments of the present disclosure, the first shielding electrode BML1 may also be a floating electrode isolated from other electrodes or wiring lines.

[0113] The buffer layer BFL may be located on the barrier layer BRL. The buffer layer BFL may reduce or prevent metal atoms or impurities from diffusing from the base layer BL to the first semiconductor pattern SC1. The buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0114] The first semiconductor pattern SC1 may be located on the buffer layer BFL. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 may include low temperature polycrystalline silicon.

[0115] The first semiconductor pattern SC1 may have different electrical properties depending on whether the first semiconductor pattern SC1 is doped. The first semiconductor pattern SC1 may include a first region having relatively high conductivity and a second region having relatively low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped at a lower concentration than that of the first region. In one or more embodiments, the first semiconductor pattern SC1 may be an N-type transistor.

[0116] The conductivity of the first region may be greater than that of the second region, and the first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to a channel region AC1 (or an active region) of a silicon transistor S-TFT. In other words, a portion of the first semiconductor pattern SC1 may be a channel of the silicon transistor S-TFT, another portion of the first semiconductor pattern SC1 may be a source or drain of the silicon transistor S-TFT, and another portion of the first semiconductor pattern SC1 may be a connection electrode or a connection signal line.

[0117] A source region SE1, a channel region AC1 (or active region), and a drain region DE1 of the silicon transistor S-TFT may be formed from the first semiconductor pattern SC1. The source region SE1 and the drain region DE1 may extend in opposite directions from the channel region AC1, respectively, in a cross section.

[0118] The first insulating layer 10 may be located on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layer silicon oxide layer. The first insulating layer 10 and the inorganic layer of the circuit layer DP-CL described below may have a single-layer structure or a multi-layer structure and include at least one of the above materials, but the present disclosure is not limited thereto.

[0119] The gate GT1 of the silicon transistor S-TFT is located on the first insulating layer 10. The gate GT1 may be a part of the metal pattern. The gate GT1 overlaps the channel region AC1. The gate GT1 may be used as a mask in the process of doping the first semiconductor pattern SC1. The first electrode CE10 of the capacitor Cst is located on the first insulating layer 10. Figure 6 Different from the illustration, the first electrode CE10 may have a shape integral with the gate electrode GT1.

[0120] The second insulating layer 20 may be located on the first insulating layer 10 and may cover the gate electrode GT1. In one or more embodiments of the present disclosure, an upper electrode overlapping the gate electrode GT1 may be further located on the second insulating layer 20. The second electrode CE20 overlapping the first electrode CE10 may be located on the second insulating layer 20. The upper electrode may have a shape integral with the second electrode CE20 in a plane, or may be the same as the second electrode CE20.

[0121] The second shielding electrode BML2 is located on the second insulating layer 20. The second shielding electrode BML2 may correspond to the oxide transistor O-TFT. In one or more embodiments of the present disclosure, the second shielding electrode BML2 may be omitted. According to one or more embodiments of the present disclosure, the first shielding electrode BML1 may extend to the lower portion of the oxide transistor O-TFT and replace the second shielding electrode BML2.

[0122] The third insulating layer 30 may be located on the second insulating layer 20. The second semiconductor pattern SC2 may be located on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x ) or indium oxide (In 2 O 3 ).

[0123] The metal oxide semiconductor may include a plurality of regions SE2, AC2, and DE2 divided according to whether the TCO is reduced. The region where the TCO is reduced (hereinafter, referred to as the reduction region) may have a higher conductivity than the region where the TCO is not reduced (hereinafter, referred to as the non-reduction region). The reduction region is substantially used as a source region SE2 / drain region DE2 or a signal line of the oxide transistor O-TFT. The non-reduction region substantially corresponds to the semiconductor region (or channel region AC2) of the oxide transistor O-TFT. In other words, a portion of the second semiconductor pattern SC2 may be a semiconductor region of the oxide transistor O-TFT, another portion of the region may be a source region SE2 / drain region DE2 of the oxide transistor O-TFT, and another portion of the region may be a signal transmission region.

[0124] The fourth insulating layer 40 may be located on the third insulating layer 30. Figure 6As shown in FIG. 4 , the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In one or more embodiments of the present disclosure, the fourth insulating layer 40 may be an insulating pattern overlapping the gate electrode GT2 of the oxide transistor O-TFT and exposing the source region SE2 of the oxide transistor O-TFT.

[0125] The gate GT2 of the oxide transistor O-TFT is located on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a part of the metal pattern. The gate GT2 of the oxide transistor O-TFT overlaps with the channel region AC2.

[0126] The fifth insulating layer 50 may be located on the fourth insulating layer 40, and the fifth insulating layer 50 may cover the gate GT2. Each of the first to fifth insulating layers 10 to 50 may be an inorganic layer.

[0127] The first connection pattern CNP1 and the second connection pattern CNP2 may be arranged on the fifth insulating layer 50. The first connection pattern CNP1 and the second connection pattern CNP2 may be formed by the same process and thus may have the same material and the same stacked structure. The first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT through a first pixel contact hole PCH1 passing through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT through a second pixel contact hole PCH2 passing through the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship between the first connection pattern CNP1 and the second connection pattern CNP2 for the silicon transistor S-TFT and the oxide transistor O-TFT is not necessarily limited thereto.

[0128] The sixth insulating layer 60 may be located on the fifth insulating layer 50. The third connection pattern CNP3 may be located on the sixth insulating layer 60. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 through the third pixel contact hole PCH3 passing through the sixth insulating layer 60. The data line DL may be located on the sixth insulating layer 60. The seventh insulating layer 70 may be located on the sixth insulating layer 60 and may cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL may be formed by the same process and thus may have the same material and the same stacked structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0129] The first shielding electrode BML1, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium having suitable heat resistance. The first connection pattern CNP1 and the second connection pattern CNP2 may include aluminum having relatively high conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a three-layer structure in which titanium / aluminum / titanium are stacked.

[0130] The light emitting element LD may include an anode AE ​​(or a first electrode), a light emitting layer EL, and a cathode CE (or a second electrode). The anode AE ​​of the light emitting element LD may be located on the seventh insulating layer 70. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may include a stacked structure of ITO / Ag / ITO. The positions of the anode AE ​​and the cathode CE may be changed with each other.

[0131] The pixel definition film PDL may be located on the seventh insulating layer 70. The pixel definition film PDL may be an organic layer. The pixel definition film PDL may have the property of absorbing light beams, and for example, the pixel definition film PDL may have a black color. The pixel definition film PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel definition film PDL may correspond to a shading pattern having a shading property.

[0132] The pixel defining film PDL may cover a portion of the anode AE. For example, an opening PDL-OP through which a portion of the anode AE ​​is exposed may be defined in the pixel defining film PDL. The light emitting area LA may be defined to correspond to the opening PDL-OP. In one or more embodiments of the present disclosure, a hole control layer may be located between the anode AE ​​and the light emitting layer EL. The hole control layer may include a hole transport layer and may also include a hole injection layer. The electron control layer may be located between the light emitting layer EL and the cathode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer.

[0133] The encapsulation layer TFE may cover the light emitting element LD. The encapsulation layer TFE may include a first encapsulation insulating layer IL1, a second encapsulation insulating layer IL2, and a third encapsulation insulating layer IL3. However, the present disclosure is not limited thereto, and the encapsulation layer TFE may also include a plurality of inorganic layers and a plurality of organic layers.

[0134] The first encapsulation insulating layer IL1 may be an inorganic layer. The first encapsulation insulating layer IL1 may reduce or prevent external moisture or oxygen from penetrating into the light emitting element LD. For example, the first encapsulation insulating layer IL1 may include silicon nitride, silicon oxide, or a compound obtained by combining them. The first encapsulation insulating layer IL1 may be formed by a chemical vapor deposition process.

[0135] The second encapsulation insulating layer IL2 may be an organic layer. The second encapsulation insulating layer IL2 may be located on the first encapsulation insulating layer IL1 and may be in contact with the first encapsulation insulating layer IL1. The second encapsulation insulating layer IL2 may provide a flat surface on the first encapsulation insulating layer IL1. The curve formed in the upper surface of the first encapsulation insulating layer IL1 and the particles present on the first encapsulation insulating layer IL1 may be covered by the second encapsulation insulating layer IL2, and thus the possibility that the surface state of the upper surface of the first encapsulation insulating layer IL1 affects the components formed on the second encapsulation insulating layer IL2 may be reduced or prevented. In addition, the second encapsulation insulating layer IL2 may relieve stress between contact layers. The second encapsulation insulating layer IL2 may be formed by a solution process such as spin coating, slit coating, and inkjet process.

[0136] The third encapsulation insulating layer IL3 is located on the second encapsulation insulating layer IL2 and may cover the second encapsulation insulating layer IL2. Compared with a state where the third encapsulation insulating layer IL3 is located on the first encapsulation insulating layer IL1, the third encapsulation insulating layer IL3 may be stably formed on a relatively flat surface. The third encapsulation insulating layer IL3 may reduce or prevent moisture from being introduced from the outside.

[0137] The third encapsulation insulating layer IL3 may be optically transparent. For example, the third encapsulation insulating layer IL3 may have a visible light transmittance of about 90% or more. The third encapsulation insulating layer IL3 may have a relatively high light transmittance compared to the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 may be an inorganic layer. The third encapsulation insulating layer IL3 may include silicon oxide (SiO x ) or silicon oxynitride (SiON). The third encapsulation insulating layer IL3 may be formed by a chemical vapor deposition process. Meanwhile, each of the first encapsulation insulating layer IL1, the second encapsulation insulating layer IL2, and the third encapsulation insulating layer IL3 may include a plurality of layers, but the present disclosure is not limited to one or more embodiments.

[0138] The input sensing layer ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In one or more embodiments, the input sensing layer ISL may include a first detection insulating layer IS-IL1, a first conductive layer ICL1, a second insulating layer IS-IL2, a second conductive layer ICL2, and a third insulating layer IS-IL3. Figure 6 The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 are schematically shown.

[0139] The first detection insulating layer IS-IL1 may be directly located on the display panel DP. The first detection insulating layer IS-IL1 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer ICL1 and the second conductive layer ICL2 may have a single-layer structure or a multi-layer structure in which multiple layers are stacked in the third direction DR3. The first conductive layer ICL1 and the second conductive layer ICL2 may include conductive wires defining electrodes in a mesh shape. The conductive wires of the first conductive layer ICL1 and the conductive wires of the second conductive layer ICL2 may or may not be connected through contact holes passing through the second insulating layer IS-IL2. The connection relationship between the conductive wires of the first conductive layer ICL1 and the conductive wires of the second conductive layer ICL2 may be determined according to the type of sensor formed in the input sensing layer ISL.

[0140] The first conductive layer ICL1 and the second conductive layer ICL2 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ) or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, graphene, etc.

[0141] The first conductive layer ICL1 and the second conductive layer ICL2 having a multi-layer structure may include a metal layer. The metal layer may, for example, have a three-layer structure of titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer IS-IL2 may be located between the first conductive layer ICL1 and the second conductive layer ICL2. The third insulating layer IS-IL3 may cover the second conductive layer ICL2. In one or more embodiments of the present disclosure, the third insulating layer IS-IL3 may be omitted. The second insulating layer IS-IL2 and the third insulating layer IS-IL3 may include an inorganic layer or an organic layer.

[0142] Fig. 7A is an enlarged view of a portion of a display device according to the present disclosure. Figure 7B It is along Fig. 7A Hereinafter, the same description as that described above will be omitted, and reference will be made to Fig. 7A and Figure 7B A structure in which the display module DM and the flexible circuit boards FCB1 and FCB2 are connected to each other is described.

[0143] refer to Fig. 7A and Figure 7BThe display device DD of the present disclosure may include a first connection electrode CNE1 (or a connection pattern) and a second connection electrode CNE2 (or a connection electrode). The first connection electrode CNE1 may be connected to Figure 6 The first connection pattern CNP1 shown in FIG. 1 is at the same layer as the layer of the first connection pattern CNP1, and the portion of the data link line DL-C overlapping the non-display area DM-NDA may be at the same layer as the layer of the first connection pattern CNP1 shown in FIG. Figure 6 The gate electrode GT1 of the silicon transistor S-TFT is at the same layer as that of the gate electrode GT1 of the silicon transistor S-TFT. The data link line DL-C may be electrically connected to the data line DL.

[0144] The second connection electrode CNE2 may be exposed to the outside through the lower surface BL-LS of the base layer BL for rear surface bonding with the flexible circuit boards FCB1 and FCB2. However, the present disclosure is not limited thereto, and the second connection electrode CNE2 may not be directly exposed to the outside, but may instead be exposed to the outside through a contact hole, etc. The lower surface BL-LS of the base layer BL faces the upper surface BL-US of the base layer BL in the third direction DR3.

[0145] The base layer BL may include a first sub-base layer SBL1, a first basic insulating layer BIL1, a second basic insulating layer BIL2, and a second sub-base layer SBL2. The first basic insulating layer BIL1 is located on the first sub-base layer SBL1, and the second basic insulating layer BIL2 is located on the first basic insulating layer BIL1 and covers the second connection electrode CNE2 (e.g., the upper surface of the second connection electrode CNE2). The second sub-base layer SBL2 is located on the second basic insulating layer BIL2.

[0146] The first sub-base layer SBL1 and the second sub-base layer SBL2 may include a synthetic resin material, for example, polyimide. The first basic insulating layer BIL1 and the second basic insulating layer BIL2 may include an inorganic material. For example, the first basic insulating layer BIL1 and the second basic insulating layer BIL2 may include silicon nitride, silicon oxynitride, or silicon oxide.

[0147] The first basic insulating layer BIL1 is located on the first sub-base layer SBL1, and a first opening B1-OP through which a portion of the second connection electrode CNE2 is exposed is defined in the first basic insulating layer BIL1. The first sub-base layer SBL1 may be located below the first basic insulating layer BIL1. The first sub-base layer SBL1 provides a lower surface BL-LS of the base layer BL, and a second opening B2-OP through which the second connection electrode CNE2 is exposed to the outside of the display module DM is defined in the first sub-base layer SBL1. The second opening B2-OP may expose a portion of the first basic insulating layer BIL1 (e.g., a lower portion of the first basic insulating layer BIL1) to the outside. The size of the second opening B2-OP may be greater than the size of the first opening B1-OP.

[0148] The second connection electrode CNE2 may be embedded in the base layer BL. However, the present disclosure is not limited thereto, and the second connection electrode CNE2 may be located on the lower surface BL-LS of the base layer BL. Even when the base layer BL includes a single synthetic resin layer or a plurality of layers, the first opening B1-OP and the second opening B2-OP to be described below may not be limited. The second connection electrode CNE2 located on the lower surface BL-LS of the base layer BL may be connected to a conductive pattern located on the upper surface BL-US of the base layer BL through a contact hole passing through the base layer BL.

[0149] The first connection electrode CNE1 may be connected to the second connection electrode CNE2 through the first contact hole CH1, and may be connected to the data line DL through the second contact hole CH2. The first contact hole CH1 and the second contact hole CH2 may be arranged in the non-display area DM-NDA. The first contact hole CH1 may be formed by passing through a plurality of insulating layers 10, 20, 30, 40, and 50, a barrier layer BRL, a buffer layer BFL, and a portion of a base layer BL. The first contact hole CH1 may be connected to the second connection electrode CNE2 through the second base insulating layer BIL2 and the second sub-base layer SBL2. The second contact hole CH2 may be formed by passing through the second insulating layer 20 to the fifth insulating layer 50. The first connection electrode CNE1 may be connected to the data line DL through the second contact hole CH2.

[0150] refer to Fig. 7A and Figure 7B , the base layer BL may further include pad electrodes PD1 and PD2 connected to the second connection electrode CNE2. The pad electrodes PD1 and PD2 contacting the second connection electrode CNE2 may be exposed to the outside through a second opening B2-OP defined in the first sub-base layer SBL1. The pad electrodes PD1 and PD2 may include a first pad electrode PD1 extending in a first direction DR1 and a second pad electrode PD2 extending in a direction opposite to the first direction DR1.

[0151] The first pad electrode PD1 and the second pad electrode PD2 may overlap the non-display area NDA. For example, the first pad electrode PD1 and the second pad electrode PD2 may be arranged at Figure 2 In the pad area PA shown in . The first pad electrode PD1 and the second pad electrode PD2 may be arranged in the second direction DR2. The first pad electrode PD1 and the second pad electrode PD2 may face each other in the first direction DR1. For example, the first pad electrode PD1 and the second pad electrode PD2 (eg, ends thereof) may be spaced apart from each other in the first direction DR1.

[0152] The first flexible circuit board FCB1 may include a first base film BF1 and a first bump electrode BMP1, the first bump electrode BMP1 including a first contact portion CPT1 located on (e.g., above) the first base film BF1 and exposed from (e.g., extending beyond) the first edge BE1 of the first base film BF1. The first bump electrode BMP1 may overlap with the first pad electrode PD1 on a plane. The first bump electrode BMP1 may contact with and be electrically connected to the first pad electrode PD1. A plurality of first bump electrodes BMP1 may be provided. The plurality of first bump electrodes BMP1 may correspond to the plurality of first pad electrodes PD1, respectively. That is, one first bump electrode BMP1 may correspond to one first pad electrode PD1. The plurality of first bump electrodes BMP1 may extend in the first direction DR1 and may be arranged in the second direction DR2.

[0153] The second flexible circuit board FCB2 may include a second base film BF2 and a second bump electrode BMP2, the second bump electrode BMP2 including a second contact portion CPT2 located on the second base film BF2 and exposed from a second edge BE2 of the second base film BF2 (e.g., extending beyond the second edge BE2 of the second base film BF2). The second bump electrode BMP2 may overlap with the second pad electrode PD2 on a plane. The second bump electrode BMP2 may contact with the second pad electrode PD2 and be electrically connected to the second pad electrode PD2. A plurality of second bump electrodes BMP2 may be provided. The plurality of second bump electrodes BMP2 may correspond to the plurality of second pad electrodes PD2, respectively. That is, one second bump electrode BMP2 may correspond to one second pad electrode PD2. The plurality of second bump electrodes BMP2 may extend in the first direction DR1 and may be arranged in the second direction DR2. The plurality of first bump electrodes BMP1 may face the plurality of second bump electrodes BMP2, and the first bump electrode BMP1 and the second bump electrode BMP2 may be spaced apart from each other in the first direction DR1.

[0154] The first bump electrodes BMP1 may be electrically connected to the first pad electrodes PD1, respectively. In detail, the display device DD may further include a first metal pattern MP1 electrically connecting the first bump electrode BMP1 and the first pad electrode PD1, and a second metal pattern MP2 electrically connecting the second bump electrode BMP2 and the second pad electrode PD2. The first metal pattern MP1 contacts the first pad electrode PD1 and the first contact portion CPT1, and electrically connects the first bump electrode BMP1 and the first pad electrode PD1. The second metal pattern MP2 contacts the second pad electrode PD2 and the second contact portion CPT2, and electrically connects the second bump electrode BMP2 and the second pad electrode PD2.

[0155] Each of the first metal pattern MP1 and the second metal pattern MP2 may be a pattern obtained by curing metal ink. The metal patterns MP1 and MP2 may include solder paste. Each of the first metal pattern MP1 and the second metal pattern MP2 may be formed of a metal ink containing silver or copper. The first metal pattern MP1 may be located on each of the first pad electrodes PD1. The second metal pattern MP2 may be located on each of the second pad electrodes PD2.

[0156] In one or more embodiments, one or more adhesive layers may be further disposed between the first pad electrode PD1 and the first bump electrode BMP1 and between the second pad electrode PD2 and the second bump electrode BMP2, respectively. When the adhesive layer includes an insulating material, the first pad electrode PD1 and the first bump electrode BMP1 may be electrically connected only through the first metal pattern MP1, and the second pad electrode PD2 and the second bump electrode BMP2 may be electrically connected only through the second metal pattern MP2.

[0157] Each of the first metal pattern MP1 and the second metal pattern MP2 may be formed by curing the metal ink and then patterning the metal ink. Each of the first metal pattern MP1 and the second metal pattern MP2 may be formed at a relatively low temperature, and the first pad electrode PD1 and the first bump electrode BMP1 and the second pad electrode PD2 and the second bump electrode BMP2 may be electrically connected to each other, respectively, and simultaneously bonded to each other without a press process at a high temperature.

[0158] The first pad electrode PD1 may include a first main portion P-M1 overlapping the first bump electrode BMP1 on a plane, and may further include a first extension portion P-E1 extending from the first main portion P-M1 in a direction opposite to the first direction DR1. The second pad electrode PD2 may include a second main portion P-M2 overlapping the second bump electrode BMP2 on a plane, and may further include a second extension portion P-E2 extending from the second main portion P-M2 in the first direction DR1.

[0159] The first main part P-M1 and the second main part P-M2 may be arranged in the second direction DR2, and may be spaced apart from each other in the first direction DR1 to face each other. The first main part P-M1 and the second main part P-M2 may overlap each other in the first direction DR1. However, one or more embodiments are not limited thereto, and for example, only some of the first main part P-M1 and the second main part P-M2 may overlap each other in the first direction DR1. According to one or more embodiments of the present disclosure, the spacing d1 between adjacent first main parts P-M1 in the first main part P-M1 may be greater than or equal to about 30 μm and less than or equal to about 50 μm. For example, the spacing d1 between the first main parts P-M1 adjacent to each other may be about 40 μm. All spacings d1 between the first main parts P-M1 adjacent to each other may be the same. However, the present disclosure is not limited thereto, and the spacings d1 between the first main parts P-M1 adjacent to each other may be different from each other. The spacing d2 between the second main parts P-M2 adjacent to each other may be equal to the spacing d1 between the first main parts P-M1 adjacent to each other.

[0160] refer to Fig. 7A and Figure 7B , the first extension portion P-E1 is a portion exposed from the first bump electrode BMP1. That is, the first extension portion P-E1 may be a portion exposed from the first bump electrode BMP1 and electrically connected to the first contact portion CPT1 through the first metal pattern MP1. The first extension portion P-E1 may be aligned in the second direction DR2. The second extension portion P-E2 is a portion exposed from the second bump electrode BMP2. That is, the second extension portion P-E2 may be a portion exposed from the second bump electrode BMP2 and electrically connected to the second contact portion CPT2 through the second metal pattern MP2. The second extension portion P-E2 may be aligned in the second direction DR2.

[0161] Return to reference Fig. 7A, the first extension portion P-E1 and the second extension portion P-E2 may be spaced apart from each other in the first direction DR1. The first extension portion P-E1 and the second extension portion P-E2 may not overlap each other on a plane. According to one or more embodiments of the present disclosure, the first extension portion P-E1 and the second extension portion P-E2 may include a portion whose width with respect to the second direction DR2 is reduced (e.g., gradually reduced). For example, the first extension portion P-E1 includes a portion whose width is reduced (e.g., gradually reduced) in a direction opposite to the first direction DR1, and the second extension portion P-E2 may include a portion whose width is reduced (e.g., gradually reduced) in the first direction DR1. The first extension portion P-E1 may include a first middle portion P-MD1 whose width is gradually reduced and a first end P-ED1 extending from the first middle portion P-MD1. The second extension portion P-E2 may include a second middle portion P-MD2 whose width is gradually reduced and a second end P-ED2 extending from the second middle portion P-MD2.

[0162] According to one or more embodiments of the present disclosure, the first extension portion P-E1 and the second extension portion P-E2 may be alternately arranged in the second direction DR2. The first extension portion P-E1 and the second extension portion P-E2 may include portions overlapping each other in the second direction DR2. As described above, a portion of the first extension portion P-E1 whose width is reduced and a portion of the second extension portion P-E2 whose width is reduced may face each other. In detail, the first end P-ED1 and the second end P-ED2 may face each other and may be alternately arranged. Fig. 7A 2 shows that the first extension portions PE1 and the second extension portions PE2 are alternately arranged in the second direction DR2, but the present disclosure is not limited thereto, and the first extension portions PE1 and the second extension portions PE2 may be alternately arranged in groups of two.

[0163] A gap between the second ends P-ED2 adjacent in the second direction DR2 among the second ends P-ED2 may be defined as a third gap d3, and a gap (e.g., one of the gaps) between the second ends P-ED2 and the first ends P-ED1 adjacent in the second direction DR2 among the second ends P-ED2 and the first ends P-ED1 may be defined as a fourth gap d4. The third gap d3 may be greater than the fourth gap d4.

[0164] The display device DD of the present disclosure may include a first flexible circuit board FCB1 and a second flexible circuit board FCB2 spaced apart from each other in a first direction DR1. According to one or more embodiments of the present disclosure, the first pad electrode PD1 may contact the first bump electrode BMP1 of the first flexible circuit board FCB1 to be electrically connected to each other. The second pad electrode PD2 may contact the second bump electrode BMP2 of the second flexible circuit board FCB2 to be electrically connected to each other.

[0165] When the spacing between the first pad electrodes PD1 aligned in the second direction DR2 is less than or equal to the corresponding gap, a defect may occur due to misalignment between the first bump electrode BMP1 and the first pad electrode PD1. Similarly, when the spacing between the second pad electrodes PD2 aligned in the second direction DR2 is less than or equal to the corresponding gap, a defect may occur due to misalignment between the second bump electrode BMP2 and the second pad electrode PD2.

[0166] Since the first flexible circuit board FCB1 and the second flexible circuit board FCB2 spaced apart from each other in the first direction DR1 are arranged under the display module DM, the interval d1 between the first main portions P-M1 of the first pad electrodes PD1 adjacent to each other and the interval d2 between the second main portions P-M2 of the second pad electrodes PD2 adjacent to each other may be greater than or equal to about 30 μm and less than or equal to about 50 μm. Therefore, when the first flexible circuit board FCB1 and the display module DM contact each other, defects caused by alignment between the first bump electrode BMP1 and the first pad electrode PD1 may be reduced or prevented, and when the second flexible circuit board FCB2 and the display module DM contact each other, defects caused by alignment between the second bump electrode BMP2 and the second pad electrode PD2 may be reduced or prevented.

[0167] Fig. 8A and Figure 8B is an enlarged view of a portion of a display device of the present disclosure.

[0168] refer to Fig. 8A The first pad electrode PD1a may include a first main portion P-M1a overlapping the first bump electrode BMP1 on a plane and a first extension portion P-E1a extending from the first main portion P-M1a in a direction opposite to the first direction DR1. The second pad electrode PD2a may include a second main portion P-M2a overlapping the second bump electrode BMP2 on a plane and a second extension portion P-E2a extending from the second main portion P-M2a in the first direction DR1.

[0169] The first main portion P-M1a and the second main portion P-M2a may be arranged along the second direction DR2 and may be spaced apart from each other in the first direction DR1 to face each other. The first main portion P-M1a and the second main portion P-M2a may overlap each other in the first direction DR1.

[0170] According to one or more embodiments of the present disclosure, the first extension portion P-E1a and the second extension portion P-E2a may include a portion whose width in the second direction DR2 is reduced (e.g., gradually reduced). The first extension portion P-E1a may include a first middle portion P-MD1a whose width is reduced (e.g., gradually reduced) and a first end P-ED1a extending from the first middle portion P-MD1a, and the second extension portion P-E2a may include a second middle portion P-MD2a whose width is reduced (e.g., gradually reduced) and a second end P-ED2a extending from the second middle portion P-MD2a.

[0171] The first end P-ED1a and the second end P-ED2a may face each other and may be arranged alternately. In detail, two first ends P-ED1a adjacent to each other and two second ends P-ED2a adjacent to each other (for example, without any first end P-ED1a in between) may be arranged alternately in the second direction DR2. For example, one or more of the first ends P-ED1a and / or one or more of the second ends P-ED2a may extend from the corresponding first middle portion P-MD1a and the second middle portion P-MD2a along both the first direction DR1 and the second direction DR2. The present disclosure is not limited thereto, and the first ends P-ED1a and the second ends P-ED2a may be arranged alternately in groups of three.

[0172] refer to Figure 8B , the first pad electrode PD1b may include a first main portion P-M1b overlapping the first bump electrode BMP1 on a plane and a first extension portion P-E1b extending from the first main portion P-M1b in a direction opposite to the first direction DR1. The second pad electrode PD2b may include a second main portion P-M2b overlapping the second bump electrode BMP2 on a plane and a second extension portion P-E2b extending from the second main portion P-M2b in the first direction DR1.

[0173] The first extension portion P-E1b may include a first middle portion P-MD1b whose width is reduced (e.g., gradually reduced) and a first end P-ED1b extending from the first middle portion P-MD1b. The second extension portion P-E2b may include a second middle portion P-MD2b whose width is reduced (e.g., gradually reduced) and a second end P-ED2b extending from the second middle portion P-MD2b.

[0174] like Figure 8B As shown in , a direction in which the widths of the first middle portions P- MD1b adjacent to each other are reduced and a direction in which the widths of the second middle portions P- MD2b adjacent to each other are reduced may be different from each other. Fig. 7A The directions in which the width of the first middle portion P-MD1b and the width of the second middle portion P-MD2 shown in can be reduced may be the same. However, the directions in which the width of the first middle portion P-MD1b and the width of the second middle portion P-MD2b are reduced (for example, the directions in which the corresponding edges are adjusted along the first direction DR1 to achieve a reduced width relative to the second direction DR2) may alternate with each other, and thus the width may decrease with an edge moving in the second direction DR2, or may then decrease with another edge moving in a direction opposite to the second direction DR2.

[0175] A gap between the second ends P-ED2b adjacent in the second direction DR2 in the second end P-ED2b may be defined as a third gap d3a, and a gap (e.g., one of the gaps) between the second ends P-ED2b and the first ends P-ED1b adjacent in the second direction DR2 in the second end P-ED2b and the first ends P-ED1b may be defined as a fourth gap d4a. The fourth gap d4a may be greater than the third gap d3a.

[0176] Fig. 9 is an enlarged view of a portion of the display device DDa of the present disclosure. Fig. 10A It is along Fig. 9 1 is a cross-sectional view of the display module DMa taken along line III-III'. Fig. 10B It is along Fig. 9 4 is a cross-sectional view of the display module DMa taken along line IV-IV'. Fig. 10C yes Fig. 10A Magnified view of area AA'.

[0177] refer to Figures 9 to 10C , the insulating layer IL may be arranged between the pad electrodes PD1 and PD2 and the second connection electrode CNE2, and the third contact holes CH3a and CH3b (or contact holes) may be formed in the insulating layer IL. The insulating layer IL may cover the lower surface of the second connection electrode CNE2. The insulating layer IL may include an inorganic material, and for example, the insulating layer IL may include silicon nitride, silicon oxynitride, or silicon oxide. However, the present disclosure is not limited thereto, and the insulating layer IL may include the same material as the first sub-base layer SBL1. For example, the insulating layer IL may include a synthetic resin material, such as polyimide. The insulating layer IL may be formed integrally with the first sub-base layer SBL1.

[0178] refer to Fig. 9 , Fig. 10A and Fig. 10C , a third contact hole CH3b may be formed in the insulating layer IL. The second pad electrode PD2 and the second connection electrode CNE2 may be electrically connected through the third contact hole CH3b formed in the insulating layer IL. Fig. 9 As shown in , a plurality of third contact holes CH3b may be provided. That is, the third contact holes CH3b may be formed at the second pad electrode PD2, respectively. In detail, the third contact hole CH3b may be formed at the second end P-ED2 of the second pad electrode PD2. It is shown that one third contact hole CH3b is formed at the corresponding second pad electrode PD2 in the second pad electrode PD2, but the present disclosure is not limited thereto, and two or more third contact holes CH3b may be formed at one second pad electrode PD2. The third contact holes CH3b may be arranged in the second direction DR2. As shown in the figure, the third contact holes CH3b may be arranged side by side in the second direction DR2, but the present disclosure is not limited thereto, and the third contact holes CH3b may be formed at any portion of the second end P-ED2, and therefore do not need to be arranged side by side in the second direction DR2. The third contact holes CH3a and CH3b may be arranged in a sawtooth pattern on a plane.

[0179] refer to Fig. 9 and Fig. 10B , a third contact hole CH3a may be formed in the insulating layer IL. The first pad electrode PD1 and the second connection electrode CNE2 may be electrically connected through the third contact hole CH3a formed in the insulating layer IL. Fig. 9 As shown in , a plurality of third contact holes CH3a may be provided. That is, the third contact holes CH3a may be formed at the first pad electrodes PD1, respectively. In detail, the third contact hole CH3a may be formed at the first end P-ED1 of the first pad electrode PD1. It is shown that the third contact hole CH3a is formed at the corresponding first pad electrode PD1 in the first pad electrode PD1, but the present disclosure is not limited thereto, and two or more third contact holes CH3a may be formed at one first pad electrode PD1. The third contact holes CH3a may be arranged in the second direction DR2. As shown in the figure, the third contact holes CH3a may be arranged side by side in the second direction DR2, but the present disclosure is not limited thereto, and the third contact holes CH3a may be formed at any portion of the first end P-ED1, and therefore do not need to be arranged side by side in the second direction DR2.

[0180] According to the present disclosure, a flexible circuit board is bonded to the rear surface of a display panel (rear surface bonding). Since the non-display area of ​​the display panel is not bent, defects that may occur when the non-display area of ​​the display panel is bent can be reduced or prevented. The area of ​​the frame area of ​​the window for covering the non-display area of ​​the display panel can be reduced.

[0181] The metal pattern formed by curing and then patterning the metal ink electrically connects the flexible circuit board and the pad electrode. The metal pattern can be formed at a low temperature and can combine the flexible circuit board and the display panel without the process of pressing the flexible circuit board and the display panel at a high temperature.

[0182] When the first flexible circuit board and the second flexible circuit board are arranged to be spaced apart from each other, the spacing between the first pad electrodes adjacent to each other and the spacing between the second pad electrodes adjacent to each other may be a corresponding gap or a larger gap. Therefore, defects caused by alignment between the first bump electrode and the first pad electrode of the first flexible circuit board and between the second bump electrode and the second pad electrode of the second flexible circuit board can be reduced or prevented.

[0183] Although described above with reference to one or more embodiments of the present disclosure, it will be appreciated that those skilled in the art or persons of ordinary skill in the art may make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the appended claims.

[0184] Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the appended claims and their functional equivalents included therein.

Claims

1. Display equipment, including: a first circuit board; a second circuit board; as well as A display panel is electrically connected to the first circuit board and the second circuit board, defines a display area and a non-display area, and includes: The base layer includes: A first sub-base layer, overlapping the display area and the non-display area; a second sub-base layer, above the first sub-base layer; a connection electrode between the first sub-base layer and the second sub-base layer and electrically connected to a signal line; and a pad electrode, exposed through an opening defined in the first sub-base layer, electrically connected to the connection electrode, and comprising: a first pad electrode electrically connected to the first circuit board and extending in a first direction; and a second pad electrode electrically connected to the second circuit board, spaced apart from the first pad electrode in the first direction, and extending in a direction opposite to the first direction; and The circuit layer is above the base layer and includes a transistor and at least one signal line connected to the transistor.

2. The display device according to claim 1, wherein: The first circuit board includes a first base film and a first bump electrode above the first base film, and The second circuit board includes a second base film and a second bump electrode above the second base film.

3. The display device according to claim 1, wherein: The first circuit board includes a first base film and a first bump electrode above the first base film, and The second circuit board includes a second base film and a second bump electrode above the second base film and facing the first bump electrode in the first direction.

4. The display device according to claim 3, wherein: The first pad electrodes contact the first bump electrodes respectively, and Wherein, the second pad electrodes contact the second bump electrodes respectively.

5. The display device according to claim 2, wherein: The first bump electrode includes a first contact portion extending beyond an edge of the first base film, and The second bump electrode includes a second contact portion extending beyond an edge of the second base film.

6. The display device according to claim 5, further comprising: a first metal pattern electrically connecting the first bump electrode and the first pad electrode; as well as a second metal pattern electrically connecting the second bump electrode and the second pad electrode, wherein the first metal pattern contacts the first pad electrode and the first contact portion, and Wherein, the second metal pattern contacts the second pad electrode and the second contact portion.

7. The display device according to claim 6, further comprising: a first adhesive layer between the first bump electrode and the first pad electrode; as well as A second adhesive layer is between the second bump electrode and the second pad electrode.

8. The display device according to claim 2, wherein: The first pad electrode comprises: a first main portion overlapping the first bump electrode in a plane; and a first extension portion that does not overlap with the first bump electrode in a plane and extends from the first main portion, and Wherein, the second pad electrode comprises: a second main portion overlapping the second bump electrode in a plane; and The second extension portion does not overlap with the second bump electrode in a plane and extends from the second main portion.

9. The display device according to claim 8, wherein: The first main portion and the second main portion face each other in the first direction, and are arranged in a second direction perpendicular to the first direction.

10. The display device according to claim 9, wherein: The first extending portions and the second extending portions are alternately arranged in the second direction.

11. The display device according to claim 9, wherein: The first extending portion and the second extending portion partially overlap each other in the second direction.

12. The display device according to claim 8, wherein: Respective widths of the first extension portion and the second extension portion decrease along the first direction.

13. The display device according to claim 1, wherein: The first circuit board includes a bent portion bent toward a lower side of the display panel, and Wherein, a portion of the first circuit board overlaps with the second circuit board in a plane.

14. The display device according to claim 1, wherein: The first pad electrode and the second pad electrode overlap the non-display area. 15 . The display device according to claim 1 , further comprising an insulating layer between the pad electrode and the connection electrode, the pad electrode and the connection electrode being electrically connected through a contact hole defined by the insulating layer.

16. The display device according to claim 1, further comprising a connection pattern penetrating a portion of the base layer, in, The signal line is over an upper surface of the second sub base layer and is electrically connected to corresponding ones of the pad electrodes through the connection pattern.

17. Display equipment, including: A display panel defining a display area and a non-display area; as well as a first circuit board and a second circuit board, the first circuit board being electrically connected to the display panel, the second circuit board being electrically connected to the display panel and spaced apart from the first circuit board in a first direction, Wherein, the display panel comprises: The base layer includes: A first sub-base layer, overlapping the display area and the non-display area; a second sub-base layer, above the first sub-base layer; a connection electrode between the first sub-base layer and the second sub-base layer and electrically connected to a signal line; and a pad electrode, exposed through an opening defined in the first sub-base layer, electrically connected to the connection electrode, and comprising: a first pad electrode overlapping the first circuit board and not overlapping the second circuit board; and second pad electrodes overlapping the second circuit board and not overlapping the first circuit board, at least one of the second pad electrodes facing at least one of the first pad electrodes in a second direction perpendicular to the first direction; and The circuit layer is above the base layer and includes a transistor and at least one signal line connected to the transistor.

18. The display device according to claim 17, wherein: The first pad electrode and the second pad electrode are spaced apart from each other in the first direction.

19. The display device according to claim 18, wherein: The first pad electrode comprises: a first main portion overlapping the first circuit board in a plane; and a first extension portion that does not overlap the first circuit board in plane and extends from the first main portion, and Wherein, the second pad electrode comprises: a second main portion overlapping the second circuit board in plane; and The second extension portion does not overlap with the second circuit board in plane and extends from the second main portion.

20. The display device according to claim 19, wherein The first extending portions and the second extending portions are alternately arranged in the second direction.

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