Root mean square voltage calculation circuit and nuclear radiation detector

Abstract

The application discloses a root mean square voltage calculation circuit and a nuclear radiation detector, which comprise an absolute value sub-circuit, a root mean square operation sub-circuit and a result output sub-circuit. The absolute value sub-circuit performs absolute value processing on an input voltage signal of the nuclear radiation detector, so as to convert the input voltage signal into an absolute value current signal; the root mean square operation sub-circuit comprises a first input end, a second input end and a signal output end, the first input end is electrically connected with the absolute value sub-circuit, the signal output end is electrically connected with the second input end, and the root mean square operation sub-circuit is used for performing root mean square operation on the absolute value current signal by using a first root mean square current signal, so as to convert the input voltage signal into a second root mean square current signal, the first root mean square current signal being a current signal fed back from the signal output end to the second input end; and the result output sub-circuit is electrically connected with the signal output end, the result output sub-circuit converts the second root mean square current signal into a root mean square voltage signal, and outputs the root mean square voltage signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of nuclear radiation detectors, and particularly relates to a root mean square voltage calculation circuit and a nuclear radiation detector. BACKGROUND

[0002] In the field of nuclear radiation detector measurement, the nuclear instrument system of a nuclear power plant is one of the most critical systems of a reactor. The reactor power is monitored by monitoring the neutron fluence rate level in the reactor by using the out-of-core nuclear measurement detector distributed on the periphery of the reactor pressure vessel. The principle of neutron fluence rate level detection is that the nuclear reaction occurs between neutrons and sensitive materials inside the nuclear radiation detector to form reaction products. These reaction products enter the ionized gas molecules in the gas detector cavity to form positive ion-electron pairs, which are subjected to directional drift under the action of an external electric field to generate a voltage difference. In the demand for a very wide measurement range, the neutron flux can be calculated by measuring the root mean square voltage of the nuclear radiation detector and the change of the root mean square voltage. In the related art, the calculation of the root mean square voltage usually depends on the related software algorithm, and the design of the software algorithm is usually complex, thereby causing the calculation of the root mean square voltage to be prone to deviation and low calculation accuracy. SUMMARY

[0003] The present application aims to provide a root mean square voltage calculation circuit and a nuclear radiation detector, which can solve the problem of low calculation accuracy of the root mean square voltage of the software algorithm.

[0004] In a first aspect, an embodiment of the present application provides a root mean square voltage calculation circuit, comprising:

[0005] An absolute value sub-circuit, configured to perform absolute value processing on an input voltage signal of a nuclear radiation detector, so as to convert the input voltage signal into an absolute value current signal;

[0006] A root mean square operation sub-circuit, comprising a first input end, a second input end and a signal output end, the first input end is electrically connected with the absolute value sub-circuit, the signal output end is electrically connected with the second input end, and the root mean square operation sub-circuit is configured to perform root mean square operation on the absolute value current signal by using a first root mean square current signal, so as to convert the input voltage signal into a second root mean square current signal, the first root mean square current signal being a current signal fed back from the signal output end to the second input end;

[0007] A result output sub-circuit, electrically connected with the signal output end, configured to convert the second root mean square current signal into a root mean square voltage signal, and output the root mean square voltage signal.

[0008] According to some embodiments of the present application, the absolute value sub-circuit comprises:

[0009] a first operational amplifier, a non-inverting input terminal of the first operational amplifier being configured to input the input voltage signal;

[0010] a first transistor, an output terminal of the first operational amplifier being electrically connected to a base of the first transistor, the first transistor being configured to be turned on when the input voltage signal is positive;

[0011] a first resistor, an emitter of the first transistor being electrically connected to one end of the first resistor, the non-inverting input terminal of the first operational amplifier being electrically connected to the one end of the first resistor, the other end of the first resistor being grounded;

[0012] a first mirror current source sub-circuit, the first mirror current source sub-circuit being electrically connected to a collector of the first transistor, the first mirror current source sub-circuit being electrically connected to the root mean square operation sub-circuit, the first mirror current source sub-circuit being configured to copy a collector current of the first transistor to obtain and output the absolute value current signal when the first transistor is turned on;

[0013] a second transistor, the output terminal of the first operational amplifier being electrically connected to a base of the second transistor, an emitter of the second transistor being electrically connected to the one end of the first resistor, a collector of the second transistor being electrically connected to the root mean square operation sub-circuit, the second transistor being configured to be turned on when the input voltage signal is negative, so that the collector of the second transistor outputs the absolute value current signal.

[0014] According to some embodiments of the present application, the first mirror current source sub-circuit comprises:

[0015] a third transistor, an emitter of the third transistor being configured to be electrically connected to a positive power supply terminal;

[0016] a fourth transistor, a collector of the third transistor being electrically connected to an emitter of the fourth transistor, the collector of the fourth transistor being electrically connected to the collector of the first transistor, the collector of the fourth transistor being electrically connected to a base of the fourth transistor;

[0017] a fifth transistor, the emitter of the fifth transistor being configured to be electrically connected to the positive power supply terminal, a base of the fifth transistor being electrically connected to the base of the third transistor, the base of the fifth transistor being electrically connected to a collector of the fifth transistor;

[0018] a sixth transistor, the collector of the fifth transistor being electrically connected to an emitter of the sixth transistor, the collector of the sixth transistor being electrically connected to the root mean square operation sub-circuit.

[0019] According to some embodiments of the present application, the absolute value sub-circuit further comprises:

[0020] a first proportional amplification unit, an output terminal of the first operational amplifier is electrically connected to an input terminal of the first proportional amplification unit, and an output terminal of the first proportional amplification unit is electrically connected to a base of the first triode;

[0021] a second proportional amplification unit, an output terminal of the first operational amplifier is electrically connected to an input terminal of the second proportional amplification unit, and an output terminal of the second proportional amplification unit is electrically connected to a base of the second triode.

[0022] According to some embodiments of the present application, the root mean square operation sub-circuit comprises:

[0023] a square operation unit, the square operation unit is electrically connected to the absolute value sub-circuit, and the square operation unit is configured to perform square operation on the absolute value current signal to obtain a square current signal;

[0024] a division operation unit, the division operation unit is electrically connected to the square operation unit, and the division operation unit is configured to perform division operation on the square current signal and the first root mean square current signal to obtain a division current signal;

[0025] an average operation unit, the average operation unit is electrically connected to the division operation unit, and the average operation unit is configured to perform average operation on the division current signal to obtain the second root mean square current signal.

[0026] According to some embodiments of the present application, the square operation unit comprises:

[0027] a seventh triode, an emitter of the seventh triode is electrically connected to the absolute value sub-circuit, an emitter of the seventh triode is electrically connected to the division operation unit, and a base of the seventh triode is electrically connected to a collector of the seventh triode;

[0028] an eighth triode, a collector of the seventh triode is electrically connected to an emitter of the eighth triode, a collector of the eighth triode is electrically connected to a base of the eighth triode, and a collector of the eighth triode is grounded.

[0029] According to some embodiments of the present application, the division operation unit comprises:

[0030] a ninth triode, an emitter of the ninth triode is electrically connected to the square operation unit, and a collector of the ninth triode is electrically connected to the average operation unit;

[0031] A logarithmic amplification subunit, the average operation unit is electrically connected with the logarithmic amplification subunit, the logarithmic amplification subunit is electrically connected with the base of the ninth transistor, and the logarithmic amplification subunit is used for taking natural logarithm of the first root mean square current signal to obtain a logarithmic current signal, and inputting the logarithmic current signal into the base of the ninth transistor, so that the ninth transistor performs division operation according to the square current signal and the logarithmic current signal to obtain the division current signal.

[0032] According to some embodiments of the present application, the average operation unit comprises:

[0033] A second resistor, one end of the second resistor is electrically connected with the division operation unit, and the other end of the second resistor is electrically connected with the result output subcircuit;

[0034] A capacitor, one end of the capacitor is electrically connected with the division operation unit, and the other end of the capacitor is grounded.

[0035] According to some embodiments of the present application, the result output subcircuit comprises:

[0036] A second mirror current source subcircuit, the second mirror current source subcircuit is electrically connected with the root mean square operation subcircuit, and the second mirror current source subcircuit is used for copying the second root mean square current signal;

[0037] A third resistor, one end of the third resistor is electrically connected with the second mirror current source subcircuit, and the other end of the third resistor is grounded, and the third resistor is used for outputting the root mean square voltage signal according to the second root mean square current signal.

[0038] In a second aspect, the embodiments of the present application provide a nuclear radiation detector, comprising the root mean square voltage calculation circuit as described above.

[0039] In the embodiments of the present application, the absolute value subcircuit performs absolute value processing on the input voltage signal, converts the input voltage signal into an absolute value current signal, the root mean square operation subcircuit performs root mean square operation on the absolute value current signal by using the first root mean square current signal to obtain the second root mean square current signal, and the result output subcircuit obtains and outputs the root mean square voltage signal according to the second root mean square current signal. The embodiments provided in the present application calculate the root mean square voltage through the circuit, and the calculation precision is high.

[0040] Additional aspects and advantages of the present application will be given in part in the following description, part will become apparent from the following description, or will be understood by those skilled in the art through practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0041] The present application will be further described below in combination with the drawings and embodiments, wherein:

[0042] Figure 1 a functional block diagram of an embodiment of the root mean square voltage calculation circuit provided in the present application;

[0043] Figure 2 a functional block diagram of the second mirror current source sub-circuit, the third mirror current source sub-circuit and the fourth mirror current source sub-circuit in an embodiment of the root mean square voltage calculation circuit provided in the present application;

[0044] Figure 3 a first circuit diagram of an embodiment of the root mean square voltage calculation circuit provided in the present application;

[0045] Figure 4 a second circuit diagram of an embodiment of the root mean square voltage calculation circuit provided in the present application.

[0046] Reference Signs:

[0047] absolute value sub-circuit 100, second mirror current source sub-circuit 200, third mirror current source sub-circuit 300, fourth mirror current source sub-circuit 400, root mean square operation sub-circuit 500, square operation unit 510, division operation unit 520, filter unit 530, follower unit 540. DETAILED DESCRIPTION

[0048] Embodiments of the present application will be described in detail below with reference to drawings, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to drawings are exemplary and are for the purpose of explaining the present application only and should not be understood as a limitation of the present application.

[0049] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, etc. is based on the orientation or position relationship shown in the drawings and is only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0050] In the description of the present application, plural means more than two. If there is a description of first, second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the sequence of technical features indicated.

[0051] In the description of the present application, unless otherwise explicitly limited, the words such as arrangement, installation, electrical connection, etc. should be broadly understood, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0052] The following description will be made with reference toFigures 1 to 4 The application discloses a root mean square voltage calculation circuit and a nuclear radiation detector.

[0053] The application provides a root mean square voltage calculation circuit, which comprises:

[0054] The absolute value sub-circuit 100 is configured to perform absolute value processing on the input voltage signal of the nuclear radiation detector, so as to convert the input voltage signal into an absolute value current signal.

[0055] The root mean square operation sub-circuit 500 comprises a first input end, a second input end and a signal output end. The first input end is electrically connected with the absolute value sub-circuit 100. The signal output end is electrically connected with the second input end. The root mean square operation sub-circuit 500 is configured to perform root mean square operation on the absolute value current signal by using a first root mean square current signal, so as to convert the input voltage signal into a second root mean square current signal. The first root mean square current signal is a current signal fed back from the signal output end to the second input end.

[0056] The result output sub-circuit is electrically connected with the signal output end. The result output sub-circuit is configured to convert the second root mean square current signal into a root mean square voltage signal and output the root mean square voltage signal.

[0057] In the application, the absolute value sub-circuit 100 performs absolute value processing on the input voltage signal, so as to convert the input voltage signal into an absolute value current signal. The root mean square operation sub-circuit 500 performs root mean square operation on the absolute value current signal by using a first root mean square current signal, so as to obtain a second root mean square current signal. The result output sub-circuit obtains and outputs a root mean square voltage signal according to the second root mean square current signal. The application has high calculation precision by calculating the root mean square voltage through the circuit.

[0058] In some embodiments of the application, the absolute value sub-circuit 100 can adopt a diode precision full-wave rectifier circuit, an operational amplifier-based full-wave rectifier circuit or a power half-wave and full-wave rectifier. The absolute value sub-circuit 100 can convert a negative input voltage signal into a positive signal, so as to realize absolute value operation, i.e. converting the input voltage signal into an absolute value current signal, and the absolute value current signal is positive.

[0059] In some embodiments of the application, as shown in FIG. 1, the absolute value sub-circuit 100 comprises a diode precision full-wave rectifier circuit. Figure 1As shown in the figure, the absolute value sub-circuit 100 is configured to perform absolute value processing on the input voltage signal Vin of the nuclear radiation detector, so as to convert the input voltage signal Vin into an absolute value voltage signal |Vin|. The RMS operation sub-circuit 500 includes a square operation unit 510, a division operation unit 520, a filter unit 530 and a follower unit 540 connected in sequence. The square operation unit 510 is configured to perform square operation on the absolute value voltage signal |Vin| to obtain a square voltage signal |Vin| 2 The follower unit 540 is configured to feed back the first RMS voltage signal to the division operation unit 520, the first RMS voltage signal being a voltage signal output by the RMS operation sub-circuit 500. The division operation unit 520 performs division operation on the square voltage signal |Vin| 2 / Vrms1 by using the first RMS voltage signal, to obtain a division voltage signal |Vin| 2 / Vrms1. The filter unit 530 performs filtering, i.e., average operation, on the division voltage signal |Vin| 2 / Vrms1, to obtain and output a second RMS voltage signal Vrms2, so as to realize RMS voltage calculation.

[0060] An embodiment of the present application is shown in the figure, wherein the absolute value sub-circuit 100 is configured to perform absolute value processing on the input voltage signal Vin of the nuclear radiation detector, so as to convert the input voltage signal Vin into an absolute value voltage signal |Vin|. Figure 3

[0061] A first operational amplifier U3, a non-inverting input terminal of the first operational amplifier U3 being configured to input the input voltage signal;

[0062] A first transistor Q6, an output terminal of the first operational amplifier U3 being electrically connected to a base of the first transistor Q6, the first transistor Q6 being configured to be turned on when the input voltage signal is positive.

[0063] A first resistor R12, an emitter of the first transistor Q6 being electrically connected to one end of the first resistor R12, a non-inverting input terminal of the first operational amplifier U3 being electrically connected to one end of the first resistor R12, the other end of the first resistor R12 being grounded.

[0064] A first mirror current source sub-circuit, the first mirror current source sub-circuit being electrically connected to a collector of the first transistor Q6, the first mirror current source sub-circuit being electrically connected to the RMS operation sub-circuit 500, the first mirror current source sub-circuit being configured to copy the collector current of the first transistor Q6 to obtain and output an absolute value current signal when the first transistor Q6 is turned on.

[0065] ​The second triode Q7 is electrically connected to the base of the first operational amplifier U3, and the emitter of the second triode Q7 is electrically connected to one end of the first resistor R12. The collector of the second triode Q7 is electrically connected to the RMS operational sub-circuit 500. The second triode Q7 is used to turn on when the input voltage signal is negative, so that the collector of the second triode Q7 outputs the absolute value current signal.

[0066] In this embodiment, the input voltage signal is output to the base of the first triode Q6 and the base of the second triode Q7 through the first operational amplifier U3. When the input voltage signal is positive, the first triode Q6 is turned on, and the second triode Q7 is turned off. The load current is provided by the first mirror current source sub-circuit and flows to the first resistor R12 through the first triode Q6, thereby generating the absolute value current signal. The first mirror current source sub-circuit copies the collector current of the first triode Q6, and outputs the absolute value current signal to the RMS operational sub-circuit 500. The size of the absolute value current signal is the ratio of the voltage value of the input voltage signal and the resistance value of the first resistor R12. When the input signal is negative, the first triode Q6 is turned off, and the second triode Q7 is turned on. The current flows from the first resistor R12 to the second triode Q7, and the absolute value current signal is output to the RMS operational sub-circuit 500 through the collector of the second triode Q7. The size of the absolute value current signal is the ratio of the voltage value of the input voltage signal and the resistance value of the first resistor R12. Therefore, when the input voltage signal is positive or negative, the absolute value current signal flows from the absolute value sub-circuit 100 to the RMS operational sub-circuit 500, i.e., the absolute value current signal is positive, and the absolute value operation is realized.

[0067] In an embodiment of the present application, as shown in Figure 3 The first mirror current source sub-circuit comprises:

[0068] The third triode Q1 is electrically connected to the positive power supply;

[0069] The fourth triode Q3 is electrically connected to the emitter of the third triode Q1, and the collector of the fourth triode Q3 is electrically connected to the collector of the first triode Q6. The collector of the fourth triode Q3 is electrically connected to the base of the fourth triode Q3.

[0070] The fifth triode Q2 is electrically connected to the positive power supply, and the base of the fifth triode Q2 is electrically connected to the base of the third triode Q1. The base of the fifth triode Q2 is electrically connected to the collector of the fifth triode Q2.

[0071] The sixth triode Q4 is electrically connected to the emitter of the fifth triode Q2, and the collector of the sixth triode Q4 is electrically connected to the RMS operational sub-circuit 500.

[0072] In the embodiment, the positive power supply end provides a positive voltage, when the first triode Q6 is turned on, the third triode Q1, the fourth triode Q3, the fifth triode Q2 and the sixth triode Q4 are all turned on, and the current flows from the fourth triode Q3 to the first triode Q6 and the first resistor R12. The collector current of the sixth triode Q4 is the same as the collector current of the fourth triode Q3, that is, the collector current of the fourth triode Q3 is copied to obtain an absolute value current signal, which is then output to the root mean square operation circuit 500.

[0073] In an embodiment of the present application, the absolute value sub-circuit 100 further comprises:

[0074] The first proportional amplification unit has an input end electrically connected to the output end of the first operational amplifier U3, and an output end electrically connected to the base of the first triode Q6.

[0075] The second proportional amplification unit has an input end electrically connected to the output end of the first operational amplifier U3, and an output end electrically connected to the base of the second triode Q7.

[0076] In the embodiment, the input voltage signal is output to the base of the first triode Q6 after proportional amplification by the first proportional amplification unit. The input voltage signal is output to the base of the second triode Q7 after proportional amplification by the second proportional amplification unit. The first proportional amplification unit and the second proportional amplification unit can ensure that the root mean square voltage calculation circuit can quickly respond and accurately perform root mean square calculation even when the input voltage signal is very small, and can also eliminate the crossover distortion caused by the first triode Q6 and the second triode Q7.

[0077] As shown in some embodiments of the present application, Figure 3 The first proportional amplification unit comprises:

[0078] The second operational amplifier U1 has an output end electrically connected to the non-inverting input end of the first operational amplifier U3, and an output end electrically connected to the base of the first triode Q6.

[0079] The fourth resistor R4 has one end electrically connected to the output end of the second operational amplifier U1.

[0080] The fifth resistor R3 has one end electrically connected to the other end of the fourth resistor R4.

[0081] The sixth resistor R2 has one end electrically connected to the other end of the fifth resistor R3, and the other end electrically connected to the negative power supply end.

[0082] The seventh resistor R5 has one end electrically connected to one end of the sixth resistor R2, and the other end grounded.

[0083] In this embodiment, the negative supply end provides a negative voltage, and the second operational amplifier U1, the fourth resistor R4, the fifth resistor R3, the sixth resistor R2 and the seventh resistor R5 constitute a proportional amplifier with positive bias, thereby realizing proportional amplification.

[0084] Some embodiments of the present application, as shown in Figure 3 The second proportional amplification unit comprises:

[0085] The third operational amplifier U4 has its non-inverting input electrically connected to the output of the first operational amplifier U3, and the output of the third operational amplifier U4 electrically connected to the base of the second transistor Q7.

[0086] The eighth resistor R9 has one end electrically connected to the output of the third operational amplifier U4.

[0087] The ninth resistor R8 has one end electrically connected to the other end of the eighth resistor R9.

[0088] The tenth resistor R7 has one end electrically connected to the other end of the ninth resistor R8, and the other end electrically connected to the positive supply end.

[0089] The eleventh resistor R11 has one end electrically connected to one end of the tenth resistor R7, and the other end grounded.

[0090] In this embodiment, the positive supply end provides a positive voltage, and the third operational amplifier U4, the eighth resistor R9, the ninth resistor R8, the tenth resistor R7 and the eleventh resistor R11 constitute a proportional amplifier with negative bias, thereby realizing proportional amplification.

[0091] Some embodiments of the present application, as shown in Figure 4 The third mirror current source sub-circuit 300 comprises:

[0092] The first MOS transistor M6 has its drain electrically connected to the collector of the second transistor Q7, its drain electrically connected to the collector of the sixth transistor Q4, its source electrically connected to the negative supply end, and its gate electrically connected to its drain.

[0093] The second MOS transistor M7 has its gate electrically connected to the gate of the first MOS transistor M6, its source electrically connected to the negative supply end, and its drain electrically connected to the root mean square operation sub-circuit 500.

[0094] In this embodiment, as shown in Figure 2 The third mirror current source sub-circuit 300 copies the absolute value current signal. The absolute value current signal flows into the drain of the first MOS tube M6, and is output to the square root operation sub-circuit 500 through the drain of the second MOS tube M7.

[0095] In an embodiment of the present application, the square root operation sub-circuit 500 comprises:

[0096] The square operation unit 510 is electrically connected to the absolute value sub-circuit 100, and is configured to perform square operation on the absolute value current signal to obtain a square current signal.

[0097] The division operation unit 520 is electrically connected to the square operation unit 510, and is configured to perform division operation on the square current signal and the first square root current signal to obtain a division current signal.

[0098] The average operation unit is electrically connected to the division operation unit 520, and is configured to perform average operation on the division current signal to obtain a second square root current signal.

[0099] In this embodiment, the absolute value current signal is squared by the square operation unit 510 to obtain a square current signal, the square current signal and the first square root current signal are divided by the division operation unit 520 to obtain a division current signal, and the division current signal is averaged by the average operation unit to obtain a second square root current signal.

[0100] In an embodiment of the present application, as shown in Figure 4 The square operation unit 510 comprises:

[0101] The seventh transistor Q9 has its emitter electrically connected to the absolute value sub-circuit 100, its emitter electrically connected to the division operation unit 520, and its base electrically connected to its collector.

[0102] The eighth transistor Q10 has its emitter electrically connected to the collector of the seventh transistor Q9, its collector electrically connected to its base, and its collector grounded.

[0103] In this embodiment, the absolute value current signal flows through the eighth transistor Q10 and the seventh transistor Q9, and the emitter voltage of the seventh transistor Q9 is calculated by the following formula:

[0104] U A =-U be9-U be10 = -V T *In(|Iin| / Is) = -V T *In(|Iin| / Is) = -V T *In(|Iin| 2 / Is 2 ),

[0105] wherein, U A is an emitter voltage of the seventh transistor Q9, U be9 is a voltage between a base and an emitter of the seventh transistor Q9, U be10 is a voltage between a base and an emitter of the eighth transistor Q10, VT is a temperature voltage equivalent of the seventh transistor Q9, Is is a saturation current of the seventh transistor Q9, and |Iin| is an absolute value current signal.

[0106] Therefore, the absolute value current signal can be squared by the eighth transistor Q10 and the seventh transistor Q9 to obtain a square current signal.

[0107] Some embodiments of the present application, as shown in Figure 4 , further comprise a fourth operational amplifier U2, an emitter of the seventh transistor Q9 is electrically connected to a non-inverting input terminal of the fourth operational amplifier U2, an output terminal of the fourth operational amplifier U2 is electrically connected to the division operation unit 520, and the output terminal of the fourth operational amplifier U2 is electrically connected to an inverting input terminal of the fourth operational amplifier U2. The fourth operational amplifier U2 functions as a follower for inputting the square current signal to the division operation unit 520.

[0108] An embodiment of the present application, as shown in Figure 4 , the division operation unit 520 comprises:

[0109] a ninth transistor Q5, an emitter of the ninth transistor Q5 is electrically connected to the square operation unit 510, and a collector of the ninth transistor Q5 is electrically connected to the average operation unit;

[0110] a logarithmic amplification subunit, the average operation unit is electrically connected to the logarithmic amplification subunit, the logarithmic amplification subunit is electrically connected to a base of the ninth transistor Q5, and the logarithmic amplification subunit is configured to take a natural logarithm of the first root mean square current signal to obtain a logarithmic current signal, and input the logarithmic current signal to the base of the ninth transistor Q5, so that the ninth transistor Q5 performs a division operation according to the square current signal and the logarithmic current signal to obtain a division current signal.

[0111] In this embodiment, the square current signal is input to the emitter of the ninth transistor Q5, the logarithmic amplification subunit obtains the logarithmic current signal by taking the natural logarithm of the first root-mean-square current signal, and inputs the logarithmic current signal to the base of the ninth transistor Q5, so that the ninth transistor Q5 performs division operation according to the square current signal and the logarithmic current signal to obtain the division current signal.

[0112] Some embodiments of the present application, as shown in Figure 4 The logarithmic amplification subunit comprises:

[0113] The fifth operational amplifier U5, the non-inverting input terminal of the fifth operational amplifier U5 is grounded, the inverting input terminal of the fifth operational amplifier U5 is electrically connected to the average operation unit, and the output terminal of the fifth operational amplifier U5 is electrically connected to the base of the ninth transistor Q5.

[0114] The thirteenth transistor Q8, the collector of the thirteenth transistor Q8 is electrically connected to the inverting input terminal of the fifth operational amplifier U5, the base of the thirteenth transistor Q8 is grounded, and the emitter of the thirteenth transistor Q8 is electrically connected to the base of the ninth transistor Q5.

[0115] In this embodiment, the thirteenth transistor Q8 and the fifth operational amplifier U5 constitute a logarithmic amplifier, and the current signal flowing to the logarithmic amplifier output by the average operation unit is the first root-mean-square current signal, and the logarithmic amplifier takes the natural logarithm of the first root-mean-square current signal to obtain the logarithmic current signal. The seventh transistor Q9, the eighth transistor Q10, the ninth transistor Q5 and the thirteenth transistor Q8 can offset the temperature drift to each other, thereby improving the temperature drift performance.

[0116] The emitter voltage of the ninth transistor Q5 is the same as the emitter voltage of the seventh transistor Q9, and the base voltage of the ninth transistor Q5 is calculated by the following formula:

[0117] U B = -U be8 = -V T *In(Irms1 / Is),

[0118] Wherein, U be8 is the voltage between the base and the emitter of the thirteenth transistor Q8, V T is the temperature voltage equivalent of the thirteenth transistor Q8, Is is the saturation current of the thirteenth transistor Q8, and Irms1 is the first root-mean-square current signal.

[0119] The voltage between the base and the emitter of the ninth transistor Q5 is calculated by the following formula:

[0120] U be5 = U B -U A = -V T*In(Irms1 / Is)+V T *In(|Iin| 2 / Is 2 )=V T *In(|Iin| 2 / Irms1 / Is 2 ),

[0121] As can be seen from the above formula, the ninth transistor Q5 performs a division operation on the square current signal and the logarithmic current signal. The collector current of the ninth transistor Q5 is subjected to an average calculation by the average operation unit to obtain a second root mean square current signal, and the calculation formula is as follows:

[0122] I c5 =Irms2=mean(|Iin| 2 / Irms1),

[0123] wherein, I c5 is the collector current of the ninth transistor Q5, Irms2 is the second root mean square current signal, and mean is an average value operation operator.

[0124] An embodiment of the present application, as shown in the figure, the average operation unit comprises: Figure 4

[0125] The second resistor R1, the division operation unit 520 is electrically connected to one end of the second resistor R1, and the other end of the second resistor R1 is electrically connected to the result output sub-circuit;

[0126] The capacitor C1, the division operation unit 520 is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded.

[0127] In this embodiment, the second resistor R1 and the capacitor C1 constitute a first-order filter current, and the division current signal is subjected to an average operation by the first-order filter circuit to obtain the second root mean square current signal, and the current flowing through the second resistor R1 is the second root mean square current signal.

[0128] Some embodiments of the present application also include a fourth mirror current source sub-circuit 400, which comprises:

[0129] The third MOS tube M1, the source of the third MOS tube M1 is electrically connected to the positive power supply end, the gate of the third MOS tube M1 is electrically connected to the drain of the third MOS tube M1, and the drain of the third MOS tube M1 is electrically connected to the other end of the second resistor R1;

[0130] ​The fourth MOS transistor M2 has its source electrically connected to the positive power supply end, and the gate of the third MOS transistor M1 is electrically connected to the gate of the fourth MOS transistor M2. The drain of the fourth MOS transistor M2 is electrically connected to the collector of the thirteenth diode Q8, and the drain of the fourth MOS transistor M2 is electrically connected to the inverting input terminal of the fifth operational amplifier U5.

[0131] The fifth MOS transistor M3 has its source electrically connected to the positive power supply end, and the gate of the third MOS transistor M1 is electrically connected to the gate of the fifth MOS transistor M3. The drain of the fifth MOS transistor M3 is electrically connected to the result output sub-circuit.

[0132] In the embodiment, as shown in Figure 2 The fourth mirror current source sub-circuit 400 copies the second root mean square current signal, and inputs the logarithmic amplification sub-unit through the drain of the fourth MOS transistor M2, and inputs the result output sub-circuit through the drain of the fifth MOS transistor M3.

[0133] In the embodiment, as shown in Figure 4 The result output sub-circuit includes:

[0134] The second mirror current source sub-circuit 200 is electrically connected to the root mean square operation sub-circuit 500, and is used to copy the second root mean square current signal.

[0135] The third resistor R14 has one end electrically connected to the second mirror current source sub-circuit 200, and the other end grounded. The third resistor R14 is used to output a root mean square voltage signal according to the second root mean square current signal.

[0136] In the embodiment, as shown in Figure 2 The second mirror current source sub-circuit 200 copies the second root mean square current signal, and the second root mean square current signal flows through the third resistor R14, so as to be converted into a root mean square voltage signal output. The second mirror current source sub-circuit 200 and the fourth mirror current source sub-circuit 400 use symmetrical MOS transistors to eliminate the error introduced by the mirror current source to a certain extent, so as to provide measurement and calculation accuracy.

[0137] The root mean square voltage signal is calculated by the following formula:

[0138] Vrms=Irms2*R,

[0139] Wherein, Vrms is the root mean square voltage signal, and R is the resistance value of the third resistor R14.

[0140] In the embodiment, as shown in Figure 4 The second mirror current source sub-circuit 200 includes:

[0141] The drain of the sixth MOS transistor M4 is electrically connected to the drain of the fifth MOS transistor M3, the drain of the sixth MOS transistor M4 is electrically connected to the gate of the sixth MOS transistor M4, and the source of the sixth MOS transistor M4 is electrically connected to the negative power supply end;

[0142] The gate of the seventh MOS transistor M5 is electrically connected to the gate of the sixth MOS transistor M4, the drain of the seventh MOS transistor M5 is electrically connected to the third resistor R14, and the source of the seventh MOS transistor M5 is electrically connected to the negative power supply end.

[0143] In the embodiment, the drain current of the sixth MOS transistor M4 is the same as the drain current of the seventh MOS transistor M5, and the drain current of the sixth MOS transistor M4 is the second root mean square current signal, so that the second root mean square current signal is copied to the third resistor R14.

[0144] In addition, the embodiment of the present application further provides a nuclear radiation detector, which comprises the root mean square voltage calculation circuit as described above.

[0145] The nuclear radiation detector provided by the embodiment of the present application can realize the various processes realized by the circuit embodiment described above and achieve the same beneficial effects. To avoid repetition, details are not described here.

[0146] The above describes the embodiments of the present application in detail in combination with the drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge range of ordinary skilled in the art without departing from the purpose of the present application.

Claims

1. A root mean square voltage calculation circuit, characterized by comprising: The application relates to a nuclear radiation detector, which comprises: an absolute value sub-circuit for absolute value processing of an input voltage signal of the nuclear radiation detector to convert the input voltage signal into an absolute value current signal; a root mean square operation sub-circuit comprising a first input end, a second input end and a signal output end, the first input end being electrically connected with the absolute value sub-circuit, the signal output end being electrically connected with the second input end, the root mean square operation sub-circuit being used for root mean square operation of the absolute value current signal by using a first root mean square current signal to convert the input voltage signal into a second root mean square current signal, the first root mean square current signal being a current signal fed back from the signal output end to the second input end; a result output sub-circuit electrically connected with the signal output end, the result output sub-circuit being used for converting the second root mean square current signal into a root mean square voltage signal and outputting the root mean square voltage signal.

2. The root mean square voltage calculation circuit according to claim 1, characterized in that, The absolute value sub-circuit comprises: a first operational amplifier, a non-inverting input end of the first operational amplifier being used for inputting the input voltage signal; a first triode, an output end of the first operational amplifier being electrically connected with a base of the first triode, the first triode being used for being turned on when the input voltage signal is positive; a first resistor, an emitter of the first triode being electrically connected with one end of the first resistor, a non-inverting input end of the first operational amplifier being electrically connected with the one end of the first resistor, the other end of the first resistor being grounded; a first mirror current source sub-circuit, a collector of the first triode being electrically connected with the first mirror current source sub-circuit, the first mirror current source sub-circuit being electrically connected with the root mean square operation sub-circuit, the first mirror current source sub-circuit being used for copying a collector current of the first triode to obtain and output the absolute value current signal when the first triode is turned on; a second triode, an output end of the first operational amplifier being electrically connected with a base of the second triode, an emitter of the second triode being electrically connected with the one end of the first resistor, a collector of the second triode being electrically connected with the root mean square operation sub-circuit, the second triode being used for being turned on when the input voltage signal is negative, so that the collector of the second triode outputs the absolute value current signal.

3. The root mean square voltage calculation circuit according to claim 2, characterized in that The first mirror current source sub-circuit comprises: a third triode, an emitter of the third triode being used for being electrically connected with a positive power supply end; a fourth triode, a collector of the third triode being electrically connected with an emitter of the fourth triode, the collector of the fourth triode being electrically connected with a collector of the first triode, the collector of the fourth triode being electrically connected with a base of the fourth triode; a fifth triode, an emitter of the fifth triode being used for being electrically connected with the positive power supply end, a base of the fifth triode being electrically connected with a base of the third triode, the base of the fifth triode being electrically connected with a collector of the fifth triode; A sixth transistor, an emitter of the fifth transistor is electrically connected to an emitter of the sixth transistor, a collector of the sixth transistor is electrically connected to the RMS operation sub-circuit.

4. The root mean square voltage calculation circuit according to claim 2, characterized in that, The absolute value sub-circuit further comprises: A first proportional amplification unit, an output of the first operational amplifier is electrically connected to an input of the first proportional amplification unit, an output of the first proportional amplification unit is electrically connected to a base of the first transistor; A second proportional amplification unit, an output of the first operational amplifier is electrically connected to an input of the second proportional amplification unit, an output of the second proportional amplification unit is electrically connected to a base of the second transistor.

5. The root mean square voltage calculation circuit of claim 1, wherein, The RMS operation sub-circuit comprises: A square operation unit, the square operation unit is electrically connected to the absolute value sub-circuit, the square operation unit is used for performing square operation on the absolute value current signal to obtain a square current signal; A division operation unit, the division operation unit is electrically connected to the square operation unit, the division operation unit is used for performing division operation on the square current signal and the first RMS current signal to obtain a division current signal; An average operation unit, the average operation unit is electrically connected to the division operation unit, the average operation unit is used for performing average operation on the division current signal to obtain the second RMS current signal.

6. The root mean square voltage calculation circuit of claim 5, wherein, The square operation unit comprises: A seventh transistor, an emitter of the seventh transistor is electrically connected to the absolute value sub-circuit, an emitter of the seventh transistor is electrically connected to the division operation unit, a base of the seventh transistor is electrically connected to a collector of the seventh transistor; An eighth transistor, a collector of the seventh transistor is electrically connected to an emitter of the eighth transistor, a collector of the eighth transistor is electrically connected to a base of the eighth transistor, the collector of the eighth transistor is grounded.

7. The root mean square voltage calculation circuit of claim 5, wherein, The division operation unit comprises: A ninth transistor, an emitter of the ninth transistor is electrically connected to the square operation unit, a collector of the ninth transistor is electrically connected to the average operation unit; A logarithmic amplification sub-unit, the average operation unit is electrically connected to the logarithmic amplification sub-unit, the logarithmic amplification sub-unit is electrically connected to the base of the ninth transistor, the logarithmic amplification sub-unit is used for taking natural logarithm of the first RMS current signal to obtain a logarithmic current signal, and inputting the logarithmic current signal to the base of the ninth transistor, so that the ninth transistor performs division operation according to the square current signal and the logarithmic current signal to obtain the division current signal.

8. The root mean square voltage calculation circuit of claim 5, wherein, The average operation unit comprises: A second resistor, one end of the second resistor is electrically connected to the division operation unit, the other end of the second resistor is electrically connected to the result output sub-circuit; A capacitor, one end of the capacitor is electrically connected to the division operation unit, the other end of the capacitor is grounded.

9. The root mean square voltage calculation circuit of claim 1, wherein, The result output sub-circuit comprises: A second mirror current source sub-circuit, the second mirror current source sub-circuit is electrically connected to the RMS operation sub-circuit, the second mirror current source sub-circuit is used for copying the second RMS current signal; A third resistor, one end of the third resistor is electrically connected with the second mirror current source sub-circuit, the other end of the third resistor is grounded, the third resistor is used for outputting the root mean square voltage signal according to the second root mean square current signal.

10. A nuclear radiation detector, characterized by The root mean square voltage calculation circuit as claimed in any one of claims 1 to 9.

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