Command processing method, controller and computer system

Abstract

The embodiment of the invention provides a command processing method, a controller and a computer system.The method comprises the steps that an analysis result of a data processing command is obtained, and the analysis result comprises all operations used for completing interaction between the data processing command and a memory; determining the operation type of each operation, and setting a loose sorting value for each operation based on the out-of-order execution definition corresponding to each operation type, so as to realize out-of-order execution of each operation interacting with the memory among different data processing commands according to the loose sorting value set by the out-of-order execution definition; the out-of-order execution definition is used for indicating whether out-of-order execution of the operation is allowed or not according to conditions for correct execution of the data processing command; and performing packing processing on each operation for completing the setting of the loose sorting value to obtain a data packet corresponding to the data processing command. According to the technical scheme provided by the embodiment of the invention, the execution efficiency of the data processing command can be improved while the execution correctness of the data processing command is ensured.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a command processing method, a controller, and a computer system. Background Art

[0002] As the demand for chip computing power and storage increases, the amount of data that the processor needs to process also increases. Correspondingly, the amount of data moved also increases. In the process of data movement, multiple data processing commands are usually sent at one time to move the data required for each calculation in different addresses. The data transmission process executed by the data processing command must support the corresponding transmission protocol to ensure that the data processing command is executed correctly.

[0003] However, there is a problem of not being able to strike a good balance between the correctness of data processing command execution and the efficiency of data processing command execution. Therefore, how to provide a technical solution to ensure the correctness of data processing command execution while improving the efficiency of data processing command execution has become a technical problem that those skilled in the art need to solve urgently. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a command processing method, a controller and a computer system to ensure the correctness of the execution of data processing commands while improving the execution efficiency of data processing commands.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a command processing method, including:

[0007] Obtaining a parsing result of the data processing command, wherein the parsing result includes various operations for interacting with the memory to complete the data processing command;

[0008] Determine the operation type of each operation, and set a relaxed ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, so as to implement out-of-order execution of each operation interacting with the memory between different data processing commands according to the relaxed ordering value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether the operation allows out-of-order execution according to the condition for correct execution of the data processing command;

[0009] The operations for setting the loose sorting value are grouped and processed to obtain a data packet corresponding to the data processing command.

[0010] In a second aspect, an embodiment of the present invention provides a controller, including:

[0011] A parsing result acquisition module, used to acquire the parsing result of the data processing command, wherein the parsing result includes various operations for completing the data processing command and interacting with the memory;

[0012] A loose ordering value setting module, used to determine the operation type of each operation, and set a loose ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, so as to realize out-of-order execution of each operation interacting with the memory between different data processing commands according to the loose ordering value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether the operation allows out-of-order execution according to the conditions for the correct execution of the data processing command;

[0013] The packet assembly module is used to perform packet assembly processing on each operation of setting the loose sort value to obtain a data packet corresponding to the data processing command.

[0014] In a third aspect, an embodiment of the present invention provides a computer system, comprising: a controller as described in the second aspect.

[0015] A command processing method provided by an embodiment of the present invention includes: obtaining a parsing result of a data processing command, wherein the parsing result includes various operations for completing the data processing command to interact with a memory; determining the operation type of each operation, and setting a loose sorting value for each operation based on an out-of-order execution definition corresponding to each operation type, so as to implement out-of-order execution of various operations for interacting with a memory between different data processing commands according to the loose sorting value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether an operation is allowed to be executed out-of-order according to a condition for the correct execution of the data processing command; and performing packet processing on various operations for which the loose sorting value is set to obtain a data packet corresponding to the data processing command.

[0016] It can be seen that the technical solution provided by the embodiment of the present invention analyzes and processes the parsing results of the data processing command, so as to define out-of-order execution corresponding to different operation types and determine whether the operation can be executed out-of-order; because it is usually necessary to parse the data processing command to obtain the parsing result when processing the data processing command, the parsing result may include various operations involved in executing the data processing command, and the operation of interacting with the memory is the main execution content of the data processing command. Different data processing commands contain different operations of interacting with the memory, and the transmission address and data block for transmitting the data block to the memory are different, and the corresponding memory address corresponding to the completion queue of updating the memory is also different. Therefore, between different data processing commands, the various operations of interacting with the memory are independent of each other. Each operation can be executed out of order based on the setting control of the loose sorting value, but when processing data processing commands, there is no mechanism for flexibly controlling the loose sorting value of each operation interacting with the memory in each data processing command; thus, when executing a large number of data processing commands, the parallelism of each operation interacting with the memory between different data processing commands is reduced, and the execution efficiency of the data processing commands is reduced; so that the execution efficiency of the data processing commands and the execution correctness of the data processing commands cannot be guaranteed at the same time. Based on this, in the technical solution provided by the embodiment of the present invention, based on the parsing result of the data processing command, the specific operation type corresponding to each operation interacting with the memory is first determined, and then based on the out-of-order execution definition corresponding to the operation type, the loose sorting value is set for each operation interacting with the memory in each data processing command. Since each operation of the memory interaction is allowed to be executed out of order to ensure the correct execution of the data processing command, it is indicated by the out-of-order execution definition corresponding to each operation type, so that the execution order of each operation can meet the conditions for the correct execution of the data processing command by setting the loose sorting value according to the out-of-order execution definition. Therefore, in the technical solution provided by the embodiment of the present invention, the execution efficiency of the data processing commands can be improved while ensuring the correctness of the execution of the data processing commands. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0018] Figure 1 It is a flowchart of a command processing method provided by an embodiment of the present invention;

[0019] Figure 2is a schematic diagram of the working process of the controller provided by an embodiment of the present invention;

[0020] Figure 3 It is a schematic diagram of the execution order of data processing commands when the loose sorting value is not enabled according to an embodiment of the present invention;

[0021] Figure 4 It is a schematic diagram of the execution order of data processing commands when a loose sorting value is enabled according to an embodiment of the present invention;

[0022] Figure 5 It is a schematic diagram of the execution sequence of data processing commands in the technical solution provided by an embodiment of the present invention;

[0023] Figure 6 It is a schematic diagram of an implementation flow of a command processing method provided by an embodiment of the present invention;

[0024] Figure 7 is a schematic diagram of a structure of a controller provided by an embodiment of the present invention;

[0025] Figure 8 It is a structural diagram of a computer system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] With the continuous development of computer technology, the design of processors is becoming more and more complex, and computer systems have higher and higher requirements for bandwidth latency of disk access. For example, solid-state drives (SSDs) are becoming more and more the development trend of future disks because of their fast access speed, low power consumption, and light weight. Among them, solid-state drives using the NVME protocol (Non-Volatile Memory Express protocol: a protocol designed specifically for non-volatile memory) and PCIE (Peripheral Component Interconnect Express: Peripheral Component Interconnect Express bus) interface are gradually becoming the main disk choice for high-performance scenarios because of their multi-threaded transmission and high link bandwidth.

[0028] When executing data processing commands, the controller of the solid-state drive must transmit and process the commands according to the transmission protocol of its transmission interface. For example, the controller of the solid-state drive using the NVME protocol and the PCIE interface mentioned above must comply with the execution order defined in the PCIE protocol when processing and transmitting data processing commands.

[0029] When executing a data processing command, the controller usually parses the data processing command, splits it into multiple data blocks, and then packages each data block into a transaction layer packet (TLP). Therefore, when the transmission interface processes the data processing command, it transmits and processes the packaged transaction layer packets. The transmission order of the transaction layer packets must comply with the order defined in the protocol of the transmission interface.

[0030] Continuing to take the PCIE protocol used by the transmission interface as an example, when the transaction layer data packet is transmitted, it is transmitted and processed according to the transaction order specified in the PCIE protocol.

[0031] The transaction order of the PCIE protocol stipulates:

[0032] In a data processing command, between the operations interacting with the memory: the update operation of the completion queue of the memory cannot exceed the operation of transferring the data block to the memory;

[0033] Between operations that interact with memory and operations that do not interact with memory: An interrupt operation that sends an interrupt to the processor cannot override an operation that interacts with memory.

[0034] That is to say, the PCIE protocol stipulates that the transaction layer data packets after each operation group must be executed sequentially, but the various data processing commands read and executed by NVME can be processed in parallel, that is, the data flow between data processing commands (various operations interacting with memory) has no dependency.

[0035] In the above-mentioned SSD structure, the protocol used by the controller to read and execute data processing commands is called the upper layer protocol, and the transmission protocol of the transmission interface used to transmit transaction layer data packets is the lower layer protocol. Due to the usage rules of the upper layer protocol and the lower layer protocol, when the controller transmits and processes data processing commands, it cannot ensure the parallelism of data processing commands while ensuring the correctness of the execution of data processing commands.

[0036] Based on this, an embodiment of the present invention provides a command processing method for improving the transmission efficiency of data processing commands while ensuring the correctness of the execution of data processing commands.

[0037] Please refer to Figure 1 , Figure 1 It is a flowchart of a command processing method provided by an embodiment of the present invention.

[0038] like Figure 1 As shown, the method comprises the following steps:

[0039] Step S101, obtaining a parsing result of a data processing command, wherein the parsing result includes various operations for interacting with a memory to complete the data processing command.

[0040] Data processing commands can be read and executed by the controller from the command queue in the memory to avoid using the processor's resources to execute data transmission, ensuring that the processor has sufficient resources to handle other tasks and improving the performance of the computer system.

[0041] At the same time, the purpose of the controller reading and executing the data processing command is to replace the processor to perform the task of data transmission. Therefore, the process of the controller executing the data processing command also includes sending an interrupt to the processor, which is not an operation of interacting with the memory, to inform the processor that the data processing command has been executed.

[0042] Therefore, in the embodiments provided by the present invention, operations related to the memory are referred to as operations interacting with the memory, and operations related to the processor are referred to as operations not interacting with the memory.

[0043] To understand the controller read and execute the data processing command implementation process. Please refer to Figure 2 , Figure 2 It is a schematic diagram of the working process of the controller provided by an embodiment of the present invention.

[0044] Figure 2 The controller shown may be an NVME controller.

[0045] like Figure 2 As shown, the steps of the controller executing the data processing command include:

[0046] 1. Host 2 writes the data processing command to the next free slot in the command queue (submission queue) in memory 3.

[0047] 2. Host 2 updates the Submission Queue TailDoorbell register in controller 01. The Submission Queue TailDoorbell register is usually used to describe a hardware or software mechanism in an input / output (I / O) operation.

[0048] 3. Controller 01 reads the data processing command from the command queue of memory 3.

[0049] 4. Controller 01 executes the data processing command and completes the read and write access to memory 3 (data buffer).

[0050] 5. Controller 01 submits a completion signal to the completion queue in memory 3, wherein the completion queue includes multiple completion queue entries; each completion queue entry includes: the latest completed entry of the command queue (consumed entry) and a phase tag invert. In the PCIE architecture, the phase tag invert is used to ensure the correct ordering of data packets and the integrity of transactions in PCIE transactions.

[0051] 6. Controller 01 sends an interrupt to the CPU to notify the Completion Queue to update.

[0052] 7. The CPU checks the phase tag toggle and finds all updated completed data processing commands. In the PCIE architecture, "Phase Tag Toggle" usually refers to switching the phase or phase of the tag in the tag field of the transaction layer data packet (TLP) to ensure the correct ordering of the data packet and the integrity of the transaction.

[0053] 8. Host 2 writes the Completion Queue Head Doorbell register in controller 01 to notify controller 01 of the completion queue release.

[0054] The communication network is used to realize the interaction among the controller 01, the host 2, and the memory 3. The communication network may be, for example, a Network-on-Chip (NoC).

[0055] NoC is a communication architecture for System-on-Chip (SoC) that solves the communication problems caused by large-scale integration by implementing a network-like structure inside the chip.

[0056] Step S102 : determining the operation type of each operation, and setting a loose sorting value for each operation based on the out-of-order execution definition corresponding to each operation type.

[0057] Out-of-order execution of various operations interacting with memory is implemented between different data processing commands with a loose sort value set according to an out-of-order execution definition; the out-of-order execution definition is used to indicate whether an operation is allowed to be executed out-of-order based on the conditions for correct execution of the data processing command.

[0058] Relaxed order (RO) is used to describe the relaxation of the order of operations in concurrent programming and multithreaded environments. "Relax" means allowing the execution order of certain operations to not strictly adhere to the order in which they appear in the program, which may improve the parallelism and performance of the program.

[0059] In a controller of a solid-state drive using a PCIE interface and an NVME protocol, a loose ordering value is used to specify an attribute of a transaction layer data packet after PCIE packetization, so as to indicate that a receiving end can adopt a loose order when processing the transaction layer data packet.

[0060] The out-of-order execution definition can be defined according to the execution scenario of the data processing command. For example, it can be defined based on the transmission protocol used when executing the data processing command, so as to ensure that the data processing command can be executed correctly.

[0061] The following continues to use the PCIE transmission protocol using the PCIE interface as an example to illustrate the processing and transmission of data processing commands.

[0062] When using the PCIE transport protocol, the out-of-order execution definition corresponding to the operation type of each operation can be defined according to the transaction layer data packet execution order in the PCIE transport protocol. For example, Figure 2 The out-of-order execution definition corresponding to the operation type of the "4" operation shown indicates that the operation allows out-of-order execution, and the out-of-order execution definition corresponding to the operation type of the "5" operation indicates that the operation does not allow out-of-order execution, thereby avoiding the situation where when the "5" operation is allowed to be out-of-order, the "5" operation is executed before the "4" operation, resulting in an error in the execution of the data processing command.

[0063] Based on the above content, it can be seen that different data processing commands in NVME can be processed in parallel, but PCIE needs to ensure that the transaction layer data packets are executed in sequence, which will reduce the parallelism of operations interacting with the memory in the data processing commands and reduce the execution efficiency of the data processing commands.

[0064] For example, Figure 2 Taking the controller workflow diagram shown in the figure as an example, in the process of executing a data processing command, the operations included are:

[0065] The controller performs the steps of data transfer (i.e. Figure 2 The "4" operation shown in the figure) is used to write a data block to the memory or read it from the memory.

[0066] The controller submits the completion to the completion queue in memory, which is the complement of the completion queue that updates the memory (i.e. Figure 2 "5" operation shown).

[0067] The step where the controller sends an interrupt to the processor (i.e. Figure 2 The "6" operation shown is used to inform the processor that the controller has completed the execution of the data processing command.

[0068] In the above operations, operations "4", "5" and "6" of different data processing commands can be processed in parallel. Therefore, under the provisions of the PCIE protocol, if the RO value of each operation is not enabled during the process of forming a transaction layer data packet, for example, the RO value is "0", then when the controller executes multiple data processing commands, operations "4", "5" and "6" of each data processing command need to be executed sequentially. Please refer to Figure 3 , Figure 3 It is a schematic diagram of the execution order of data processing commands when the loose sorting value is not enabled according to an embodiment of the present invention.

[0069] like Figure 3 As shown, the controller processes each data processing command: CMD1, CMD2, CMD3, and the execution order is to execute in sequence according to the order of reading and executing the data processing commands ( Figure 3 The sequence of increasing time from right to left is used as an example for display).

[0070] It can be seen that, although there is no sequential execution relationship essentially between the "5" operation: CMD1.5 of the command (for example, CMD1) with a later reading and execution order and the interrupt request CMD0.6 of the command (for example, CMD0) with an earlier reading and execution order, they must be completed sequentially due to the PCIE transaction layer data packet execution order regulations. At this time, the operations that interact with the memory in different data processing commands are reduced: the parallelism of the "5" operation is reduced, and the bandwidth is reduced.

[0071] If the loose ordering value of the operation is enabled, for example, RO is "1", the RO value of each operation in the data processing command is usually uniformly set using the PCI Express Device Control Register defined in the NVME controller.

[0072] Since the PCIE device control register does not distinguish the operation type of different operations in each data processing command, it will set the RO of all operations to "1", please refer to Figure 4 , Figure 4 It is a schematic diagram of the execution order of data processing commands when the loose sorting value is enabled according to an embodiment of the present invention.

[0073] like Figure 4As shown in the figure, if the RO of all operations are set to "1", the second data processing command read and executed: CMD1's "4" operation CMD1.4 can surpass the first data processing command read and executed: CMD0's "6" operation CMD0.6, thereby realizing the out-of-order execution of data processing commands and improving parallelism. However, the third data processing command read and executed: CMD2's "5" operation CMD2.5 surpasses its own "4" operation CMD2.4, and the operation of updating the completion queue of the memory is completed before the operation of executing the data transfer, resulting in data transmission errors and data processing command execution errors.

[0074] exist Figure 3 and Figure 4 In the execution sequence diagram shown, it can be seen that regardless of whether the loose sorting value is enabled, the order of the "6" operation of each data processing command corresponds to the reading and execution order of each data processing command, and is later than the execution time of the operation of interacting with the memory ("4" and "5" operations) of each data processing command, thereby ensuring the correctness of the execution order of each data processing command.

[0075] Therefore, in the embodiment of the present invention, for each operation of each data processing command interacting with the memory, a targeted loose sorting value is set based on the out-of-order execution definition corresponding to the operation type, so that an accurate loose sorting value can be set for each operation. Figure 4 As shown in , when the loose sorting values ​​of all operations are uniformly set, although the parallelism of data processing commands can be improved, it may cause errors in the execution of data processing commands.

[0076] Step S103, grouping the operations for setting the loose sorting value to obtain a data packet corresponding to the data processing command.

[0077] The data packet corresponding to the data processing command is, for example, the transaction layer data packet mentioned above.

[0078] After processing the data processing commands using the technical solution provided by the embodiment of the present invention, the execution status of each data processing command can be referred to Figure 5 , Figure 5 It is a schematic diagram of the execution sequence of data processing commands in the technical solution provided by an embodiment of the present invention.

[0079] Figure 5 The PCIE protocol is used as an example for the transmission protocol.

[0080] like Figure 5As shown, between different data processing commands, the operations of interacting with the memory: "4" operation and "5" operation may not be executed in the order of reading and executing the data processing commands; in each data processing command, the execution order of "4" operation is guaranteed to be earlier than the execution order of "5" operation, so as to meet the provisions of the PCIE transmission protocol and ensure the correct execution of each data processing command.

[0081] The execution order of the "6" operation between different data processing commands corresponds to the reading and execution time of each data processing command, so that the order between data processing commands can be maintained. For example, in the same data processing command, the operation of executing data transmission is sequenced with the operation of sending interrupts, the operation of executing data transmission is sequenced with the operation of updating the completion queue of the memory, and the operation of updating the completion queue of the memory is sequenced with the operation of sending interrupts.

[0082] It can be seen that the technical solution provided by the embodiment of the present invention analyzes and processes the parsing results of the data processing command, so as to define out-of-order execution corresponding to different operation types and determine whether the operation can be executed out of order; because it is usually necessary to parse the data processing command to obtain the parsing result when processing the data processing command, the parsing result may include various operations involved in executing the data processing command, and the operation of interacting with the memory is the main execution content of the data processing command. Different data processing commands contain different operations of interacting with the memory, and the transmission address and data block for transmitting the data block to the memory are different, and the corresponding memory address corresponding to the completion queue of updating the memory is also different. Therefore, between different data processing commands, the various operations of interacting with the memory are independent of each other. Each operation can be executed out of order based on the setting control of the loose sorting value, but when processing data processing commands, there is no mechanism for flexibly controlling the loose sorting value of each operation interacting with the memory in each data processing command; thus, when executing a large number of data processing commands, the parallelism of each operation interacting with the memory between different data processing commands is reduced, and the execution efficiency of the data processing commands is reduced; so that the execution efficiency of the data processing commands and the execution correctness of the data processing commands cannot be guaranteed at the same time. Based on this, in the technical solution provided by the embodiment of the present invention, based on the parsing result of the data processing command, the specific operation type corresponding to each operation interacting with the memory is first determined, and then based on the out-of-order execution definition corresponding to the operation type, the loose sorting value is set for each operation interacting with the memory in each data processing command. Since each operation of the memory interaction is allowed to be executed out of order to ensure the correct execution of the data processing command, it is indicated by the out-of-order execution definition corresponding to each operation type, so that the execution order of each operation can meet the conditions for the correct execution of the data processing command by setting the loose sorting value according to the out-of-order execution definition. Therefore, in the technical solution provided by the embodiment of the present invention, the execution efficiency of the data processing commands can be improved while ensuring the correctness of the execution of the data processing commands.

[0083] Please continue to refer to Figure 1 , as shown in the figure, the method may also include:

[0084] Step S100, reading a data processing command, and parsing the data processing command to obtain a parsing result of the data processing command.

[0085] After reading the data processing command, the controller can parse the data processing command to obtain a parsing result, so as to facilitate the subsequent determination of the operation type of different operations based on the parsing result.

[0086] Please continue to refer to Figure 1 , after step S103, the following may also be included:

[0087] Step S104: transmitting a data packet corresponding to the data processing command.

[0088] After setting the loose sorting value for each operation, the data packet can be grouped and transmitted to perform subsequent operations on the data packet. The data packet is the basic unit of the data processing command in the data transmission process, carrying all necessary information of the data processing command.

[0089] For example, a data packet (such as the transaction layer data packet described above) is transmitted to the data link layer for further processing. In the data link layer, the data packet is further encapsulated, and the data link layer adds a sequence number (Sequence ID) to the front of the data packet and calculates a link layer cyclic redundancy check (Link Cyclic Redundancy Check, LCRC) to ensure the transmission integrity of the encapsulated link layer data packet on the link layer.

[0090] Based on the above analysis, it can be known that when executing a data processing command, it includes: executing data transmission to transfer the data block to the memory, updating the completion queue of the memory, and sending an interrupt to the processor. Among them, the operations related to the memory are the operations that interact with the memory, and the operations that interact with the memory may include: the execution operation of transmitting data, the update operation of updating the completion queue of the memory;

[0091] Step S102 may include:

[0092] Determining that the operation type of the execution operation is a first type, and setting a loose sort value for the execution operation according to an out-of-order execution definition corresponding to the first type;

[0093] It is determined that the operation type of the update operation is the second type, and according to the out-of-order execution definition corresponding to the second type, a loose sort value is set for the update operation.

[0094] The execution operation described above corresponds to the process of "transferring the data block to the memory", and the update operation corresponds to the process of "updating the completion queue of the memory".

[0095] Since the conditions for correct execution of data processing commands are different in different data processing command execution scenarios, the out-of-order execution definitions that allow execution operations and update operations to be executed out of order are also different; therefore, after determining the operation type of each operation, a targeted loose sorting value can be set in combination with the out-of-order execution definition corresponding to the operation type; this ensures the correctness of the execution of data processing commands while satisfying the out-of-order execution of each operation and improving the execution efficiency of data processing commands.

[0096] In one embodiment, the out-of-order execution definition is based on a transmission protocol definition for processing the data processing command, the transmission protocol being a condition for the data processing command to be correctly executed;

[0097] Determining that the operation type of the execution operation is the first type, and setting a loose ordering value for the execution operation according to an out-of-order execution definition corresponding to the first type, may include:

[0098] According to the out-of-order execution definition corresponding to the first type, a relaxed ordering value of a first value is set for the execution operation to indicate that out-of-order execution is allowed when processing the data processing command using the transport protocol;

[0099] Determining that the operation type of the update operation is the second type, and setting a loose sort value for the update operation according to an out-of-order execution definition corresponding to the second type, includes:

[0100] Determine whether out-of-order execution is allowed for update operations in a data transfer protocol that defines out-of-order execution;

[0101] If yes, setting a loose sort value of the first value for the update operation corresponding to the second type;

[0102] If not, a loose ordering value of a second value is set for the update operation corresponding to the second type to indicate that out-of-order execution is not allowed when processing the data processing command using the transport protocol.

[0103] According to the provisions of the data transmission order in the transmission protocol, the execution operation is the operation of writing data into the memory or reading data from the memory, so the execution operations between the various data processing commands are independent of each other; thus, the loose sorting value of the execution operation can be set to the first value, for example, "1", indicating that the execution operation (at the receiving end) is allowed to be executed out of order.

[0104] The update operation is judged according to the specific data transmission protocol used to determine whether the loose order value can be set to the first value. For example, in the above embodiment, when the transmission protocol is the PCIE transmission protocol, the PCIE transmission protocol stipulates that the execution order of the execution operation must be earlier than the execution order of the update operation. Therefore, when the PCIE transmission protocol is used, the loose order value of the update operation is set to the second value, and out-of-order execution is not allowed.

[0105] In the PCIE architecture, some transmission protocols allow the operation of transmitting data (execution operation) to be performed later than the operation of updating the completion queue of the memory (update operation). This mechanism is usually called "Posted Writes" or "Write Posting".

[0106] Among them, Posted Writes is a transmission mechanism in which a write transaction can be sent to the target device without waiting for confirmation that the write operation is complete. This means that the data transfer can start even if the completion queue in memory has not been updated.

[0107] Write Posting allows a device to receive a write request and queue it, then immediately send a completion acknowledgment to the initiator, while the actual write operation may be performed later.

[0108] Therefore, according to the specific situation of the data transmission protocol, a suitable out-of-order execution definition is defined to accurately and reliably set the loose ordering value of the update operation and the loose ordering of the execution operation to ensure that the execution of the data processing command will not have errors.

[0109] The out-of-order execution used in the aforementioned embodiment is defined as a method of flexibly setting a loose ordering value based on understanding the system structure.

[0110] Of course, in other embodiments, the out-of-order execution definition can also be defined based on the architecture system that executes the data processing command. For example, in a multi-processor or distributed system, the setting of the loose ordering value can take into account the architectural characteristics of the system, such as cache consistency, memory access mode, etc. Exemplarily, the loose ordering value can be set according to the structure of the NoC system, whether it has natural hardware order preservation, and the binding status of NUMA (Non-Uniform Memory Access). In other words, the conditions for the correct execution of data processing commands are specified in the architecture system.

[0111] To improve the implementation flexibility and practicality of the command processing method in the embodiment of the present invention, in one implementation, the implementation of step S102 may include:

[0112] The software program is executed to determine the operation type of each operation in the analysis result, and based on the out-of-order execution definition corresponding to the determined operation type, a loose ordering value is set for the operation corresponding to each operation type.

[0113] In the embodiment of the present invention, a software program can be used to implement the setting of a loose sorting value. That is, the software program is used to detect the parsing results of the data processing command, identify operations of different operation types, and then, based on the out-of-order execution definition corresponding to each operation type, each operation is set in a targeted manner to meet the accurate setting of the loose sorting value of each operation.

[0114] In some other implementations, step S102 may include:

[0115] Indexing the loose ordering control register, based on the loose ordering values ​​of the out-of-order execution definition records corresponding to the respective operation types, determines the loose ordering values ​​set for the operations corresponding to the respective operation types;

[0116] The loose ordering control register is arranged in a controller that executes the data processing command.

[0117] In the embodiment of the present invention, a hardware structure (loose sort control register) may also be used to implement the setting of a loose sort value for each operation, thereby enhancing the implementation flexibility of the technical solution provided by the embodiment of the present invention.

[0118] In one embodiment, in order to facilitate the use of a hardware structure to implement the setting of a loose ordering value in a command processing method, the loose ordering control register is provided with an execution table entry and a completion queue update table entry; the indexing of the loose ordering control register determines the loose ordering value set for the operation corresponding to each operation type based on the loose ordering value of the out-of-order execution definition record corresponding to each operation type, including:

[0119] When determining that the operation is an execution operation, indexing the loose ordering control register, based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, determines a loose ordering value set for the execution operation;

[0120] When the operation is determined to be an update operation, the loose ordering control register is indexed, and based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, a loose ordering value set for the update operation is determined.

[0121] A relaxed order control register (RELAX ORDER CONTROL REGISTER) is added to the controller. The relaxed order control register may include two entries (fields): an execution entry (MWR RO) and a completion queue update entry (CQUP RO).

[0122] Among them, MWR RO is used to control the attributes of the transaction layer data packet formed in the process of executing the operation: the setting of TLP RO ATTRIBUTE bit. Generally, the TLP RO ATTRIBUTE bit is set to RO=1, indicating that the execution operation can be executed out of order between different data processing commands, thereby increasing the parallelism of the data flow.

[0123] CQUP RO is used to control the attributes of the transaction layer data packet formed in the process of updating the completion queue: TLP RO ATTRIBUTE bit. Generally, TLP RO ATTRIBUTE bit is set to RO=0 to maintain the order of the data blocks of this round of IOPS (Input / Output Operations per Second, one of the disk performance indicators) operation, and ensure that the data blocks in its data processing command have been completely written into the memory.

[0124] In the two entries of the loose order control register, values ​​that can meet the out-of-order execution definition of each operation are set, so as to provide a suitable loose order value for each operation during the process of parsing and packaging the data processing command.

[0125] When the hardware structure (relaxed sorting control register) is used to implement step S102, the corresponding implementation process can refer to Figure 6 , Figure 6 It is a schematic diagram of an implementation flow of a command processing method provided in an embodiment of the present invention.

[0126] like Figure 6 As shown, a loose order control register is added on one side of the controller 1, and the loose order control register is used to provide a loose order value for each operation of each data processing command that interacts with the memory.

[0127] Figure 6 The controller shown in the figure may be an NVME controller, and its implementation process includes the following steps:

[0128] 1. Host 2 writes the data processing command to the next free slot in the command queue (submission queue) in memory 3.

[0129] 2. Host 2 updates the Submission Queue Tail Doorbell register in controller 1.

[0130] 3. Controller 1 reads the data processing command from the command queue of memory 3.

[0131] 4. Controller 1 parses the command, executes the command, and initiates the execution operation to read and write the memory.

[0132] Among them, in the process of processing the execution operation to form a packet, the MWR RO field of the index loose sort control register is indexed, and the TLP ATTRIBUTE value in the transaction layer data packet is determined according to its value. The TLP ATTRIBUTE value is related to the specific transmission protocol. Taking the PCIE protocol as an example here, it is a value in PCIE, which is used to identify the specific attribute of the transaction layer data packet: execution order.

[0133] 5. Controller 1 performs the update operation and submits the completion to the Completion Queue in memory. Each Completion Queue entry contains: the latest entry in the command queue and the phase tag invert.

[0134] In the process of packing the update operation, the CQUP RO entry of the loose ordering control register is indexed, and the TLP RO ATTRIBUTE value is determined according to its value.

[0135] When the controller sends a CQ update to the memory, the host detects the TLP ROATTRIBUTE value carried in the transaction layer data packet to determine whether to disrupt the execution order of the update operation in the data processing command.

[0136] 6. Controller 1 sends an interrupt to the CPU to notify the completion queue to update.

[0137] 7. The CPU checks the phase tag toggle and finds all updated complete.

[0138] 8. Host 2 writes the Completion Queue Head Doorbell register to notify controller 1 that the completion queue is released.

[0139] An embodiment of the present invention provides a controller for implementing the command processing method provided by the above embodiment.

[0140] Please refer to Figure 7 , Figure 7 It is a schematic diagram of the structure of a controller provided by an embodiment of the present invention.

[0141] like Figure 7 As shown, the controller 1 may include:

[0142] A parsing result acquisition module 10, used to acquire the parsing result of the data processing command, wherein the parsing result includes various operations for completing the data processing command and interacting with the memory;

[0143] A loose ordering value setting module 11 is used to determine the operation type of each operation, and set a loose ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, so as to realize out-of-order execution of each operation interacting with the memory between different data processing commands according to the loose ordering value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether the operation allows out-of-order execution according to the conditions for the correct execution of the data processing command;

[0144] The packet assembly module 12 is used to perform packet assembly processing on each operation of setting the loose sort value to obtain a data packet corresponding to the data processing command.

[0145] The controller provided by the embodiment of the present invention can be applied to all transmissions based on the PCIE protocol.

[0146] Optionally, the operations interacting with the memory include: an execution operation of executing data transmission, an update operation of updating a completion queue of the memory;

[0147] The loose order value setting module 11 is used to determine the operation type of each operation, and set a loose order value for each operation based on the out-of-order execution definition corresponding to each operation type, including:

[0148] Determining that the operation type of the execution operation is a first type, and setting a loose sort value for the execution operation according to an out-of-order execution definition corresponding to the first type;

[0149] It is determined that the operation type of the update operation is the second type, and according to the out-of-order execution definition corresponding to the second type, a loose sort value is set for the update operation.

[0150] Optionally, the out-of-order execution definition is based on a transmission protocol definition for processing the data processing command, the transmission protocol being a condition for the correct execution of the data processing command;

[0151] The loose order value setting module 11 is used to determine that the operation type of the execution operation is the first type, and set a loose order value for the execution operation according to the out-of-order execution definition corresponding to the first type, including:

[0152] According to the out-of-order execution definition corresponding to the first type, a relaxed ordering value of a first value is set for the execution operation to indicate that out-of-order execution is allowed when processing the data processing command using the transport protocol;

[0153] The loose sort value setting module 11 is used to determine that the operation type of the update operation is the second type, and set a loose sort value for the update operation according to the out-of-order execution definition corresponding to the second type, including:

[0154] Determine whether out-of-order execution is allowed for update operations in a data transfer protocol that defines out-of-order execution;

[0155] If yes, setting a loose sort value of the first value for the update operation corresponding to the second type;

[0156] If not, a loose ordering value of a second value is set for the update operation corresponding to the second type to indicate that out-of-order execution is not allowed when processing the data processing command using the transport protocol.

[0157] Optionally, the loose order value setting module 11 is a software program; the loose order value setting module 11 is used to determine the operation type of each operation, and set a loose order value for each operation based on the out-of-order execution definition corresponding to each operation type, including:

[0158] Execute the software program to determine the operation type of each operation in the analysis result, and set a loose order value for the operation corresponding to each operation type based on the out-of-order execution definition corresponding to the determined operation type

[0159] Optionally, the loose ordering value setting module 11 is a loose ordering control register; the loose ordering value setting module 11 is used to set a loose ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, including:

[0160] The relaxed ordering control register is indexed, and based on the relaxed ordering values ​​of the out-of-order execution definition records corresponding to the respective operation types, the relaxed ordering values ​​set for the operations corresponding to the respective operation types are determined.

[0161] Optionally, the loose ordering control register is provided with an execution table entry and a completion queue update table entry; the loose ordering value setting module 11 is used to index the loose ordering value of the out-of-order execution definition record corresponding to each operation type in the loose ordering control register, and determine the loose ordering value set for the operation corresponding to each operation type, including:

[0162] When determining that the operation is an execution operation, indexing the loose ordering control register, based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, determines a loose ordering value set for the execution operation;

[0163] When the operation is determined to be an update operation, the loose ordering control register is indexed, and based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, a loose ordering value set for the update operation is determined.

[0164] Alternatively, if Figure 7 As shown, the controller 1 also includes:

[0165] The command reading and parsing module 13 is used to read the data processing command and parse the data processing command to obtain the parsing result of the data processing command;

[0166] The data packet transmission module 14 is used to transmit the data packet corresponding to the data processing command.

[0167] It can be seen that the technical solution provided by the embodiment of the present invention analyzes and processes the parsing results of the data processing command, so as to define out-of-order execution corresponding to different operation types and determine whether the operation can be executed out of order; because it is usually necessary to parse the data processing command to obtain the parsing result when processing the data processing command, the parsing result may include various operations involved in executing the data processing command, and the operation of interacting with the memory is the main execution content of the data processing command. Different data processing commands contain different operations of interacting with the memory, and the transmission address and data block for transmitting the data block to the memory are different, and the corresponding memory address corresponding to the completion queue of updating the memory is also different. Therefore, between different data processing commands, the various operations of interacting with the memory are independent of each other. Each operation can be executed out of order based on the setting control of the loose sorting value, but when processing data processing commands, there is no mechanism for flexibly controlling the loose sorting value of each operation interacting with the memory in each data processing command; thus, when executing a large number of data processing commands, the parallelism of each operation interacting with the memory between different data processing commands is reduced, and the execution efficiency of the data processing commands is reduced; so that the execution efficiency of the data processing commands and the execution correctness of the data processing commands cannot be guaranteed at the same time. Based on this, in the technical solution provided by the embodiment of the present invention, based on the parsing result of the data processing command, the specific operation type corresponding to each operation interacting with the memory is first determined, and then based on the out-of-order execution definition corresponding to the operation type, the loose sorting value is set for each operation interacting with the memory in each data processing command. Since each operation of the memory interaction is allowed to be executed out of order to ensure the correct execution of the data processing command, it is indicated by the out-of-order execution definition corresponding to each operation type, so that the execution order of each operation can meet the conditions for the correct execution of the data processing command by setting the loose sorting value according to the out-of-order execution definition. Therefore, in the technical solution provided by the embodiment of the present invention, the execution efficiency of the data processing commands can be improved while ensuring the correctness of the execution of the data processing commands.

[0168] The embodiment of the present invention provides a computer system, please refer to Figure 8 , Figure 8 It is a structural diagram of a computer system provided by an embodiment of the present invention.

[0169] like Figure 8 Said computer system may include the controller 1 as described in any one of the aforementioned embodiments.

[0170] It can be seen that the technical solution provided by the embodiment of the present invention can analyze and process the parsing results of the data processing commands because a loose sorting setting module is provided in the controller 1, so as to determine whether the operations can be executed out of order according to the out-of-order execution definitions corresponding to different operation types; because it is usually necessary to parse the data processing commands to obtain parsing results when processing data processing commands, the parsing results may include various operations involved in executing the data processing commands, and the operations interacting with the memory are the main execution contents of the data processing commands. Different data processing commands contain different operations of interacting with the memory, and the transmission address and data block for transmitting the data block to the memory are different, and the corresponding memory address corresponding to the completion queue of updating the memory is also different. Therefore, between different data processing commands, the various operations interacting with the memory are independent of each other. Each operation can be executed out of order based on the setting control of the loose sorting value, but when processing data processing commands, there is no mechanism for flexibly controlling the loose sorting value of each operation interacting with the memory in each data processing command; thus, when executing a large number of data processing commands, the parallelism of each operation interacting with the memory between different data processing commands is reduced, and the execution efficiency of the data processing commands is reduced; so that the execution efficiency of the data processing commands and the execution correctness of the data processing commands cannot be guaranteed at the same time. Based on this, in the technical solution provided by the embodiment of the present invention, based on the parsing result of the data processing command, the specific operation type corresponding to each operation interacting with the memory is first determined, and then based on the out-of-order execution definition corresponding to the operation type, the loose sorting value is set for each operation interacting with the memory in each data processing command. Since each operation of the memory interaction is allowed to be executed out of order to ensure the correct execution of the data processing command, it is indicated by the out-of-order execution definition corresponding to each operation type, so that the execution order of each operation can meet the conditions for the correct execution of the data processing command by setting the loose sorting value according to the out-of-order execution definition. Therefore, in the technical solution provided by the embodiment of the present invention, the execution efficiency of the data processing commands can be improved while ensuring the correctness of the execution of the data processing commands.

[0171] The computer system provided in the embodiment of the present invention may be a NUMA system or a CHIPLET system. NUMA (Non-Uniform Memory Access) is a design and organization method of a computer architecture. It is mainly used in a multi-processor system, allowing each processor or processor group to have its own local memory and access the memory of other nodes through system interconnection.

[0172] CHIPLET is not a protocol, but an integrated circuit (IC) design and manufacturing method. CHIPLET architecture, also known as modular chip design, involves breaking down a large monolithic chip into multiple smaller, function-specific modules, which are called "CHIPLETS". Each CHIPLET can be designed to perform a specific task or a set of tasks and can be manufactured independently and then integrated together through advanced packaging technologies such as 3D stacking, high-density interconnects, etc.

[0173] In computer systems with different architectures, using the controller 1 (NVME controller) provided by an embodiment of the present invention, when executing data processing commands inside the controller 1, a loose sorting value can be set for each operation of each data processing command interacting with the memory in a targeted manner, so that all NVME transmission data that complies with the PCIE protocol is correct, ensuring the stability (robustness) of the execution of data processing commands in computer systems with different architectures, so as to ensure the correctness of the execution of data processing commands while improving the execution efficiency of data processing commands.

[0174] Please continue to refer to Figure 8 , the computer system further comprises:

[0175] The host 2 is used to update the controller 1 so that the controller 1 reads and executes data processing commands;

[0176] The memory 3 is used to store the data processing commands written by the host 2 into the command queue, and to update the completion queue based on the interruption issued by the controller 1, wherein the interruption indicates that the execution of the data processing command is completed.

[0177] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0178] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A command processing method, characterized in that: include: Obtaining a parsing result of the data processing command, wherein the parsing result includes various operations for interacting with the memory to complete the data processing command; Determine the operation type of each operation, and set a loose ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, so as to implement out-of-order execution of each operation interacting with the memory between different data processing commands according to the loose ordering value set by the out-of-order execution definition; The out-of-order execution definition is used to indicate whether the operation is allowed to be executed out of order according to the conditions for correct execution of the data processing command; The operations for setting the loose sorting value are grouped and processed to obtain a data packet corresponding to the data processing command.

2. The command processing method according to claim 1, characterized in that: The various operations interacting with the memory include: an execution operation for executing data transmission, an update operation for updating a completion queue of the memory; The determining of the operation type of each operation and setting a loose sort value for each operation based on the out-of-order execution definition corresponding to each operation type include: Determining that the operation type of the execution operation is a first type, and setting a loose sort value for the execution operation according to an out-of-order execution definition corresponding to the first type; It is determined that the operation type of the update operation is the second type, and according to the out-of-order execution definition corresponding to the second type, a loose sort value is set for the update operation.

3. The command processing method according to claim 2, characterized in that: The out-of-order execution definition is based on a transmission protocol definition for processing the data processing command, and the transmission protocol is a condition for correctly executing the data processing command; Determining that the operation type of the execution operation is a first type, and setting a loose sort value for the execution operation according to an out-of-order execution definition corresponding to the first type, includes: According to the out-of-order execution definition corresponding to the first type, a relaxed ordering value of a first value is set for the execution operation to indicate that out-of-order execution is allowed when processing the data processing command using the transport protocol; Determining that the operation type of the update operation is the second type, and setting a loose sort value for the update operation according to an out-of-order execution definition corresponding to the second type, includes: Determine whether out-of-order execution is allowed for update operations in a data transfer protocol that defines out-of-order execution; If yes, setting a loose sort value of the first value for the update operation corresponding to the second type; If not, a loose ordering value of a second value is set for the update operation corresponding to the second type to indicate that out-of-order execution is not allowed when processing the data processing command using the transport protocol.

4. The command processing method according to claim 2, characterized in that: The out-of-order execution definition is based on an architectural system definition for executing data processing instructions.

5. The command processing method according to any one of claims 1 to 4, characterized in that: The determining of the operation type of each operation and setting a loose sort value for each operation based on the out-of-order execution definition corresponding to each operation type include: The software program is executed to determine the operation type of each operation in the analysis result, and based on the out-of-order execution definition corresponding to the determined operation type, a loose ordering value is set for the operation corresponding to each operation type.

6. The command processing method according to any one of claims 1 to 4, characterized in that: The determining of the operation type of each operation and setting a loose sort value for each operation based on the out-of-order execution definition corresponding to each operation type include: In the index loose order control register, based on the loose order value of the out-of-order execution definition record corresponding to each operation type, determine the loose order value set for the operation corresponding to each operation type; The loose ordering control register is arranged in a controller that executes the data processing command.

7. The command processing method according to claim 6, characterized in that: The loose order control register is provided with an execution table entry and a completion queue update table entry; the loose order control register is provided with a loose order value set for an operation corresponding to each operation type based on the loose order value of the out-of-order execution definition record corresponding to each operation type, including: When determining that the operation is an execution operation, indexing the loose ordering control register, based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, determines a loose ordering value set for the execution operation; When it is determined that the operation is an update operation, the loose ordering control register is indexed, and based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, a loose ordering value set for the update operation is determined.

8. The command processing method according to any one of claims 1 to 4, characterized in that: Before the step of obtaining the parsing result of the data processing command, the method further includes: Reading a data processing command, and parsing the data processing command to obtain a parsing result of the data processing command; After the step of grouping the operations of setting the loose sorting value to obtain the data packet corresponding to the data processing command, the method further includes: Transmitting a data packet corresponding to the data processing command.

9. A controller, characterized in that: include: A parsing result acquisition module, used to acquire the parsing result of the data processing command, wherein the parsing result includes various operations for completing the data processing command and interacting with the memory; A loose ordering value setting module is used to determine the operation type of each operation, and set a loose ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, so as to realize out-of-order execution of each operation interacting with the memory between different data processing commands according to the loose ordering value set by the out-of-order execution definition; The out-of-order execution definition is used to indicate whether the operation is allowed to be executed out of order according to the conditions for correct execution of the data processing command; The packet assembly module is used to perform packet assembly processing on each operation of setting the loose sort value to obtain a data packet corresponding to the data processing command.

10. The controller according to claim 9, characterized in that The various operations interacting with the memory include: an execution operation for executing data transmission, an update operation for updating a completion queue of the memory; The loose order value setting module is used to determine the operation type of each operation, and set a loose order value for each operation based on the out-of-order execution definition corresponding to each operation type, including: Determining that the operation type of the execution operation is a first type, and setting a loose sort value for the execution operation according to an out-of-order execution definition corresponding to the first type; It is determined that the operation type of the update operation is the second type, and according to the out-of-order execution definition corresponding to the second type, a loose sort value is set for the update operation.

11. The controller according to claim 10, characterized in that The out-of-order execution definition is based on a transmission protocol definition for processing the data processing command, and the transmission protocol is a condition for correctly executing the data processing command; The loose order value setting module is used to determine that the operation type of the execution operation is the first type, and set a loose order value for the execution operation according to the out-of-order execution definition corresponding to the first type, including: According to the out-of-order execution definition corresponding to the first type, a relaxed ordering value of a first value is set for the execution operation to indicate that out-of-order execution is allowed when processing the data processing command using the transport protocol; The loose sort value setting module is used to determine that the operation type of the update operation is the second type, and set a loose sort value for the update operation according to the out-of-order execution definition corresponding to the second type, including: Determine whether out-of-order execution is allowed for update operations in a data transfer protocol that defines out-of-order execution; If yes, setting a loose sort value of the first value for the update operation corresponding to the second type; If not, a loose ordering value of a second value is set for the update operation corresponding to the second type to indicate that out-of-order execution is not allowed when processing the data processing command using the transport protocol.

12. The controller according to any one of claims 9 to 10, characterized in that: The loose order value setting module is a software program; the loose order value setting module is used to determine the operation type of each operation, and set a loose order value for each operation based on the out-of-order execution definition corresponding to each operation type, including: The software program is executed to determine the operation type of each operation in the analysis result, and based on the out-of-order execution definition corresponding to the determined operation type, a loose ordering value is set for the operation corresponding to each operation type.

13. The controller according to any one of claims 9 to 10, characterized in that: The loose ordering value setting module is a loose ordering control register; the loose ordering value setting module is used to set a loose ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, including: The relaxed ordering control register is indexed, and based on the relaxed ordering values ​​of the out-of-order execution definition records corresponding to the respective operation types, the relaxed ordering values ​​set for the operations corresponding to the respective operation types are determined.

14. The controller according to claim 13, characterized in that The loose ordering control register is provided with an execution table entry and a completion queue update table entry; the loose ordering value setting module is used to index the loose ordering value of the out-of-order execution definition record corresponding to each operation type in the loose ordering control register, and determine the loose ordering value set for the operation corresponding to each operation type, including: When determining that the operation is an execution operation, indexing the loose ordering control register, based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, determines a loose ordering value set for the execution operation; When it is determined that the operation is an update operation, the loose ordering control register is indexed, and based on the loose ordering value of the out-of-order execution definition record corresponding to the first type, a loose ordering value set for the update operation is determined.

15. The controller according to any one of claims 9 to 10, characterized in that: Also includes: A command reading and parsing module is used to read a data processing command and parse the data processing command to obtain a parsing result of the data processing command; The data packet transmission module is used to transmit the data packet corresponding to the data processing command.

16. A computer system, characterized in that: include: A controller as claimed in any one of claims 9 to 15.

17. The computer system of claim 16, wherein: Also includes: A host, used to update the controller so that the controller reads and executes data processing commands; The memory is used to store the data processing commands written by the host into the command queue, and to update the completion queue based on the interruption issued by the controller, wherein the interruption indicates that the data processing command is executed.

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