Command processing method, controller and computer system

Abstract

Embodiments of the present application provide a command processing method, a controller and a computer system, wherein the method comprises: obtaining an analysis result of a data processing command, the analysis result comprising each operation for completing the data processing command and interacting with a memory; determining an operation type of each operation, setting a loose ordering value for each operation based on a corresponding out-of-order execution definition of the operation type, and implementing out-of-order execution of each operation interacting with the memory among different data processing commands according to the loose ordering value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether an operation is allowed to execute out of order according to a condition for correct execution of a data processing command; and each operation with the set loose ordering value is packaged to obtain a data packet corresponding to the data processing command. The technical solution provided by the embodiments of the present application can guarantee the correctness of data processing command execution while improving the execution efficiency of the data processing command.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer, in particular to a command processing method, a controller and a computer system. BACKGROUND

[0002] With the increasing demand for computing power and storage of chips, the amount of data that processors need to process also increases synchronously. Correspondingly, the amount of data for data transfer also increases. In the process of data transfer, multiple data processing commands are usually sent at a time to transfer the data required for each calculation in different addresses. The data transmission process performed by the data processing command needs to support the corresponding transmission protocol, so as to ensure that the data processing command is correctly executed.

[0003] However, the correctness of the execution of the data processing command and the efficiency of the execution of the data processing command cannot be well balanced. Therefore, how to provide a technical solution to ensure the correctness of the execution of the data processing command while improving the execution efficiency of the data processing command has become a technical problem that needs to be solved by the technical personnel in the field. SUMMARY

[0004] Therefore, embodiments of the present application provide a command processing method, a controller and a computer system to ensure the correctness of the execution of the data processing command while improving the execution efficiency of the data processing command.

[0005] To achieve the above object, embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, embodiments of the present application provide a command processing method, comprising:

[0007] obtaining an analysis result of a data processing command, wherein the analysis result includes each operation for completing the data processing command and interacting with a memory;

[0008] determining the operation type of each operation, setting a loose ordering value for each operation based on the out-of-order execution definition corresponding to each operation type, and implementing the out-of-order execution of each operation interacting with the memory between different data processing commands according to the loose ordering value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether the operation is allowed to execute out of order according to the condition for correct execution of the data processing command;

[0009] packaging each operation with the set loose ordering value to obtain a data packet corresponding to the data processing command.

[0010] In a second aspect, embodiments of the present application provide a controller, comprising:

[0011] The parsing result obtaining module is configured to obtain a parsing result of the data processing command, wherein the parsing result comprises various operations for completing the data processing command and interacting with the memory;

[0012] The loose ordering value setting module is configured to determine operation types of the various operations, set loose ordering values for the various operations based on out-of-order execution definitions corresponding to the operation types, and implement out-of-order execution of the various operations for interacting with the memory between different data processing commands according to the loose ordering values set by the out-of-order execution definitions; the out-of-order execution definitions are used to indicate whether the operations are allowed to execute out of order according to conditions for correct execution of the data processing command;

[0013] The packet assembling module is configured to assemble the various operations with the set loose ordering values to obtain a data packet corresponding to the data processing command.

[0014] In a third aspect, an embodiment of the present application provides a computer system, comprising the controller according to the second aspect.

[0015] The command processing method provided by the embodiment of the present application comprises the following steps: obtaining a parsing result of a data processing command, wherein the parsing result comprises various operations for completing the data processing command and interacting with the memory; determining operation types of the various operations, setting loose ordering values for the various operations based on out-of-order execution definitions corresponding to the operation types, and implementing out-of-order execution of the various operations for interacting with the memory between different data processing commands according to the loose ordering values set by the out-of-order execution definitions; the out-of-order execution definitions are used to indicate whether the operations are allowed to execute out of order according to conditions for correct execution of the data processing command; and assembling the various operations with the set loose ordering values to obtain a data packet corresponding to the data processing command.

[0016] It can be seen that the technical scheme provided by the embodiment of the present application analyzes and processes the analysis result of the data processing command, so as to determine whether the operation can be executed out of order according to the out-of-order execution definition corresponding to different operation types. Since the data processing command usually needs to be parsed to obtain the analysis result when the data processing command is processed, the analysis result can include each operation involved in executing the data processing command, and the operation interacting with the memory is the main execution content of the data processing command. Different data processing commands have different transmission addresses and data blocks in the operation of transmitting the data block to the memory in each operation interacting with the memory, and the corresponding memory address of the completion queue of the memory is also different. Therefore, each operation interacting with the memory is independent of each other between different data processing commands. Each operation can be executed out of order based on the setting control of the relaxed ordering value, but there is no mechanism for flexibly controlling the relaxed ordering value of each operation interacting with the memory in each data processing command when the data processing command is processed. Therefore, when a large number of data processing commands are executed, the parallelism of each operation interacting with the memory between different data processing commands is reduced, the execution efficiency of the data processing command is reduced, and the execution efficiency and the execution correctness of the data processing command cannot be guaranteed at the same time. Based on this, in the technical scheme provided by the embodiment of the present application, the specific operation type corresponding to each operation interacting with the memory is first determined based on the analysis result of the data processing command, and then the relaxed ordering value of each operation interacting with the memory in each data processing command is set according to the out-of-order execution definition corresponding to the operation type. Since whether each operation interacting with the memory is allowed to be executed out of order to ensure the correct execution of the data processing command is indicated by the out-of-order execution definition corresponding to each operation type, the execution order of each operation can meet the condition of the correct execution of the data processing command according to the targeted relaxed ordering value setting according to the out-of-order execution definition. Therefore, the technical scheme provided by the embodiment of the present application can guarantee the correct execution of the data processing command while improving the execution efficiency of the data processing command. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed in the following embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0018] Figure 1 is a flowchart of the command processing method provided by the embodiment of the present application;

[0019] Figure 2is a controller working process schematic diagram provided by an embodiment of the present application;

[0020] Figure 3 is a data processing command execution sequence schematic diagram when the relaxed ordering value is not enabled, provided by an embodiment of the present application;

[0021] Figure 4 is a data processing command execution sequence schematic diagram when the relaxed ordering value is enabled, provided by an embodiment of the present application;

[0022] Figure 5 is a data processing command execution sequence schematic diagram in the technical solution provided by an embodiment of the present application;

[0023] Figure 6 is an implementation flow schematic diagram of the command processing method provided by an embodiment of the present application;

[0024] Figure 7 is a structure schematic diagram of the controller provided by an embodiment of the present application;

[0025] Figure 8 is a structure schematic diagram of the computer system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work, fall within the protection scope of the present application.

[0027] With the continuous development of computer technology, the design of the processor is becoming more and more complex, and the bandwidth delay requirement of the computer system for disk access is becoming higher and higher. For example, the solid state disk (SSD, Solid State Drive) is becoming the development trend of the future disk because of its fast access speed, low power consumption and light weight. Among them, the solid state disk using NVME protocol (Non-Volatile Memory Express protocol: a protocol designed for non-volatile memory) and PCIE (Peripheral Component Interconnect Express: Peripheral Component Interconnect Express bus) interface gradually becomes the main disk selection of high performance scene because of its multi-thread transmission and high link bandwidth.

[0028] The controller of the solid state disk transmits and processes the data processing commands according to the transmission protocol of the transmission interface when executing the data processing commands. For example, the controller of the solid state disk using the NVME protocol and the PCIE interface needs to comply with the execution sequence defined in the PCIE protocol when processing and transmitting the data processing commands.

[0029] When executing the data processing commands, the controller usually parses the data processing commands, splits them into multiple data blocks, and then packs each data block to form a transaction layer packet (TLP). Therefore, when the transmission interface processes the data processing commands, it transmits and processes the transaction layer packets after the packing. The transmission sequence of the transaction layer packets needs to comply with the sequence defined in the protocol of the transmission interface.

[0030] Taking the PCIE protocol as an example, the transaction layer packets are transmitted according to the transaction order defined in the PCIE protocol when transmitting the transaction layer packets.

[0031] The transaction order of the PCIE protocol stipulates that:

[0032] Among the operations interacting with the memory in a data processing command: the update operation of updating the completion queue of the memory cannot surpass the operation of transmitting the data block to the memory;

[0033] Between the operation interacting with the memory and the operation not interacting with the memory: the sending interrupt operation of sending an interrupt to the processor cannot surpass the operation interacting with the memory.

[0034] That is, the PCIE protocol stipulates that the transaction layer packets of each operation after packing need to be executed in sequence, but the data processing commands read and executed by the NVME can be processed in parallel, that is, there is no dependency relationship between the data streams (each operation interacting with the memory) of the data processing commands.

[0035] In the above solid state disk structure, the protocol used by the controller when reading and executing the data processing commands is called an upper protocol, and the transmission protocol of the transmission interface used when transmitting the transaction layer packets is called a lower protocol. Due to the use rules of the upper protocol and the lower protocol, when the controller transmits and processes the data processing commands, it cannot guarantee the parallelism of the data processing commands while ensuring the execution correctness of the data processing commands.

[0036] Based on this, the embodiment of the present application provides a command processing method for improving the transmission efficiency of the data processing commands while ensuring the execution correctness of the data processing commands.

[0037] Please refer toFigure 1 , Figure 1 is a flowchart of a command processing method provided by an embodiment of the application.

[0038] As shown in Figure 1 , the method comprises the following steps:

[0039] Step S101, obtaining a parsing result of a data processing command, the parsing result comprising various operations for completing the data processing command and interacting with a memory.

[0040] The data processing command can be read and executed by a controller from a command queue of the memory, so as to avoid using the resources of the processor to execute the data transmission, ensure that the processor has enough resources to process other tasks, and improve the performance of the computer system.

[0041] Meanwhile, the purpose of the controller reading and executing the data processing command is to replace the processor to execute the task of data transmission. Therefore, the process of the controller executing the data processing command also comprises a non-memory interaction operation of sending an interrupt to the processor to inform the processor that the execution of the data processing command is completed.

[0042] Therefore, in the embodiments provided by the application, the operation related to the memory is referred to as the memory interaction operation, and the operation related to the processor is referred to as the non-memory interaction operation.

[0043] In order to facilitate the understanding of the implementation process of the controller reading and executing the data processing command, please refer to Figure 2 , Figure 2 is a schematic diagram of the working process of the controller provided by an embodiment of the application.

[0044] Figure 2 The controller in the figure can be an NVME controller.

[0045] As shown in Figure 2 , the steps of the controller executing the data processing command comprise:

[0046] 1. The host 2 writes the data processing command into the next free slot in the command queue (submission queue) in the memory 3.

[0047] 2. The host 2 updates the submission queue tail doorbell register in the controller 01. The submission queue tail doorbell register is usually used to describe a hardware or software mechanism in an input / output (I / O) operation.

[0048] 3. The controller 01 reads the data processing command from the command queue of the memory 3.

[0049] 4. The controller 01 executes the data processing command, and completes the read / write access to the memory 3 (data buffer).

[0050] 5. The controller 01 submits a completion signal to a completion queue in the memory 3, wherein the completion queue contains a plurality of completion queue entries; each completion queue entry contains a consumed entry of the command queue and a phase tag invert. In the PCIE architecture, the phase tag invert is used to ensure the correct ordering of data packets in the PCIE transaction and the integrity of the transaction.

[0051] 6. The controller 01 sends an interrupt to the CPU to notify the completion queue update.

[0052] 7. The CPU checks the phase tag toggle to find all updated consumed data processing commands. In the PCIE architecture, the phase tag toggle generally refers to the phase or phase of the tag in the tag field of the transaction layer packet (TLP) to ensure the correct ordering of data packets and the integrity of the transaction.

[0053] 8. The host 2 writes the completion queue head doorbell register in the controller 01 to notify the controller 01 that the completion queue is released.

[0054] The communication network is used to realize the interaction between the controller 01, the host 2 and the memory 3. The communication network can be, for example, a Network-on-Chip (NoC).

[0055] The NoC is a communication architecture for a system-on-chip (SoC), which solves the communication problem caused by large-scale integration by implementing a network-like structure inside the chip.

[0056] In step S102, the operation type of each operation is determined, and a relaxed ordering value is set for each operation based on the out-of-order execution definition corresponding to each operation type.

[0057] The relaxed ordering value set according to the out-of-order execution definition is used to realize the out-of-order execution of each operation interacting with the memory between different data processing commands; the out-of-order execution definition is used to indicate whether the operation is allowed to execute out of order according to the condition of correct execution of the data processing command.

[0058] Relax order (RO) is used to describe the relaxation of the order of operations in concurrent programming and multi-threaded environments. "relax" means that the execution order of certain operations does not have to strictly follow their appearance order in the program, so as to possibly improve the parallelism and performance of the program.

[0059] In the controller of a solid state disk using a PCIE interface and an NVME protocol, the relax order is used to specify the attributes of the transaction layer data packet after the PCIE packet is packaged, to indicate that the receiving end can adopt a relaxed order when processing the transaction layer data packet.

[0060] The out-of-order execution definition can be defined according to the execution scenario of the data processing command, for example, it can be defined based on the transmission protocol used when the data processing command is executed, which can ensure that the data processing command can be executed correctly.

[0061] Taking the processing and transmission of the data processing command as an example, the PCIE transmission protocol using the PCIE interface is continued.

[0062] When using the PCIE transmission protocol, the out-of-order execution definition corresponding to the operation type of each operation can be defined according to the transaction layer data packet execution order provision in the PCIE transmission protocol. For example, Figure 2 The out-of-order execution definition corresponding to the operation type of the "4" operation indicates that the operation allows out-of-order execution, and the out-of-order execution definition corresponding to the operation type of the "5" operation indicates that the operation does not allow out-of-order execution, so as to avoid the case that the "5" operation is executed before the "4" operation when the "5" operation allows out-of-order execution, causing the data processing command to be executed incorrectly.

[0063] Based on the foregoing, it can be known that different data processing commands in NVME can be processed in parallel, but the transaction layer data packet needs to be executed in order in PCIE, so the parallelism of the operation interacting with the memory in the data processing command is reduced, and the execution efficiency of the data processing command is reduced.

[0064] For example, taking Figure 2 the controller workflow diagram as an example, in the process of executing a data processing command, the operations included are:

[0065] The step of the controller executing data transmission (i.e., the "4" operation shown in the figure) is used to write data blocks to the memory or read them out from the memory. Figure 2

[0066] The controller submits the completion to the completion queue in the memory, that is, updates the supplement of the completion queue of the memory (i.e., the "5" operation shown in the figure). Figure 2

[0067] ​​The step of sending an interrupt by the controller to the processor (i.e. Figure 3 The "6" operation shown) is used to inform the processor that the controller has completed the execution of the data processing command.

[0068] In the above operation, the "4", "5" and "6" operations of different data processing commands can be processed in parallel. Therefore, under the provisions of the PCIE protocol, if the RO value of each operation is not enabled in the process of forming a transaction layer data packet by packet, for example, the RO value is "0", then the "4", "5" and "6" operations of each data processing command need to be executed sequentially when the controller executes multiple data processing commands. Please refer to Figure 3 , Figure 3 The execution sequence of the data processing command when the relaxed ordering value is not enabled is shown in FIG. 1.

[0069] As shown in FIG. 1, the controller processes each data processing command: CMD1, CMD2, and CMD3, and the execution sequence is executed in the order of reading and executing the data processing command (for example, the order from right to left in FIG. 1 is gradually increasing in time). Figure 3 Figure 4 As can be seen, the "5" operation of the command (for example, CMD1) with a reading and execution sequence after (for example, CMD1) and the interrupt request CMD0.6 of the command (for example, CMD0) with a reading and execution sequence before have no sequential execution relationship in nature, but must be completed sequentially due to the provisions of the PCIE transaction layer data packet execution sequence, which reduces the parallelism of the "5" operation of the operation interacting with the memory in different data processing commands, and reduces the bandwidth.

[0070] If the relaxed ordering value of the operation is enabled, for example, the RO is "1", the RO value of each operation in the data processing command is usually set uniformly by using the PCIE device control register (PCI Express Device Control Register) defined in the NVME controller.

[0071] Since the PCIE device control register does not distinguish the operation types of different operations in each data processing command, it will set the RO of all operations to "1". Please refer to ,

[0072] The execution sequence of the data processing command when the relaxed ordering value is enabled is shown in FIG. 2. Figure 4 Figure 4 As shown in FIG. 2, the controller processes each data processing command: CMD1, CMD2, and CMD3, and the execution sequence is executed in the order of reading and executing the data processing command (for example, the order from right to left in FIG. 2 is gradually increasing in time).

[0073] As can be seen, the "5" operation of the command (for example, CMD1) with a reading and execution sequence after (for example, CMD1) and the interrupt request CMD0.6 of the command (for example, CMD0) with a reading and execution sequence before have no sequential execution relationship in nature, but must be completed sequentially due to the provisions of the PCIE transaction layer data packet execution sequence, which reduces the parallelism of the "5" operation of the operation interacting with the memory in different data processing commands, and reduces the bandwidth. Figure 3 ​If all ROs of all operations are set to "1", a second read and execute data processing command, "4" operation of CMD1, CMD1.4, can be executed out of order and override a first read and execute data processing command, "6" operation of CMD0, CMD0.6, to improve parallelism. However, a third read and execute data processing command, "5" operation of CMD2, CMD2.5, can override its own "4" operation, CMD2.4, to cause an operation of updating a completion queue of a memory to be completed before an operation of performing data transmission, resulting in data transmission error and data processing command execution error.

[0074] In Figure 4 and Figure 4 the execution sequence diagram shown, it can be seen that whether the relaxed ordering value is enabled or not, the sequence of the "6" operation of each data processing command corresponds to the read and execute sequence of each data processing command, and is later than the execution time of the operation ("4" and "5" operations) of each data processing command interacting with the memory, thereby ensuring the correctness of the execution sequence of each data processing command.

[0075] Therefore, in the embodiment of the present application, for each operation of each data processing command interacting with the memory, a corresponding relaxed ordering value setting is performed based on the out-of-order execution definition corresponding to the operation type, so that accurate relaxed ordering value setting can be performed for each operation. When the manner of uniformly setting the relaxed ordering value of all operations as shown in Figure 5 is used, although the parallelism of the data processing command can be improved, the data processing command execution error can occur.

[0076] In step S103, each operation with the set relaxed ordering value is packetized to obtain a data packet corresponding to the data processing command.

[0077] The data packet corresponding to the data processing command is, for example, the transaction layer data packet described above.

[0078] After the technical solution provided by the embodiment of the present application is used to process the data processing command, the execution of each data processing command can refer to Figure 5 , Figure 5 which is an execution sequence diagram of the data processing command in the technical solution provided by the embodiment of the present application.

[0079] Figure 5 The transmission protocol is taken as the PCIE protocol for example and is continuously displayed in

[0080] As shown in Figure 1As shown, the operations of interacting with the memory: the "4" operation and the "5" operation between different data processing commands can not be executed according to the reading and execution time sequence of the data processing commands; in each data processing command, the execution sequence of the "4" operation is ensured to be earlier than the execution sequence of the "5" operation, so as to meet the regulation of the PCIE transmission protocol and ensure the correct execution of each data processing command.

[0081] And the execution sequence of the "6" operation between different data processing commands corresponds to the reading and execution time of each data processing command, so that the order preservation between data processing commands can be realized. For example, in the same data processing command, the order preservation between the operation of executing data transmission and the operation of sending an interrupt, the order preservation between the operation of executing data transmission and the operation of updating the completion queue of the memory, and the order preservation between the operation of updating the completion queue of the memory and the operation of sending an interrupt.

[0082] It can be seen that the technical scheme provided by the embodiment of the application analyzes and processes the analysis result of the data processing command, so as to determine whether the operation can be executed out of order according to the out-of-order execution definition corresponding to different operation types; since the data processing command usually needs to be analyzed to obtain an analysis result when the data processing command is processed, the analysis result can include each operation involved in executing the data processing command, and the operation interacting with the memory is the main execution content of the data processing command. Different data processing commands have different transmission addresses and data blocks for transmitting the data block to the memory in each operation interacting with the memory, and the corresponding memory address of the completion queue of the memory is also different. Therefore, each operation interacting with the memory is independent of each other between different data processing commands. Each operation can be executed out of order based on the setting control of the relaxed ordering value, but there is no mechanism for flexibly controlling the relaxed ordering value of each operation interacting with the memory in each data processing command when the data processing command is processed; thereby reducing the parallelism of each operation interacting with the memory between different data processing commands and the execution efficiency of the data processing command when a large number of data processing commands are executed; so that the execution efficiency of the data processing command and the execution correctness of the data processing command cannot be guaranteed at the same time. Based on this, in the technical scheme provided by the embodiment of the application, the specific operation type corresponding to each operation interacting with the memory is first determined based on the analysis result of the data processing command, and then the relaxed ordering value of each operation interacting with the memory in each data processing command is set according to the out-of-order execution definition corresponding to the operation type. Since whether each operation interacting with the memory is allowed to be executed out of order to ensure the correct execution of the data processing command is indicated by the out-of-order execution definition corresponding to each operation type, the execution order of each operation can meet the condition of the correct execution of the data processing command according to the targeted relaxed ordering value setting according to the out-of-order execution definition. Therefore, the technical scheme provided by the embodiment of the application can guarantee the correct execution of the data processing command while improving the execution efficiency of the data processing command.

[0083] Please continue to refer to Figure 1 The method can further include, as shown in the figure:

[0084] In step S100, the data processing command is read and analyzed to obtain an analysis result of the data processing command.

[0085] After reading the data processing command, the controller can analyze the data processing command to obtain an analysis result, so as to facilitate subsequent determination of the operation type of different operations based on the analysis result.

[0086] Please continue to refer to Figure 6 After step S103, it can further include:

[0087] Step S104, transmitting the data packet corresponding to the data processing command.

[0088] After setting the loose ordering value for each operation, the packet can be packaged and the data packet obtained after the packet is transmitted, so as to perform subsequent operations on the data packet. The data packet is a basic unit of the data processing command in the data transmission process, and carries all necessary information of the data processing command.

[0089] For example, the data packet (such as the transaction layer data packet described above) is transmitted to the data link layer for further processing. In the data link layer, the data packet is further encapsulated, and the data link layer adds a sequence number (Sequence ID) in front of the data packet and calculates a link layer cyclic redundancy check code (LCRC) to ensure the transmission integrity of the encapsulated link layer data packet in the link layer.

[0090] Based on the foregoing analysis, executing a data processing command includes: executing data transmission, transmitting data blocks to the memory, updating the completion queue of the memory, and sending an interrupt to the processor. Among them, the operations related to the memory are the operations interacting with the memory, and the operations interacting with the memory include: the execution operation of transmitting data, and the update operation of updating the completion queue of the memory.

[0091] Step S102 can include:

[0092] Determine that the operation type of the execution operation is a first type, and set a loose ordering value for the execution operation according to the out-of-order execution definition corresponding to the first type;

[0093] Determine that the operation type of the update operation is a second type, and set a loose ordering value for the update operation according to the out-of-order execution definition corresponding to the second type.

[0094] The execution operation corresponds to the process of "transmitting data blocks to the memory", and the update operation corresponds to the process of "updating the completion queue of the memory".

[0095] Because the conditions for correct execution of data processing commands are different in different execution scenarios of data processing commands, the out-of-order execution definitions allowing the execution operation and the update operation to execute out of order are also different; therefore, after determining the operation type of each operation, the loose ordering value can be set in combination with the out-of-order execution definition corresponding to the operation type; so as to ensure the correct execution of the data processing command, meet the out-of-order execution of each operation, and improve the execution efficiency of the data processing command.

[0096] In an embodiment, the out-of-order execution definition is based on a transmission protocol definition for processing the data processing commands, the transmission protocol defining conditions for correct execution of the data processing commands;

[0097] The operation type of the execution operation is determined to be a first type, and a relaxed ordering value is set for the execution operation according to the out-of-order execution definition corresponding to the first type, which can include:

[0098] The relaxed ordering value of the first value is set for the execution operation according to the out-of-order execution definition corresponding to the first type, to indicate that the out-of-order execution is allowed when the data processing commands are processed using the transmission protocol;

[0099] The operation type of the update operation is determined to be a second type, and a relaxed ordering value is set for the update operation according to the out-of-order execution definition corresponding to the second type, which can include:

[0100] It is determined whether the update operation is allowed to execute out-of-order in the data transmission protocol defining the out-of-order execution definition;

[0101] If yes, the relaxed ordering value of the first value is set for the update operation corresponding to the second type;

[0102] If no, the relaxed ordering value of the second value is set for the update operation corresponding to the second type, to indicate that the out-of-order execution is not allowed when the data processing commands are processed using the transmission protocol.

[0103] According to the provision of the data transmission order in the transmission protocol, the execution operation is an operation of writing data into memory or reading data out of memory, and thus the execution operations between the various data processing commands are independent of each other; therefore, the relaxed ordering value of the execution operation can be set to the first value, for example, "1", indicating that the execution operation (at the receiving end) is allowed to execute out-of-order.

[0104] The update operation is determined according to the specific data transmission protocol whether the relaxed ordering value can be set to the first value. For example, in the aforementioned embodiment, the transmission protocol is the PCIE transmission protocol, and the PCIE transmission protocol provides that the execution order of the execution operation is earlier than the execution order of the update operation. Therefore, when the PCIE transmission protocol is used, the relaxed ordering value of the update operation is set to the second value, and the out-of-order execution is not allowed.

[0105] In the PCIE architecture, some transmission protocols allow the operation of transmitting data (execution operation) to be executed later than the operation of updating the completion queue of the memory (update operation). This mechanism is commonly referred to as "Posted Writes" or "Write Posting".

[0106] Among them, the posted writes is a transmission mechanism in which a write transaction can be sent to the target device without waiting for the confirmation of the completion of the write operation. This means that data transmission can begin even if the completion queue in the memory has not been updated.

[0107] Write posting allows a device to receive a write request and queue it, then send a completion acknowledgement to the initiator immediately, while the actual write operation can be performed later.

[0108] Therefore, according to the specific circumstances of the data transmission protocol, a suitable out-of-order execution definition is defined to accurately and reliably set the relaxed ordering value of the update operation and the relaxed ordering value of the execution operation, ensuring that the execution of the data processing command will not be erroneous.

[0109] The out-of-order execution definition used in the foregoing embodiment is a way to flexibly set the relaxed ordering value based on the understanding of the system structure.

[0110] Of course, in other embodiments, the out-of-order execution definition can also be defined based on the architecture of the system that executes the data processing command. For example, in a multi-processor or distributed system, the setting of the relaxed ordering value can take into account the architectural characteristics of the system, such as cache coherence, memory access mode, etc. For example, according to the structure of the NoC system, whether it has a natural hardware ordering, the binding condition of NUMA (Non-Uniform Memory Access), the relaxed ordering value can be set. That is, the architecture system specifies the conditions for the correct execution of the data processing command.

[0111] To improve the flexibility and practicability of the implementation of the command processing method in the embodiment of the application, in an embodiment, the implementation of step S102 can include:

[0112] The software program determines the operation type of each operation in the parsing result, and sets the relaxed ordering value for the operation corresponding to each operation type based on the out-of-order execution definition corresponding to the determined operation type.

[0113] In the embodiment of the application, the software program can be used to set the relaxed ordering value. That is, the software program detects the parsing result of the data processing command, identifies operations of different operation types, and then sets each operation based on the out-of-order execution definition corresponding to each operation type, to meet the accurate setting of the relaxed ordering value of each operation.

[0114] In other embodiments, step S102 can include:

[0115] indexing the relaxed order control register, determining the relaxed order value set for each operation type corresponding operation based on the relaxed order value recorded in the out-of-order execution definition record corresponding to each operation type;

[0116] The relaxed order control register is arranged in a controller for executing the data processing command.

[0117] In the embodiment of the present application, the hardware structure (relaxed order control register) can also be used to set the relaxed order value of each operation, thereby enhancing the implementation flexibility of the technical solution provided by the embodiment of the present application.

[0118] In one embodiment, in order to use the hardware structure to implement the setting of the relaxed order value in the command processing method, the relaxed order control register is provided with an execution table item and a completion queue update table item; and the indexing the relaxed order control register, determining the relaxed order value set for each operation type corresponding operation based on the relaxed order value recorded in the out-of-order execution definition record corresponding to each operation type, comprises:

[0119] When the operation is determined to be an execution operation, the relaxed order value set for the execution operation is determined based on the relaxed order value recorded in the out-of-order execution definition record corresponding to the first type in the relaxed order control register;

[0120] When the operation is determined to be an update operation, the relaxed order value set for the update operation is determined based on the relaxed order value recorded in the out-of-order execution definition record corresponding to the first type in the relaxed order control register.

[0121] A relaxed order control register (RELAX ORDER CONTROL REGISTER) is added in the controller, and the relaxed order control register can contain two table items (fields): an execution table item (MWR RO) and a completion queue update table item (CQUP RO).

[0122] The MWR RO is used to control the setting of the TLP RO ATTRIBUTE bit of the transaction layer data packet formed in the packet forming process of the execution operation. Generally, the TLP RO ATTRIBUTE bit is set to RO=1, indicating that the execution operation can be executed out of order between different data processing commands, thereby increasing the parallelism of the data flow.

[0123] The CQUP RO is used to control the attribute of the transaction layer data packet formed in the group packet process of the update completion queue: TLP RO ATTRIBUTE bit. The TLP RO ATTRIBUTE bit is generally set to RO=0, which is used to maintain the order of the data block of the IOPS (Input / Output Operations per Second) operation and ensure that the data block in the data processing command has been completely written into the memory.

[0124] In the two table entries of the relaxed ordering control register, values that can meet the out-of-order execution definition of each operation are set, so as to provide appropriate relaxed ordering values for each operation in the data processing command analysis and packet forming process.

[0125] When the hardware structure (relaxed ordering control register) is used to implement step S102, the corresponding implementation process can refer to Figure 6 , Figure 6 which is an implementation flowchart of the command processing method provided by the embodiment of the application.

[0126] As shown in Figure 6 , the relaxed ordering control register is additionally arranged on the side of the controller 1, and the relaxed ordering control register is used to provide the relaxed ordering value for each operation of each data processing command interacting with the memory.

[0127] Figure 7 The controller in the figure can be an NVME controller, and the implementation process thereof includes the following steps:

[0128] 1. The host 2 writes the data processing command into the next free slot in the command queue (submission queue) in the memory 3.

[0129] 2. The host 2 updates the Submission Queue Tail Doorbell register in the controller 1.

[0130] 3. The controller 1 reads the data processing command from the command queue in the memory 3.

[0131] 4. The controller 1 analyzes the command, executes the command, initiates the execution operation, and performs the read / write access of the memory.

[0132] In the process of processing and performing the operation of packetizing, the MWR RO field of the index loose ordering control register determines the TLP ATTRIBUTE value in the transaction layer data packet according to the value, and the TLP ATTRIBUTE value is related to a specific transmission protocol, and here, the PCIE protocol is taken as an example, and the value in the PCIE is used to identify the specific attribute of the transaction layer data packet: execution order.

[0133] 5. The controller 1 performs an update operation and submits a completion to the completion queue in the memory, and each completion queue entry includes: the latest entry of the command queue and the phase tag toggle.

[0134] In the process of packetizing the update operation, the CQUP RO table entry of the index loose ordering control register determines the TLP RO ATTRIBUTE value according to the value.

[0135] In the process of sending the CQ update to the memory by the controller, the host detects the TLP RO ATTRIBUTE value carried in the transaction layer data packet to determine whether to disturb the execution order of the update operation in the data processing command.

[0136] 6. The controller 1 sends an interrupt to the CPU to notify the completion queue update.

[0137] 7. The CPU checks the phase tag toggle to find all updated completions.

[0138] 8. The host 2 writes the completion queue head doorbell register to notify the controller 1 to release the completion queue.

[0139] The embodiment of the application provides a controller for implementing the command processing method provided in the foregoing embodiment.

[0140] Please refer to Figure 7 , Figure 7 is a structural schematic diagram of the controller provided in the embodiment of the application.

[0141] As shown in Figure 7 , the controller 1 can include:

[0142] The analysis result acquisition module 10 is configured to acquire an analysis result of a data processing command, and the analysis result includes each operation of interacting with a memory for completing the data processing command.

[0143] The loose ordering value setting module 11 is configured to determine operation types of each operation, set loose ordering values for each operation based on out-of-order execution definitions corresponding to the operation types, and implement out-of-order execution of each operation interacting with the memory among different data processing commands according to the loose ordering values set according to the out-of-order execution definitions; the out-of-order execution definitions are used to indicate whether the operation is allowed to execute out of order according to conditions for correct execution of the data processing command;

[0144] The packet assembling module 12 is configured to perform packet assembling processing on each operation with the set loose ordering value, and obtain a data packet corresponding to the data processing command.

[0145] The controller provided by the embodiment of the application can be applied to all transmissions based on the PCIE protocol.

[0146] Optionally, the each operation interacting with the memory includes an execution operation of executing data transmission and an update operation of updating a completion queue of the memory.

[0147] The loose ordering value setting module 11 is configured to determine operation types of each operation, set loose ordering values for each operation based on out-of-order execution definitions corresponding to the operation types, and implement out-of-order execution of each operation interacting with the memory among different data processing commands according to the loose ordering values set according to the out-of-order execution definitions; the out-of-order execution definitions are used to indicate whether the operation is allowed to execute out of order according to conditions for correct execution of the data processing command.

[0148] The loose ordering value setting module 11 is configured to determine that the operation type of the execution operation is a first type, and set a loose ordering value for the execution operation according to an out-of-order execution definition corresponding to the first type.

[0149] The loose ordering value setting module 11 is configured to determine that the operation type of the update operation is a second type, and set a loose ordering value for the update operation according to an out-of-order execution definition corresponding to the second type.

[0150] Optionally, the out-of-order execution definition is defined based on a transmission protocol for processing the data processing command, and the transmission protocol is a condition for correct execution of the data processing command.

[0151] The loose ordering value setting module 11 is configured to determine that the operation type of the execution operation is a first type, and set a loose ordering value for the execution operation according to an out-of-order execution definition corresponding to the first type.

[0152] The loose ordering value setting module 11 is configured to determine that the operation type of the execution operation is a first type, and set a loose ordering value for the execution operation according to an out-of-order execution definition corresponding to the first type.

[0153] The loose ordering value setting module 11 is configured to determine that the operation type of the update operation is a second type, and set a loose ordering value for the update operation according to an out-of-order execution definition corresponding to the second type.

[0154] The loose ordering value setting module 11 is configured to determine that the operation type of the update operation is a second type, and set a loose ordering value for the update operation according to an out-of-order execution definition corresponding to the second type.

[0155] If yes, set a first value of a relaxed ordering value for the update operation corresponding to the second type;

[0156] If no, set a second value of a relaxed ordering value for the update operation corresponding to the second type, to indicate that out-of-order execution is not allowed when processing the data processing command using a transmission protocol.

[0157] Optionally, the relaxed ordering value setting module 11 is a software program; the relaxed ordering value setting module 11 is configured to determine operation types of each operation, and set a relaxed ordering value for each operation based on an out-of-order execution definition corresponding to each operation type, including:

[0158] The software program is configured to determine operation types of each operation in the parsing result, and set a relaxed ordering value for each operation corresponding to each operation type based on an out-of-order execution definition corresponding to each operation type.

[0159] Optionally, the relaxed ordering value setting module 11 is a relaxed ordering control register; the relaxed ordering value setting module 11 is configured to set a relaxed ordering value for each operation based on an out-of-order execution definition corresponding to each operation type, including:

[0160] The relaxed ordering control register is configured to record the relaxed ordering value for each operation type based on the out-of-order execution definition corresponding to each operation type, and the relaxed ordering value setting module 11 is configured to index the relaxed ordering value recorded in the relaxed ordering control register to determine the relaxed ordering value set for each operation corresponding to each operation type.

[0161] Optionally, the relaxed ordering control register is configured to record an execution table item and a completion queue update table item; the relaxed ordering value setting module 11 is configured to index the relaxed ordering value recorded in the relaxed ordering control register based on the out-of-order execution definition corresponding to each operation type to determine the relaxed ordering value set for each operation corresponding to each operation type.

[0162] When determining that the operation is an execution operation, the relaxed ordering control register is configured to record the relaxed ordering value based on the out-of-order execution definition corresponding to the first type, and the relaxed ordering value setting module 11 is configured to index the relaxed ordering value recorded in the relaxed ordering control register to determine the relaxed ordering value set for the execution operation.

[0163] When determining that the operation is an update operation, the relaxed ordering control register is configured to record the relaxed ordering value based on the out-of-order execution definition corresponding to the first type, and the relaxed ordering value setting module 11 is configured to index the relaxed ordering value recorded in the relaxed ordering control register to determine the relaxed ordering value set for the update operation.

[0164] Optionally, as shown in Figure 8 The controller 1 further includes:

[0165] A command reading and parsing module 13 is configured to read a data processing command, and parse the data processing command to obtain a parsing result of the data processing command.

[0166] The data packet transmission module 14 is configured to transmit a data packet corresponding to the data processing command.

[0167] As can be seen, the technical solution provided by the embodiment of the present application analyzes and processes the analysis result of the data processing command, so as to determine whether the operation can be executed out of order according to the out-of-order execution definition corresponding to different operation types; since the data processing command usually needs to be analyzed to obtain an analysis result when the data processing command is processed, the analysis result can include each operation involved in executing the data processing command, and the operation interacting with the memory is the main execution content of the data processing command. Different data processing commands have different transmission addresses and data blocks for transmitting the data block to the memory in each operation interacting with the memory, and the corresponding memory address of the completion queue of the memory is also different. Therefore, each operation interacting with the memory is independent of each other between different data processing commands. Each operation can be executed out of order based on the setting control of the relaxed ordering value, but there is no mechanism for flexibly controlling the relaxed ordering value of each operation interacting with the memory in each data processing command when the data processing command is processed; thereby reducing the parallelism of each operation interacting with the memory between different data processing commands and reducing the execution efficiency of the data processing command when a large number of data processing commands are executed; so that the execution efficiency of the data processing command and the execution correctness of the data processing command cannot be guaranteed at the same time. Based on this, in the technical solution provided by the embodiment of the present application, the specific operation type corresponding to each operation interacting with the memory is first determined based on the analysis result of the data processing command, and then the relaxed ordering value of each operation interacting with the memory in each data processing command is set according to the out-of-order execution definition corresponding to the operation type. Since whether each operation interacting with the memory is allowed to be executed out of order to ensure the correct execution of the data processing command is indicated by the out-of-order execution definition corresponding to each operation type, the execution order of each operation can meet the condition of the correct execution of the data processing command according to the targeted relaxed ordering value setting according to the out-of-order execution definition. Therefore, the technical solution provided by the embodiment of the present application can guarantee the correct execution of the data processing command while improving the execution efficiency of the data processing command.

[0168] The embodiment of the present application provides a computer system, please refer to Figure 8 , Figure 8 is a structural schematic diagram of the computer system provided by the embodiment of the present application.

[0169] As Figure 8 indicated, the computer system can include the controller 1 as described in any of the preceding embodiments.

[0170] It can be seen that the technical scheme provided by the embodiment of the application can analyze and process the analysis result of the data processing command, so as to determine whether the operation can be executed out of order according to the out-of-order execution definition corresponding to different operation types. When processing the data processing command, the data processing command usually needs to be analyzed to obtain an analysis result, and the analysis result can include each operation involved in executing the data processing command, and the operation interacting with the memory is the main execution content of the data processing command. Different data processing commands have different transmission addresses and data blocks for transmitting data blocks to the memory in each operation interacting with the memory, and the corresponding memory addresses of the completion queue of the memory are also different. Therefore, each operation interacting with the memory is independent of each other between different data processing commands. Each operation can be executed out of order based on the setting of the relaxed sorting value, but there is no mechanism for flexibly controlling the relaxed sorting value of each operation interacting with the memory in each data processing command when processing the data processing command. Therefore, when a large number of data processing commands are executed, the parallelism of each operation interacting with the memory between different data processing commands is reduced, the execution efficiency of the data processing command is reduced, and the execution efficiency and the execution correctness of the data processing command cannot be guaranteed at the same time. Based on this, in the technical scheme provided by the embodiment of the application, the specific operation type corresponding to each operation interacting with the memory is first determined based on the analysis result of the data processing command, and then the relaxed sorting value is set for each operation interacting with the memory in each data processing command according to the out-of-order execution definition corresponding to the operation type. Whether the operation interacting with the memory allows out-of-order execution to ensure the correct execution of the data processing command is indicated by the out-of-order execution definition corresponding to each operation type, so that the execution order of each operation can meet the condition of the correct execution of the data processing command according to the targeted relaxed sorting value setting according to the out-of-order execution definition. Therefore, the technical scheme provided by the embodiment of the application can guarantee the correct execution of the data processing command while improving the execution efficiency of the data processing command.

[0171] The computer system provided by the embodiment of the application can be a NUMA system or a CHIPLET system. NUMA (Non-Uniform Memory Access) is a design and organization method of computer architecture. It is mainly used in multi-processor systems and allows each processor or processor group to have its own local memory and access the memory of other nodes through a system interconnection.

[0172] CHIPLET is not a protocol, but an integrated circuit (IC) design and manufacturing method. CHIPLET architecture, also known as modular chip design, involves breaking a large monolithic chip into multiple smaller, function-specific modules, which are called "CHIPLETS". Each CHIPLET can be designed to perform a specific task or a set of tasks, and can be independently manufactured and then integrated together through advanced packaging technologies such as 3D stacking, high-density interconnection, etc.

[0173] In different architecture computer systems, using the controller 1 (NVME controller) provided by the embodiments of the present application, when executing data processing commands inside the controller 1, the setting of the loose ordering value can be performed for each operation of the data processing command interacting with the memory, so that all NVME transmission data conforming to the PCIE protocol is correct, and the stability (robustness) of the execution of the data processing command in the different architecture computer systems is ensured, so as to ensure the correctness of the execution of the data processing command while improving the execution efficiency of the data processing command.

[0174] Please continue to refer to ​ , the computer system further comprises:

[0175] a host 2 for updating the controller 1 to read and execute data processing commands;

[0176] a memory 3 for storing the data processing commands written by the host 2 to the command queue, and updating the completion queue based on the interrupt issued by the controller 1, the interrupt indicating that the execution of the data processing command is completed.

[0177] The above describes a plurality of embodiment schemes provided by the embodiments of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced without conflict, thereby extending a plurality of possible embodiment schemes, which can be considered as the embodiment schemes disclosed and disclosed by the embodiments of the present application.

[0178] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be limited by the scope defined by the claims.

Claims

1. A command processing method characterized by comprising: The method comprises the following steps: obtaining a parsing result of a data processing command, wherein the parsing result comprises various operations for completing the data processing command and interacting with a memory; determining operation types of the various operations, setting a loose ordering value for each operation based on a corresponding out-of-order execution definition of the operation type, and implementing out-of-order execution of the various operations interacting with the memory among different data processing commands according to the loose ordering value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether an operation is allowed to execute out of order according to a condition for correct execution of a data processing command; packaging the various operations with the set loose ordering value to obtain a data packet corresponding to the data processing command.

2. The command processing method of claim 1, wherein, The various operations interacting with the memory comprise an execution operation for executing data transmission and an update operation for updating a completion queue of the memory; The method comprises the following steps: determining that the operation type of the execution operation is a first type, and setting a loose ordering value for the execution operation according to the out-of-order execution definition corresponding to the first type; determining that the operation type of the update operation is a second type, and setting a loose ordering value for the update operation according to the out-of-order execution definition corresponding to the second type.

3. The command processing method of claim 2, wherein, The out-of-order execution definition is defined based on a transmission protocol for processing the data processing command, and the transmission protocol is a condition for correct execution of the data processing command; The method comprises the following steps: setting a loose ordering value of a first value for the execution operation according to the out-of-order execution definition corresponding to the first type, to indicate that out-of-order execution is allowed when the data processing command is processed using the transmission protocol; The method comprises the following steps: judging whether the update operation is allowed to execute out of order in the data transmission protocol defining the out-of-order execution definition; if yes, setting a loose ordering value of the first value for the update operation corresponding to the second type; if no, setting a loose ordering value of a second value for the update operation corresponding to the second type, to indicate that out-of-order execution is not allowed when the data processing command is processed using the transmission protocol.

4. The command processing method of claim 2, wherein, The out-of-order execution definition is defined based on an architecture system for executing the data processing command.

5. The command processing method according to any one of claims 1 to 4, wherein The method comprises the following steps: determining operation types of the various operations in the parsing result by executing a software program, setting a loose ordering value for each operation corresponding to the determined operation type based on the out-of-order execution definition corresponding to the operation type.

6. The command processing method according to any one of claims 1 to 4, wherein The method comprises the following steps: determining the loose ordering value set for each operation corresponding to the operation type based on the loose ordering value recorded in the loose ordering control register according to the out-of-order execution definition corresponding to the operation type. The loose ordering control register is arranged in a controller for executing the data processing command.

7. The command processing method of claim 6, wherein, The loose ordering control register is arranged with an execution entry and a completion queue update entry; and in the index loose ordering control register, a loose ordering value set for each operation type is determined based on a loose ordering value of a corresponding out-of-order execution definition record of each operation type. When the operation is determined to be an execution operation, the loose ordering value set for the execution operation is determined based on a loose ordering value of a corresponding out-of-order execution definition record of the first type in the index loose ordering control register. When the operation is determined to be an update operation, the loose ordering value set for the update operation is determined based on a loose ordering value of a corresponding out-of-order execution definition record of the first type in the index loose ordering control register.

8. The command processing method according to any one of claims 1 to 4, wherein Before the step of obtaining the analysis result of the data processing command, the method further comprises: reading the data processing command and analyzing the data processing command to obtain the analysis result of the data processing command; After the step of packetizing the operations with the set loose ordering values to obtain the data packet corresponding to the data processing command, the method further comprises: transmitting the data packet corresponding to the data processing command.

9. A controller characterized by comprising: The method comprises: an analysis result obtaining module configured to obtain an analysis result of a data processing command, the analysis result comprising operations for completing memory interaction of the data processing command; a loose ordering value setting module configured to determine an operation type of each operation, set a loose ordering value for each operation based on a corresponding out-of-order execution definition of each operation type, and implement out-of-order execution of the operations for memory interaction between different data processing commands according to the loose ordering value set by the out-of-order execution definition; the out-of-order execution definition is used to indicate whether an operation is allowed to execute out of order according to a condition for correct execution of a data processing command; a packetizing module configured to packetize the operations with the set loose ordering values to obtain a data packet corresponding to the data processing command.

10. The controller of claim 9, wherein, The operations for memory interaction comprise an execution operation for executing data transmission and an update operation for updating a completion queue of a memory. The loose ordering value setting module is configured to determine an operation type of each operation, set a loose ordering value for each operation based on a corresponding out-of-order execution definition of each operation type, and comprise: determining that the operation type of the execution operation is a first type and setting a loose ordering value for the execution operation according to the out-of-order execution definition of the first type; determining that the operation type of the update operation is a second type and setting a loose ordering value for the update operation according to the out-of-order execution definition of the second type.

11. The controller of claim 10, wherein, The out-of-order execution definition is based on a transmission protocol for processing the data processing command, and the transmission protocol is a condition for correct execution of a data processing command. The loose ordering value setting module is configured to determine that the operation type of the execution operation is a first type and set a loose ordering value for the execution operation according to the out-of-order execution definition of the first type, and comprise: According to the first type corresponding to the out-of-order execution definition, a relaxed ordering value of the first value is set for the execution operation, to indicate that the out-of-order execution is allowed when the data processing command is processed using the transmission protocol; The relaxed ordering value setting module is configured to determine that the operation type of the update operation is the second type, and set a relaxed ordering value for the update operation according to the second type corresponding to the out-of-order execution definition, including: Judging whether the update operation is allowed to execute out-of-order in the data transmission protocol defining the out-of-order execution definition; If yes, setting the relaxed ordering value of the first value for the update operation corresponding to the second type; If no, setting the relaxed ordering value of the second value for the update operation corresponding to the second type, to indicate that the out-of-order execution is not allowed when the data processing command is processed using the transmission protocol.

12. The controller of any one of claims 9-10, wherein, The relaxed ordering value setting module is a software program; the relaxed ordering value setting module is configured to determine the operation type of each operation, and set a relaxed ordering value for each operation based on the out-of-order execution definition corresponding to the operation type, including: The software program is configured to determine the operation type of each operation in the analysis result, and set a relaxed ordering value for each operation corresponding to the operation type based on the out-of-order execution definition corresponding to the determined operation type.

13. The controller of any one of claims 9-10, wherein, The relaxed ordering value setting module is a relaxed ordering control register; the relaxed ordering value setting module is configured to set a relaxed ordering value for each operation based on the out-of-order execution definition corresponding to the operation type, including: Indexing the relaxed ordering value recorded in the relaxed ordering control register based on the out-of-order execution definition corresponding to each operation type, to determine the relaxed ordering value set for each operation corresponding to the operation type.

14. The controller of claim 13, wherein, The relaxed ordering control register is provided with an execution entry and a completion queue update entry; the relaxed ordering value setting module is configured to index the relaxed ordering value recorded in the relaxed ordering control register based on the out-of-order execution definition corresponding to each operation type, to determine the relaxed ordering value set for each operation corresponding to the operation type, including: When determining that the operation is an execution operation, indexing the relaxed ordering value recorded in the relaxed ordering control register based on the out-of-order execution definition corresponding to the first type, to determine the relaxed ordering value set for the execution operation; When determining that the operation is an update operation, indexing the relaxed ordering value recorded in the relaxed ordering control register based on the out-of-order execution definition corresponding to the first type, to determine the relaxed ordering value set for the update operation.

15. The controller of any one of claims 9-10, wherein, Further comprising: A command reading and analyzing module configured to read a data processing command, and analyze the data processing command to obtain an analysis result of the data processing command; A data packet transmission module configured to transmit a data packet corresponding to the data processing command.

16. A computer system, characterized by Including: The controller of any one of claims 9-15.

17. The computer system of claim 16, wherein, Further comprising: A host configured to update the controller, so that the controller reads and executes a data processing command; A memory configured to store a data processing command written by the host to a command queue, and update a completion queue based on an interrupt issued by the controller, the interrupt indicating that the execution of the data processing command is completed.

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