Debugging jig, debugging system and debugging method for liquid-cooled hard disk back plate

Abstract

The application discloses a liquid-cooled hard disk backboard debugging jig, a debugging system and a debugging method thereof, and comprises the following steps: when the to-be-debugged mode of a to-be-tested backboard is an SGPIO mode, a first CPLD module is used for generating a first analog signal and an SGPIO signal for controlling an indication module; when the to-be-debugged mode is a Legacy VPP or NPEM mode, the first CPLD module is used for reading a target I2C address of the to-be-tested backboard, generating a second analog signal, receiving an interrupt signal sent by a second CPLD module, and generating an I2C signal for controlling the indication module, so that the function debugging of the firmware of the to-be-tested backboard can be realized before the to-be-tested backboard and a mainboard are assembled and put into cooling liquid, the SGPIO, Legacy VPP and NPEM modes are simultaneously supported, and the problem of the assembled backboard is avoided, and the production efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hard disk backboard testing, in particular to a liquid-cooled hard disk backboard debugging jig, a debugging system and a debugging method thereof. BACKGROUND

[0002] Liquid-cooled servers, as an efficient, energy-saving and environmentally friendly heat dissipation solution, have received more and more attention. Among them, the immersion liquid cooling is to immerse the server completely in the coolant, and rely on the circulation of liquid flow to take away the heat. The liquid-cooled backboard, as an important part of the liquid-cooled server, is mainly used to connect the storage hard disk of the server and provide a management interface for the management of the storage hard disk. However, since the liquid-cooled server is completely immersed in the cooling liquid when working, it is very inconvenient to debug the CPLD (Complex Programmable Logic Device) firmware on the hard disk backboard.

[0003] In addition, the patent with the publication number CN115640186A discloses a test system and a test method for an NVMe hard disk backboard. This scheme can only test the backboard of a specific hard disk, and the CPLD function verification part is only for the firmware of a certain CPLD, which has certain limitations and cannot comprehensively cover different types of hard disk backboards and CPLD firmware. SUMMARY

[0004] The present application provides a liquid-cooled hard disk backboard debugging jig, a debugging system and a debugging method thereof, aiming to solve the problem of inconvenient debugging of CPLD firmware on the hard disk backboard and certain limitations in the prior art.

[0005] In a first aspect, the present application provides a liquid-cooled hard disk backboard debugging jig applied to a to-be-tested backboard. The debugging jig comprises a first CPLD module, a display module, a first connection module, a key module and a cable module. The display module, the first connection module, the key module and the cable module are connected with the first CPLD module. The first CPLD module is connected with the hard disk connection module of the to-be-tested backboard through the cable module. The first CPLD module is connected with the second CPLD module of the to-be-tested backboard through the first connection module and the second connection module of the to-be-tested backboard. The second CPLD module is connected with the indication module of the to-be-tested backboard.

[0006] When the first CPLD module determines that the mode to be debugged is the SGPIO mode through the display module and the key module, the first CPLD module is configured to generate a first analog signal for simulating a hard disk to access the hard disk connection module, and generate an SGPIO signal for controlling an indication module of the backboard to be tested; when the first CPLD module determines that the mode to be debugged is the Legacy VPP mode or the NPEM mode through the display module and the key module, the first CPLD module is configured to read a target I2C address of the backboard to be tested, generate a second analog signal for simulating a hard disk to access the hard disk connection module, receive and detect an interrupt signal sent by the second CPLD module, and generate an I2C signal for controlling the indication module of the backboard to be tested.

[0007] In a second aspect, an embodiment of the present application provides a debugging system for a liquid-cooled hard disk backboard, which comprises the debugging fixture for the liquid-cooled hard disk backboard as described in the first aspect, and further comprises a backboard to be tested, wherein a hard disk connection module of the backboard to be tested is connected to the cable module in the debugging fixture, a second connection module of the backboard to be tested is connected to the first connection module in the debugging fixture, and the second connection module is further connected to a second CPLD module of the backboard to be tested, and the second CPLD module is connected to an indication module of the backboard to be tested.

[0008] In a third aspect, an embodiment of the present application further provides a debugging method for a liquid-cooled hard disk backboard, which is applied to the debugging system for the liquid-cooled hard disk backboard as described in the first aspect, and comprises the following steps:

[0009] When the first CPLD module of the debugging fixture receives an information selection instruction through the display module and the key module of the debugging fixture, target information corresponding to the backboard to be tested is selected from preset information according to the information selection instruction, wherein the target information comprises a target mode to be debugged and a number of target hard disks, and the target mode to be debugged comprises an SGPIO mode, a Legacy VPP mode and an NPEM mode.

[0010] If the first CPLD module determines that the target mode to be debugged is the SGPIO mode, a first analog signal is generated, and the first analog signal is sent to a hard disk connector corresponding to the number of target hard disks in the hard disk connection module of the backboard to be tested through a first target cable piece corresponding to the number of target hard disks in the cable module of the debugging fixture, and an SGPIO signal for controlling an indication module of the backboard to be tested is generated, and the SGPIO signal is sent to a second CPLD module of the backboard to be tested through the first connection module of the debugging fixture and the second connection module of the backboard to be tested.

[0011] The first CPLD module reads a target I2C address from a preset I2C address if it is determined that the target debugging mode is a Legacy VPP or NPEM mode, generates a second analog signal, sends the second analog signal to a second target hard disk connector in the hard disk connection module equal in number to the target hard disk through a second target cable piece in the cable module equal in number to the target hard disk, and receives and detects an interrupt signal sent by the second CPLD module through the first connection module and the second connection module;

[0012] The first CPLD module controls to end interrupt detection if it is detected that the interrupt signal corresponds to the target hard disk one by one, generates an I2C signal for controlling the indication module of the backboard under test, and sends the I2C signal to the second CPLD module through the first connection module and the second connection module based on the target I2C address;

[0013] The second CPLD module controls the indication module of the backboard under test according to the SGPIO signal or the I2C signal, obtains a first state indication result or a second state indication result, and sends the first state indication result or the second state indication result to the first CPLD module;

[0014] The first CPLD module controls to end debugging of the backboard under test if it is detected that the first state indication result is consistent with a first preset state or the second state indication result is consistent with a second preset state.

[0015] The embodiment of the application discloses a debugging jig, a debugging system and a debugging method of a liquid-cooled hard disk backboard. The debugging jig comprises a first CPLD module, a display module, a first connection module, a key module and a cable module. When the debugging mode of the backboard under test is an SGPIO mode, the first CPLD module is used to generate a first analog signal and also generate an SGPIO signal for controlling the indication module. When the debugging mode is a Legacy VPP or NPEM mode, the first CPLD module is used to read a target I2C address of the backboard under test, generate a second analog signal, receive an interrupt signal sent by a second CPLD module, and also generate an I2C signal for controlling the indication module. Therefore, the function debugging of the firmware of the backboard under test can be realized before the backboard under test and the mainboard are assembled and put into the cooling liquid, SGPIO, Legacy VPP and NPEM modes are supported, and the problem after assembly is avoided, thereby improving the production efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings described in the following are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0017] Figure 1 The structural schematic diagram of the debugging system of the liquid-cooled hard disk backboard provided by the embodiment of the present application is shown in the figure.

[0018] Figure 2 Another structural schematic diagram of the debugging system of the liquid-cooled hard disk backboard provided by the embodiment of the present application is shown in the figure.

[0019] Figure 3 The flowchart of the debugging method of the liquid-cooled hard disk backboard provided by the embodiment of the present application is shown in the figure.

[0020] In the figure, the various reference signs are as follows:

[0021] 10, debugging system of liquid-cooled hard disk backboard; 100, debugging fixture; 110, first CPLD module; 120, display module; 130, first connection module; 131, first connector; 132, second connector; 133, third connector; 134, fourth connector; 140, key module; 141, reset key; 142, function selection key; 143, function confirmation key; 150, cable module; 151, first cable piece; 152, second cable piece; 153, third cable piece; 154, fourth cable piece; 200, backboard to be tested; 210, second CPLD module; 220, hard disk connection module; 221, first hard disk connector; 222, second hard disk connector; 223, third hard disk connector; 224, fourth hard disk connector; 230, second connection module; 231, fifth connector; 232, sixth connector; 233, seventh connector; 234, eighth connector; 240, indication module; 241, first indication lamp; 242, second indication lamp; 243, third indication lamp; 244, fourth indication lamp; 250, field replaceable unit; 260, temperature sensor. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, and for those skilled in the art, all other embodiments obtained without creative labor on the basis of these embodiments also belong to the scope of protection of the present application.

[0023] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0024] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0025] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0026] In order to better understand the technical solution of this application, the terminals involved are described in detail below. In this application, the technical solution is described from the perspectives of the sending end and the server.

[0027] See also Figure 1 and Figure 2 , Figure 1 A schematic structural diagram of a debugging system for a liquid-cooled hard disk backplane provided by an embodiment of the present invention; Figure 2 Another structural schematic diagram of the debugging system for the liquid-cooled hard disk backplane provided by an embodiment of the present invention. The debugging fixture 100 for the liquid-cooled hard disk backplane of the embodiment of the present invention is applied to the backplane to be tested 200, and the debugging fixture 100 includes a first CPLD module 110, a display module 120, a first connection module 130, a key module 140, and a cable module 150; the display module 120, the first connection module 130, the key module 140, and the cable module 150 are all connected to the first CPLD module 110; the first CPLD module 110 is connected to the hard disk connection module 220 of the backplane to be tested 200 via the cable module 150; the first CPLD module 110 is connected to the second CPLD module 210 of the backplane to be tested 200 via the first connection module 130 and the second connection module 230 of the backplane to be tested 200, and the second CPLD module 210 is connected to the indication module 240 of the backplane to be tested 200;

[0028] When the first CPLD module 110 determines that the mode to be debugged is SGPIO mode through the display module 120 and the key module 140, the first CPLD module 110 is configured to generate a first analog signal for simulating a hard disk accessing the hard disk connection module 220, and generate an SGPIO signal for controlling the indication module 240 of the backboard 200 to be tested; when the first CPLD module 110 determines that the mode to be debugged is LegacyVPP mode or NPEM mode through the display module 120 and the key module 140, the first CPLD module 110 is configured to read a target I2C address of the backboard 200 to be tested, generate a second analog signal for simulating a hard disk accessing the hard disk connection module 220, receive and detect an interrupt signal sent by the second CPLD module 210, and generate an I2C signal for controlling the indication module 240 of the backboard 200 to be tested.

[0029] In the embodiment, the debugging jig 100 of the liquid-cooled hard disk backboard comprises a first CPLD module 110, a display module 120, a first connection module 130, a key module 140 and a cable module 150; the display module 120, the first connection module 130, the key module 140 and the cable module 150 are connected with the first CPLD module 110; preferably, the display module 120 can be an LCD 1602 display module 120 in the embodiment, the display module 120 is connected with the first CPLD module 110 through an IO interface, and the display module 120 can be used to display information and states in the debugging process; the key module 140 is used for user input and selection of a mode and parameters to be debugged; the first connection module 130 is connected with a second connection module 230 of the backboard 200 to be tested, so as to connect the first CPLD module 110 and a second CPLD module 210 of the backboard 200 to be tested; and the cable module 150 is used to connect the first CPLD module 110 and a hard disk connection module 220 of the backboard 200 to be tested.

[0030] In specific implementation, the first CPLD module 110 controls the display module 120 to display "mode:" through the IO interface, at this time, based on the type of the to-be-tested backboard 200, and the to-be-debugged mode is determined through the key module 140, wherein the to-be-debugged mode includes an SGPIO mode, a Legacy VPP mode, and an NPEM mode. Moreover, the first CPLD module 110 can also control the display module 120 to display "SAS / SATA QTY:" through the IO interface, wherein the display module 120 also displays the number of regular hard disks for the user to select, for example, 2 / 4 / 8 / 16 / 24. In addition, if the number of regular hard disks cannot meet the user's demand, the number of hard disks can also be automatically adjusted through the key module 140. In addition, after the selection of the to-be-debugged mode and the target number of hard disks of the to-be-tested backboard 200 is completed, when the first CPLD module 110 determines that the to-be-debugged mode of the to-be-tested backboard 200 is the SGPIO mode through the display module 120 and the key module 140, the first CPLD module 110 sends the generated first analog signal to the Pin4 and pin10 pins of the target hard disk connector in the hard disk connection module 220 of the to-be-tested backboard 200 through the cable module 150, wherein when no hard disk is connected to the hard disk connector of the hard disk connection module 220, the Pin4 and pin10 pins of the hard disk connector are high level, after receiving the first analog signal, the pin4 pin of the hard disk connector is controlled to change from high level to low level, and the Pin10 pin is controlled to change from high level 1 to low level, so as to simulate that the SAS / SATA hard disk is connected to the hard disk connection module 220. Then, the first CPLD module 110 is connected with the second CPLD module 210 through the first connection module 130 and the second connection module 230, so that the SGPIO signal generated by the first CPLD module 110 is analyzed through the second CPLD module 210, and the analyzed result is sent to the corresponding indicator lamp in the indication module 240, so as to control the working state of the target indicator lamp in the indication module 240, and then the working state of the target indicator lamp is used to indicate the state of the hard disk simulated to be connected to the hard disk connection module 220; for example, the state of the SAS / SATA hard disk includes four states of OK, positioning, error, and reconstruction, which can be indicated by the indicator lamp working in four working states of off, 4Hz flashing, constant lighting, and 1Hz flashing, respectively. In this embodiment, the indication module 240 preferably includes a first indicator lamp 241, a second indicator lamp 242, a third indicator lamp 243, and a fourth indicator lamp 244, and the number of indicator lamps in the indication module 240 can be set according to the number of connected hard disks.In addition, when the first CPLD module 110 determines that the debugging mode of the to-be-tested backboard 200 is the Legacy VPP mode or the NPEM mode through the display module 120 and the button module 140, the first CPLD module 110 first controls the display module 120 to display "I2C ADDR0:" through the IO interface, and selects a target I2C address from the preset I2C addresses 0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, and 0x4E through the button module 140, so that the first CPLD module 110 reads the target I2C address for subsequent storage of I2C signals. Then, the first CPLD module 110 sends the generated second analog signal to the pin4 and pin10 pins of the target hard disk connector in the hard disk connection module 220 through the cable module 150. When no hard disk is connected to the hard disk connector of the hard disk connection module 220, the pin4 and pin10 pins of the hard disk connector are at a high level. After receiving the second analog signal, the pin10 pin of the hard disk connector remains at a high level, and the pin4 changes from a high level 1 to a low level, so as to simulate that an NVMe hard disk is connected to the hard disk connection module 220. In order to verify the interrupt function of the to-be-tested backboard, the second CPLD module 210 sends an interrupt signal to the first CPLD module 110 through the second connection module 230 and the first connection module 130. If the first CPLD module 110 receives an interrupt signal corresponding to the simulated NVMe hard disk connected to the hard disk connection module 220, the first CPLD module 110 sends the same I2C signal based on each I2C address in the target I2C address, and sends the I2C signal in parallel to each PCA9555 chip in the second CPLD module 210 through the first connection module 130 and the second connection module 230 for analysis, and sends the analyzed result to the target indicator light in the indication module 240 connected to the second CPLD module 210, so as to control the working state of the target indicator light in the indication module 240, and then indicate the state of the simulated NVMe hard disk connected to the hard disk connection module 220 through the working state of the target indicator light. For example, the states of the NVMe hard disk include OK, positioning, error, and rebuilding, which can be indicated by the working states of the indicator light, i.e., the four working states of off, 4Hz flashing, constant lighting, and 1Hz flashing.

[0031] When the to-be-debugged mode is the Legacy VPP mode, the PCA9555 chip in the second CPLD module 210 parses serial data of an I2C signal, and controls a target indicator light (i.e., an LED) in the indication module 240 through IOx.0 and IOx.1 pins on an IO port of the PCA9555 chip, in a manner shown in Table 1.

[0032] Table 1

[0033] Hard disk status Fault (IO x. 0) Locate (IO x. 1) LED status OK 0 0 Off Locate 0 1 4 Hz blinking Fault 1 0 Constantly on Rebuild 1 1 1 Hz blinking

[0034] When the to-be-debugged mode is the NPEM mode, the PCA9555 chip in the second CPLD module 210 parses serial data of an I2C signal, and controls a target indicator light (i.e., an LED) in the indication module 240 through IO0.2, IO0.3, IO0.4, and IO0.5 pins on an IO port of the PCA9555 chip, in a manner shown in Table 2.

[0035] Table 2

[0036]

[0037]

[0038] The debugging jig of the liquid-cooled hard disk backboard provided in the embodiment of the present application realizes functional debugging of a to-be-tested backboard firmware, supports SGPIO, Legacy VPP, and NPEM modes, and solves the problems of inconvenient debugging and certain limitation of CPLD firmware on a hard disk backboard.

[0039] In an embodiment, as shown in Figure 1 and 2 The first connection module 130 includes a first connector 131, a second connector 132, a third connector 133, and a fourth connector 134. The first connector 131 is connected with the first CPLD module 110 through an SGPIO bus. The second connector 132 is connected with the first CPLD module 110 through an I2C bus. The third connector 133 is connected with the first CPLD module 110 through the I2C bus. The fourth connector 134 is connected with the first CPLD module 110 through the I2C bus.

[0040] In the embodiment, the first CPLD module 110 is a host end of SGPIO signal and I2C signal, the first connector 131 is connected with the first CPLD module 110 through SGPIO bus for transmitting SGPIO signal generated by the first CPLD module 110, the second connector 132 is connected with the first CPLD module 110 through I2C bus for transmitting I2C signal generated by the first CPLD module 110, the third connector 133 is connected with the first CPLD module 110 through I2C bus for transmitting I2C signal generated by the first CPLD module 110, the fourth connector 134 is connected with the first CPLD module 110 through I2C bus for transmitting the obtained information of the backboard 200 to be tested to the first CPLD module 110, wherein the information of the backboard 200 to be tested includes firmware version of the second CPLD module 210, information of the field replaceable unit 250 and temperature of the backboard 200 to be tested; and the SGPIO bus and the I2C bus can be one group or multiple groups, which is determined by the indication module 240 on the backboard 200 to be tested, and is not specifically limited in the embodiment.

[0041] In an embodiment, as shown in Figure 1 and 2 The key module 140 includes a reset key 141, a function selection key 142 and a function confirmation key 143, and the reset key 141, the function selection key 142 and the function confirmation key 143 are connected with the first CPLD module 110.

[0042] In the embodiment, the reset button 141, the function selection button 142 and the function confirmation button 143 in the key module 140 are connected with the first CPLD module 110, for determining the debugging mode to be debugged and the number of hard disks to be accessed of the first CPLD module 110. Specifically, when the first CPLD module 110 controls the display module 120 to display "mode:" through the IO interface, the user can switch the debugging mode to be debugged through the function selection button 142 in the key module 140, and confirm the selected debugging mode to be debugged through the function confirmation button 143 in the key module 140. In addition, when the first CPLD module 110 also controls the display module 120 to display "SAS / SATA QTY:" through the IO interface, the user can switch the preset number of hard disks, for example, 2 / 4 / 8 / 16 / 24, through the function selection button 142 in the key module 140, and confirm the number of target hard disks selected through the function confirmation button 143 in the key module 140. Moreover, when the preset number of hard disks cannot meet the user's demand, the preset number of hard disks can also be adjusted by long-pressing the function selection button 142 in the key module 140 until the preset number of hard disks on the display module 120 becomes 0 and flashes, and then short-pressing the function selection button 142 to realize the increment of the number, until the number to be selected appears on the display module 120, and then confirming through the function confirmation button 143.

[0043] In an embodiment, as shown in Figure 1 and 2 The cable module 150 includes a first cable piece 151, a second cable piece 152, a third cable piece 153 and a fourth cable piece 154, which are all connected with the first CPLD module 110.

[0044] In the embodiment, in order to realize the transmission of the first analog signal and the second analog signal generated by the first CPLD module 110 for simulating the hard disk to access the hard disk connection module 220 to the hard disk connection module 220 of the to-be-tested backboard 200, the external IO interface of the first CPLD module 110 is connected to the first cable piece 151, the second cable piece 152, the third cable piece 153 and the fourth cable piece 154 of the cable module 150. The first cable piece 151 comprises a first cable connector and a first cable line, and the first cable line is connected to the first CPLD module 110 through the first cable connector; the second cable piece 152 comprises a second cable connector and a second cable line, and the second cable line is connected to the second CPLD module 210 through the second cable connector; the third cable piece 153 comprises a third cable connector and a third cable line, and the third cable line is connected to the first CPLD module 110 through the third cable connector; and the fourth cable piece 154 comprises a fourth cable connector and a fourth cable line, and the fourth cable line is connected to the first CPLD module 110 through the fourth cable connector. Since the cable pieces of the cable module 150 correspond to the cable connectors in the hard disk connection module 220 one by one, the hard disk connection module 220 comprises a first hard disk connector 221, a second hard disk connector 222, a third hard disk connector 223 and a fourth hard disk connector 224 in the embodiment. In the implementation, when the first CPLD module 110 controls the display module 120 to display "SAS / SATA QTY:" through the IO interface, the user switches the preset number of hard disks through the function selection button 142 in the key module 140, and confirms the number of the target hard disks through the function confirmation button 143 in the key module 140, and then selects the same number of cable pieces as the number of the target hard disks from the cable module 150 based on the number of the target hard disks. For example, when the number of the target hard disks is two, the first cable piece 151 and the second cable piece 152 are selected from the cable module 150, the first cable line in the first cable piece 151 is connected to the first hard disk connector 221 of the hard disk connection module 220, and the first cable line in the first cable piece 151 is connected to the first hard disk connector 221 of the hard disk connection module 220, so as to transmit the first analog signal or the second analog signal generated by the first CPLD module 110 to the corresponding first hard disk connector 221 and the second hard disk connector 222, thereby realizing the access of the simulated hard disk to the hard disk connection module 220.

[0045] Please refer to Figure 1 and Figure 2The embodiment of the present application also provides a debugging system 10 of the liquid-cooled hard disk backboard, which comprises any one of the aforementioned debugging jigs 100 of the liquid-cooled hard disk backboard, and further comprises a to-be-tested backboard 200, wherein the hard disk connecting module 220 of the to-be-tested backboard 200 is connected with the cable module 150 in the debugging jig 100, the second connecting module 230 of the to-be-tested backboard 200 is connected with the first connecting module 130 in the debugging jig 100, the second connecting module 230 is further connected with the second CPLD module 210 of the to-be-tested backboard 200, and the second CPLD module 210 is connected with the indicating module 240 of the to-be-tested backboard 200.

[0046] In the embodiment, the working principle of the debugging system 10 of the liquid-cooled hard disk backboard is consistent with the working principle of the debugging jig 100 of the liquid-cooled hard disk backboard and the to-be-tested backboard 200 after being connected, and thus is not repeated here. The debugging system of the liquid-cooled hard disk backboard provided by the embodiment of the present application can realize the functional debugging of the firmware of the to-be-tested backboard 200 before the to-be-tested backboard 200 and the main board are assembled and put into the cooling liquid, and meanwhile supports the SGPIO, Legacy VPP and NPEM modes, thereby avoiding the problem that the to-be-tested backboard 200 and the main board are assembled and then problems occur, and improving the production efficiency.

[0047] In an embodiment, as shown in Figure 1 and 2 The second connecting module 230 comprises a fifth connector 231, a sixth connector 232, a seventh connector 233 and an eighth connector 234, the fifth connector 231 is connected with the second CPLD module 210 through an SGPIO bus, the sixth connector 232 is connected with the second CPLD module 210 through an I2C bus, the seventh connector 233 is connected with the second CPLD module 210 through an I2C bus, and the eighth connector 234 is connected with the second CPLD module 210, and is further connected with a field replaceable unit 250 and a temperature sensor 260.

[0048] In the embodiment, the first connecting module 130 in the liquid-cooled hard disk backboard debugging jig 100 includes a first connector 131, a second connector 132, a third connector 133 and a fourth connector 134, and the second connecting module 230 on the to-be-tested backboard 200 corresponding to the first connecting module 130 includes a fifth connector 231, a sixth connector 232, a seventh connector 233 and an eighth connector 234, wherein the fifth connector 231 is connected with the second CPLD module 210 through an SGPIO bus, the sixth connector 232 is connected with the second CPLD module 210 through an I2C bus, the seventh connector 233 is connected with the second CPLD module 210 through an I2C bus, and the eighth connector 234 is connected with the second CPLD module 210, the field replaceable unit 250 and the temperature sensor 260; and the fifth connector 231 is connected with the first connector 131 through a high-speed cable for transmitting an SGPIO signal for controlling a target indicator lamp in the indication module 240; the sixth connector 232 is connected with the second connector 132 through a high-speed cable, and the seventh connector 233 is connected with the third connector 133 through a high-speed cable for transmitting an I2C signal for controlling a target indicator lamp in the indication module 240; and the eighth connector 234 is connected with the fourth connector 134 through a low-speed cable for obtaining hard disk backboard information such as a second CPLD module 210 firmware version, field replaceable unit 250 information and to-be-tested backboard 200 temperature.

[0049] The embodiment of the present application further provides a liquid-cooled hard disk backboard debugging method applied to the liquid-cooled hard disk backboard debugging system. Figure 3 , Figure 3 The flowchart of the liquid-cooled hard disk backboard debugging method provided by the embodiment of the present application includes steps S101-S106.

[0050] S101, when the first CPLD module of the debugging jig receives an information selection instruction through the display module and the key module of the debugging jig, target information corresponding to the to-be-tested backboard is selected from preset information according to the information selection instruction; wherein the target information includes a target to-be-debugged mode and the number of target hard disks, and the target to-be-debugged mode includes an SGPIO mode, a Legacy VPP mode and an NPEM mode.

[0051] In the embodiment, the information selection instruction can be triggered by a relevant staff, and the selecting target information corresponding to the to-be-tested backboard 200 from the preset information according to the information selection instruction includes: the first CPLD module 110 decomposes the information selection instruction to obtain a mode acquisition instruction and a hard disk quantity acquisition instruction; the target to-be-debugged mode of the to-be-tested backboard 200 is acquired from the preset information according to the mode acquisition instruction; and the quantity of the target hard disk is acquired from the preset information according to the hard disk quantity acquisition instruction. Specifically, when the first CPLD module 110 controls the display module 120 of the debugging fixture 100 to display a to-be-debugged mode through an IO interface, if the key module 140 of the debugging fixture 100 receives a mode acquisition instruction for the to-be-debugged mode, the target to-be-debugged mode is determined through the mode acquisition instruction; and the first CPLD module 110 also controls the display module 120 to display a hard disk quantity through the IO interface, and if the key module 140 receives a hard disk quantity acquisition instruction for the hard disk quantity, the quantity of the target hard disk is determined through the hard disk quantity acquisition instruction.

[0052] S102, if the first CPLD module determines that the target to-be-debugged mode is an SGPIO mode, a first analog signal is generated, and the first analog signal is sent to a first target hard disk connector in a hard disk connection module of the to-be-tested backboard through a first target cable piece in a cable module of the debugging fixture and equal to the quantity of the target hard disk, and an SGPIO signal for controlling an indication module of the to-be-tested backboard is generated, and the SGPIO signal is sent to a second CPLD module of the to-be-tested backboard through a first connection module of the debugging fixture and a second connection module of the to-be-tested backboard.

[0053] In the embodiment, after the steps of completing the selection of the target debugging mode and the number of target hard disks, the first CPLD module 110 generates a first simulation signal for simulating the SAS / SATA hard disk accessing the hard disk connection module 220 if it is determined that the current target debugging mode is the SGPIO mode. Specifically, the first CPLD module 110 sends the first simulation signal through the first target cable pieces in the cable module 150 of the debugging tool 100 equal to the number of target hard disks to the first target hard disk connectors in the hard disk connection module 220 of the backboard under test 200 equal to the number of target hard disks, so as to control the pin4 and pin10 pins of each hard disk connector in the first target hard disk connector, thereby controlling the pin4 pin of each hard disk connector to change from high level to low level, and the pin10 pin to change from high level 1 to low level, and further simulating the SAS / SATA hard disk accessing the hard disk connection module 220. Moreover, the first CPLD module 110 generates an SGPIO signal for controlling the indication module 240 of the backboard under test 200, and controls the SCPIO bus to send the SGPIO signal through the first connection module 130 of the debugging tool 100 and the second connection module 230 of the backboard under test 200 in sequence to the second CPLD module 210 of the backboard under test 200, so as to subsequently control the corresponding indicator lights on the indication module 240 to simulate the SAS / SATA hard disk in the OK, locate, error, and rebuild states in sequence through the SGPIO signal, thereby indicating the working state of the SAS / SATA hard disk simulated to access the hard disk connection module 220. In addition, the display module 120 connected with the first CPLD module 110 also synchronously displays the state corresponding to the serial data stream of the current SGPIO signal in real time, i.e., OK, Locate, Fault, and Rebuild.

[0054] S103, if the first CPLD module determines that the target debugging mode is the Legacy VPP or NPEM mode, it reads a target I2C address from a preset I2C address, generates a second simulation signal, sends the second simulation signal through the second target cable pieces in the cable module equal to the number of target hard disks to the second target hard disk connectors in the hard disk connection module equal to the number of target hard disks, and receives and detects the interrupt signal sent by the second CPLD module through the first connection module and the second connection module.

[0055] In the embodiment, if the first CPLD module 110 determines that the current target debugging mode is the LegacyVPP mode or the NPEM mode, the first CPLD module 110 reads each I2C address in the target I2C address from the preset I2C address through the display module 120 and the button module 140. Specifically, the first CPLD module 110 controls the display module 120 to display "I2C ADDR0:" through the IO interface, and selects the target I2C address from the preset I2C addresses 0x40, 0x42, 0x44, 0x46, 0x48, 0x4A, 0x4C, 0x4E through the function selection button 142 in the button module 140, and confirms the target I2C address through the function confirmation button 143 in the button module 140, so that the first CPLD module 110 can send based on each I2C address in the target I2C address after generating the I2C signal. Then, the first CPLD module 110 generates a second analog signal, which is used to simulate that the NVMe hard disk accesses the hard disk connector of the hard disk connection module 220. Specifically, the first CPLD module 110 sends the second analog signal to the hard disk connection module 220 of the to-be-tested backboard 200 through the second target cable in the cable module 150 of the debugging tool 100, which is equal in number to the target hard disk, and controls the pin 4 and pin 10 pins of each hard disk connector in the second target hard disk connector, so as to control the pin 10 pin of each hard disk connector to keep high level, and the pin 4 pin to change from high level 1 to low level, thereby simulating that the NVMe hard disk accesses the hard disk connection module 220. At this time, if the firmware design of the second CPLD module 210 of the to-be-tested backboard 200 is correct, the first CPLD module 110 receives and detects the interrupt signal sent by the second CPLD module 210 through the first connection module 130 and the second connection module 230, and the first CPLD module 110 controls the display module 120 to display "NVMe1 / 2 / 3 / 4…ADDInterrupt" synchronously and sequentially, so as to realize interrupt verification on each NVMe hard disk accessed in the hard disk connection module 220.

[0056] In an embodiment, after receiving and detecting the interrupt signal sent by the second CPLD module 210 through the first connection module 130 and the second connection module 230, the method further comprises:

[0057] If the first CPLD module 110 detects that the interrupt signal does not correspond to the target hard disk one by one, the first CPLD module 110 generates interrupt exception information.

[0058] In the embodiment, if in the interrupt verification process, if it is detected that the interrupt signal does not correspond to the target hard disk (i.e., the second CPLD module 210 does not receive a corresponding interrupt signal when the NVMe hard disk is simulated to access the corresponding hard disk connector), it indicates that there is a problem with the code for interrupt detection in the second CPLD module 210 of the to-be-tested backboard 200, at which time interrupt exception information is generated and sent to the display module 120 for display to prompt relevant staff to modify the current interrupt detection code in the second CPLD module 210 and the like.

[0059] S104, if the first CPLD module detects that the interrupt signal corresponds to the target hard disk, the first CPLD module controls to end interrupt detection, and generates an I2C signal for controlling an indication module of the to-be-tested backboard, and sends the I2C signal to the second CPLD module through the first connection module and the second connection module based on the target I2C address.

[0060] In the embodiment, after receiving the interrupt signal, the first CPLD module 110 controls the display module 120 to display "NVMe 1 / 2 / 3 / 4... ADD Interrupt Pass" in turn until the interrupt verification of the last NVMe hard disk is completed. If in the interrupt verification process, if the first CPLD module 110 detects that the interrupt signal corresponds to the target hard disk (i.e., it indicates that the first CPLD module 110 receives a corresponding interrupt signal when the NVMe hard disk is simulated to access the corresponding hard disk connector), the first CPLD module 110 controls to end the interrupt detection of the second CPLD module 210, and generates an I2C signal for controlling the indication module 240 of the to-be-tested backboard 200, and sends the I2C signal to the second CPLD module 210 of the to-be-tested backboard 200 through the first connection module 130 of the debug tool 100 and the second connection module 230 of the to-be-tested backboard 200 in turn based on the target I2C address, so as to facilitate subsequent control of the target indication lamp on the indication module 240 through the I2C signal to simulate that the NVMe hard disk is in the OK, locate, error, and rebuild states in turn, thereby indicating the working state of the hard disk simulated to access the hard disk connection module 220. In addition, the display module 120 connected with the first CPLD module 110 also synchronously displays the state corresponding to the serial data stream of the current I2C signal in real time, i.e., "OK", "Locate", "Fault", and "Rebuild".

[0061] S105, the second CPLD module controls a state of the indication module of the to-be-tested backboard according to the SGPIO signal or the I2C signal, obtains a first state indication result or a second state indication result, and sends the first state indication result or the second state indication result to the first CPLD module.

[0062] In the embodiment, after receiving the SGPIO signal or the I2C signal, the second CPLD module 210 controls a target indicator lamp in the indication module 240 according to the SGPIO signal or the I2C signal, to obtain a first state indication result or a second state indication result of the target indicator lamp, and sends the first state indication result or the second state indication result to the first CPLD module 110 through the second connection module 230 and the second connection module 230, so as to determine whether the first state indication result is consistent with a first preset state or whether the second state indication result is consistent with a second preset state.

[0063] In an embodiment, the second CPLD module 210 controls a state of the indication module 240 of the to-be-tested backboard 200 according to the SGPIO signal or the I2C signal, to obtain a first state indication result or a second state indication result, including:

[0064] The second CPLD module 210 parses the SGPIO signal or the I2C signal to obtain a first parsing result or a second parsing result.

[0065] The second CPLD module 210 controls a state of a target indicator lamp in the indication module 240 according to the first parsing result or the second parsing result, to obtain a first state indication result or a second state indication result.

[0066] In the embodiment, after receiving the SGPIO signal or the I2C signal, the second CPLD module 210 specifically first parses the SGPIO signal or the I2C signal to obtain a first parsing result corresponding to the SGPIO signal or a second parsing result corresponding to the I2C signal, and controls states of target indicator lamps in the indication module 240 equal in number to the target hard disks according to the first parsing result or the second parsing result to obtain a first state indication result or a second state indication result of the target indicator lamps, so that the first CPLD module 110 subsequently compares the first state indication result with a first preset state or the second state indication result with a second preset state to confirm whether they are consistent, thereby realizing the function debugging of the firmware of the second CPLD module 210.

[0067] S106, if the first CPLD module detects that the first state indication result is consistent with the first preset state or the second state indication result is consistent with the second preset state, the first CPLD module controls to end the debugging of the to-be-tested backboard.

[0068] In the embodiment, after obtaining the first state indication result or the second state indication result, the first CPLD module 110 detects whether the first state indication result is consistent with the first preset state or the second state indication result is consistent with the second preset state, wherein if the first CPLD module 110 detects that the first state indication result is consistent with the first preset state or the second state indication result is consistent with the second preset state, it indicates that the firmware of the second CPLD module 210 of the to-be-tested backboard 200 is normal, and at this time, the first CPLD module 110 controls to end the debugging of the to-be-tested backboard 200 to end the debugging process.

[0069] In an embodiment, after obtaining the first state indication result or the second state indication result, the method further includes:

[0070] If the first CPLD module 110 detects that the first state indication result is inconsistent with the first preset state or the second state indication result is inconsistent with the second preset state, the first CPLD module 110 generates a light abnormality prompt information.

[0071] In the embodiment, after receiving the first state indication result or the second state indication result, the first CPLD module 110 further comprises: if the first CPLD module 110 detects that the first state indication result is inconsistent with the first preset state or the second state indication result is inconsistent with the second preset state, it indicates that the firmware about the lighting operation in the second CPLD module 210 of the to-be-tested backboard 200 is abnormal, at this time, the lighting abnormal prompt information is generated and sent to the display module 120 for display, so that the relevant staff can re-change, burn and verify the code of the second CPLD module 210 based on the lighting abnormal prompt information, and then complete the final debugging of the code of the second CPLD module 210, so as to avoid the problem that the to-be-tested backboard 200 and the mainboard are assembled.

[0072] The debugging method of the liquid-cooled hard disk backboard provided by the embodiment of the application can realize the functional debugging of the firmware of the to-be-tested backboard before the to-be-tested backboard and the mainboard are assembled and put into the cooling liquid, supports the SGPIO, Legacy VPP and NPEM modes, and avoids the problem that the to-be-tested backboard and the mainboard are assembled, thereby improving the production efficiency.

[0073] The above merely describes the specific embodiments of the application, but the protection scope of the application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the application, and these modifications or replacements should be covered in the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A debugging jig for liquid-cooled hard disk backplanes, characterized by, The debugging jig applied to a to-be-tested backboard comprises a first CPLD module, a display module, a first connecting module, a key module and a cable module; the display module, the first connecting module, the key module and the cable module are connected with the first CPLD module; the first CPLD module is connected with a hard disk connecting module of the to-be-tested backboard through the cable module; the first CPLD module is connected with a second CPLD module of the to-be-tested backboard through the first connecting module and a second connecting module of the to-be-tested backboard, and the second CPLD module is connected with an indicating module of the to-be-tested backboard; When the first CPLD module determines that a to-be-tested mode is an SGPIO mode through the display module and the key module, the first CPLD module is used for generating a first analog signal for simulating a hard disk accessing the hard disk connecting module, and is also used for generating an SGPIO signal for controlling the indicating module of the to-be-tested backboard; when the first CPLD module determines that the to-be-tested mode is a Legacy VPP mode or an NPEM mode through the display module and the key module, the first CPLD module is used for reading a target I2C address of the to-be-tested backboard, is also used for generating a second analog signal for simulating a hard disk accessing the hard disk connecting module, is also used for receiving and detecting an interrupt signal sent by the second CPLD module, and is also used for generating an I2C signal for controlling the indicating module of the to-be-tested backboard.

2. The debug tool for liquid-cooled hard disk backplane according to claim 1, wherein, The first connecting module comprises a first connector, a second connector, a third connector and a fourth connector; the first connector is connected with the first CPLD module through an SGPIO bus; the second connector is connected with the first CPLD module through an I2C bus; the third connector is connected with the first CPLD module through the I2C bus; and the fourth connector is connected with the first CPLD module through the I2C bus.

3. The debug tool for liquid-cooled hard disk backplane according to claim 1, wherein, The key module comprises a reset key, a function selection key and a function confirmation key; the reset key, the function selection key and the function confirmation key are connected with the first CPLD module.

4. The debug tool for liquid-cooled hard disk backplane according to claim 1, wherein, The cable module comprises a first cable piece, a second cable piece, a third cable piece and a fourth cable piece; the first cable piece, the second cable piece, the third cable piece and the fourth cable piece are connected with the first CPLD module.

5. A debugging system of a liquid-cooled hard disk backplane, characterized in that, The debugging jig comprising the liquid-cooled hard disk backboard according to any one of claims 1-4 further comprises a to-be-tested backboard; a hard disk connecting module of the to-be-tested backboard is connected with a cable module in the debugging jig; a second connecting module of the to-be-tested backboard is connected with a first connecting module in the debugging jig; the second connecting module is further connected with a second CPLD module of the to-be-tested backboard; and the second CPLD module is connected with an indicating module of the to-be-tested backboard.

6. The liquid-cooled hard disk backplane commissioning system of claim 5, wherein, The second connection module comprises a fifth connector, a sixth connector, a seventh connector and an eighth connector, the fifth connector is connected with the second CPLD module through an SGPIO bus, the sixth connector is connected with the second CPLD module through an I2C bus, the seventh connector is connected with the second CPLD module through an I2C bus, and the eighth connector is connected with the second CPLD module, and is also connected with a field replaceable unit and a temperature sensor.

7. A method for debugging a liquid-cooled hard disk backplane, characterized in that: The debugging system applied to the liquid-cooled hard disk backboard of any one of claims 5-6 comprises: When the first CPLD module of the debugging jig receives an information selection instruction through the display module and the key module of the debugging jig, target information corresponding to the backboard to be tested is selected from preset information according to the information selection instruction; wherein the target information comprises a target hard disk to be debugged mode and the number of target hard disks, and the target hard disk to be debugged mode comprises an SGPIO mode, a Legacy VPP mode and an NPEM mode; If the first CPLD module determines that the target hard disk to be debugged mode is the SGPIO mode, a first simulation signal is generated, and the first simulation signal is sent to the hard disk connector in the hard disk connection module of the backboard to be tested through the first target cable piece in the cable module of the debugging jig which is equal to the number of target hard disks, and an SGPIO signal for controlling the indication module of the backboard to be tested is generated, and the SGPIO signal is sent to the second CPLD module of the backboard to be tested through the first connection module of the debugging jig and the second connection module of the backboard to be tested; If the first CPLD module determines that the target hard disk to be debugged mode is the Legacy VPP or NPEM mode, a target I2C address is read from a preset I2C address, a second simulation signal is generated, and the second simulation signal is sent to the second target hard disk connector in the hard disk connection module through the second target cable piece in the cable module which is equal to the number of target hard disks, and an interrupt signal sent by the second CPLD module is received and detected through the first connection module and the second connection module; If the first CPLD module detects that the interrupt signal corresponds to the target hard disk one by one, the end of interrupt detection is controlled, an I2C signal for controlling the indication module of the backboard to be tested is generated, and the I2C signal is sent to the second CPLD module through the first connection module and the second connection module based on the target I2C address; The second CPLD module controls the state of the indication module of the backboard to be tested according to the SGPIO signal or the I2C signal, obtains a first state indication result or a second state indication result, and sends the first state indication result or the second state indication result to the first CPLD module; The first CPLD module controls to end the debugging of the to-be-tested backboard if the first state indication result is consistent with a first preset state or the second state indication result is consistent with a second preset state.

8. The method of claim 7, wherein, The second CPLD module controls the state of the indication module of the to-be-tested backboard according to the SGPIO signal or the I2C signal, and obtains a first state indication result or a second state indication result, including: The second CPLD module analyzes the SGPIO signal or the I2C signal, and obtains a first analysis result or a second analysis result. The second CPLD module controls the state of target indication lamps equal in number to the target hard disks in the indication module according to the first analysis result or the second analysis result, and obtains a first state indication result or a second state indication result.

9. The method of claim 7, wherein, After receiving and detecting the interrupt signal sent by the second CPLD module through the first connection module and the second connection module, the method further includes: The first CPLD module generates interrupt exception information if the interrupt signal does not correspond to the target hard disks one by one.

10. The method of claim 7, wherein, After obtaining the first state indication result or the second state indication result, the method further includes: The first CPLD module generates a light-on exception prompt information if the first state indication result is inconsistent with the first preset state or the second state indication result is inconsistent with the second preset state.

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