Method and apparatus for automating testing of spi peripherals

Abstract

The application relates to a method and device for automatically testing an SPI peripheral, based on a designed host computer and slave computer test architecture and test mode, high flexibility of the test, various SPI signals can be flexibly generated according to requirements, the test is more comprehensive, random data is supported to better verify the pressure resistance and robustness of the SPI peripheral, potential boundary conditions and abnormal conditions can be found, and the stability and reliability of a vehicle-mounted system are ensured, the application has a wide application range and strong reusability, an MCU of an SPI (host computer / slave computer) device can be tested, the test operation is simple, the test efficiency is high, the cost is low, and a single-chip can be self-tested to reduce interference.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of peripheral testing, and relates to a method and device for automatically testing SPI peripherals. BACKGROUND

[0002] The technical development status of SPI (Serial Peripheral Interface) in the vehicle-mounted field is characterized by high reliability, high-speed transmission, support for multiple channels, low power consumption, safety, encryption, standardization and compatibility. In modern vehicle-mounted systems, SPI is not only used for high-speed data transmission of sensor networks and camera systems, but also supports real-time monitoring and control of power systems and vehicle-mounted entertainment systems. In practical applications, SPI is widely used in vehicle-mounted sensor networks such as temperature sensors, pressure sensors and acceleration sensors to realize high-speed and reliable transmission of sensor data; in multi-camera systems, SPI communication is used to transmit image data to support real-time transmission of high-definition video streams; in vehicle-mounted entertainment systems, SPI communication is used to transmit audio and video data to support high-quality multimedia experience; in power systems, SPI communication is used to transmit data of key components such as engines and gearboxes to support real-time monitoring and control.

[0003] In order to test and verify the functions of SPI, the traditional testing method is: 1. The actual vehicle body SPI sensor is used as a test input, but a SPI sensor can only cover one scene, and as a peripheral test, it needs to cover various SPI functions and modes, and the test types are complex and diverse, so it cannot meet the testing requirements and can only be used as a sampling test. 2. Purchase a simulation device for simulation testing, which can simulate communication in various modes and cover all functions of SPI peripherals; but this simulation device can only send one kind of data repeatedly at a time, and cannot simulate the actual configuration change situation, and if you need to change the test mode, you also need to re-set and send it, so this testing method can cover various mode protocols, but cannot verify the real data change situation and requires a lot of repeated confirmation work by manpower, which is time-consuming and laborious. SUMMARY

[0004] In view of the problems in the above-mentioned traditional technology, the application provides a method and device for automatically testing SPI peripherals, which can efficiently and automatically realize the testing of SPI peripherals.

[0005] In order to achieve the above-mentioned purpose, the embodiments of the application adopt the following technical solutions:

[0006] On the one hand, a method for automatically testing SPI peripherals is provided, comprising the steps of:

[0007] The host computer sends configuration parameters to an MCU where the SPI peripheral to be tested is located; the configuration parameters include the transmission rate of the SPI, the data length, and a test mode;

[0008] An interface between the SPI peripheral to be tested and an analog SPI device on the MCU is connected, and the MCU initializes the SPI peripheral to be tested and the analog SPI device according to the configuration parameters and configures the clock frequency of a high-precision timer in the MCU; when the test mode is a host mode, the SPI peripheral to be tested is an SPI host, and the analog SPI device is an SPI slave;

[0009] The MCU lowers a chip select line through a GPIO operation register to make the SPI peripheral to be tested and the analog SPI device start working; the high-precision timer is configured as a PWM mode;

[0010] The SPI peripheral to be tested transmits the sending data of this test to the analog SPI device through a data line MOSI; the analog SPI device reads each bit in the data line MOSI at a rising edge of a PWM interrupt, and starts to receive the next frame of sending data after a frame of data is satisfied;

[0011] The analog SPI device writes the data MSB to be sent to the SPI peripheral to be tested to a data line MISO at a falling edge of the PWM interrupt;

[0012] The SPI peripheral to be tested judges that the transmission ends when the remaining bytes of the sending data are 0 and performs data verification;

[0013] If the data verification result is correct, a test pass log of this test is generated, otherwise, a test error log of this test is generated.

[0014] On the other hand, an apparatus for automatically testing an SPI peripheral is also provided, including a host computer and an MCU as a lower computer, the MCU including an SPI peripheral to be tested and an analog SPI device;

[0015] The host computer is used to send configuration parameters to the MCU; the configuration parameters include the transmission rate of the SPI, the data length, and a test mode;

[0016] After the interface between the SPI peripheral to be tested and the analog SPI device on the MCU is connected, the MCU initializes the SPI peripheral to be tested and the analog SPI device according to the configuration parameters and configures the clock frequency of a high-precision timer in the MCU; when the test mode is a host mode, the SPI peripheral to be tested is an SPI host, and the analog SPI device is an SPI slave;

[0017] The MCU lowers a chip select line through a GPIO operation register to make the SPI peripheral to be tested and the analog SPI device start working; the high-precision timer is configured as a PWM mode;

[0018] The SPI peripheral to be tested transmits the sending data of this test to the analog SPI device through the data line MOSI, the analog SPI device reads each bit in the data line MOSI at the rising edge of the PWM interrupt, and starts the reception of the next frame of sending data after a frame of data is satisfied; the analog SPI device writes the data MSB to be sent to the SPI peripheral to be tested into the data line MISO at the falling edge of the PWM interrupt;

[0019] When the SPI peripheral to be tested judges that the remaining bytes of the sending data are 0, the transmission is ended and data checking is performed, if the data checking result is correct, the test pass log of this test is generated, otherwise the test error log of this test is generated.

[0020] One of the above technical solutions has the following advantages and beneficial effects:

[0021] The above method and device for automatically testing the SPI peripheral are based on the designed host computer and lower computer test architecture and test mode, have high flexibility in testing, can customize parameters according to requirements, and can flexibly generate various SPI signals; the testing is more comprehensive, supports random data to better verify the pressure resistance and robustness of the SPI peripheral, can also find potential boundary conditions and abnormal conditions, and ensures the stability and reliability of the vehicle-mounted system; the use range is wide and the reusability is strong, the MCUs of the SPI (host / slave) devices can be tested; the testing operation is simple, the testing efficiency is high, and the cost is low, and a single chip can also be self-tested to reduce interference. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description only illustrate some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0023] Figure 1 It is a flowchart of the method for automatically testing the SPI peripheral in an embodiment;

[0024] Figure 2 It is a test flowchart of the SPI host mode in an embodiment;

[0025] Figure 3 It is a test flowchart of the SPI slave mode in an embodiment;

[0026] Figure 4 It is a general test flowchart of the method for automatically testing the SPI peripheral in an embodiment;

[0027] Figure 5A schematic diagram of a module structure of an apparatus for automating testing of SPI peripherals in one embodiment of the application;

[0028] Figure 6 A schematic diagram of a module structure of an apparatus for automating testing of SPI peripherals in another embodiment of the application. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application.

[0030] It should be noted that the reference herein to "embodiments" means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase is exhibited at various places in the specification does not necessarily mean the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0031] The embodiments of the present application will be described in detail below with reference to the accompanying drawings of the embodiments of the present application.

[0032] High reliability is a key feature of SPI in vehicle systems, and there is a large amount of electromagnetic interference in the vehicle environment, so modern SPI design adopts differential signal transmission, shielded cable and signal integrity design to ensure the reliability of data transmission. At the same time, some vehicle systems also use redundant SPI communication paths, so that even if one SPI communication path fails, the other SPI communication path can still work, thereby further improving the reliability of the vehicle system.

[0033] High-speed transmission is another important feature of SPI in vehicle systems. As the demand for data transmission rate in vehicle systems continues to increase, the speed of modern SPI communication can reach tens of Mbps or even higher. This feature is particularly important in intelligent driving and other real-time control systems. The low latency feature makes SPI perform well in these systems, enabling real-time transmission of large amounts of data and supporting complex algorithms and decisions. In terms of multi-channel support, a SPI master device (SPI host) in modern vehicle systems can connect multiple slave devices (SPI slaves), achieving efficient data transmission through multiplexing technology. This is very useful in sensor networks, multi-camera systems, and other multi-device communication scenarios. SPI interfaces support multiple configuration modes, such as single-wire mode, double-wire mode, and four-wire mode, which can be flexibly selected according to actual needs, improving the flexibility and scalability of the system.

[0034] In addition, low power consumption is also an important advantage of SPI in vehicle systems. Vehicle systems have strict requirements for power consumption. Modern SPI designs use various energy-saving technologies, such as low-power mode, automatic sleep and wake-up mechanisms, to reduce power consumption. SPI communication modules can enter a low-power state when inactive, reducing energy consumption, which is particularly important for battery-powered devices. In terms of security and encryption, modern SPI communication supports data encryption technologies such as AES (Advanced Encryption Standard) encryption to ensure data security during transmission. At the same time, SPI communication supports security authentication mechanisms to ensure that only authenticated devices can communicate, preventing unauthorized access and protecting the data security of vehicle systems.

[0035] Standardization and compatibility are also important features of SPI in vehicle systems. SPI communication follows standard protocol specifications to ensure interoperability between devices from different manufacturers. Vehicle systems undergo strict compatibility testing during design and production to ensure the stability and reliability of SPI communication, which is very important in vehicle systems that are usually composed of multiple components from different suppliers. Standardization and compatibility ensure seamless communication between components.

[0036] With the continuous development of real-world needs and technology, SPI communication technology will continue to evolve in vehicle systems. Higher integration will be the future trend, and SPI communication will be combined with other communication technologies (such as CAN bus, LIN communication, and Ethernet) to form more complex communication networks. In addition, with the development of artificial intelligence and machine learning, SPI communication will play a greater role in the intelligentization of vehicle systems, supporting more complex algorithms and decisions. Wireless SPI communication technology may also be introduced to enable more flexible communication methods, further improving the performance and reliability of vehicle systems.

[0037] In one embodiment, as shown in Figure 1 A method for automatically testing an SPI peripheral device can include the following processing steps S10-S22:

[0038] S10, a host computer sends configuration parameters to an MCU where the SPI peripheral device to be tested is located; the configuration parameters include the transmission rate, data length and test mode of the SPI;

[0039] S12, connect the interface between the SPI peripheral device to be tested and the analog SPI device on the MCU, initialize the SPI peripheral device to be tested and the analog SPI device according to the configuration parameters on the MCU, and configure the clock frequency of the high-precision timer in the MCU; when the test mode is the host mode, the SPI peripheral device to be tested is the SPI host and the analog SPI device is the SPI slave;

[0040] S14, the MCU pulls down the chip select line through the GPIO operation register to make the SPI peripheral device to be tested and the analog SPI device start working; the high-precision timer is configured as the PWM mode;

[0041] S16, the SPI peripheral device to be tested transmits the sending data of this test to the analog SPI device through the data line MOSI; the analog SPI device reads each bit in the data line MOSI at the rising edge of the PWM interrupt, and starts the reception of the next frame of sending data after a frame of data is satisfied;

[0042] S18, the analog SPI device writes the data MSB to be sent to the SPI peripheral device to be tested to the data line MISO at the falling edge of the PWM interrupt;

[0043] S20, the SPI peripheral device to be tested judges the transmission to be ended and performs data verification when the remaining bytes of the sending data are 0;

[0044] S22, if the data verification result is correct, a test pass log of this test is generated, otherwise a test error log of this test is generated.

[0045] It can be understood that the host computer refers to the host computer APP application, which is used to set configuration parameters according to whether the to-be-tested SPI peripheral is in a test slave mode or a test master mode and the like. The configuration parameters can include transmission rate, data length, master / slave mode, clock polarity and clock phase and the like of SPI. After the configuration parameters are sent to the lower computer (i.e. MCU), the lower computer will initialize the to-be-tested SPI peripheral and the analog SPI device according to the configuration parameters, so as to prepare for the subsequent communication in the test process. As the MCU of the lower computer, the analog SPI device and the to-be-tested SPI peripheral are arranged thereon. The analog SPI device and the to-be-tested SPI peripheral both have master and slave modes. When the to-be-tested SPI peripheral as the to-be-tested device is tested as a slave, the analog SPI device is used as an SPI master. When the to-be-tested SPI peripheral is tested as an SPI master, the analog SPI device is used as an SPI slave.

[0046] In the test master mode when the to-be-tested SPI peripheral is an SPI master, the PWM (Pulse Width Modulation) mode of the high-precision timer (used to determine the clock of the analog SPI device) in the lower computer is used as the clock line, the GPIO peripheral of the lower computer is used to flip the level to simulate the data line (such as MISO (Master In Slave OUT) and MOSI (Master Out Slave In)) and the chip selection line (CS) shared by the to-be-tested SPI peripheral and the analog SPI device, so as to be connected to the to-be-tested SPI peripheral. The clock frequency of the high-precision timer in the lower computer is the transmission rate of SPI, which avoids the problem that the rate of GPIO flip level is uncontrollable in the test code execution.

[0047] In addition, the length of the data frame of the transmitted data can be selected by detecting the overflow number of the high-precision timer, and the data check mode used in the test process can also be selected, such as parity check or CRC check.

[0048] The above method for automatically testing SPI peripherals has high flexibility in testing based on the designed host computer and lower computer test architecture and test mode. Various SPI signals can be flexibly generated according to the requirements. The test is more comprehensive, supports random data to better verify the pressure resistance and robustness of the SPI peripheral, and can also find potential boundary conditions and abnormal conditions to ensure the stability and reliability of the vehicle-mounted system. The method has a wide range of use and strong reusability. The MCU of the SPI (master / slave) device can be tested. The test operation is simple, the test efficiency is high, and the cost is low. The single chip can also be self-tested to reduce interference.

[0049] Specifically, the host computer configures parameters: the host computer selects the transmission rate, data length, master / slave mode, clock polarity and clock phase of the SPI to be tested, and then sends the configuration parameters to the slave computer through the communication interface. During testing, the host computer can also send data as defined by the host computer, or the slave computer can generate random transmission data.

[0050] When the SPI peripheral to be tested performs host mode testing as an SPI host, first, connect the SPI interface of the SPI peripheral to be tested on the MCU of the vehicle-mounted system to the corresponding analog SPI interface of the analog SPI device (which acts as an SPI slave at this time) and ensure that the interface line communication is normal. Then, the slave computer configures the clock frequency of the high-precision timer (i.e., the transmission rate of the SPI host) and other parameters according to the configuration parameters issued by the host computer.

[0051] Further, the transmission data can be transmission data provided after the host computer is customized.

[0052] Further, the transmission data can also be transmission data generated by the MCU using a random number generation algorithm.

[0053] It can be understood that if the host computer provides transmission data, the slave computer uses the transmission data specified after the host computer is customized; if the host computer does not provide transmission data, the slave computer generates random data as transmission data using the existing random number generation algorithm (random number algorithm code), and calculates the check code according to the selected check algorithm (such as CRC-16 / IBM) to pack the check code into the data frame of the transmission data.

[0054] After the analog SPI device is initialized and the transmission data is verified, the MCU starts working by pulling down the chip select line (chip select level) through the GPIO operation register, configures the high-precision timer to PWM mode to determine the length of each transmission period and the high-low level ratio, counts the number of interrupt triggers in the PWM interrupt, flips and reads the corresponding data lines MISO and MOSI in the interrupt function every time the PWM interrupt is triggered, sets the parameter in the PWM interrupt to 1 every time a bit is transmitted, and continues until the data frame of the transmission data is sent.

[0055] After the SPI peripheral to be tested receives the data, it judges whether the current reception is normal through the data register and the state register responsible for receiving. If the current reception is normal, data verification is performed, the received data should be consistent with the transmission data, there is no error state position and the check code is the same. If it is an error mode SPI waveform of transmission, the received data should be incorrect and the corresponding error state should be positioned.

[0056] The host mode transmission process of the SPI peripheral to be tested is as follows Figure 2As shown, after the chip select line starts to work, the SPI host sends data written in its own SPI serial register to the SPI slave through the data line MOSI, and the SPI slave reads each bit of the data line MOSI at the rising edge of the PWM interrupt, and starts to receive the next frame of data after a frame of data is received; and the SPI slave writes the data MSB (Most Significant Byte, high-order byte of data) to be sent to the SPI host to the data line MISO at the falling edge of the PWM interrupt. The SPI host judges whether the remaining bytes of the transmitted data are 0, if yes, the transmission is ended, otherwise the transmission is continued.

[0057] In one embodiment, when the test mode is the slave mode, the SPI device to be tested is the SPI slave, and the simulation SPI device is the SPI host. After the SPI device to be tested and the simulation SPI device are initialized, the above method for automatically testing the SPI device can further include the following steps:

[0058] The simulation SPI device enables the clock signal interrupt when the chip select line CS interrupt signal state is a valid edge, and the SPI device to be tested fills the MSB of the transmitted data of this test to the data line MISO;

[0059] At the falling edge of the clock signal interrupt, the SPI device to be tested reads each bit in the data line MOSI and shifts and saves it until a data frame transmission is ended;

[0060] At the rising edge of the clock signal interrupt, the SPI device to be tested writes the MSB of the transmitted data to be sent to the simulation SPI device to the data line MISO until a data frame transmission is ended;

[0061] The simulation SPI device performs data verification, and if the data verification result is correct, a test pass log of this test is generated, otherwise a test error log of this test is generated.

[0062] It can be understood that in the test slave mode when the SPI device to be tested is the SPI slave, the chip select line (CS) pin GPIO interrupt (wherein the chip select line CS and the high-precision timer CLK both use the GPIO interrupt) can be used to judge the reception and start; accordingly, the I2S mode test of the SPI device to be tested is the same, only the format of the data frame is different, which will not be expanded here. In combination with the host computer, all test implementation details are processed by the lower computer, and the host computer is used to open the test option interface.

[0063] Specifically, when the to-be-tested SPI peripheral device as a slave performs a slave mode test, the SPI slave mode first waits for a change in the signal state of the chip select line, confirms that the SPI slave is selected, and then opens the clock IO interrupt. After that, the SPI slave transmits and receives data according to the configuration parameters sent by the host computer in the clock IO interrupt until the data transmission process is completed. The data received by the SPI slave is checked (such as CRC check), and whether the transmitted data is correct and the check result is correct is verified.

[0064] As shown in Figure 3 The transmission process in the SPI slave mode is shown in the figure. The MCU configures (such as initialization parameters and test mode) according to the configuration parameters sent by the host computer. When the chip select line CS interrupt signal state is invalid edge, the SPI device judges to clear the related flag and close the CLK (clock) signal interrupt. When the chip select line CS interrupt signal state is valid edge, the SPI device enables the CLK signal interrupt and fills the sending data MSB to the data line MISO. Then, the SPI device judges the edge of the CLK signal interrupt. If it is the falling edge of the CLK signal interrupt, the SPI device reads each bit of the data line MOSI, shifts and saves it until the end of a data frame. If it is the rising edge of the CLK signal interrupt, the SPI device writes the data MSB to be sent to the SPI host to the data line MISO until the end of a data frame. Finally, the transmission is completed after data check (such as CRC check).

[0065] As shown in Figure 4 The figure is a specific application flowchart of the method for automatically testing the SPI peripheral device.

[0066] In one embodiment, the method for automatically testing the SPI peripheral device described above can further include the following steps:

[0067] Viewing whether there is waveform error in the SPI protocol waveform transmitted between the to-be-tested SPI peripheral device and the simulated SPI device through an oscilloscope; the waveform error includes waveform distortion and frequency error;

[0068] If there is waveform error, report the waveform error to the host computer.

[0069] It can be understood that in the test host mode when the to-be-tested SPI peripheral device as a SPI host, a random number generation algorithm in the prior art can be used to generate sending data, simulate the SPI protocol waveform, access the to-be-tested SPI peripheral device, and judge whether the current test passes by judging whether the sending data matches the data received by the to-be-tested SPI peripheral device and whether the data check passes. In addition, in order to ensure that the SPI protocol waveform is normal, an oscilloscope can also be used to detect whether the simulated SPI protocol waveform is severely deformed.

[0070] In addition, when the check error occurs, whether the SPI protocol waveform is distorted or not, whether the output frequency (i.e. the frequency of the SPI protocol waveform) is correct, and whether the timing of the SPI protocol waveform is normal can be determined in sequence through the oscilloscope, and the waveform error of the check can be fed back to the host computer.

[0071] Compared with the prior art, the method for automatically testing the SPI peripheral device has high flexibility of testing, can customize parameters according to requirements, and flexibly generates various SPI signals; the testing is more comprehensive, supports random data to better verify the pressure resistance and robustness of the SPI peripheral device, and can find potential boundary conditions and abnormal conditions to ensure the stability and reliability of the vehicle-mounted system; the method has wide application range and strong reusability, and the MCU of the SPI (host / slave) device can be tested; the method has simple testing operation, high testing efficiency and low cost, and the single-chip can be self-tested to reduce interference; the oscilloscope can be externally connected for error checking and monitoring, and the problem can be located when an error occurs.

[0072] It should be understood that, although Figure 1 each step is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1 at least part of the steps of may include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0073] In one embodiment, as shown in Figure 5 , an apparatus 100 for automatically testing an SPI peripheral device is provided, which can include a host computer and an MCU as a lower computer, and the MCU includes a SPI peripheral device to be tested and a simulated SPI device. The host computer is configured to issue configuration parameters to the MCU; the configuration parameters include the transmission rate, data length and test mode of the SPI. After the interface between the SPI peripheral device to be tested and the simulated SPI device on the MCU is connected, the MCU initializes the SPI peripheral device to be tested and the simulated SPI device according to the configuration parameters, and configures the clock frequency of the high-precision timer in the MCU; when the test mode is the host mode, the SPI peripheral device to be tested is the SPI host, and the simulated SPI device is the SPI slave. The MCU lowers the chip select line through the GPIO operation register to make the SPI peripheral device to be tested and the simulated SPI device start working; the high-precision timer is configured as the PWM mode.

[0074] The SPI device under test transmits the sending data of this test to the analog SPI device through the data line MOSI. The analog SPI device reads each bit in the data line MOSI at the rising edge of the PWM interrupt, and starts to receive the sending data of the next frame after a frame of data is satisfied. The analog SPI device writes the data MSB to be sent to the SPI device under test to the data line MISO at the falling edge of the PWM interrupt. The SPI device under test judges the remaining bytes of the sending data to be 0, and the transmission is ended and the data is checked. If the data check result is correct, the test pass log of this test is generated, otherwise the test error log of this test is generated.

[0075] The device 100 for automatically testing the SPI device is based on the designed host computer and lower computer test architecture and test mode, has high flexibility in testing, can customize parameters according to requirements, and can flexibly generate various SPI signals; the test is more comprehensive, supports random data to better verify the pressure resistance and robustness of the SPI device, can also find potential boundary conditions and abnormal conditions, and ensures the stability and reliability of the vehicle-mounted system; the use range is wide and the reusability is strong, the MCUs of the SPI (host / slave) devices can be tested; the test operation is simple, the test efficiency is high, and the cost is low, and the single-chip can also be self-tested to reduce interference.

[0076] In one embodiment, when the test mode is the slave mode, the SPI device under test is the SPI slave, and the analog SPI device is the SPI host. After the SPI device under test and the analog SPI device are initialized, the analog SPI device enables the clock signal interrupt when the chip selection line CS interrupt signal state is valid edge. The SPI device under test fills the sending data MSB of this test to the data line MISO.

[0077] At the falling edge of the clock signal interrupt, the SPI device under test reads each bit in the data line MOSI and shifts and saves it until a data frame transmission is ended. At the rising edge of the clock signal interrupt, the SPI device under test writes the sending data MSB to be sent to the analog SPI device to the data line MISO until a data frame transmission is ended. The analog SPI device performs data checking. If the data check result is correct, the test pass log of this test is generated, otherwise the test error log of this test is generated.

[0078] In one embodiment, the sending data is the sending data provided after the host computer customizes.

[0079] In one embodiment, the sending data is the sending data generated by the MCU using a random number generation algorithm.

[0080] In one embodiment, the device 100 for automatically testing the SPI peripheral can further include an oscilloscope, which is used to check whether there is a waveform error in the SPI protocol waveform transmitted between the to-be-tested SPI peripheral and the simulated SPI device, and if so, report the waveform error to the host computer; the waveform error includes waveform distortion and frequency error. At this time, the system connection mode of the error checking test can be as shown in Figure 6

[0081] It can be understood that the specific limitations of the device 100 for automatically testing the SPI peripheral can refer to the corresponding limitations of the method for automatically testing the SPI peripheral described above, and will not be described here.

[0082] Each module in the device 100 for automatically testing the SPI peripheral described above can be realized by software, hardware, and a combination thereof, in whole or in part. The above-mentioned modules can be embedded in or independent of a device with data processing function in hardware form, or can be stored in the memory of the aforementioned device in software form, so that the processor can call and execute the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of test terminals in the art.

[0083] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, RDRAM) and interface dynamic random access memory (DRDRAM) and the like.

[0084] Each technical feature of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present disclosure.​

[0085] The above embodiments only express several implementation manners of the present application, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the protection scope of the present application. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method of automating testing of an SPI peripheral, the method comprising: The method comprises the steps of: issuing configuration parameters to an MCU where an SPI peripheral to be tested is located by a host computer; the configuration parameters include transmission rate, data length and test mode of the SPI; connecting an interface between the SPI peripheral to be tested and an analog SPI device on the MCU, initializing the SPI peripheral to be tested and the analog SPI device according to the configuration parameters on the MCU, and configuring a clock frequency of a high-precision timer in the MCU; when the test mode is a host mode, the SPI peripheral to be tested is an SPI host, and the analog SPI device is an SPI slave; the MCU lowers a chip select line by operating a GPIO register to make the SPI peripheral to be tested and the analog SPI device start working; the high-precision timer is configured as a PWM mode; the SPI peripheral to be tested transmits sending data of this test to the analog SPI device through a data line MOSI; the analog SPI device reads each bit in the data line MOSI at a rising edge of a PWM interrupt, and starts receiving sending data of the next frame after a frame of data is satisfied; the analog SPI device writes data MSB to be sent to the SPI peripheral to be tested to a data line MISO at a falling edge of the PWM interrupt; the SPI peripheral to be tested judges that transmission ends when remaining bytes of the sending data are 0 and performs data checking; if the data checking result is correct, a test pass log of this test is generated, otherwise a test error log of this test is generated.

2. The method of claim 1, wherein, when the test mode is a slave mode, the SPI peripheral to be tested is an SPI slave, and the analog SPI device is an SPI host; after the SPI peripheral to be tested and the analog SPI device are initialized, the method further comprises the steps of: the analog SPI device enables a clock signal interrupt when an interrupt signal state of a chip select line CS is a valid edge; the SPI peripheral to be tested fills sending data MSB of this test to a data line MISO; the SPI peripheral to be tested reads each bit in the data line MOSI and shifts and saves until a frame of data transmission ends at a falling edge of the clock signal interrupt; the SPI peripheral to be tested writes sending data MSB to be sent to the analog SPI device to the data line MISO until a frame of data transmission ends at a rising edge of the clock signal interrupt; the analog SPI device performs data checking; if the data checking result is correct, a test pass log of this test is generated, otherwise a test error log of this test is generated.

3. The method of claim 1 or 2, wherein, the sending data is sending data provided after being defined by the host computer.

4. The method of claim 1 or 2, wherein, the sending data is sending data generated by the MCU using a random number generation algorithm.

5. The method of claim 1, wherein, The method further comprises the steps of: checking whether there is waveform error in SPI protocol waveforms transmitted between the SPI peripheral to be tested and the analog SPI device by an oscilloscope; the waveform error includes waveform distortion and frequency error; if there is waveform error, the waveform error is reported to the host computer.

6. An apparatus for automating testing of SPI peripherals, the apparatus comprising: The application relates to a test device for an SPI peripheral device, comprising an upper computer and an MCU as a lower computer, wherein the MCU comprises the SPI peripheral device to be tested and an analog SPI device. The upper computer is used for issuing configuration parameters to the MCU; the configuration parameters comprise a transmission rate, data length and test mode of the SPI. After the interface connection between the SPI peripheral device to be tested and the analog SPI device on the MCU, the MCU initializes the SPI peripheral device to be tested and the analog SPI device according to the configuration parameters, and configures the clock frequency of a high-precision timer in the MCU; when the test mode is a host mode, the SPI peripheral device to be tested is an SPI host, and the analog SPI device is an SPI slave. The MCU starts the work of the SPI peripheral device to be tested and the analog SPI device by pulling down a chip select line through a GPIO operation register; and the high-precision timer is configured as a PWM mode. The SPI peripheral device to be tested transmits sending data of this test to the analog SPI device through a data line MOSI; the analog SPI device reads each bit in the data line MOSI at the rising edge of the PWM interrupt, and starts the reception of the next frame of sending data after one frame of data is satisfied; and the analog SPI device writes the data MSB to be sent to the SPI peripheral device to be tested into a data line MISO at the falling edge of the PWM interrupt. When the remaining bytes of the sending data are 0, the SPI peripheral device to be tested transmits the data and performs data checking; if the data checking result is correct, a test pass log of this test is generated, otherwise, a test error log of this test is generated.

7. The apparatus of claim 6, wherein, When the test mode is a slave mode, the SPI peripheral device to be tested is an SPI slave, and the analog SPI device is an SPI host. After the initialization of the SPI peripheral device to be tested and the analog SPI device, the analog SPI device enables the clock signal interrupt when the interrupt signal state of the chip select line CS is a valid edge; and the SPI peripheral device to be tested fills the sending data MSB of this test into the data line MISO. At the falling edge of the clock signal interrupt, the SPI peripheral device to be tested reads each bit in the data line MOSI and shifts and saves the bit until the transmission of one frame of data is completed; at the rising edge of the clock signal interrupt, the SPI peripheral device to be tested writes the sending data MSB to be sent to the analog SPI device into the data line MISO until the transmission of one frame of data is completed. The analog SPI device performs data checking; if the data checking result is correct, a test pass log of this test is generated, otherwise, a test error log of this test is generated.

8. The apparatus of claim 6 or 7, wherein, The sending data is sending data provided after the upper computer is customized.

9. The apparatus of claim 6 or 7, wherein, The sending data is sending data generated by the MCU by using a random number generation algorithm.

10. The apparatus of claim 6, wherein, The application further comprises an oscilloscope, which is used for checking whether there is waveform error in the SPI protocol waveform transmitted between the SPI peripheral device to be tested and the analog SPI device; if there is waveform error, the waveform error is reported to the upper computer. The waveform error comprises waveform distortion and frequency error.

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