Performance optimization method, system and device of PCIe link and medium

Abstract

The invention relates to the technical field of computers, and discloses a PCIe link performance optimization method, system and device and a medium. The method comprises the following steps: in response to initialization of target PCIe equipment, enabling an auto-negotiation mechanism of a corresponding equalization parameter; training a link where the target PCIe device is located based on an equalization parameter obtained by the auto-negotiation mechanism to obtain a training result of the link; judging whether to disable the auto-negotiation mechanism according to the training result; and in response to disabling of the auto-negotiation mechanism, training the link again based on the preset equalization parameter to enable the performance of the link to meet the target requirement. By means of the scheme, the problems of PCIe link speed reduction and bandwidth reduction caused by the fact that the PCIe equipment cannot normally conduct EQ auto-negotiation are solved, and it is guaranteed that the PCIe equipment can operate in a high-performance state.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a PCIe link performance optimization method, system, device and medium. Background Art

[0002] PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) devices play an important role in servers and are used to connect high-speed peripheral devices to computer systems (such as servers). PCIe Link is a data transmission channel in PCIE devices. A PCIe Link consists of a Downstream Port on the Host side, an Upstream Port on the device side, and the signal lines connecting them. The performance of PCIe Link is evaluated by two indicators: rate and bandwidth, and the performance of PCIe Link is limited by the capabilities of Downstream Port and Upstream Port. In order to ensure the high data transmission performance of PCIe Link, that is, the performance of PCIe Link is optimal, it is necessary to ensure the integrity of the link signal. For this purpose, the PCIe protocol defines the EQ (Equalization, PCIe link equalization parameter) parameter to optimize the transmission quality of the link signal. The EQ parameter is obtained through the auto-negotiation of Downstream port and Upstream port. However, in actual use, EQ auto-negotiation failures or unsatisfactory negotiation results are often encountered, resulting in the performance of PCIe Link being affected.

[0003] Therefore, it is urgent to propose a performance optimization method for PCIe links to solve the above defects. Summary of the invention

[0004] In view of this, the present invention proposes a performance optimization method, system, device and medium for a PCIe link, which solves the problem of PCIe link speed reduction and bandwidth reduction caused by the inability of PCIe devices to perform EQ self-negotiation normally, and ensures that the PCIe devices can operate in a high-performance state.

[0005] Based on the above purpose, an embodiment of the present invention provides a method for optimizing the performance of a PCIe link, which specifically includes the following steps: In response to the target PCIe device initialization, enabling a self-negotiation mechanism of its corresponding equalization parameters; Based on the equalization parameters obtained by the auto-negotiation mechanism, training the link where the target PCIe device is located to obtain a training result of the link; Determining whether to disable the auto-negotiation mechanism according to the training result; In response to disabling the auto-negotiation mechanism, the link is retrained based on preset equalization parameters so that the performance of the link reaches a target requirement.

[0006] In some implementations, the step of determining whether to disable the auto-negotiation mechanism according to the training result includes: Determining whether the performance of the link meets the target requirement according to the training result; In response to the performance of the link not meeting the target requirement, obtaining a preset whitelist; Determine whether the target PCIe device matches the preset whitelist; In response to the target PCIe device matching the preset whitelist, disabling the auto-negotiation mechanism.

[0007] In some implementations, the step of determining whether the target PCIe device matches the preset whitelist includes: Obtain a target identification array corresponding to the target PCIe device; Querying whether there is an identification array matching the target identification array in a preset whitelist; In response to the presence of an identification array matching the target identification array in the preset whitelist, it is determined that the target PCIe device matches the preset whitelist.

[0008] In some implementations, the step of determining whether the performance of the link meets the target requirement according to the training result includes: Determining a first link width and a first link speed according to the training result; Reading a register of a downlink device to determine a second link width and a second link speed corresponding to the downlink; Reading a register of an uplink device to determine a third link width and a third link speed corresponding to the uplink; Determine whether the first link width, the second link width, and the third link width satisfy a first preset condition, and determine whether the first link speed, the second link speed, and the third link speed satisfy a second preset condition; If the first link width, the second link width and the third link width satisfy a first preset condition and the first link speed, the second link speed and the third link speed satisfy a second preset condition, it is determined that the performance of the link meets the target requirement.

[0009] In some implementations, the step of determining whether the first link width, the second link width, and the third link width satisfy a first preset condition includes: comparing the second link width and the third link width to determine a minimum link width; Determining whether the first link width is greater than or equal to the minimum link width; In response to the first link width being greater than or equal to the minimum link width, it is determined that a first preset condition is satisfied among the first link width, the second link width, and the third link width.

[0010] In some implementations, the step of determining whether the first link speed, the second link speed, and the third link speed satisfy a second preset condition includes: comparing the second link speed and the third link speed to determine a minimum link speed therebetween; determining whether the first link speed is greater than or equal to the minimum link speed; In response to the first link speed being greater than or equal to the minimum link speed, it is determined that a second preset condition is satisfied among the first link speed, the second link speed, and the third link speed.

[0011] In some embodiments, the method further comprises: Acquire all first PCIe devices in the server that have a requirement to disable the auto-negotiation mechanism; Constructing a plurality of first identification arrays based on the device identification and the manufacturer identification of each of the first PCIe devices; The preset whitelist is generated based on all the first identification arrays.

[0012] Another aspect of the embodiment of the present invention further provides a PCIe link performance optimization system, including: An enabling unit configured to enable a self-negotiation mechanism of a corresponding equalization parameter in response to initialization of a target PCIe device; A training unit configured to train the link where the target PCIe device is located based on the equalization parameters obtained by the auto-negotiation mechanism to obtain a training result of the link; A judging unit, configured to judge whether to disable the auto-negotiation mechanism according to the training result; The optimization unit is configured to, in response to disabling the auto-negotiation mechanism, retrain the link based on preset equalization parameters so that the performance of the link reaches a target requirement.

[0013] According to another aspect of an embodiment of the present invention, a computer device is provided, comprising: at least one processor; and a memory, wherein the memory stores a computer program executable on the processor, and the computer program implements the steps of the above method when executed by the processor.

[0014] According to another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, which stores a computer program that implements the above method steps when executed by a processor.

[0015] The present invention has at least the following beneficial technical effects: the performance optimization method of the PCIe link of the present invention enables the EQ self-negotiation mechanism and starts link training in the PCIe device initialization stage, determines whether the performance of the PCIe link has reached the optimal state according to the training result, further controls the enabling and disabling states of the EQ self-negotiation mechanism of the PCIe device whose link has not reached the optimal state based on the training result and a preset whitelist, retrains the PCIe link with the disabled EQ self-negotiation mechanism so that its performance reaches the optimal state, solves the problem of PCIe link speed reduction and bandwidth reduction caused by the PCIe device being unable to perform EQ self-negotiation normally, and ensures that the PCIe device can operate in a high-performance state. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A block diagram of an embodiment of a method for optimizing the performance of a PCIe link provided by the present invention; Figure 2 A schematic diagram of an embodiment of the execution process of the PCIe link performance optimization method provided by the present invention; Figure 3 A schematic diagram of an embodiment of an execution code for determining whether a target PCIe device matches a preset whitelist provided by the present invention; Figure 4 A schematic diagram of an embodiment of creating a preset whitelist provided by the present invention; Figure 5 A schematic diagram of an embodiment of a PCIe link performance optimization system provided by the present invention; Figure 6 A schematic diagram of the structure of an embodiment of a computer device provided by the present invention; Figure 7 A schematic diagram of the structure of an embodiment of a computer-readable storage medium provided by the present invention. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0019] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.

[0020] PCIe Link consists of multiple Lanes. The rate of PCIe Link refers to the data transmission speed on a single Lane, and the width of PCIe Link refers to the number of Lanes that can perform data transmission simultaneously. The maximum rate and maximum bandwidth supported by PCIe Link are called Link capability. Generally, whether the rate and width of PCIe Link reach Link capability is used as the standard to evaluate whether the link performance reaches the optimal level. Linkcapability is limited by Downstream capability and Upstream capability. The maximum speed and maximum bandwidth supported by Downstream are called Downstream capability, and the maximum speed and maximum bandwidth supported by Upstream are called Upstream capability. Downstream refers to CPU (Central Processing Unit), and Upstream refers to external card.

[0021] In high-generation PCIe (such as Gen5), link signal integrity is particularly critical to ensure high data transmission performance. For this reason, the PCIe protocol defines EQ parameters to optimize the signal transmission quality of the link. During the initialization of the PCIe device, the Downstream port and the Upstream port will negotiate the best EQ parameters by sending Training Sequen to each other to adapt to the characteristics of the current PCIe Link. However, in actual applications, it is often encountered that EQ self-negotiation fails or the negotiated EQ parameters do not meet the PCIe signal integrity requirements, resulting in the performance of the PCIe Link failing to meet the Link capability standard. In the related art, to solve this problem, the PCIe protocol allows disabling the EQ self-negotiation mechanism and directly using the EQ parameters provided by the firmware. That is, the server firmware can disable the EQ self-negotiation mechanism by configuring registers to disable the EQ self-negotiation mechanism in the PCIe protocol. When training the PCIe Link, the PCIe device will skip the EQ self-negotiation step and use the default EQ parameters provided by the server firmware to ensure the stable operation of the PCIe Link. Although the method in the related art can solve the problem of EQ self-negotiation failure to a certain extent, it has great limitations. As mentioned above, the EQ self-negotiation mechanism is confidentially related to the Downstream port and the Upstream port. When a server is configured with multiple external cards of different models, the requirements of the external cards of different models for the EQ self-negotiation mechanism are different, that is, some models of external cards may want to enable the EQ self-negotiation mechanism to self-negotiate EQ parameters through PCIe devices, while other models of external cards may want to disable the EQ self-negotiation mechanism to use the default EQ parameters. Therefore, the single firmware configuration method in the related art cannot meet the needs of adjusting the EQ self-negotiation mechanism for each external card separately.

[0022] Based on the above defects, the first aspect of the embodiment of the present invention proposes a performance optimization method for PCIe link, which solves the problem that when configuring certain external cards on the PCIe slot of the server, the optimal EQ parameters cannot be obtained through the self-negotiation mechanism of the PCIe hardware, thereby affecting the PCIe performance. Figure 1 As shown, the performance optimization method of the PCIe link specifically includes the following steps: Step S100, in response to the target PCIe device being initialized, enabling a self-negotiation mechanism of its corresponding equalization parameters; Step S200, based on the equalization parameters obtained by the self-negotiation mechanism, the link where the target PCIe device is located is trained to obtain a training result of the link; Step S300, judging whether to disable the auto-negotiation mechanism according to the training result; Step S400 , in response to disabling the auto-negotiation mechanism, retraining the link based on preset equalization parameters so that the performance of the link reaches the target requirement.

[0023] In some implementations, the target PCIe device is any one of the multiple PCIe devices in the server that needs to be optimized for performance. The preset equalization parameters are EQ parameters pre-configured in the server firmware, which can be obtained through simulation or actual measurement. Figure 2 As shown in the figure, when PCIe is initialized, the EQ auto-negotiation mechanism is enabled and Link training is started. Based on the training results of the link and the preset whitelist, it is dynamically determined whether the current PCIe link performance meets the Link capability requirements, so as to decide whether to disable the EQ auto-negotiation mechanism and re-perform link training.

[0024] The PCIe link performance optimization method of the present invention enables the EQ self-negotiation mechanism and starts link training in the PCIe device initialization stage, determines whether the performance of the PCIe link has reached the optimal state according to the training result, further controls the enabling and disabling states of the EQ self-negotiation mechanism of the PCIe device whose link has not reached the optimal state based on the training result and a preset white list, and retrains the PCIe link with the disabled EQ self-negotiation mechanism so that its performance reaches the optimal state, thereby solving the problem of PCIe link speed reduction and bandwidth reduction caused by the PCIe device being unable to perform EQ self-negotiation normally, and ensuring that the PCIe device can operate in a high-performance state.

[0025] In some embodiments, the step of determining whether to disable the auto-negotiation mechanism based on the training results includes: determining whether the performance of the link meets the target requirements based on the training results; in response to the performance of the link not meeting the target requirements, obtaining a preset whitelist; determining whether the target PCIe device matches the preset whitelist; in response to the target PCIe device matching the preset whitelist, disabling the auto-negotiation mechanism.

[0026] In some embodiments, the step of determining whether the target PCIe device matches a preset whitelist includes: obtaining a target identification array corresponding to the target PCIe device; querying whether there is an identification array matching the target identification array in the preset whitelist; and in response to the presence of an identification array matching the target identification array in the preset whitelist, determining that the target PCIe device matches the preset whitelist.

[0027] In some embodiments, Figure 3The figure shows a schematic diagram of an embodiment of the execution code for determining whether the target PCIe device matches the preset whitelist provided by the present invention. After reading the Device ID and Vendor ID of the PCIe device, the preset whitelist is traversed to query whether the Device ID and Vendor ID exist in the preset whitelist. If not, the process ends; if so, the EQ self-negotiation mechanism of the PCIe device is disabled and Link training is restarted. Taking the Power server as an example, the self-negotiation mechanism of the PCIe device is disabled by setting the 4th and 5th bits of the PHB_PCIE_DLP_CTL register (address 0x1A78).

[0028] The PCIe link performance optimization method of the present invention can dynamically disable the EQ self-negotiation mechanism according to the PCIe device and the preset white list to optimize the link performance when the performance of the PCIe Link cannot meet the Linkcapability standard.

[0029] In some embodiments, the step of determining whether the performance of the link meets the target requirements based on the training results includes: determining the first link width and the first link speed based on the training results; reading the register of the downlink device to determine the second link width and the second link speed corresponding to the downlink; reading the register of the uplink device to determine the third link width and the third link speed corresponding to the uplink; determining whether the first link width, the second link width and the third link width meet the first preset condition, and determining whether the first link speed, the second link speed and the third link speed meet the second preset condition; if the first link width, the second link width and the third link width meet the first preset condition and the first link speed, the second link speed and the third link speed meet the second preset condition, it is determined that the performance of the link meets the target requirements.

[0030] In some embodiments, the step of determining whether the first link width, the second link width, and the third link width satisfy a first preset condition includes: comparing the second link width and the third link width to determine the minimum link width; determining whether the first link width is greater than or equal to the minimum link width; in response to the first link width being greater than or equal to the minimum link width, determining that the first link width, the second link width, and the third link width satisfy the first preset condition.

[0031] In some embodiments, the step of determining whether the second preset condition is satisfied among the first link speed, the second link speed, and the third link speed includes: comparing the second link speed and the third link speed to determine the minimum link speed therebetween; determining whether the first link speed is greater than or equal to the minimum link speed; and in response to the first link speed being greater than or equal to the minimum link speed, determining that the second preset condition is satisfied among the first link speed, the second link speed, and the third link speed.

[0032] In some implementations, after Link training is completed, the training results are read to determine whether the performance of the PCIe Link meets the Link capability requirements. Taking the Power server as an example, the PHB_PCIE_DLP_TRAIN_CTL register (address 0x1A40) is read to obtain the Link width (link bandwidth) as bits 30-35, and the Link speed (link speed) as bits 36-39. Read the PCICAP_EXP_LCAP PCIe Capability register (address 0x0C) of the Downstream, and obtain the maximum link speed of the Downstream as bits 0-3, and the maximum link bandwidth as bits 4-bit9. Read the PCICAP_EXP_LCAPP PCIe Capability register (address 0x0C) of the Upstream, and obtain the maximum link speed of the Upstream as bits 0-3, and the maximum link bandwidth as bits 4-bit9. If the Link width is greater than or equal to the minimum of the maximum link bandwidths corresponding to the Downstream and Upstream, respectively, and the Link speed is greater than or equal to the minimum of the maximum link speeds corresponding to the Downstream and Upstream, respectively, it means that the performance of the PCIe Link meets the Linkcapability requirements.

[0033] The PCIe link performance optimization method of the present invention determines whether the performance of the PCIe Link has reached the optimal state according to the training results, which helps to subsequently control the enabling or disabling state of the EQ self-negotiation mechanism of the PCIe device, so that the performance of the PCIe Link reaches the optimal state.

[0034] In some embodiments, the method also includes: obtaining all first PCIe devices in the server that have a requirement to disable the auto-negotiation mechanism; constructing several first identification arrays based on the device identification and manufacturer identification of each first PCIe device; and generating a preset whitelist based on all first identification arrays.

[0035] In some embodiments, Figure 4Shown is a schematic diagram of an embodiment of creating a preset whitelist provided by the present invention. Figure 4 The EQ negotiation disabled whitelist (i.e., preset whitelist) consists of multiple identification arrays, each of which includes the Vendor ID (manufacturer ID) and Device ID (device ID) of the PCIe device. The Vendor ID and Device ID of the PCIe device in the server that needs to disable the EQ auto-negotiation mechanism are used to generate an identification array and stored in the EQ negotiation disabled whitelist.

[0036] The performance optimization method of the PCIe link of the present invention maintains an EQ negotiation disabled whitelist, so that when the PCIe device is initialized, the server firmware can selectively skip the self-negotiation step according to the Vendor ID, Device ID and EQ negotiation disabled whitelist of the PCIe device, thereby providing flexible EQ parameter configuration for external cards of different models.

[0037] Based on the same inventive concept, according to another aspect of the present invention, Figure 5 As shown, an embodiment of the present invention further provides a PCIe link performance optimization system, and the PCIe link performance optimization system includes: The enabling unit 110 is configured to enable a self-negotiation mechanism of a corresponding equalization parameter in response to the initialization of the target PCIe device; The training unit 120 is configured to train the link where the target PCIe device is located based on the equalization parameters obtained by the self-negotiation mechanism to obtain a training result of the link; A determination unit 130 is configured to determine whether to disable the auto-negotiation mechanism according to the training result; The optimization unit 140 is configured to, in response to disabling the auto-negotiation mechanism, retrain the link based on preset equalization parameters so that the performance of the link reaches the target requirement.

[0038] The PCIe link performance optimization system of the present invention enables the EQ self-negotiation mechanism and starts link training in the PCIe device initialization stage, determines whether the performance of the PCIe link has reached the optimal state according to the training result, further controls the enabling and disabling states of the EQ self-negotiation mechanism of the PCIe device whose link has not reached the optimal state based on the training result and a preset white list, and retrains the PCIe link with the disabled EQ self-negotiation mechanism so that its performance reaches the optimal state, thereby solving the problem of PCIe link speed reduction and bandwidth reduction caused by the PCIe device being unable to perform EQ self-negotiation normally, and ensuring that the PCIe device can operate in a high-performance state.

[0039] Based on the same inventive concept, according to another aspect of the present invention, Figure 6As shown, an embodiment of the present invention further provides a computer device 30, which includes a processor 310 and a memory 320. The memory 320 stores a computer program 321 that can be run on the processor. When the processor 310 executes the program, the steps of the above method are performed.

[0040] Based on the same inventive concept, according to another aspect of the present invention, Figure 7 As shown, an embodiment of the present invention further provides a computer-readable storage medium 40, which stores a computer program 410 for executing the above method when executed by a processor.

[0041] Finally, it should be noted that a person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium of the program can be a disk, an optical disk, a read-only storage memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding above-mentioned any method embodiments.

[0042] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0043] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0044] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0045] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A PCIe link performance optimization method, characterized in that: include: In response to the target PCIe device initialization, enabling a self-negotiation mechanism of its corresponding equalization parameters; Based on the equalization parameters obtained by the self-negotiation mechanism, training the link where the target PCIe device is located to obtain a training result of the link; Determining whether to disable the auto-negotiation mechanism according to the training result; In response to disabling the auto-negotiation mechanism, the link is retrained based on preset equalization parameters so that the performance of the link reaches a target requirement.

2. The PCIe link performance optimization method according to claim 1, characterized in that: The step of determining whether to disable the auto-negotiation mechanism according to the training result includes: Determining whether the performance of the link meets the target requirement according to the training result; In response to the performance of the link not meeting the target requirement, obtaining a preset whitelist; Determine whether the target PCIe device matches the preset whitelist; In response to the target PCIe device matching the preset whitelist, disabling the auto-negotiation mechanism.

3. The PCIe link performance optimization method according to claim 2, characterized in that: The step of determining whether the target PCIe device matches the preset whitelist includes: Obtain a target identification array corresponding to the target PCIe device; Querying whether there is an identification array matching the target identification array in a preset whitelist; In response to the presence of an identification array matching the target identification array in the preset whitelist, it is determined that the target PCIe device matches the preset whitelist.

4. The PCIe link performance optimization method according to claim 2, characterized in that: The step of judging whether the performance of the link meets the target requirement according to the training result comprises: Determining a first link width and a first link speed according to the training result; Reading a register of a downlink device to determine a second link width and a second link speed corresponding to the downlink; Reading a register of an uplink device to determine a third link width and a third link speed corresponding to the uplink; Determine whether the first link width, the second link width, and the third link width satisfy a first preset condition, and determine whether the first link speed, the second link speed, and the third link speed satisfy a second preset condition; If the first link width, the second link width and the third link width satisfy a first preset condition and the first link speed, the second link speed and the third link speed satisfy a second preset condition, it is determined that the performance of the link meets the target requirement.

5. The PCIe link performance optimization method according to claim 4, characterized in that: The step of determining whether the first link width, the second link width, and the third link width satisfy a first preset condition comprises: comparing the second link width and the third link width to determine a minimum link width; Determining whether the first link width is greater than or equal to the minimum link width; In response to the first link width being greater than or equal to the minimum link width, it is determined that a first preset condition is satisfied among the first link width, the second link width, and the third link width.

6. The PCIe link performance optimization method according to claim 4, characterized in that: The step of determining whether the first link speed, the second link speed, and the third link speed satisfy a second preset condition comprises: comparing the second link speed and the third link speed to determine a minimum link speed therebetween; determining whether the first link speed is greater than or equal to the minimum link speed; In response to the first link speed being greater than or equal to the minimum link speed, it is determined that a second preset condition is satisfied among the first link speed, the second link speed, and the third link speed.

7. The PCIe link performance optimization method according to claim 2, characterized in that: Also includes: Acquire all first PCIe devices in the server that have a requirement to disable the auto-negotiation mechanism; Constructing a plurality of first identification arrays based on the device identification and the manufacturer identification of each of the first PCIe devices; The preset whitelist is generated based on all the first identification arrays.

8. A PCIe link performance optimization system, characterized in that: include: An enabling unit configured to enable a self-negotiation mechanism of a corresponding equalization parameter in response to initialization of a target PCIe device; A training unit, configured to train the link where the target PCIe device is located based on the equalization parameters obtained by the self-negotiation mechanism to obtain a training result of the link; A judging unit, configured to judge whether to disable the auto-negotiation mechanism according to the training result; The optimization unit is configured to, in response to disabling the auto-negotiation mechanism, retrain the link based on preset equalization parameters so that the performance of the link reaches a target requirement.

9. A computer device comprising: at least one processor; as well as A memory storing a computer program executable on the processor, wherein the processor executes the steps of the method according to any one of claims 1 to 7 when executing the program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are performed.

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