Isolated communication interface and data transmission system thereof

Abstract

The invention discloses an isolation communication interface and a data transmission system thereof, and relates to the technical field of communication. The isolated communication interface comprises a window comparator, a current regulation differential driver, a data input / output pin and a data sending / receiving pin, the mode selection pin sets a working mode for the isolation communication interface; the window comparator is used for receiving data sent by the host through the sending / receiving pin when the isolation communication interface is in the slave mode, and sending the data sent by the host to the slave through the data input / output pin; and the current regulation differential driver is used for receiving data sent by the host through the data input / output pin when the isolation communication interface is in the host mode, and sending the data sent by the host to the slave through the sending / receiving pin. The isolated communication interface can simultaneously transmit and receive data.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an isolated communication interface and a data transmission system thereof. Background Art

[0002] Currently, there are a variety of physical interface standards related to serial data communication for instrumentation and control systems. Serial communication is the process of sending data one bit at a time in sequence through a communication channel or computer bus. Each interface standard defines the electrical and mechanical details that enable devices from different manufacturers to connect and communicate. Among them, the isolated communication interface is an important component used in electronic devices, providing electrical isolation between different circuits to prevent dangerous direct current or uncontrolled transient current from flowing between different circuits. Used in conjunction with battery acquisition chips, it can realize information collection and safe control of lithium battery new energy systems under complex working conditions. It has significant advantages in improving the safety of lithium battery applications and can be fully applied to electric or hybrid vehicles, backup battery systems, energy storage systems and industrial battery packs.

[0003] Taking the battery management system as an example, for a battery management system in which multiple battery modules communicate with each other, serial communication needs to consider the characteristics of galvanic isolation. The battery modules stacked in series operate at different voltage potentials. Galvanic isolation prevents charge from flowing between the two sides of the isolation barrier while allowing information to pass through the isolation layer. This isolation minimizes the impact of noise, allows common mode voltage differences, and prevents ground loops.

[0004] However, the battery management system needs to consider bidirectionality. In some traditional circuits, the isolated communication interface does not support full-duplex operation and cannot send and receive data at the same time. Summary of the invention

[0005] Based on this, it is necessary to provide an isolated communication interface and a data transmission system thereof to address the above technical problems, wherein the isolated communication interface can send and receive data simultaneously.

[0006] The present invention adopts the following technical solutions:

[0007] The present invention provides an isolation communication interface, which is connected between two isolation devices. The isolation communication interface comprises: a window comparator, a current regulating differential driver, a data input / output pin and a sending / receiving pin; the data input / output pin is respectively connected to one end of the window comparator and one end of the current regulating differential driver, and the other end of the window comparator and the other end of the current regulating differential driver are both connected to the sending / receiving pin;

[0008] a window comparator, for receiving data sent by the host through a transmit / receive pin when the isolated communication interface is in a slave mode, and for sending the data sent by the host to the slave through a data input / output pin;

[0009] A current-regulated differential driver is used to receive data sent by a master through a data input / output pin and to transmit the data sent by the master to a slave through a transmit / receive pin when the isolated communication interface is in a master mode.

[0010] Preferably, the isolated communication interface further comprises a timing control module, a port encoding and decoding module and an analog-to-digital conversion module; one end of the analog-to-digital conversion module is connected to the resistor timeout pin, and the other end of the analog-to-digital conversion module is connected to the timing control module; the data input / output pin is connected to the port encoding and decoding module, and the other end of the port encoding and decoding module is respectively connected to one end of the window comparator and one end of the current regulating differential driver;

[0011] An analog-to-digital conversion module, used for converting the analog signal sent by the resistor timeout pin into a digital signal and sending it to the timing control module;

[0012] A timing control module is used to generate a clock signal according to the received digital signal to drive each component in the isolated communication interface to work;

[0013] The port encoding and decoding module is used to encode or decode data.

[0014] Preferably, the isolated communication interface further comprises a wake-up detection module and a wake-up pin, one end of the wake-up detection module is connected to the send / receive pin, and the other end of the wake-up detection module is connected to the timing control module; the wake-up pin is connected to the timing control module;

[0015] A wake-up pin is used to limit the current output / input of the wake-up state of the isolated communication interface;

[0016] If the wake-up detection module does not receive the heartbeat information within the preset time period, a prompt signal is issued.

[0017] Preferably, the isolated communication interface further comprises a mode selection pin, when the mode selection pin is connected to the power supply voltage, the isolated communication interface is in the host mode, when the mode selection pin is grounded, the isolated communication interface is in the slave mode.

[0018] Preferably, the data input / output pins include a data input pin, a data output pin, a clock input / output pin and a chip select input / output pin.

[0019] Preferably, the sending / receiving pin includes a positive input / output pin and a negative input / output pin; the window comparator is an operational amplifier, the positive input / output pin is connected to the non-inverting input terminal of the operational amplifier, and the negative input / output pin is connected to the inverting input terminal of the operational amplifier.

[0020] The present invention provides a data transmission system, which comprises a master serial peripheral interface device, a master isolation communication interface in a host mode, a plurality of slave serial peripheral interface devices and a slave isolation communication interface in a slave mode; the master isolation communication interface and the plurality of slave isolation communication interfaces are the isolation communication interfaces provided above;

[0021] The master isolation communication interface is connected to the master serial peripheral interface device through the data input / output pin, the master isolation communication interface is connected to one side of the isolation barrier through the send / receive pin, the other side of the isolation barrier is respectively connected to the send / receive pins of multiple slave isolation communication interfaces, and the data input / output pins of the multiple slave isolation communication interfaces are connected to the corresponding slave serial peripheral interface devices.

[0022] At least one of the above technical solutions adopted by the present invention can achieve the following beneficial effects:

[0023] In the present invention, by setting a window comparator to receive data sent by the host and send it to the slave when the isolated communication interface is in the slave mode, and by setting a current regulating differential driver to send data to the slave when the isolated communication interface is in the master mode, such an isolated communication interface is set between two isolation devices, which can provide bidirectional isolated communication for each data link. Therefore, the isolated communication interface can realize simultaneous sending and receiving of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0025] Figure 1 A schematic diagram of the structure of an isolated communication interface provided by the present invention;

[0026] Figure 2 A schematic diagram of the structure of another isolated communication interface provided by the present invention;

[0027] Figure 3 A schematic diagram of the timing specifications of the +1isoSPI pulse and the -1isoSPI pulse provided by the present invention;

[0028] Figure 4 A schematic diagram of the structure of four isolated communication interfaces configured to communicate with each other provided by the present invention;

[0029] Figure 5 A timing diagram of the interaction between the isolated communication interface in the host mode and the isolated communication interface in the slave mode provided by the present invention;

[0030] Figure 6 This is a schematic diagram of the application structure of low-power battery monitoring when the isolated transceiver provided by the present invention is paired with a BMS.

[0031] Description of reference numerals:

[0032] 100, isolated communication interface; 101, window comparator; 102, current regulation differential driver; 103, data input / output pin; 104, transmit / receive pin;

[0033] 201, timing control module; 202, port encoding and decoding module; 203, analog-to-digital conversion module; 204, resistor timeout pin; 205, wake-up detection module; 206, wake-up pin; 207, data input pin; 208, data output pin; 209, clock input / output pin; 210, chip select input / output pin; 211, positive input / output pin; 212, negative input / output pin; 213, PHAPOL pin; 214, XCVRMD pin; 215, INTR pin; 216, mode selection pin. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] For battery management systems where multiple battery modules communicate with each other, serial communication needs to consider the characteristics of galvanic isolation. Battery modules stacked in series operate at different voltage potentials. Galvanic isolation prevents charge from flowing between the two sides of the isolation barrier while allowing information to pass through the isolation layer. This isolation minimizes the impact of noise, allows common-mode voltage differences, and prevents ground loops. Battery management systems also need to consider balanced and impedance-matched differential signals. Cables used for serial communication links can act as transmission lines. If the transmission lines are not linked with appropriate impedance, the communication signals may be reflected back and forth between the transmitter (on one side of the communication link) and the receiver (on the other side of the communication link), thereby destroying the communication signals. Therefore, the balance, differentiation, and impedance matching of serial communication are critical. Battery management systems also need to consider bidirectionality. In some traditional circuits, the isolated communication interface does not support full-duplex operation and cannot send and receive data at the same time.

[0036] ISO Serial Peripheral Interface (isoSPI) is a new type of high-speed isolated communication protocol with the advantages of long communication distance, high communication rate and stable communication. However, the traditional isolated communication interface has a single mode and cannot meet the data communication at various rates. It has poor compatibility, does not support low power consumption and has high power consumption.

[0037] Based on this, the present invention provides an isolated communication interface, which can realize bidirectional transmission of a serial peripheral interface (Serial Peripheral Interface, SPI) bus across an isolation barrier of up to 100 meters. The isolated communication interface supports isolated bidirectional serial data communication up to 2Mbps, 4Mbps unidirectional serial data transmission, supports pairing with a battery management system (Battery Management System, BMS), and can also perform battery voltage and sensor detection when the BMS performs low power battery monitoring (Low Power Cell Monitoring, LPCM). The isolated communication interface provides a timeout function, which can wake up or remind the system when the heartbeat information passed is not received within the programmed time period. The isolated communication interface implements a completely independent dual transceiver, is compatible with single-channel and dual-channel data communications, has extremely low idle current, provides a 3V to 30V power supply voltage for the wake-up function and the monitoring function, and is compatible with a 12V battery pack.

[0038] The technical solutions provided by various embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0039] In an exemplary embodiment, Figure 1 As shown, Figure 1The present invention is a structural schematic diagram of an isolated communication interface, wherein the isolated communication interface 100 comprises: a window comparator 101 and a current regulating differential driver 102, a data input / output pin 103, and a send / receive pin 104; the data input / output pin 103 is respectively connected to one end of the window comparator 101 and one end of the current regulating differential driver 102, and the other end of the window comparator 101 and the other end of the current regulating differential driver 102 are both connected to the send / receive pin 104.

[0040] A window comparator is used to receive data sent by the host through a transmit / receive pin when the isolated communication interface is in a slave mode, and to send the data sent by the host to the slave through a data input / output pin; a current regulating differential driver is used to receive data sent by the host through a data input / output pin when the isolated communication interface is in a master mode, and to send the data sent by the host to the slave through a transmit / receive pin.

[0041] The isolated communication interface uses a capacitor or a transformer to convert standard SPI signals (Chip Select (CS) signal, Serial Clock (SCK) signal, Master Out Slave In (MOSI) signal and Master In Slave Out (MISO) signal) into pulses that can be sent back and forth through a twisted pair cable. The current-regulated differential driver 102 is a differential driver that implements the function of current driving to complete the reception of data sent by the host through the data input / output pin when the isolated communication interface is in the host mode, and to send the data sent by the host to the slave through the send / receive pin.

[0042] like Figure 2 As shown, the isolated communication interface 100 also includes a timing control module 201, a port encoding and decoding module 202 and an analog-to-digital conversion module 203; one end of the analog-to-digital conversion module 203 is connected to the resistor timeout pin 204, and the other end of the analog-to-digital conversion module 203 is connected to the timing control module 201; the data input / output pin 103 is connected to the port encoding and decoding module 202, and the other end of the port encoding and decoding module 202 is respectively connected to one end of the window comparator 105 and one end of the current regulating differential driver 102.

[0043] The isolated communication interface 100 also includes a wake-up detection module 205 and a wake-up pin 206 , one end of the wake-up detection module 205 is connected to the send / receive pin 104 , and the other end of the wake-up detection module 205 is connected to the timing control module 201 ; the wake-up pin 206 is connected to the timing control module 201 .

[0044] Specifically, the analog-to-digital conversion module is used to convert the analog signal sent by the resistor timeout pin into a digital signal and send it to the timing control module; the timing control module is used to generate a clock signal according to the received digital signal to drive the various components in the isolated communication interface to work; the port encoding and decoding module is used to encode or decode the data. The wake-up pin is used to limit the output / input of the wake-up state of the isolated communication interface; if the wake-up detection module does not receive the heartbeat information within the preset time period, a prompt signal is issued.

[0045] In addition, the data input / output pin 103 includes a data input pin 207, a data output pin 208, a clock input / output pin 209 and a chip select input / output pin 210; the send / receive pin 104 includes a positive input / output pin 211 and a negative input / output pin 212; the window comparator 101 is an operational amplifier, the positive input / output pin 211 is connected to the non-inverting input terminal of the operational amplifier, and the negative input / output pin 212 is connected to the inverting input terminal of the operational amplifier.

[0046] Specifically, the resistor timeout pin is an LPCM resistor timeout pin, which can be called an RTO pin, and the LPCM timeout time is selected by an input resistor; the wake-up pin can be a WAKE pin, which is a current-limited output / input in the wake-up state of the transceiver; the data input pin can be a MISO pin, which is an SPI master mode input / slave mode input data pin; the data output pin can be a MOSI pin, which is a master mode output or slave mode output data pin; the clock input / output pin can be an SCK pin, which is a master mode clock input / slave mode clock output pin; the chip select input and output pin can be a CS pin, which is a low-effective SPI chip select input (host mode) / chip select output (slave mode); the positive input / output pin can be an IP pin, which is an isolated communication positive input / output; the negative input / output pin can be an IM pin, which is an isolated communication negative input / output.

[0047] Please refer to Figure 2 The isolated communication interface also includes a PHAPOL pin 213, an XCVRMD pin 214 and an INTR pin 215; wherein the PHAPOL pin sets the working polarity of the isolated communication interface by detecting the pin input resistance; the XCVRMD pin sets the working mode of the isolated communication interface by detecting the pin input resistance; and the INTR pin is the LPCM interrupt current limiting output. Figure 2 I pu and I PD They are pull-up current and pull-down current respectively, which drive the INTR pin high / low to determine the success / failure of the heartbeat information transmission in LPCM mode.

[0048] Among them, the isolated communication interface also includes a mode selection pin 216, which is an SPI mode selection bit. When the mode selection pin is connected to the power supply voltage, the isolated communication interface is in host mode. When the mode selection pin is grounded, the isolated communication interface is in slave mode. The mode selection pin can be a master mode selection (Master Mode Select, MSTR) pin.

[0049] The transmitter in the isolated communication interface of the present invention is composed of a current-regulated differential driver. The voltage amplitude is determined by the driving current and the equivalent resistance load (cable characteristic impedance and terminal resistance RM).

[0050] The receiver in the isolated communication interface has a differential voltage with a preset voltage value V RX The window comparator is composed of IP -V IM Greater than V RX When the comparator detects logic 1, V IP is the voltage of the negative input / output pin, V IM is the voltage of the negative input / output pin. IP -V IM Less than V RX , the comparator detects a logic -1. A logic 0 indicates that V IP -V IM Between the positive and negative thresholds. The window comparator output is sent to a pulse timer (filter) that distinguishes short pulses from long pulses. Two identical independent isolated communication interfaces can serve as termination devices for bidirectional isolated SPI systems.

[0051] The isolated communication interface of the present invention supports four SPI polarity working modes, which are configured by the PHAPOL pin, and has four working modes at the same time, and can enhance functions through different system configurations. The isolated communication interface is set by connecting to the XCVRMD pin, and the specific settings are shown in Table 1 and Table 2, Table 1 is the SPI polarity phase setting, and Table 2 is the SPI working mode.

[0052] Table 1

[0053]

[0054] Table 2

[0055] describe XCVRMD Pin Connections Standard bidirectional isoSPI GND Standard bidirectional isoSPI with LPCM timeout monitor support 20KΩ resistor to ground 4Mbps one-way communication 100KΩ resistor to ground 2Mbps, 1Bit delay communication VDDS

[0056] Among them, when the XCVRMD pin is connected to the ground line, the isolated communication interface is set to standard bidirectional isoSPI, and the transceiver supports up to 2Mbps communication when configured in master mode. When the XCVRMD pin is connected to the ground line through a 20kΩ resistor, the isolated communication interface is configured in master mode, and its behavior is the same as the standard bidirectional isoSPI mode. When the isolated communication interface is configured in slave mode, the LPCM feature is enabled, and communication can be received at a speed of 2Mbps. The isolated communication interface receives data and decodes it to the SPI port. When the XCVRMD pin is connected to the ground line through a 100kΩ resistor, the isolated communication interface supports unidirectional data transmission at a rate of 4Mbps. When the XCVRMD pin is connected to the power supply, the isolated communication interface is configured in a 2Mbps rate transmission mode with a 1bit delay. In order to achieve a rate of 2Mbps, the isolated communication interface configured in slave mode sends back data from the latch edge of its clock (SCK) instead of the non-latched edge.

[0057] The current regulated differential driver 107 provides three logic levels: +VA, 0V and -VA. In order to eliminate the DC signal component and improve reliability, the isoSPI pulse is defined as a symmetrical pulse pair. A +1 pulse pair is defined as a +VA pulse followed by a -VA pulse. A -1 pulse pair is defined as a -VA pulse followed by a +VA pulse. The duration of each pulse is defined as t 1 / 2PW , (total isoSPI pulse duration is 2×t 1 / 2PW ). The isolated communication interface allows two different 1 / 2PW value, so four types of pulses can be transmitted, further divided into CS (long) and data (short) parameters, such as Figure 3 The timing specifications of the +1isoSPI pulse and the -1isoSPI pulse are shown in Table 3. Table 3 defines the timing specifications of the +1isoSPI pulse and the -1isoSPI pulse.

[0058] Table 3

[0059] Pulse type The first level The second level End Level Length +1 <![CDATA[+VA(t 1 / 2PW =150ns)]]> <![CDATA[-VA(t 1 / 2PW =150ns)]]> 0V Length - 1 <![CDATA[-VA(t 1 / 2PW =150ns)]]> <![CDATA[+VA(t 1 / 2PW =150ns)]]> 0V Short +1 <![CDATA[+VA(t 1 / 2PW =50ns)]]> <![CDATA[-VA(t 1 / 2PW =50ns)]]> 0V Short +1 <![CDATA[-VA(t 1 / 2PW =50ns)]]> <![CDATA[+VA(t 1 / 2PW =50ns)]]> 0V

[0060] Among them, long pulses are used to transmit CS changes. Short pulses transmit data (MOSI and MISO). The isolated communication interface of the present invention detects four communication events from the SPI host: CS falling edge, CS rising edge, SCK latched MOSI=0, SCK latched MOSI=1. The isolated communication interface of the present invention converts each event into one of the four pulse types, as shown in Table 4.

[0061] Table 4

[0062]

[0063] This isolated communication interface device is used in a typical battery management system (BMS) as a bridge between the microcontroller SPI port and the isoSPI port of the BMS monitor. IP and IM on the isolated communication interface

[0064] (Transmit / Receive pin) is connected across the isolation barrier to the first BMS monitor in the daisy chain.

[0065] Two of these isolated communication interfaces are used in a typical non-battery management system (BMS). The first is paired with a microcontroller or other SPI master. The IP and IM (transmit / receive pins) of this isolated communication interface are connected through an isolation barrier to a second isolated communication interface, which generates SPI signals for use by one or more slave devices.

[0066] Therefore, in an exemplary embodiment, the present invention provides a data transmission system, which includes a master serial peripheral interface device, a master isolation communication interface in host mode, multiple slave serial peripheral interface devices and a slave isolation communication interface in slave mode; the master isolation communication interface and the multiple slave isolation communication interfaces are the isolation communication interfaces provided above; the master isolation communication interface is connected to the master serial peripheral interface device through a data input / output pin, the master isolation communication interface is connected to one side of the isolation barrier through a send / receive pin, the other side of the isolation barrier is respectively connected to the send / receive pins of multiple slave isolation communication interfaces, and the data input / output pins of multiple slave isolation communication interfaces are connected to the corresponding slave serial peripheral interface devices.

[0067] In one embodiment, Figure 4 As shown, Figure 4The example application of four isolated communication interfaces configured to communicate with each other is shown. The isolated communication interfaces 100a and 100b, 100c, and 100d of the present invention communicate with each other in a master / slave mode, wherein the master SPI device 400 initiates data communication, and the isolated communication interface 100a is connected to the master SPI device 400 through the four pins of CS, SCK, MISO, and MOSI. The MSTR pin of the isolated communication interface 100a is connected to the power supply voltage and is set to the master mode, with CS, SCK, and MOSI as inputs and MISO as a push-pull output. The MSTR pins of the isolated communication interfaces 100b, 100c, and 100d are connected to the ground line and are set to the slave mode. The slave isolated communication interfaces 100b, 100c, and 100d are connected to the slave SPI devices 401, 402, and 403 through the four pins of CS, SCK, MISO, and MOSI, respectively, wherein CS, SCK, and MOSI are outputs and MISO is a push-pull input. The master isolated communication interface 100a communicates with the slave isolated communication interfaces 100b, 100c and 100d via twisted pair cables, and the twisted pair cables are impedance matched by terminal resistors RM. It should be noted that in practical applications, the number of isolated communication interfaces that can be configured to communicate with each other is not limited.

[0068] like Figure 5 As shown, Figure 5 It is a timing diagram of the interaction between the isolated communication interface in the host mode and the isolated communication interface in the slave mode; the figure describes in detail the operation when PHA=0 (and shows the SCK signal when POL=0 or 1), and different SPI modes, namely PHA and POL settings, can be used in the host device and the slave device.

[0069] according to Figure 4 In the example application of several communication interfaces shown, the master SPI device 400 starts communication by lowering CS. The communication interface 100a will convert this signal into a long -1 pulse on the IP and IM pins, which passes through the isolation barrier (with associated cable delays) and reaches the IP and IM pins of the slave communication interfaces 100b, 100c and 100d. After verification, the long -1 pulse is converted to a CS falling edge for the slave SPI devices 401, 402 and 403.

[0070] Before the master SPI device 400 provides the first latch clock edge, the slave communication interfaces 100b, 100c and 100d must transmit the initial slave data as SN. The value of SN is determined by sampling the state of MISO. If MISO = 0, the slave communication interfaces 100b, 100c and 100d send a short pulse of -1 to the master communication interface 100a, the master communication interface 100a receives and decodes the pulse, and sets the master MISO = 0 (matching the slave end).

[0071] If MISO=1 of slave communication interfaces 100b, 100c and 100d, slave communication interfaces 100b, 100c and 100d do not send pulses. Master communication interface 100a interprets this empty response as 1 and sets master MISO=1. This behavior makes it possible to connect multiple slave communication interfaces to one cable without conflicting signals.

[0072] After the CS falling edge, each latch clock edge on the master communication interface 100a converts the state of the MOSI pin into an isoSPI data pulse (M N , M N-1 , ..., M0), while latching the data bits from the slave communication interface. When the slave communication interface receives each data bit, it sets the slave MOSI pin to the appropriate state, and then generates an SCK pulse (as a short -1 pulse, or as a null) before returning the slave MISO data.

[0073] At the end of the communication, the final data bit sent by the slave communication interface (as a pulse or null) is ignored by the master communication interface. (The slave communication interface must return a data bit because it cannot predict when the communication will stop.) The master SPI device 300 can then pull CS high, which is transmitted to the slave communication interface in the form of a +1 long pulse.

[0074] like Figure 6 The schematic diagram of the application structure of the isolated transceiver of the present invention for low power battery monitoring when paired with BMS is shown, wherein the microcontroller 600 drives the MSTR pin high level when communicating with the BMS devices 601_1 to 601_n through the isolated communication interface 100, and when performing LPCM operation, the microcontroller 600 first configures the battery monitor for LPCM operation, and then drives the MSTR pin low level to activate the timeout monitor function of the isolated communication interface 100. The INTR pin of the isolated communication interface 100 is connected to the microcontroller for interrupting the current limiting output, its XCVRMD pin is connected to the ground through a 20kΩ resistor, and the RTO pin sets the timeout period for the timeout monitor.

[0075] When the isolated communication interface 100 is configured for low power battery detection (LPCM), its INTR pin is asserted high. The isolated communication interface 100 assumes that there may be a fault in the system in the initial state before the first heartbeat message is fully propagated through the daisy chain. This transition of the INTR pin from low to high also serves as an indication that the timeout monitoring function of the microcontroller 600 has been activated. At this time, the INTR pin of the communication isolation interface 100 remains high until a passed heartbeat message is received from the BMS device 601_1 to 601_n, the INTR pin is set to a low level, and then the internal timer is reset to 0. If a passed heartbeat message is received, the INTR pin remains low and the internal timer is reset. If a failed heartbeat message is received, the INTR pin is set to a high level to sound an alarm.

[0076] In summary, the isolated communication interface proposed in the present invention connects two isolated devices through a single twisted pair cable, provides a bidirectional isolated serial port interface (isoSPI) communication for each data link, can achieve hundreds of volts of isolation, uses matching current to drive differential signals, eliminates the requirement for the center tap of the transformer, and reduces electromagnetic interference. It has extremely low radiation and idle current, high compatibility, and has broad application prospects.

[0077] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present invention.

Claims

1. An isolated communication interface, the isolated communication interface is connected between two isolated devices, characterized in that: The isolated communication interface comprises: a window comparator, a current regulating differential driver, a data input / output pin and a send / receive pin; the data input / output pin is respectively connected to one end of the window comparator and one end of the current regulating differential driver, and the other end of the window comparator and the other end of the current regulating differential driver are both connected to the send / receive pin; The window comparator is used to receive data sent by the host through the send / receive pin when the isolated communication interface is in the slave mode, and send the data sent by the host to the slave through the data input / output pin; The current regulating differential driver is used to receive data sent by the host through the data input / output pin when the isolated communication interface is in the host mode, and send the data sent by the host to the slave through the send / receive pin.

2. The isolated communication interface according to claim 1, characterized in that: The isolated communication interface also includes a timing control module, a port encoding and decoding module and an analog-to-digital conversion module; one end of the analog-to-digital conversion module is connected to the resistor timeout pin, and the other end of the analog-to-digital conversion module is connected to the timing control module; the data input / output pin is connected to the port encoding and decoding module, and the other end of the port encoding and decoding module is respectively connected to one end of the window comparator and one end of the current regulating differential driver; The analog-to-digital conversion module is used to convert the analog signal sent by the resistor timeout pin into a digital signal and send it to the timing control module; The timing control module is used to generate a clock signal according to the received digital signal to drive each component in the isolated communication interface to work; The port encoding and decoding module is used to encode or decode data.

3. The isolated communication interface according to claim 2, characterized in that: The isolated communication interface also includes a wake-up detection module and a wake-up pin, one end of the wake-up detection module is connected to the send / receive pin, and the other end of the wake-up detection module is connected to the timing control module; the wake-up pin is connected to the timing control module; If the wake-up detection module does not receive the heartbeat information within the preset time period, a prompt signal is issued.

4. The isolated communication interface according to claim 2, characterized in that: The isolated communication interface also includes a mode selection pin. When the mode selection pin is connected to a power supply voltage, the isolated communication interface is in a host mode. When the mode selection pin is grounded, the isolated communication interface is in a slave mode.

5. The isolated communication interface according to claim 2, characterized in that: The data input / output pins include a data input pin, a data output pin, a clock input / output pin and a chip select input / output pin.

6. The isolated communication interface according to claim 1, characterized in that: The sending / receiving pin includes a positive input / output pin and a negative input / output pin; the window comparator is an operational amplifier, the positive input / output pin is connected to the non-inverting input terminal of the operational amplifier, and the negative input / output pin is connected to the inverting input terminal of the operational amplifier.

7. A data transmission system, characterized in that: The system includes a master serial peripheral interface device, a master isolation communication interface in a host mode, a plurality of slave serial peripheral interface devices and a slave isolation communication interface in a slave mode; The master isolation communication interface and the plurality of slave isolation communication interfaces are all isolation communication interfaces according to any one of claims 1 to 6; The master isolation communication interface is connected to the master serial peripheral interface device via a data input / output pin, the master isolation communication interface is connected to one side of an isolation barrier via a send / receive pin, the other side of the isolation barrier is respectively connected to the send / receive pins of the multiple slave isolation communication interfaces, and the data input / output pins of the multiple slave isolation communication interfaces are connected to the corresponding slave serial peripheral interface devices.

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