Computing node, computing system, control method, device, equipment and medium

Abstract

The invention discloses a computing node, a computing system, a control method, a control device, equipment and a medium, and relates to the technical field of computers, a plurality of acceleration cards are interconnected through an Ethernet switching module, and low-order channels of serializer / deserializer interfaces of the acceleration cards are connected with the Ethernet switching module through retimers. A high-order channel of at least one serializer / deserializer interface of each accelerator card is connected with the Ethernet switching module through a retimer, and the working mode of the retimer is configured through a first controller on a computing node according to the signal rate of the accelerator cards, so that a framework that communication interfaces between the accelerator cards are fully interconnected is realized. Any two acceleration cards can be directly connected, the communication bandwidth between the acceleration cards is improved, meanwhile, the number of the acceleration cards can be flexibly expanded, longitudinal expansion and transverse expansion of a computing system can be conveniently achieved, the problem that a traditional acceleration card interconnection scheme is not easy to expand is solved, and the method can adapt to service requirements and flexibly adjust working loads.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a computing node, a computing system, and a control method, device, equipment, and medium thereof. Background Art

[0002] With the development of artificial intelligence technology, the demand for computing power has increased significantly. Using a Graphics Processing Unit (GPU) and other components as a computing acceleration card to achieve computing power expansion has become one of the solutions. Through the acceleration card interconnection solution, high-speed communication of the acceleration cards can be achieved to complete large-scale computing tasks. However, the current acceleration card interconnection topology is difficult to quickly adjust and optimize according to specific business changes and requirements after being determined at the initial design stage, and it is not easy to expand the scale of the computing cluster.

[0003] How to reduce the expansion difficulty of the acceleration card interconnection cluster to flexibly adapt to the needs of different business applications is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The present invention provides a computing node, a computing system, and a control method, device, equipment, and medium thereof, so as to at least solve the problem that the acceleration card interconnection system in the related art is not easy to expand.

[0005] The present invention provides a computing node, including: a first controller and a computing motherboard; The computing motherboard includes acceleration cards and retimers; Different acceleration cards are interconnected through an Ethernet switch module, and the low-order channels of the serializer / deserializer interfaces of each acceleration card are connected to the Ethernet switch module through the retimer, and the high-order channels of at least one serializer / deserializer interface of the acceleration card are connected to the Ethernet switch module through the retimer; The first controller is used to configure the working mode of the retimer according to the signal rate of the acceleration card.

[0006] The present invention also provides a computing system, including: a plurality of acceleration cards and an Ethernet switch module; Different acceleration cards are interconnected through the Ethernet switch module, and the low-order channels of the serializer / deserializer interfaces of each acceleration card are connected to the Ethernet switch module through the retimer on the computing motherboard where it is located, and the high-order channels of at least one serializer / deserializer interface of the acceleration card are connected to the Ethernet switch module through the retimer; The working mode of the retimer corresponds to the signal rate of the acceleration card; The Ethernet switching module is used to configure the address mapping table of the computing system according to the accelerator card address information of each accelerator card, and perform data transmission between different accelerator cards according to the address mapping table.

[0007] The present invention also provides a switch having an Ethernet switching module; The Ethernet switching module is connected to a plurality of accelerator cards, and the low channels of the serializer / deserializer interfaces of each accelerator card are all connected to the Ethernet switching module through a retimer on the computing motherboard where the accelerator card is located, and the high channels of at least one serializer / deserializer interface of the accelerator card are connected to the Ethernet switching module through the retimer; the working mode of the retimer corresponds to the signal rate of the accelerator card; The Ethernet switching module is used to configure the address mapping table of the computing system according to the accelerator card address information of each accelerator card, and perform data transmission between different accelerator cards according to the address mapping table.

[0008] The present invention also provides a control method for a computing system, which is applied to an Ethernet switching module and includes: Obtaining the address information of a plurality of accelerator cards through an Ethernet bus; Configuring the address mapping table of the computing system according to the address information of each accelerator card; Performing data transmission between different accelerator cards according to the address mapping table; Wherein, the low channels of the serializer / deserializer interfaces of each accelerator card are all connected to the Ethernet switching module through a retimer on the computing motherboard where the accelerator card is located, and the high channels of at least one serializer / deserializer interface of the accelerator card are connected to the Ethernet switching module through the retimer, and the working mode of the retimer corresponds to the signal rate of the accelerator card.

[0009] The present invention also provides a control device for a computing system, including: An obtaining unit for obtaining the address information of a plurality of accelerator cards through an Ethernet bus; A configuring unit for configuring the address mapping table of the computing system according to the address information of each accelerator card; A control unit for performing data transmission between different accelerator cards according to the address mapping table; Wherein, the low channels of the serializer / deserializer interfaces of each accelerator card are all connected to the Ethernet switching module through a retimer on the computing motherboard where the accelerator card is located, and the high channels of at least one serializer / deserializer interface of the accelerator card are connected to the Ethernet switching module through the retimer, and the working mode of the retimer corresponds to the signal rate of the accelerator card.

[0010] The present invention also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of the control method of the above-mentioned computing system when executing the computer program.

[0011] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the control method of the above-mentioned computing system.

[0012] The present invention also provides a computer program product including a computer program, which implements the steps of the control method of the above-mentioned computing system when executed by a processor.

[0013] Through the present invention, multiple acceleration cards are interconnected through an Ethernet switch module, and the low-order channels of the serializer / deserializer interfaces of each acceleration card are all connected to the Ethernet switch module through retimers, and the high-order channels of at least one serializer / deserializer interface of the acceleration card are connected to the Ethernet switch module through retimers, realizing an architecture with full interconnection of communication interfaces between acceleration cards, enabling direct connection between any two acceleration cards, improving the communication bandwidth between any two acceleration cards, and at the same time, the number of acceleration cards can be flexibly expanded, facilitating vertical and horizontal expansion of the computing system, solving the problem that traditional acceleration card interconnection schemes are not easy to expand, and can also flexibly adjust the workload according to business requirements. On this basis, by configuring the working mode of the retimer according to the signal rate of the acceleration card by the first controller on the computing node where it is located, different models of acceleration cards can be adapted to meet the high-speed transmission requirements in the computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0015] Figure 1 It is a schematic diagram of an acceleration card interconnection topology; Figure 2 It is a schematic diagram of the structure of a computing node provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of the structure of another computing node provided by an embodiment of the present invention; Figure 4 It is a schematic diagram of the connection of a field replaceable unit provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of a monitoring system of a computing motherboard provided by an embodiment of the present invention; Figure 6 Schematic diagram of a first monitoring subsystem provided by an embodiment of the present invention; Figure 7 Schematic diagram of a second monitoring subsystem provided by an embodiment of the present invention; Figure 8 Schematic diagram of a third monitoring subsystem provided by an embodiment of the present invention; Figure 9 Schematic diagram of a universal asynchronous receiver / transmitter management unit of a computing motherboard provided by an embodiment of the present invention; Figure 10 Schematic diagram of a debug control unit of a computing motherboard provided by an embodiment of the present invention; Figure 11 Schematic diagram of a system clock unit of a computing motherboard provided by an embodiment of the present invention; Figure 12 Schematic diagram of the power-on and power-off sequence of a single board of a computing motherboard provided by an embodiment of the present invention. Detailed implementation manners

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0017] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0018] In order to enable those skilled in the art of the present technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0019] Here, some key terms used in the embodiments of the present invention will be explained first.

[0020] An acceleration card is a hardware device specifically used to accelerate specific computing tasks. It is usually installed in the Peripheral Component Interconnect Express (PCIe) slot of a server to be connected to the server motherboard.

[0021] Serializer / Deserializer (SerDes) is a mainstream time division multiplexing (TDM) and point-to-point (P2P) serial communication technology, which is widely used in the field of high-speed data transmission. At the transmitting end, the serializer / deserializer converts multiple low-speed parallel signals into high-speed serial signals, transmits them to the receiving end through transmission media such as optical fiber or copper cable, and then converts the high-speed serial signals back into low-speed parallel signals. The advantage of serializer / deserializer transmission is that compared with parallel transmission, the number of pins and transmission channels required for serial transmission is greatly reduced. It adopts differential transmission mode, has strong anti-noise and anti-interference capabilities, and can effectively reduce switching noise. Through equalization, clock recovery and other technologies, the serializer / deserializer can maintain signal quality in high-speed transmission while reducing power consumption.

[0022] Figure 1 A schematic diagram of an accelerator card interconnection topology.

[0023] like Figure 1 As shown in FIG. 1 , in a server including eight accelerator cards (accelerator cards 0 to 7), each accelerator card has communication interfaces such as 1L to 7L, some of which are used for interconnection between accelerator cards in the server, and other interfaces are used for interconnection between accelerator cards across servers. Figure 1 As shown in the figure, a commonly used accelerator card interconnection architecture is that the high-order channel 1H of interface 1 is used to connect to the back-end switch through the server's network card, and the low-order channels 1L~7L of interfaces 1~7 are used to interconnect between accelerator cards inside the server, thereby realizing resource sharing between accelerator cards inside the server and resource sharing between servers.

[0024] Apart from Figure 1 In addition to the accelerator card interconnection solution shown, the traditional solution also includes configuring an interface for connecting to the host, an interface for connecting to the storage, etc. on the accelerator card.

[0025] These traditional accelerator card interconnect solutions all have the following disadvantages:

[0026] (1) Bandwidth limitation is relatively obvious: The interconnection within the server is limited by factors such as the wiring within the board, the number of interfaces and the communication protocol. Its internal data transmission bandwidth is relatively limited. When processing large-scale, high-concurrency data interactions, it may not be able to provide sufficient bandwidth support, which is prone to data congestion and increased transmission delays.

[0027] (2) Poor flexibility of communication topology: The topology of the interconnection between accelerator cards in the server is usually fixed during the design phase. It is relatively simple and lacks flexibility, making it difficult to quickly adjust and optimize according to specific business changes or special needs.

[0028] (3) High upgrade cost: When it is necessary to upgrade the performance of the interconnection within the server, it may be necessary to re - design and replace the entire board, involving relatively high R & D and hardware replacement costs.

[0029] In view of the disadvantages of the solution for the interconnection of acceleration cards within the server, the embodiments of the present invention provide a computing node and a computing system. Multiple acceleration cards are interconnected through an Ethernet switching module, and the low - order channels of the serializer / deserializer interfaces of each acceleration card are all connected to the Ethernet switching module through retimers. The high - order channels of at least one serializer / deserializer interface of the acceleration card are connected to the Ethernet switching module through retimers, realizing an architecture with full interconnection of the communication interfaces between acceleration cards, enabling direct connection between any two acceleration cards, improving the communication bandwidth between any two acceleration cards, and at the same time, the number of acceleration cards can be flexibly expanded, facilitating the vertical and horizontal expansion of the computing system, solving the problem that the traditional acceleration card interconnection solution is not easy to expand, and can also flexibly adjust the workload according to business requirements. On this basis, the first controller on the computing node where it is located configures the working mode of the retimer according to the signal rate of the acceleration card, which can adapt to different models of acceleration cards and meet the high - speed transmission requirements in the computing system.

[0030] Figure 2 It is a schematic structural diagram of a computing node provided by the embodiments of the present invention.

[0031] As Figure 2 shown, the computing node provided by the embodiments of the present invention may include: a first controller and a computing motherboard; the computing motherboard includes acceleration cards and retimers; different acceleration cards are interconnected through an Ethernet switching module, and the low - order channels of the serializer / deserializer interfaces of each acceleration card are all connected to the Ethernet switching module through retimers, and the high - order channels of at least one serializer / deserializer interface of the acceleration card are connected to the Ethernet switching module through retimers; the first controller is used to configure the working mode of the retimer according to the signal rate of the acceleration card.

[0032] In the embodiments of the present invention, a computing node may be a server or other computing devices.

[0033] The acceleration card includes a circuit structure for implementing relevant data operations, which may specifically be presented as: a Graphics Processing Unit (GPU), a Field - Programmable Gate Array (FPGA), etc.

[0034] As Figure 2As shown, in the computing node provided by the embodiment of the present invention, all the serializer / deserializer signals in all the lower eight channels (S1L - S7L) of the accelerator card and the higher eight channels (S1H) of the first serializer / deserializer interface can also be all connected to the Ethernet switch module, and each serializer / deserializer signal is connected to the Ethernet switch module through a retimer ( Figure 2 The retimers 0 - 11 shown). Figure 2 In, the connection lines between the accelerator card and the retimer, the dotted lines represent x2 links, and the solid lines represent x4 links.

[0035] In the embodiment of the present invention, an Open Compute Project (OCP) Accelerator Module (OAM) can be used to install the accelerator card to achieve the construction of a heterogeneous accelerator card cluster. In a specific implementation, the computing motherboard of the embodiment of the present invention can use a Universal Baseboard (UBB) to install the accelerator card and the peripheral circuits, deploy multiple OCP Accelerator Modules on the universal baseboard, and install the accelerator card in the card slot of the OCP Accelerator Module, and realize the interconnection topology between the accelerator cards based on the traces on the universal baseboard. In addition, the computing motherboard can also include power supply, heat dissipation, management interfaces, etc. provided on the universal baseboard.

[0036] In the embodiment of the present invention, the Ethernet switch module can be a switch located inside the computing node or a switch located outside the computing node. According to the interface requirements, the interconnection between the accelerator cards of the computing node can be realized through one or more Ethernet switch modules, and multiple Ethernet switch modules can be located in different switches or in the same switch. The Ethernet switch module is used to configure an address mapping table according to the address information of the connected accelerator cards, and thus perform data transmission between any two accelerator cards according to the address mapping table.

[0037] The accelerator card can be connected to the optical interface (such as a Quad Small Form-factor Pluggable (QSFP) interface) of the Ethernet switch module through optical fiber or copper cable.

[0038] Figure 2 Only 4 accelerator cards and 2 Ethernet switch modules are shown as examples in, and in actual applications, more or fewer accelerator cards and the number of Ethernet switch modules can be selected according to the computing node provided by the embodiment of the present invention. In some optional implementation manners of the embodiment of the present invention, a computing node can include 8 accelerator cards. Figure 2 The Ethernet switch module 0 and the Ethernet switch module 1 shown can be located in the same switch or in different switches. With the expansion of the number of accelerator cards and the selection of channel connection methods, more accelerator cards can be set to expand the interconnection topology of the accelerator cards.

[0039] As shown Figure 2 in the embodiments of the present invention, all serializer / deserializer interfaces of the acceleration cards are connected to the Ethernet switching module to achieve full interconnection of the serializer / deserializer interfaces between different acceleration cards. When performing vertical scaling (Scale up) of the computing resources of the computing node, through the computing node provided by the embodiments of the present invention, since the interconnection method between different acceleration cards is that each serializer / deserializer interface is interconnected through the Ethernet switching module, the number of acceleration cards can be flexibly adjusted, which is convenient for the vertical scaling of the computing node.

[0040] In some other alternative embodiments of the present invention, the Ethernet switching module used for interconnection between acceleration cards can also be used for full interconnection of serializer / deserializer interfaces between acceleration cards across hosts. At this time, the Ethernet switching module can configure an address mapping table according to the address information of the acceleration cards located in multiple hosts, and thus perform communication between acceleration cards within the same computing node and communication between acceleration cards across hosts according to the address mapping table. When performing horizontal scaling (Scale out) of the computing resources of the computing node, the acceleration cards on different computing nodes achieve cross-host communication through this full interconnection form, and can also flexibly expand the acceleration card interconnection topology.

[0041] Therefore, compared with the traditional acceleration card interconnection method, the computing node provided by the embodiments of the present invention is convenient for realizing vertical and horizontal scaling of the computing system, solves the problem that the traditional acceleration card interconnection scheme is not easy to expand, and can also flexibly adjust the workload according to business requirements.

[0042] Considering that the routing from the acceleration card to the Ethernet switching module is relatively long, especially for the Ethernet switching module located in the external switch of the server, the computing node provided by the embodiments of the present invention is provided with a retimer to enhance the driving ability of the entire serializer / deserializer signal link. The retimer can adopt a physical layer retimer (PHY Retimer).

[0043] In the embodiments of the present invention, the first controller can be a baseboard management controller (BMC) in the computing node. Since the configurations of acceleration cards from different manufacturers and different models are different, the signal rates of different acceleration cards may be different. To further improve the communication efficiency between acceleration cards, in the embodiments of the present invention, the first controller configures the working mode of the retimer between the acceleration card and the Ethernet switching module. Therefore, the retimer adopted in the embodiments of the present invention needs to include a variety of different working modes to adapt to different signal rates.

[0044] In an embodiment of the present invention, the first controller configures the working mode of the retimer according to the signal rate of the acceleration card, which may include: the first controller determines the identification of the acceleration card according to the identification configuration circuit corresponding to the acceleration card, looks up the signal rate of the acceleration card according to the identification of the acceleration card, and configures the working mode of the retimer according to the signal rate of the acceleration card.

[0045] In practical applications, different identification circuits may be set on the board of the computing motherboard to represent the identifications of different acceleration cards. The identification circuit may include a pull-up circuit or a pull-down circuit. By connecting the identification circuit to the pin of the first controller, the first controller can read the identification of the acceleration card on the local computing node according to the identification circuit. The first controller looks up the signal rate of the acceleration card, which may be a truth table pre-stored in the first controller, and the truth table includes the correspondence between the identification of the acceleration card and the signal rate of the acceleration card.

[0046] In an embodiment of the present invention, the first controller configures the working mode of the retimer according to the signal rate of the acceleration card, which may include: when the signal rate of the acceleration card is the first rate, the first controller configures the working mode of the corresponding retimer as the GearBox mode; when the signal rate of the acceleration card is the second rate, the first controller configures the working mode of the corresponding retimer as the Retimer mode; the first rate is less than the second rate.

[0047] In some optional embodiments of the embodiment of the present invention, when the signal rate of the acceleration card is the first rate, the first controller configures the working mode of the corresponding retimer as the GearBox mode, which may include: when the signal rate of the acceleration card is the first rate, the first controller configures the interface of the retimer corresponding to the acceleration card as the GearBox mode to perform variable-speed processing on the signals of the serializer / deserializer interface by combining the signals of the serializer / deserializer interface.

[0048] By configuring the working mode of the retimer according to the signal rate of the acceleration card by the first controller in the computing node provided by the embodiment of the present invention, not only can the acceleration card signals with a lower rate be converted into a higher rate for transmission, but also the problem of adapting different signal rate acceleration cards on the same computing motherboard can be solved.

[0049] For example, through the GearBox mode of the retimer, two signals of the acceleration card can be combined into one (for example, x8 is combined into x4), so that the rate of the output signal becomes twice the rate of the input signal. Then, in some optional embodiments of the embodiment of the present invention, performing variable-speed processing on the signals of the serializer / deserializer interface by combining the signals of the serializer / deserializer interface may include: combining two signals of the serializer / deserializer interface into one to change the signal rate of the serializer / deserializer interface to the second rate.

[0050] Taking two commonly used graphics processors as an example, one has a signal rate of 56 Gbps and the other has a signal rate of 112 Gbps. If the computing node provided by the embodiment of the present invention uses an acceleration card with a signal rate of 56 Gbps, the retimer connected to the serializer / deserializer interface of the acceleration card is set to the gearbox mode through the first controller, and then two groups of 56 Gbps can be combined into a group of 112 Gbps signals through the retimer, and 112 Gbps is used for transmission at the other end of the retimer. If the computing node provided by the embodiment of the present invention uses an acceleration card with a signal rate of 112 Gbps, the retimer connected to the serializer / deserializer interface of the acceleration card is set to the retimer mode through the first controller, and the requirement for 112 Gbps transmission can be achieved.

[0051] The computing node provided by the embodiment of the present invention includes a first controller and a computing mainboard. The computing mainboard includes acceleration cards and retimers. Different acceleration cards are interconnected through an Ethernet switching module, and the low-order channels of each serializer / deserializer interface of the acceleration cards are all connected to the Ethernet switching module through retimers. The high-order channels of at least one serializer / deserializer interface of the acceleration cards are connected to the Ethernet switching module through retimers, realizing an architecture with full interconnection of communication interfaces between acceleration cards, enabling direct connection between any two acceleration cards, improving the communication bandwidth between any two acceleration cards, and at the same time, the number of acceleration cards can be flexibly expanded, facilitating the vertical and horizontal expansion of the computing system, solving the problem that the traditional acceleration card interconnection scheme is not easy to expand, and can also flexibly adjust the workload according to the service requirements. On this basis, by configuring the working mode of the retimer according to the signal rate of the acceleration card through the first controller, different models of acceleration cards can be adapted to meet the high-speed transmission requirements in the computing system.

[0052] Applying the computing node provided by the embodiment of the present invention can not only achieve high-speed interconnection between acceleration cards within the computing node, but also achieve high-speed interconnection between acceleration cards of different computing nodes, solve the problem that the acceleration card topology in the traditional interconnection scheme is not easy to expand, and can also avoid the bandwidth bottleneck caused by the sharing of the in-board interconnection link. At the same time, by ensuring the driving ability of the serializer / deserializer signal through the retimer, it can ensure that any two acceleration cards can communicate at the maximum signal transmission rate, meeting the high-speed transmission requirements of a large amount of data between multiple acceleration cards.

[0053] Specifically, the computing node provided by the embodiments of the present invention achieves high bandwidth. The serializer / deserializer interfaces between different accelerator cards are fully interconnected, enabling each accelerator card to be directly connected to other accelerator cards. In theory, it can provide a bandwidth increase proportional to the number of accelerator cards. For example, in the training of large-scale artificial intelligence models, during data parallel training, the model parameters and gradient data are large. The fully interconnected architecture of accelerator cards provided by the embodiments of the present invention can meet the high-speed transmission requirements of a large amount of data between multiple accelerator cards, avoiding the bandwidth bottleneck caused by link sharing in the internal interconnection of accelerator cards within the computing node.

[0054] Moreover, the computing node provided by the embodiments of the present invention also has a low-latency effect. In the fully interconnected topology of accelerator cards provided by the embodiments of the present invention, data only needs to hop from one accelerator card to another, without intermediate transfer and queuing waiting, which can significantly reduce the transmission latency. In the pipeline parallelism of model parallel training, it is possible to reduce the idle computing resources caused by latency.

[0055] The computing node provided by the embodiments of the present invention has high flexibility. The fully interconnected topology of accelerator cards provided by the embodiments of the present invention allows direct communication between any two accelerator cards, with free selection of data transmission paths, which can be dynamically adjusted according to the real-time workload and data flow. In the traditional on-board interconnection scheme of accelerator cards, the fixed links limit the data transmission paths and have poor flexibility. For example, when dealing with complex multi-task workloads, the data interaction patterns of different tasks are different. The fully interconnected topology of accelerator cards provided by the embodiments of the present invention can adjust the communication paths according to needs and optimize data transmission.

[0056] The computing node provided by the embodiments of the present invention has high scalability. As the computing power demand increases and when it is necessary to expand the number of accelerator cards, the fully interconnected topology of accelerator cards provided by the embodiments of the present invention can easily handle it, just by adding new accelerator cards and connecting them to the fully interconnected topology of accelerator cards. In contrast, the traditional on-board interconnection scheme of accelerator cards is limited by the physical space and wiring resources within the accelerator card board, and has limited expansion ability. For example, when building a large-scale intelligent computing center, the fully interconnected topology of accelerator cards provided by the embodiments of the present invention can support a large number of accelerator card clusters to achieve powerful computing power expansion.

[0057] The computing node provided by the embodiments of the present invention has high fault tolerance. In the fully interconnected topology of accelerator cards provided by the embodiments of the present invention, even if some links fail, the data can still be transmitted through other normal links, and the computing node can still work normally, with strong fault tolerance. In the traditional on-board interconnection scheme of accelerator cards, a key link failure may cause communication interruption of some accelerator cards. For example, in long-running artificial intelligence computing tasks, link failures are inevitable. The fully interconnected topology of accelerator cards provided by the embodiments of the present invention can ensure that the system continues to run when a failure occurs without affecting the overall task progress.

[0058] The computing node provided by the embodiment of the present invention has better collaborative working ability. The fully interconnected topology of the acceleration cards provided by the embodiment of the present invention enables each acceleration card to work together more efficiently, quickly share data and exchange information, and improve the overall performance and operation efficiency of the system. In multi-modal data processing, different types of data may require different modules to process collaboratively. The fully interconnected topology of the acceleration cards provided by the embodiment of the present invention helps each acceleration card to quickly interact data and achieve the efficient fusion and processing of multi-modal data.

[0059] Figure 3 It is a schematic structural diagram of another computing node provided by the embodiment of the present invention.

[0060] The computing node provided by the embodiment of the present invention meets the high-speed transmission requirements of the acceleration card signals by setting retimers between the acceleration cards and the Ethernet switching module. On this basis, in some optional embodiments of the embodiment of the present invention, one retimer can be connected to at least two acceleration cards.

[0061] As Figure 3 shown, taking acceleration card 1 and acceleration card 2 as examples, acceleration card 1 and acceleration card 2 can share a group of retimers (retimer 0 to retimer 7), and the channels of one retimer are allocated for two acceleration cards to use. If a retimer includes 16 channels, then channels 0 to 3 (CH0-CH3) can be connected to acceleration card 1, and channels 8 to 11 (CH8-CH11) can be connected to acceleration card 2. In practical applications, one retimer can be set to connect two or more acceleration cards.

[0062] By connecting at least two acceleration cards through one retimer, the redundancy of the retimer can be achieved, the impact on the system when the retimer fails can be reduced, and the reliability of the system can be improved.

[0063] In the embodiment of the present invention, in order to further reduce the loss of the acceleration card interconnection link and improve the transmission rate of the acceleration card interconnection, each serializer / deserializer interface of the acceleration card can be connected to a cable tray through a bus, so as to be connected to the network port of the Ethernet switching module based on the cable tray.

[0064] Since the transmission trace between the acceleration card and the switch is relatively long, in related solutions, a network card is usually used to perform protocol transmission on the serializer / deserializer signals of the acceleration card and then transmit them to the switch through a network cable, that is, convert the serializer / deserializer signals into a form suitable for long-distance transmission. However, this conversion process also affects the transmission efficiency. Therefore, in the computing system provided by the embodiment of the present invention, a cable tray is used to connect the serializer / deserializer interface of the acceleration card and the Ethernet switching module, without passing through the network card conversion, shortening the transmission trace between the acceleration card and the Ethernet switching module.

[0065] In practical applications, the cable rack can be inserted into the common baseboard of the computing mainboard, so that the serializer / deserializer interface of the acceleration card can be connected to the cable rack through the on-board trace, and then the optical interface of the Ethernet switch module can be connected through the cable plugged on the cable rack.

[0066] It should be noted that on the basis of using the cable rack to shorten the transmission trace between the acceleration card and the Ethernet switch module, the connection method of connecting the serializer / deserializer interface of the acceleration card provided in the embodiment of the present invention to the Ethernet switch module through the retimer can effectively utilize the retimer to ensure the driving ability of the serializer / deserializer signal, while in the related art, only using the retimer cannot achieve the effect of ensuring the driving ability of the serializer / deserializer signal without passing through the network card.

[0067] Figure 4 It is a connection schematic diagram of a field replaceable unit provided in an embodiment of the present invention.

[0068] In the embodiment of the present invention, each serializer / deserializer interface of the acceleration card can also be connected to the cable rack through a high-speed connector; at least one high-speed connector provides pins for connecting the baseboard management controller of the computing node to the field replaceable unit of the computing mainboard.

[0069] As Figure 3 shown, a group of retimers can be connected to the cable rack through a high-speed connector, and then connected to the Ethernet switch module. Select the specification of the high-speed connector according to the number of pins required by this group of retimers. For the convenience of management by the baseboard management controller, the pins of one of the high-speed connectors can be used as the pins for the baseboard management controller to connect to the field replaceable unit board of the computing node, that is Figure 3 a group of pins of the 8×10 connector in

[0070] As Figure 4 shown, by Figure 3 connecting the pins of the 8×10 connector (PHD 8X10) shown to the pads (PAD) of the field replaceable unit board, it can be used to transmit the P3V3 standby voltage (P3V3_STBY), write protection signal (FM_FRU_WP_R), system management data signal (SMB_I2C_FRU_R_SDA0), system management clock signal (SMB_I2C_FRU_R_SCL0), etc. between the baseboard management controller and the field replaceable unit memory U2.

[0071] In practical applications, the baseboard management controller reads the signals of the field replaceable unit board through the pins of the high-speed connector to determine the position of the computing node in the cluster (whole cabinet), so as to display it on the monitoring interface when performing the monitoring task of the computing node.

[0072] In the embodiment of the present invention, the baseboard management controller and the first controller may be the same device.

[0073] Figure 5 It is a schematic structural diagram of a monitoring system for a computing motherboard provided by an embodiment of the present invention; Figure 6 It is a schematic structural diagram of a first monitoring subsystem provided by an embodiment of the present invention; Figure 7 It is a schematic structural diagram of a second monitoring subsystem provided by an embodiment of the present invention; Figure 8 It is a schematic structural diagram of a third monitoring subsystem provided by an embodiment of the present invention.

[0074] To adapt to the structure of the computing motherboard in the computing node provided by the embodiment of the present invention, the embodiment of the present invention also provides a monitoring solution for the computing motherboard.

[0075] In the embodiment of the present invention, the computing motherboard may further include a first integrated circuit bus manager U50, a second integrated circuit bus manager U96, a third integrated circuit bus manager U32, and sensors; the first integrated circuit bus manager U50, the second integrated circuit bus manager U96, and the third integrated circuit bus manager U32 are respectively connected to the baseboard management controller; the first integrated circuit bus manager U50 is used for the baseboard management controller to access the retimer to obtain the status parameters of the retimer; the second integrated circuit bus manager U96 is used for the baseboard management controller to access the acceleration card to obtain the status parameters of the acceleration card; the third integrated circuit bus manager U32 is connected to the sensors and is used for the baseboard management controller to access the sensors to obtain the status parameters of the acceleration card or the status parameters of the retimer.

[0076] As Figure 5 shown, in the computing node provided by the embodiment of the present invention, the baseboard management controller (Baseboard Management Controller, BMC) can be connected to the motherboard (MB) through an Unbuffered Dual In-Line Memory Modules or unregistered Dual In-Line Memory Modules (UDIMM), and is connected to the backplane connector J26 on the computing motherboard through the backplane connector J27 (EXMAX) on the motherboard to connect the first integrated circuit bus manager U50, the second integrated circuit bus manager U96, and the third integrated circuit bus manager U32.

[0077] In the embodiment of the present invention, the baseboard management controller and the first controller may be the same device.

[0078] For the Inter-Integrated Circuit (I2C) link of the computing motherboard, three I2C links can be output from the baseboard management controller to connect to the computing motherboard for monitoring.

[0079] Denote the monitored components connected to the first I2C bus manager U50 as the first monitoring subsystem, the monitored components connected to the second I2C bus manager U96 as the second monitoring subsystem, and the monitored components connected to the third I2C bus manager U32 as the third monitoring subsystem.

[0080] The first I2C bus manager U50, the second I2C bus manager U96, and the third I2C bus manager U32 can all adopt 9617.

[0081] The I2C 12 link of the baseboard management controller can be connected to the first I2C bus manager U50.

[0082] As Figure 6 shown, the first I2C bus manager U50 can connect multiple retimers (the retimers 0 to 15 shown) through the I2C bus switch U30. The I2C bus switch U30 can adopt CA9546. The baseboard management controller can monitor and manage 4 retimers respectively through each channel of the I2C bus switch U30, for accessing the temperature information of the retimers, etc., and remotely upgrading the retimers through the I2C channel. Figure 6 shown, the first I2C bus manager U50 can connect multiple retimers (the retimers 0 to 15 shown) through the I2C bus switch U30. The I2C bus switch U30 can adopt CA9546. The baseboard management controller can monitor and manage 4 retimers respectively through each channel of the I2C bus switch U30, for accessing the temperature information of the retimers, etc., and remotely upgrading the retimers through the I2C channel.

[0083] The I2C 14 link of the baseboard management controller can be connected to the second I2C bus manager U96.

[0084] As Figure 7 shown, the second I2C bus manager U96 can connect multiple accelerator cards (the accelerator cards 0 to accelerator card 3 shown, with interfaces J1 / J2, J3 / J4, J5 / J6, J7 / J8 respectively) through the I2C bus switch U31. The I2C bus switch U31 can adopt CA9546. The baseboard management controller can connect an accelerator card through each channel of the I2C bus switch U31 respectively to realize the monitoring and management of the accelerator card, and can be used to obtain various status information of the accelerator card. Figure 7 shown, the second I2C bus manager U96 can connect multiple accelerator cards (the accelerator cards 0 to accelerator card 3 shown, with interfaces J1 / J2, J3 / J4, J5 / J6, J7 / J8 respectively) through the I2C bus switch U31. The I2C bus switch U31 can adopt CA9546. The baseboard management controller can connect an accelerator card through each channel of the I2C bus switch U31 respectively to realize the monitoring and management of the accelerator card, and can be used to obtain various status information of the accelerator card.

[0085] The I2C 15 link of the baseboard management controller can be used to connect to the second integrated circuit bus manager U96. In addition to being connected to sensors, the second end of the second integrated circuit bus manager U96 can also be connected to a power controller (Power Monitor), a field replaceable unit (FRU), a complex programmable logic device (Complex Programmable Logic Device, CPLD), a firmware board of a cable tray, a clock buffer (CLKBUFFER), and an input / output expander on the computing motherboard.

[0086] As Figure 8 shown, the I2C 15 link of the baseboard management controller can be connected to the power controller PU61, the field replaceable unit memory U2, the complex programmable logic device U1, the field replaceable unit U43 of the cable tray, 2 clock buffers (U28, U29), and 3 input / output expanders (U54, U33, U34) on the computing motherboard. The input / output expander can use CA9555.

[0087] Among them, the board power controller PU61 is used to monitor the 54V power consumption input of the computing motherboard.

[0088] The clock buffer can be controlled by the baseboard management controller to change the state of OE by rewriting the register, thereby controlling the clock output. By default, the baseboard management controller does not operate on the clock buffer, and at this time the clock is default output enabled.

[0089] The field replaceable unit memory U2 is used to store the board information of the computing motherboard, etc.

[0090] The sensor can be a temperature sensor, which is used to monitor the temperature of the computing motherboard. In addition to the main body for temperature monitoring, it can also include 2 remote triodes for temperature monitoring.

[0091] The field replaceable unit board U4 of the cable tray is used to store the information of the cable tray, etc.

[0092] The input / output expander U33 is used for the baseboard management controller to read the identification of the acceleration card (OAM ID), the total line routing identification (PCIE RT ID), the frequency modulation type identification (FM_SCALE_TYPE_ID), the physical layer routing Ethernet switch identification (PHY_RT_ETH_SW_ID), and the write protection signal of the field replaceable unit (FRU_WP), etc.

[0093] The input / output expander U34 is used for the baseboard management controller to read the liquid leakage detection result of the computing motherboard, the acceleration card presence detection signal, etc.

[0094] The input / output expander U54 is used for the baseboard management controller to control the power consumption standards of the acceleration cards (acceleration cards 0 to 3).

[0095] Figure 9 It is a schematic structural diagram of the universal asynchronous receiver / transmitter management unit of a computing motherboard provided by an embodiment of the present invention; Figure 10 It is a schematic diagram of the debug control unit of a computing motherboard provided by an embodiment of the present invention.

[0096] As Figure 9 shown, in the computing node provided by the embodiment of the present invention, the computing motherboard may further include an external debug interface and a serial port multiplexing switch corresponding to each acceleration card one by one; the first channel of the serial port multiplexing switch is used for serial communication between the baseboard management controller and the acceleration card; the second channel of the serial port multiplexing switch is used for serial communication between the external debug interface and the acceleration card; the priority of the second channel of the serial port multiplexing switch is higher than that of the first channel of the serial port multiplexing switch.

[0097] As Figure 9 shown, on the computing motherboard provided by the embodiment of the present invention, the universal asynchronous receiver / transmitter management unit can be connected to an external serial port tool through the external debug interface J52, or can also be connected to the baseboard management controller. The switching between the two connection methods can be realized through a serial port multiplexing switch (such as Figure 7 the U38, U41, U42, U46 shown).

[0098] The external serial port tool connected to the external debug interface J52 can adopt a micro universal serial bus connector (MicroUSB).

[0099] The serial port multiplexing switch can adopt a multiplexer (MUX). Its control logic is that when the external serial port is present, the serial port multiplexing switch switches to the second channel to realize the management of the acceleration card through the serial port.

[0100] When the external serial port is not present, the serial port multiplexing switch switches to the first channel of the baseboard management controller. At this time, the baseboard management controller can access the open computing accelerator module through the serial port or the interface conversion bridge U5. The baseboard management controller switches to access the corresponding open computing accelerator module according to the serial number of the open computing accelerator module to be accessed. The interface conversion bridge U5 can adopt CH347.

[0101] When inserting the micro universal serial bus connector, the second channel obtains the first priority, and the 4-channel universal asynchronous receiver / transmitter signals are connected to the serial port multiplexing switch through the interface conversion bridge U64. The interface conversion bridge U64 can adopt CP2108. Each CP2108 supports simultaneous access to 4 open computing accelerator modules and can access the acceleration card through the hardware link.

[0102] In some alternative embodiments of the embodiments of the present invention, the serial port multiplexing switch may be a multiplexing switch of a programmable logic device; a first end of the multiplexing switch is connected to a first general-purpose input / output port of the programmable logic device, and the other end of the first general-purpose input / output port is connected to a baseboard management controller; a second end of the multiplexing switch is connected to a second general-purpose input / output port of the programmable logic device, and the other end of the second general-purpose input / output port is connected to an external debugging interface; a third end of the multiplexing switch is connected to a third general-purpose input / output port of the programmable logic device, and the other end of the third general-purpose input / output port is connected to a low-level debugging signal interface of the acceleration card; a fourth end of the multiplexing switch is connected to a fourth general-purpose input / output port of the programmable logic device, and the other end of the fourth general-purpose input / output port is connected to a high-level debugging signal interface of the acceleration card.

[0103] An embodiment of the present invention provides a debugging control unit of a computing motherboard as Figure 10 shown. The computing motherboard is designed with two ways to correct errors (Debug) for the acceleration card.

[0104] The programmable logic device may be Figure 10 the complex programmable logic device U1 shown.

[0105] The computing motherboard is provided with an extended debugging port (XDP) connector. The error correction signals on the extended debugging port connector are connected to the programmable logic device, and the programmable logic device switches to 8 groups of Joint Test Action Group (JTAG) signals of 4 acceleration cards as a multiplexer, and the acceleration card can be directly operated through an external serial port tool.

[0106] The computing motherboard is also provided with a channel for correcting errors of the acceleration card through the baseboard management controller: the upstream universal serial bus signal of the baseboard management controller is connected to the interface conversion bridge U5, and the output JTAG signal is connected to the general-purpose input / output port 0 of the complex programmable logic device U1 for transparent transmission, so as to realize register dump, memory dump and debugging access of the acceleration card.

[0107] In the embodiments of the present invention, the programmable logic device is used to control the serial port multiplexing switch to switch channels. When the external serial port is not in place, the programmable logic device switches the serial port multiplexing switch to the first channel, and at this time, the acceleration card can be directly accessed through the external serial port tool; when the external serial port is in place, the programmable logic device switches the serial port multiplexing switch to the second channel, and at this time, the baseboard management controller controls the programmable logic device to switch to any acceleration card by sending a command to the programmable logic device according to the serial number of the acceleration card to be accessed.

[0108] Figure 11A schematic diagram of the system clock unit of a computing motherboard provided by an embodiment of the present invention.

[0109] In the computing node provided by the embodiment of the present invention, the clock signal input end of the acceleration card can be connected to the clock signal output end of the central processing unit of the computing node.

[0110] That is to say, the clock signal of the acceleration card can be sourced from a set of clock signals transmitted upstream by the central processing unit. As Figure 11 shown, the reference clock 0 of the central processing unit 0 provides clocks for acceleration cards 0 to 3 respectively after passing through the clock buffer of the computing motherboard. The reference clock 0 can be a 100 MHz reference clock.

[0111] To ensure the normal operation of the physical layer retimer, as Figure 11 shown, in the computing node provided by the embodiment of the present invention, the computing motherboard may further include a first crystal oscillator Y4 and a first clock buffer U29; the clock signal input end of the first clock buffer U29 is connected to the first crystal oscillator Y4, and the clock signal output end of the first clock buffer U29 is connected to the clock signal input end of the retimer. The first crystal oscillator Y4 can be a 156.25 MHz active crystal oscillator.

[0112] Figure 12 A schematic diagram of the single-board power-on and power-off timing of a computing motherboard provided by an embodiment of the present invention.

[0113] Applying the computing node provided by the embodiment of the present invention, the single-board power-on and power-off timing of the computing motherboard can be as Figure 12 shown, and the control of the overall board timing can be realized through the complex programmable logic device U1 of the computing motherboard to ensure the normal operation of all devices on the computing motherboard.

[0114] Table 1 is Figure 12 a signal description table of the single-board power-on and power-off timing of the computing motherboard shown as follows.

[0115] Table 1

[0116] Among them, P54V_PSU represents the 54V power signal, UBB BD represents the universal backplane backplane, PDB represents the power board, P12V_STBY represents the 12V standby voltage, UBB VR represents the universal backplane power supply, P5V_STBY represents the 5V standby voltage, P3V3_STBY represents the 3.3V standby voltage, P1V8_STBY represents the 1.8V standby voltage, CPLD REDAY represents the signal that the complex programmable logic device is ready, SW CPLD represents the switch of the complex programmable logic device, UBB CPLD represents the complex programmable logic device of the computing motherboard, POWER_BTN represents the power switch, P54V_OAM_EN[0:3] represents the 54V voltage enable signal of the acceleration card, UBB EFUSE represents the non-volatile memory on the computing motherboard, P54V_OAM[0:3] represents the 54V voltage of the acceleration card, PWRGD_P54V_OAM[0:3] represents the signal that the 54V voltage of the acceleration card is ready, P12V_OAM_EN[0:3] represents the 12V voltage enable signal of the acceleration card, P12V_OAM[0:3] represents the 12V voltage of the acceleration card, PWRGD_P12V_OAM[0:3] represents the signal that the 12V voltage of the acceleration card is ready, P3V3_OAM_EN, P3V3_OAM_EN[0:3] represents the 3.3V voltage enable signal of the acceleration card, P3V3_OAM represents the 3.3V voltage signal of the acceleration card, PWRGD_P3V3_OAM represents the signal that the 3.3V voltage of the acceleration card is ready, P3V3_OAM_EN[0:3] represents the 3.3V voltage enable signal of the acceleration card, PWRGD_P3V3_OAM[0:3] represents the signal that the 3.3V voltage of the acceleration card is ready, CLK_BUFF represents the clock buffer signal, EN represents the enable signal, P1V8_PHY_EN[A:B] represents the 1.8V voltage enable signal of the physical layer retimer, P1V8_PHY[A:B] represents the 1.8V voltage signal of the physical layer retimer, PWRGD_P1V8_PHY[A:B] represents the signal that the 1.8V voltage of the physical layer retimer is ready, BMC represents the baseboard management controller, PHY RT represents the physical layer retimer, I2C_FW represents the I2C firmware, P0V75_PHY_EN[0:15] represents the 0.75V voltage enable signal of the physical layer retimer, P0V75_PHY[0:15] represents the 0.75V voltage signal of the physical layer retimer, PWRGD_P0V75_PHY[0:15] represents the 0.The 75V voltage ready signal, P1V0_PHY_EN[0:7] represents the 1V voltage enable signal of the physical layer retimer, P1V0_PHY[0:7] represents the 1V voltage signal of the physical layer retimer, PWRGD_P1V0_PHY[0:7] represents the 1V voltage ready signal of the physical layer retimer, PHY RETIMER represents the physical layer retimer, RST represents the initialization signal, OAM represents the open computing accelerator module, GPU_HOST_PWRGD[0:3] represents the host power ready signal of the accelerator card, OAM_PVREF[0:3] represents the reference voltage signal of the open computing accelerator module, GPU_MODULE_PWRGD[0:3] represents the module power ready signal of the accelerator card, UBB_PWR_READY represents the power ready signal of the common backplane, and PERST represents the PCIe device reset signal.

[0117] In Figure 12 corresponding to signal s32, after all signals on the computing motherboard are stable for 500 ms, the host power ready signal is pulled high. Corresponding to signal s34, the power ready signal is pulled high after the power ready signal [0:7] of the first accelerator card is high for 50 ms.

[0118] An embodiment of the present invention further provides a computing system, including: a plurality of accelerator cards and an Ethernet switch module; different accelerator cards are interconnected through the Ethernet switch module, and the low channels of the serializer / deserializer interfaces of each accelerator card are connected to the Ethernet switch module through the retimer on the computing motherboard where it is located, and the high channels of at least one serializer / deserializer interface of the accelerator card are connected to the Ethernet switch module through the retimer; the working mode of the retimer corresponds to the signal rate of the accelerator card; the Ethernet switch module is configured to configure the address mapping table of the computing system according to the accelerator card address information of each accelerator card, and perform data transmission between different accelerator cards according to the address mapping table.

[0119] The computing system provided by the embodiment of the present invention connects the serializer / deserializer interfaces of the acceleration cards to the Ethernet switching module. The Ethernet switching module is used to configure the address mapping table of the computing system according to the acceleration card address information of each acceleration card, and perform data transmission between different acceleration cards according to the address mapping table, realizing a computing system in which any two acceleration cards are interconnected through the Ethernet switching module and all serializer / deserializer interfaces of the acceleration cards are interconnected, enabling direct connection between different acceleration cards both within and between boards. Therefore, the number of acceleration cards can be flexibly expanded, and the workload can be flexibly adjusted according to service requirements, solving the problem that traditional interconnection solutions are not easy to expand, and also avoiding the bandwidth bottleneck caused by the sharing of the internal board interconnection link. At the same time, by using a retimer to ensure the driving ability of the serializer / deserializer signal, it can ensure that any two acceleration cards can communicate at the maximum signal transmission rate, meeting the high-speed data transmission requirements between multiple acceleration cards.

[0120] The embodiment of the present invention also provides a switch, which has an Ethernet switching module; the Ethernet switching module is connected to multiple acceleration cards, and the low channels of each serializer / deserializer interface of the acceleration cards are connected to the Ethernet switching module through the retimers on the computing main board where they are located, and the high channels of at least one serializer / deserializer interface of the acceleration cards are connected to the Ethernet switching module through the retimers; the working mode of the retimer corresponds to the signal rate of the acceleration card; the Ethernet switching module is used to configure the address mapping table of the computing system according to the acceleration card address information of each acceleration card, and perform data transmission between different acceleration cards according to the address mapping table.

[0121] For the specific implementation manner of the switch provided by the embodiment of the present invention, reference can be made to the above-mentioned computing node and computing system embodiments.

[0122] The embodiment of the present invention provides a control method for a computing system, which is applied to an Ethernet switching module and includes: obtaining the address information of multiple acceleration cards through an Ethernet bus; configuring the address mapping table of the computing system according to the address information of each acceleration card; and performing data transmission between different acceleration cards according to the address mapping table.

[0123] Among them, the low channels of each serializer / deserializer interface of the acceleration cards are connected to the Ethernet switching module through the retimers on the computing main board where they are located, and the high channels of at least one serializer / deserializer interface of the acceleration cards are connected to the Ethernet switching module through the retimers, and the working mode of the retimer corresponds to the signal rate of the acceleration card.

[0124] For the specific implementation manner of the control method for the computing system provided by the embodiment of the present invention, reference can be made to the above-mentioned computing node and computing system embodiments.

[0125] An embodiment of the present invention further provides a control device for a computing system, which is applied to an Ethernet switching module and includes: an acquisition unit for acquiring address information of multiple acceleration cards through an Ethernet bus; a configuration unit for configuring an address mapping table of the computing system according to the address information of each acceleration card; and a control unit for performing data transmission between different acceleration cards according to the address mapping table.

[0126] Wherein, the low channels of each serializer / deserializer interface of the acceleration card are all connected to the Ethernet switching module through a retimer on the computing mainboard where the acceleration card is located, and the high channels of at least one serializer / deserializer interface of the acceleration card are connected to the Ethernet switching module through a retimer, and the working mode of the retimer corresponds to the signal rate of the acceleration card.

[0127] For the specific implementation manner of the control device of the computing system provided by the embodiment of the present invention, reference can be made to the above-mentioned computing node and computing system embodiments.

[0128] An embodiment of the present invention further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above-mentioned embodiments of the control method of the computing system.

[0129] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any one of the above-mentioned embodiments of the control method of the computing system when running.

[0130] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0131] An embodiment of the present invention further provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above-mentioned embodiments of the control method of the computing system.

[0132] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above-mentioned embodiments of the control method of the computing system.

[0133] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0134] The above has introduced in detail a computing node, a computing system, and a control method, device, equipment, and medium provided by the present invention. Specific examples are used herein to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A computing node, characterized in that, Comprising: A first controller and a computing motherboard; The computing motherboard includes an acceleration card and a retimer; Different said acceleration cards are interconnected through an Ethernet switching module, and the low channels of each serializer / deserializer interface of the acceleration card are all connected to the Ethernet switching module through the retimer, and the high channels of at least one of the serializer / deserializer interfaces of the acceleration card are connected to the Ethernet switching module through the retimer; The first controller is used to configure the working mode of the retimer according to the signal rate of the acceleration card.

2. The computing node according to claim 1, wherein The first controller configures the working mode of the retimer according to the signal rate of the acceleration card, including: The first controller determines the identifier of the acceleration card according to the identifier configuration circuit corresponding to the acceleration card, looks up the signal rate of the acceleration card according to the identifier of the acceleration card, and configures the working mode of the retimer according to the signal rate of the acceleration card.

3. The computing node according to claim 1, wherein The first controller configures the working mode of the retimer according to the signal rate of the acceleration card, including: When the signal rate of the acceleration card is the first rate, the first controller configures the working mode of the corresponding retimer as the gearbox mode; When the signal rate of the acceleration card is the second rate, the first controller configures the working mode of the corresponding retimer as the retimer mode; The first rate is less than the second rate.

4. The computing node according to claim 3, wherein When the signal rate of the acceleration card is the first rate, the first controller configures the working mode of the corresponding retimer as the gearbox mode, including: When the signal rate of the acceleration card is the first rate, the first controller configures the interface of the retimer corresponding to the acceleration card as the gearbox mode, so as to perform variable-speed processing on the signal of the serializer / deserializer interface by merging the signals of the serializer / deserializer interface.

5. The computing node according to claim 3, characterized in that Performing variable-speed processing on the signal of the serializer / deserializer interface by merging the signals of the serializer / deserializer interface, including: Merging the signals of two serializer / deserializer interfaces into one path, so as to change the signal rate of the serializer / deserializer interface to the second rate.

6. The computing node according to claim 1, wherein One retimer is connected to at least two acceleration cards.

7. The computing node according to claim 1, wherein Each serializer / deserializer interface of the acceleration card is connected to a cable rack through a bus, so as to be connected to the network port of the Ethernet switching module based on the cable rack.

8. The computing node according to claim 7, characterized in that, Each serializer / deserializer interface of the acceleration card is connected to the cable rack through a high-speed connector; At least one of the high-speed connectors provides pins for connecting the baseboard management controller of the computing node to the field-replaceable unit of the computing motherboard.

9. The computing node according to claim 1, wherein The computing motherboard further includes a first integrated circuit bus manager, a second integrated circuit bus manager, a third integrated circuit bus manager, and a sensor; The first integrated circuit bus manager, the second integrated circuit bus manager, and the third integrated circuit bus manager are respectively connected to the baseboard management controller; The first integrated circuit bus manager is used for the baseboard management controller to access the retimer to obtain the status parameters of the retimer; The second integrated circuit bus manager is used for the baseboard management controller to access the acceleration card to obtain the status parameters of the acceleration card; The third integrated circuit bus manager is connected to the sensor and is used for the baseboard management controller to access the sensor to obtain the status parameters of the acceleration card or the status parameters of the retimer.

10. The computing node according to claim 1, wherein The computing motherboard further includes an external debugging interface and a serial port multiplexing switch corresponding to each acceleration card; The first channel of the serial port multiplexing switch is used for serial communication between the baseboard management controller and the acceleration card; The second channel of the serial port multiplexing switch is used for serial communication between the external debugging interface and the acceleration card; The priority of the second channel of the serial port multiplexing switch is higher than that of the first channel of the serial port multiplexing switch.

11. The computing node according to claim 10, wherein The serial port multiplexing switch is a multiplexing switch of a programmable logic device; The first end of the multiplexing switch is connected to the first general-purpose input / output port of the programmable logic device, and the other end of the first general-purpose input / output port is connected to the baseboard management controller; The second end of the multiplexing switch is connected to the second general-purpose input / output port of the programmable logic device, and the other end of the second general-purpose input / output port is connected to the external debugging interface; The third end of the multiplexing switch is connected to the third general-purpose input / output port of the programmable logic device, and the other end of the third general-purpose input / output port is connected to the low-level debugging signal interface of the acceleration card; The fourth end of the multiplexing switch is connected to the fourth general-purpose input / output port of the programmable logic device, and the other end of the fourth general-purpose input / output port is connected to the high-level debugging signal interface of the acceleration card.

12. The computing node according to claim 1, wherein The clock signal input end of the acceleration card is connected to the clock signal output end of the central processing unit of the computing node.

13. The computing node according to claim 1, wherein The computing motherboard further includes a first crystal oscillator and a first clock buffer; The clock signal input end of the first clock buffer is connected to the first crystal oscillator, and the clock signal output end of the first clock buffer is connected to the clock signal input end of the retimer.

14. A computing system, characterized in that, Including: Multiple acceleration cards and an Ethernet switch module; Different acceleration cards are interconnected through the Ethernet switch module, and the low-level channels of the serializer / deserializer interfaces of each acceleration card are all connected to the Ethernet switch module through the retimer on the computing motherboard where they are located, and the high-level channels of at least one of the serializer / deserializer interfaces of the acceleration card are connected to the Ethernet switch module through the retimer; The working mode of the retimer corresponds to the signal rate of the acceleration card; The Ethernet switch module is used to configure the address mapping table of the computing system according to the acceleration card address information of each acceleration card and perform data transmission between different acceleration cards according to the address mapping table.

15. A switch, characterized in that, Having an Ethernet switch module; The Ethernet switch module is connected to multiple acceleration cards, and the low channels of the serializer / deserializer interfaces of each acceleration card are connected to the Ethernet switch module through a retimer on the computing motherboard where the acceleration card is located. The high channel of at least one of the serializer / deserializer interfaces of the acceleration card is connected to the Ethernet switch module through the retimer; the working mode of the retimer corresponds to the signal rate of the acceleration card; The Ethernet switch module is used to configure the address mapping table of the computing system according to the acceleration card address information of each acceleration card, and perform data transmission between different acceleration cards according to the address mapping table.

16. A control method for a computing system, characterized in that, Applied to an Ethernet switch module, including: Obtaining the address information of multiple acceleration cards through an Ethernet bus; Configuring the address mapping table of the computing system according to the address information of each acceleration card; Performing data transmission between different acceleration cards according to the address mapping table; Wherein, the low channels of the serializer / deserializer interfaces of each acceleration card are connected to the Ethernet switch module through a retimer on the computing motherboard where the acceleration card is located. The high channel of at least one serializer / deserializer interface of the acceleration card is connected to the Ethernet switch module through the retimer, and the working mode of the retimer corresponds to the signal rate of the acceleration card.

17. A control device for a computing system, characterized in that, Including: An obtaining unit, configured to obtain the address information of multiple acceleration cards through an Ethernet bus; A configuration unit, configured to configure the address mapping table of the computing system according to the address information of each acceleration card; A control unit, configured to perform data transmission between different acceleration cards according to the address mapping table; Wherein, the low channels of the serializer / deserializer interfaces of each acceleration card are connected to the Ethernet switch module through a retimer on the computing motherboard. The high channel of at least one of the serializer / deserializer interfaces of the acceleration card is connected to the Ethernet switch module through the retimer, and the working mode of the retimer corresponds to the signal rate of the acceleration card.

18. A control device for a computing system, characterized in that, Including: A memory, configured to store a computer program; A processor, configured to implement the steps of the control method of the computing system as described in claim 16 when executing the computer program.

19. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the control method of the computing system as described in claim 16.

20. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the control method of the computing system as described in claim 16.

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