System on chip

Abstract

A system on chip is provided. The system on chip includes a bus including a data channel through which data is transmitted in at least one direction; and a main interface configured to receive first data from the data channel, perform a bit operation on the first data and second data input prior to the input of the first data, and determine an encoding operation for the first data based on a result of the bit operation; performing an encoding operation on the first data to obtain encoded data; and providing the encoded data and a transform signal indicating the encoding operation to the data channel.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0112251 filed in the Korean Intellectual Property Office on August 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosed embodiments relate to a system on a chip. Background Art

[0003] As the development of semiconductor process technology is concentrated on one chip, the system on chip (SoC) is in the form of a functional block with various existing functions (e.g., an intellectual property (IP) block). As electronic devices become lighter, simpler, and more functional, research on enhancing SoC integration and operating speed is also underway. As SoC integration and operating speed increase, power consumption is a developing area. When power consumption is high, the temperature of the chip rises, which may not only cause inoperability but also damage to the package, so the importance of low-power design in integrated SoCs is increasing. As one of the low-power design methods of SoC, clock gating technology is applied to the bus interface. By applying clock gating, power consumption can be improved by reducing the operation of devices within the bus interface. Summary of the invention

[0004] The present disclosure relates to systems on a chip. In general, in some aspects, the present disclosure implements a system on a chip that improves the efficiency of clock gating by reflecting data pattern characteristics before and after the data is processed.

[0005] In general, in some other aspects, the present disclosure implements a system on a chip that improves power consumption efficiency of all flip-flops in a data path.

[0006] In general, in some aspects, the present disclosure relates to a system on chip, comprising: a bus, including a data channel, through which data is sent in at least one direction; and a main interface, configured to: receive first data from the data channel, perform a bit operation on the first data and second data input before the input of the first data, determine an encoding operation for the first data based on a result of the bit operation; perform an encoding operation on the first data to obtain encoded data; and provide the encoded data and a transformation signal indicating the encoding operation to the data channel.

[0007] Some aspects of the present disclosure describe a system on chip, which includes: a bus, including a data channel, through which data is sent in at least one direction; and a slave interface, configured to: receive encoded data and a transformation signal from the data channel, the transformation signal indicating an encoding operation performed to obtain the encoded data, and perform a maintenance operation, an inversion operation, or a cyclic shift operation on the encoded data based on at least a portion of the encoded data and based on the transformation signal.

[0008] Some aspects of the present disclosure describe a system on chip, which includes: a master interface, configured to: perform a bit operation on first data and second data input before the input of the first data, perform an encoding operation on the first data based on the result of the bit operation to obtain encoded data, and output the encoded data and a transformation signal indicating the encoding operation; a bus, including: a data trigger, configured to latch the encoded data based on a clock signal, a clock gating circuit, configured to clock-gate the clock signal, and a data channel, configured to send the encoded data in at least one direction through the data trigger; and a slave interface, configured to: receive the encoded data and the transformation signal from the bus, and perform a decoding operation on the encoded data based on at least a portion of the encoded data and based on the transformation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a configuration of an example of a system on chip (SoC) according to some embodiments.

[0010] Figure 2 is a diagram illustrating an example of buses and interfaces of a SoC according to some embodiments.

[0011] Figure 3 is a diagram illustrating an example of a data channel according to some embodiments.

[0012] Figure 4 is a block diagram of an example of a data encoding circuit according to some implementations.

[0013] Figure 5 is a block diagram of an example of a data decoding circuit according to some implementations.

[0014] Figure 6 is a circuit diagram of an example of a data encoding circuit according to some implementations.

[0015] Figure 7 is a circuit diagram of an example of a data decoding circuit according to some embodiments.

[0016] Figure 8 is a diagram illustrating an example of an encoding operation of a data encoding circuit according to some embodiments.

[0017] Figures 9 and 10 is a diagram illustrating an example of an encoding operation of a data encoding circuit according to some embodiments.

[0018] Figure 11 to Figure 12 is a diagram illustrating an example of a decoding operation of a data decoding circuit.

[0019] Fig.13 is a diagram illustrating an example of a data encoding circuit according to some embodiments.

[0020] Fig.14 is a diagram illustrating an example of a data decoding circuit according to some embodiments.

[0021] Fig.15 is a diagram illustrating an example of a data encoding circuit according to some embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, with reference to the accompanying drawings, various examples of the present disclosure will be described in detail, and thus ordinary technicians can easily practice various examples in the technical field to which the present disclosure belongs. The present disclosure can be implemented in many different forms and is not limited to the examples described herein.

[0023] In order to clearly describe the disclosure with reference to the accompanying drawings, components irrelevant to the description are omitted, and like reference numerals are designated to like components throughout the specification.

[0024] In addition, for the convenience of description, the size and thickness of each component shown in the drawings are arbitrarily represented, and therefore the present disclosure is not necessarily limited to the drawings. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thickness of some layers and regions is exaggerated for the convenience of description.

[0025] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “include” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0026] Figure 1 is a block diagram illustrating a configuration of a system on chip (SoC) according to some embodiments.

[0027] Reference Figure 1 , SoC 1a is an electronic system integrated into a single chip and can perform various functions by including a plurality of functional blocks having various functions.

[0028] The SoC 1 a may include a processor 10P, a memory 10Mem, a plurality of intellectual property (IP) devices 10 a to 10 c (sometimes referred to as IP blocks), and a bus (or system bus) BUS.

[0029] The processor 10P may include at least one of a microprocessor, a digital signal processor, and a logic element that performs functions similar to those performed by the microprocessor and the digital signal processor.

[0030] The memory 10Mem may be a storage device that stores data and / or instructions, etc. Although not clearly shown, the memory 10Mem is an operation memory for the operation of the processor 10P, and may include a high-speed dynamic random access memory (DRAM) and / or a static random access memory (SRAM), etc., according to an embodiment.

[0031] The plurality of IP devices 10a to 10c may be circuit blocks that perform specific functions in the SoC 1a. In some embodiments, the plurality of IP devices 10a to 10c may include special function registers. The processor 10P may process data using the special function registers.

[0032] The processor 10P, the memory 10Mem, and the plurality of IP devices 10a to 10c may be connected to each other via a bus BUS. In some embodiments, the bus BUS may be an Advanced Microcontroller Bus Architecture (AMBA), and AMBA may be a standard bus specification for connection and management of the plurality of IP devices 10a to 10c in the SoC 1a. In some embodiments, the bus BUS may be a single-chip communication bus for designing an embedded microprocessor.

[0033] As bus types of AMBA, Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), and Advanced eXtensible Interface (AXI) can be used. Among them, AXI is an interface protocol between IP devices and can provide a multiple outstanding address function, a multiple outstanding transaction function, and a data interleaving function.

[0034] Here, the multi-way prominent address function is a function that allows the use of the empty transmission time occurring between addresses by transmitting the address of each data only once via the address line while synchronously transmitting each data and transmitting when providing information through the address line and data line of the bus. Specifically, it can be used when providing data in burst mode. In addition, the multi-way prominent transaction function is a parallel transaction processing function that can send multiple transactions to the slave device. Therefore, one of the multiple transactions can be preferentially selected and processed by the slave device, and read and write operations can be performed simultaneously through AXI.

[0035] The data interleaving function is a function that allows data to be mixed at the slave level when multiple masters send data to one slave. Therefore, bandwidth usage becomes more efficient and latency can be reduced.

[0036] Figure 2 A description of buses and interfaces is provided for a SoC according to some embodiments.

[0037] Each of the master device 10m and the slave device 10s may be Figure 1 The master device 10m is a device that plays a leading role when using the bus BUS, and the master device 10m can use the bus BUS. In some embodiments, the master device 10m can be Figure 1 The processor 10P is a processor 10P, but the embodiment is not limited thereto, and Figure 1 Other devices within the SoC 1a may be transformed into / assigned as the master device 10m and use the bus BUS.

[0038] The slave device 10s may function as a counterpart to the master device 10m and may perform functions in response to a control signal Ctrl directed by the master device 10m. Therefore, the slave device 10s determines whether the master device 10m sends a control signal Ctrl regarding the corresponding slave device 10s through the address ADDR and may need to prepare to take action in response.

[0039] The master device 10m and the slave device 10s may be connected to the bus BUS through interfaces MI and SI. The master device 10m may include a master interface MI, and the slave device 10s may include a slave interface SI. In the case where the slave device 10s operates as a master device, the slave interface SI may become a master interface MI. That is, the master device may be changed into a slave device, and the slave device may be changed into a master device according to the operating situation.

[0040] The master device 10m according to some embodiments may provide write data WD, a change signal TS, and an address ADDR or a control signal Ctrl to the slave device 10s through the bus BUS, and the slave device 10s may provide a write response WR to the master device 10m. Although not shown, the slave device 10s may provide read data to the master device 10m.

[0041] The master interface MI according to some embodiments may include a data encoding circuit 110 , and the slave interface SI according to some embodiments may include a data decoding circuit 120 .

[0042] The data encoding circuit 110 according to some embodiments may perform an encoding operation on the data before providing the data from the host device 10m to the bus BUS. The data encoding circuit 110 may provide the encoded data in the form of write data WD to a write data channel CW of the bus BUS. Figure 4 and Figure 6 A detailed description of the data encoding circuit 110 is provided.

[0043] The data decoding circuit 120 may perform a decoding operation on the write data WD received from the write data channel CW. Figure 5 and Figure 7 The data decoding circuit 120 is described in detail. The data encoding circuit 110 and the data decoding circuit 120 may be configured as a data pattern optimizer DPO.

[0044] In addition, if Figure 2 As shown in , the transformation signal TS can be provided to the data decoding circuit 120 through the write data channel CW, but the implementation is not limited thereto; in some implementations, the transformation signal TS can be sent through other additional channels of the bus BUS except the write data channel CW.

[0045] Although not shown, the master interface MI and the slave interface SI may include an arbitrator, a decoder, etc. Through the arbitrator, the master device 10m and the slave device 10s can request the right to use the bus BUS. Through the decoder, the master device 10m can activate the slave device 10s as the target of the address ADDR.

[0046] Figure 3 A description of a data channel is provided for use in accordance with some embodiments.

[0047] Reference Figure 2 and Figure 3 , the write data channel CW may include a plurality of data flip-flops FF00 to FFTx and a plurality of data clock gating circuits CG00 to CGTx arranged in parallel. In some embodiments, the plurality of data flip-flops FF00 to FFTx may be arranged in (x+2) rows and (x+1) columns, and the plurality of data clock gating circuits CG00 to CGTx may also be arranged in (x+2) rows and (x+1) columns. The write data channel CW is a data path between the master device 10m and the slave device 10s, and Figure 1 The SoC 1a can perform a buffering operation or a register slicing operation by arranging a plurality of data flip-flops FF00 to FFTx in a write data channel CW.

[0048] The (n_0)th coded data Dn[0] output from the data coding circuit 110 may be provided to the data decoding circuit 120 as the 0th output coded data Do[0] through the data flip-flops FF00 to FF0x of the 0th row. The (n_m)th coded data Dn[m] output from the data coding circuit 110 may be provided to the data decoding circuit 120 as the mth output coded data Do[m] through the data flip-flops FFm0 to FFmx of the mth row. The supply operation for the (n_0)th coded data Dn[0] and the (n_m)th coded data Dn[m] may also be applied to the remaining nth coded data Dn[0:m].

[0049] Likewise, the nth transformed signal Tsn output from the data encoding circuit 110 may be provided to the data decoding circuit 120 as the output transformed signal Tso through the (m+2)th row of data flip-flops FFT0 to FFTx.

[0050] In addition, the plurality of data flip-flops FF00 to FFTx can latch the nth coded data Dn[0:m] and the nth transformed signal Tsn based on the clock signal clk. Through repeated latching operations, the nth coded data Dn[0:m] can be provided to the data decoding circuit 120 as output coded data Do[0:m].

[0051] The plurality of data clock gating circuits CG00 to CGTx provide data of an input stage and data of an output stage to each corresponding data flip-flop FF00 to FFTx, and perform a clock gating operation on a clock signal clk input to the plurality of data flip-flops FF00 to FFTx.

[0052] As an example, the 0_0th data clock gating circuit CG00 may include a clock gating AND operator CG_A and a clock gating XOR operator CG_X.

[0053] The clock-gated XOR operator CG_X can provide the XOR operation result value to the clock-gated AND operator CG_A based on the data of the input terminal and the latched data of the 0_0th data flip-flop FF00. The clock-gated AND operator CG_A gates the XOR bit operation result value and the clock signal clk by performing an AND operation, and can provide an input as a clock of the data flip-flops FF00 to FFTx.

[0054] The 0_0th data clock gating circuit CG00 compares the (n_0)th coded data Dn[0] and the (n−1_0)th coded data Dn−1[0], and performs clock gating with respect to the clock signal clk input to the 0_0th data flip-flop FF00 .

[0055] The description of the 0_0th data clock gating circuit CG00 and the 0_0th data flip-flop FF00 may also be applied to the remaining plurality of clock gating circuits CG01 to CGTx and the plurality of data flip-flops FF01 to FFTx.

[0056] Figure 4 is a block diagram of a data encoding circuit according to some embodiments.

[0057] Reference Figure 2 and Figure 4 The data encoding circuit 110 may include a plurality of flip-flops (FF) (e.g., a plurality of encoding flip-flops) 111, a plurality of clock gating circuits (CG) (e.g., a plurality of encoding clock gating circuits) 112, a first bit operator 113, a second bit operator 114, a first adder 115, a second adder 116, a first comparator 117, a second comparator 118, a control unit (e.g., an encoding control unit) 119, a mask unit (e.g., a data inversion (DI) / data shift (DS) mask unit) 110MU, and a data transformation logic 110DT. Hereinafter, “data transformation logic” may be used interchangeably with “data transformation unit”.

[0058] The data encoding circuit 110 can perform an encoding operation to transmit the data to the host interface MI (refer to Figure 2 ) is encoded into the (n+1)th coded data Dn+1[0:m], and the (n+1)th coded data Dn+1[0:m] and the (n+1)th transformed signal Ts(n+1) can be provided to the write data channel CW.

[0059] The plurality of encoding flip-flops 111 may latch the nth encoding data Dn[0:m] and the nth conversion signal Tsn input before the input of the (n+1)th data DPn+1[0:m].

[0060] The plurality of encoding clock gating circuits 112 may perform clock gating operations on clocks of the plurality of encoding flip-flops 111 based on the nth encoding data Dn[0:m] and the nth conversion signal Tsn latched to the output terminals of the plurality of encoding flip-flops 111 and the (n+1)th encoding data D(n+1)[0:m] and the (n+1)th conversion signal Ts(n+1) input to the input terminals of the plurality of encoding flip-flops 111. The description of the plurality of encoding clock gating circuits 112 and the plurality of encoding flip-flops 111 may be as described with respect to Figure 3 As provided by the 0_0th data clock gating circuit CG00 and the 0_0th data trigger FF00.

[0061] The first bit operator 113 may perform a bit operation on the (n+1)th data DPn+1[0:m] and the nth coded data Dn[0:m] latched to the plurality of coded flip-flops 111, and may provide the result of the bit operation to the first adder 115. In some embodiments, the bit operation of the first bit operator 113 may be an XOR operation, but the embodiments are not limited to this bit operation example. When the bit operation of the first bit operator 113 is an XOR operation and the bit value of each digit of the result value of the first bit operator 113 is 1, this means that the bit value corresponding to the position in the (n+1)th data DPn+1[0:m] and the bit value corresponding to the position in the nth coded data Dn[0:m] are different from each other.

[0062] For example, when an XOR bit operation is performed on random data "1001 (2)" and "1101 (2)", the result of the bit operation may be "0100 (2)". Since the most significant bit (MSB) value of "1001 (2)" and the MSB value of "1101 (2)" are equal to each other, the MSB value of the result value "0100 (2)" is 0. Since the MSB-1 bit value of "1001 (2)" and the MSB-1 bit value of "1101 (2)" are different from each other, the MSB-1 value of the result value "0100 (2)" is 1.

[0063] The second bit operator 114 may perform a bit operation on the "(n+1)th shifted data SDPn+1[0:m] obtained by performing a cyclic shift operation on the (n+1)th data DPn+1[0:m]" and the nth encoded data Dn[0:m], and a result value of the bit operation may be provided to the second adder 116. In some embodiments, a cyclic shift operation in units of 1 bit in the right direction may be performed, but the shift direction and the shift bit unit are not limited thereto.

[0064] In some embodiments, the bit operation of the second bit operator 114 may be an exclusive OR (XNOR) operation, but the bit operation is not limited thereto. When the bit operation of the second bit operator 114 is an XNOR operation and the bit value of each digit of the result value of the second bit operator 114 is 1, this means that the bit value of the corresponding digit in the (n+1)th shift data SDPn+1[0:m] and the bit value of the corresponding digit in the nth encoded data Dn[0:m] are equal to each other.

[0065] The first adder 115 may generate a first sum value A by bit counting the result value of the first bit operator 113 , and provide the first sum value A to the first comparator 117 and the second comparator 118 .

[0066] The second adder 116 may generate a second sum value B by bit counting the result value of the second bit operator 114 , and provide the second sum value B to the second comparator 118 .

[0067] The first comparator 117 may output the (n+1)th inverted signal SIn+1 based on the first sum value A and the number of bits m+1 of the (n+1)th data DPn+1[0:m] and provide the (n+1)th inverted signal SIn+1 to the mask unit 110MU and the encoding control unit 119. For example, the first comparator 117 may perform a comparison operation based on the magnitude of the first sum value A and the m+1 value, and output the (n+1)th inverted signal SIn+1 according to the comparison result.

[0068] Through the comparison operation of the first comparator 117 , the data encoding circuit 110 may predict the clock gating efficiency of the (n+1)th encoding signal Dn+1[0:m] converted by performing an inversion operation on the (n+1)th data DPn+1[0:m].

[0069] The second comparator 118 may output the (n+1)th shift signal SSn+1 based on the first sum value A, the second sum value B, and the number of bits m+1 of the (n+1)th data DPn+1[0:m], and provide the (n+1)th shift signal SSn+1 to the mask unit 110MU and the encoding control unit 119. For example, the second comparator 118 may perform a comparison operation based on the size of the m+1 value, the first sum value A, and the second sum value B, and output the (n+1)th shift signal SSn+1 according to the comparison result.

[0070] In some embodiments, through the comparison operation of the second comparator 118 , the data encoding circuit 110 may predict the clock gating efficiency of the (n+1)th encoded signal Dn+1[0:m] converted by performing a cyclic shift operation on the (n+1)th data DPn+1[0:m].

[0071] The encoding control unit 119 may receive at least a portion of the (n+1)th data DPn+1[0:m], the (n+1)th inversion signal SIn+1, and the (n+1)th shift signal SSn+1, and may provide the inversion enable signal IEn and the shift enable signal SEn to the mask unit 110MU.

[0072] The encoding control unit 119 may include a burst counter 119B and a mode selector 119PS.

[0073] The burst counter 119B checks whether the data input / output mode of the master interface MI is the burst mode, and if it is the burst mode, the burst counter 119B may provide the inverted enable signal IEn and the shift enable signal SEn of a turn-on level to the mask unit 110MU.

[0074] For example, when the burst counter 119B is in a burst mode for continuously performing data output of the (n+1)th data DPn+1[0:m] and the nth encoding signal Dn[0:m] with one request, the inversion enable signal IEn and the shift enable signal SEn may be set to an on level.

[0075] On the other hand, when data output of the (n+1)th data DPn+1[0:m] and the nth encoding signal Dn[0:m] is performed by different requests, the burst counter 119B may turn off the inversion enable signal IEn and the shift enable signal SEn.

[0076] The mode selector 119PS may receive at least a portion of the (n+1)th data DPn+1[0:m], the (n+1)th inversion signal SIn+1, and the (n+1)th shift signal SSn+1, and may determine an encoding operation to be performed on the (n+1)th data DPn+1[0:m]. According to the determination, the mode selector 119PS may turn on or off the inversion enable signal IEn and / or the shift enable signal SEn.

[0077] The conditions for the determination of the mode selector 119PS may vary according to the implementation. Figures 9 to 12 A detailed description of the mode selector 119PS and Figure 5 Mode selector 129PS.

[0078] The mode selector 119PS may receive a separate control signal (such as a special function register (SFR) signal and a signal output from the master device 10m) in addition to the (n+1)th data DPn+1[0:m], the (n+1)th inversion signal SIn+1, and the (n+1)th shift signal SSn+1. The mode selector 119PS may immediately turn on or off the inversion enable signal IEn and / or the shift enable signal SEn through the separate control signal.

[0079] In some embodiments, the mode selector 119PS may turn on or off the inversion enable signal IEn and / or the shift enable signal SEn according to the operation mode of the master device 10m. As an example, the mode selector 119PS may turn on or off the inversion enable signal IEn and / or the shift enable signal SEn according to the operation mode of the master device 10m.

[0080] Information about the operation mode of the master device 10m may be sent to Figure 5 The information about the operation mode can be sent to the mode selector 129PS in the form of a separate flag bit or a partial pattern of the (n+1)th coded data Dn+1[0:m]. Figure 5 Mode selector 129PS.

[0081] The mask unit 110MU may receive the (n+1)th inverted signal SIn+1, the (n+1)th shift signal SSn+1, the inverted enable signal IEn, and the shift enable signal SEn, and may activate the (n+1)th inverted signal SIn+1 and the (n+1)th shift signal SSn+1 based on the inverted enable signal IEn and the shift enable signal SEn. The mask unit 110MU may output the (n+1)th transformed signal Tsn+1 based on the activated (n+1)th inverted signal SIn+1 and the (n+1)th shift signal SSn+1. In some embodiments, the output (n+1)th transformed signal Tsn+1 may be 1 bit. Since the bits allocated to the transform signal TS (refer to Figure 2 ) may be 1, and thus the bandwidth output in parallel with the (n+1)th data DPn+1[0:m] of the present disclosure may be reduced.

[0082] The mask unit 110MU may provide the activated (n+1)th inverted signal SIn+1 and the (n+1)th shift signal SSn+1 to the data transformation logic 110DT in the form of a selection signal. In addition, the mask unit 110MU may provide the (n+1)th transformation signal Tsn+1 output based on the (n+1)th inverted signal SIn+1, the (n+1)th shift signal SSn+1, the inverted enable signal IEn and the shift enable signal SEn to the plurality of encoding flip-flops 111.

[0083] The data transformation logic 110DT may perform a transformation operation on the (n+1)th data DPn+1[0:m] based on the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1. The transformation operation may include performing one of a maintenance operation, an inversion operation, and a circular shift operation on the (n+1)th data DPn+1[0:m]. The transformation operation performed on the (n+1)th data DPn+1[0:m] may be determined based on the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1.

[0084] The data transformation logic 110DT may provide the (n+1)th data DPn+1[0:m] to the input terminals of the plurality of encoding flip-flops 111 before a transformation operation.

[0085] Figure 5 is a block diagram of a data decoding circuit according to some embodiments.

[0086] Reference Figure 5 and Figure 2The data decoding circuit 120 may include a plurality of flip-flops (eg, a plurality of decoding flip-flops) 121, a plurality of clock gating circuits (eg, a plurality of decoding clock gating circuits) 122, a control unit (eg, a decoding control unit) 129, and a data transformation logic 120DT.

[0087] The data decoding circuit 120 can decode the data transmitted via the slave interface SI (refer to Figure 2 ) The output decoded data Do[0:m] input is decoded into decoded data DDo[0:m].

[0088] The plurality of decoding flip-flops 121 may receive the previous decoding data DDo-1[0:m] as input before inputting the decoding data DDo[0:m]. The plurality of decoding flip-flops 121 may receive and latch the previous decoding data DDo-1[0:m].

[0089] The plurality of decoding clock gating circuits 122 may perform clock gating operations on the plurality of decoding flip-flops 121 based on the previous decoding data DDo-1[0:m] latched to the output terminals of the plurality of decoding flip-flops 121 and the decoding data DDo[0:m] input to the input terminals of the plurality of decoding flip-flops 121. The description of the plurality of decoding clock gating circuits 122 and the plurality of decoding flip-flops 121 may be as described with respect to Figure 3 As provided by the 0_0th data clock gating circuit CG00 and the 0_0th data trigger FF00.

[0090] The decoding control unit 129 may receive the output coded data Do[0:m] and at least a portion of the output transform signal Tso, and output an output inversion signal SIo and an output shift signal SSo and provide the output inversion signal SIo and the output shift signal SSo to the data transform unit 120DT.

[0091] The decoding control unit 129 may include a mode selector 129PS. The mode selector 129PS may receive at least a portion of the output coded data Do[0:m] and the output transform signal Tso, and may determine a decoding operation to be performed on the output coded data Do[0:m]. Based on the determination, the mode selector 129PS may output an output inversion signal SIo and an output shift signal SSo.

[0092] The conditions for the determination of the mode selector 129PS may vary according to the implementation. Figure 4 Mode selector 119PS and refer to Figures 9 to 12 A detailed description of the mode selector 129PS is provided.

[0093] The mode selector 129PS may receive information about the operating mode of the main device 10m by outputting at least a portion of the encoded data Do[0:m] and a separate flag bit. In some embodiments, the mode selector 129PS may receive information about the operating mode of the main device 10m by outputting at least a portion of the encoded data Do[0:m]. The data transformation logic 120DT may perform a transformation operation on the output encoded data Do[0:m] based on the output inversion signal SIo and the output shift signal SSo. The transformation operation may include performing any one of a maintenance operation, an inversion operation, and a circular shift operation on the output encoded data Do[0:m]. The transformation operation performed on the output encoded data Do[0:m] may be determined based on the output inversion signal SIo and the output shift signal SSo.

[0094] Figure 6 is a circuit diagram provided for description of a data encoding circuit according to some embodiments.

[0095] Figure 6 The data encoding circuit 110a may be based on Figure 4 An example implementation of the data encoding circuit 110 is shown in FIG. Figure 4 and Figure 6 , the data encoding circuit 110a may include a plurality of encoding flip-flops 111, a plurality of encoding clock gating circuits 112, a first bit operator 113, a second bit operator 114a, a first adder 115, a second adder 116, a first comparator 117, a second comparator 118, an encoding control unit 119, a mask unit 110MU, and a data transformation logic 110DTa. In some embodiments, the data encoding circuit 110a may further include a buffer 110L, and the buffer 110L may include, for example, 0th inversion loop prevention buffer ILB_0 to mth inversion loop prevention buffer ILB_m and 0th shift loop prevention buffer SLB_0 to mth shift loop prevention buffer SLB_m.

[0096] The plurality of coding flip-flops 111 may include 0th to mth coding flip-flops 111_0 to 111_m and a transformation flip-flop 111_T. Each of the 0th to mth coding flip-flops 111_0 to 111_m may receive a bit of the (n+1)th data DPn+1[0:m] or a bit of the (n+1)th coded data Dn+1[0:m] output by the data transformation logic 110DTa, respectively.

[0097] For example, the 0th coding flip-flop 111_0 may receive the (n+1_0)th data DPn+1[0] before performing a transformation operation on the (n+1)th data DPn+1[0:m], and may receive the (n+1_0)th coded data Dn+1[0] after performing a transformation operation on the (n+1)th data DPn+1[0:m].

[0098] The changeover flip-flop 111_T may receive the (n+1)th changeover signal Tsn+1 output from the mask unit 110MU.

[0099] The plurality of coding clock gating circuits 112 may include 0th coding clock gating AND operators 112_0 to mth coding clock gating AND operators 112_m and a transform clock gating AND operator 112_T. A detailed description of the plurality of coding clock gating circuits 112 and a description of the first bit operator 113 are provided.

[0100] The first bit operator 113 may include 0th to mth XOR operators 113X_0 to 113X_m and a transform XOR operator 113X_T. The 0th to mth XOR operators 113X_0 to 113X_m and the transform XOR operator 113X_T may perform an XOR bit operation on the nth coded data Dn[0:m] and the nth transform signal Tsn latched to the output terminals of the 0th to mth coding flip-flops 111_0 to 111_m and the transform flip-flop 111_T, and may perform an XOR bit operation on the (n+1)th data DPn+1[0:m] and the (n+1)th transform signal Tsn+1 input to the input terminals of the 0th to mth coding flip-flops 111_0 to 111_m and the transform flip-flop 111_T.

[0101] The 0th to mth XOR operators 113X_0 and 113X_m may provide XOR result values ​​XORout[0:m] as the results of the XOR bit operation to the first adder 115 and the 0th to mth coded clock gating AND operators 112_0 and 112_m. The transformation XOR operator 113X_T may provide the operation result to the transformation clock gating AND operator 112_T.

[0102] For example, the 0th XOR operator 113X_0 performs an XOR operation on the (n_0)th coded data Dn[0] latched to the output terminal of the 0th coding flip-flop 111_0 and the (n+1_0)th data DPn+1[0] input to the input terminal of the 0th coding flip-flop 111_0, outputs the 0th XOR result value XORout[0], and provides the 0th XOR result value XORout[0] to the first adder 115 and the 0th coding clock-gated AND operator 112_0.

[0103] The XOR result values ​​XORout[0:m] of the 0th to mth XOR operators 113X_0 to 113X_m may be transmitted to the first adder 115 through the 0th to mth inverting loop prevention buffers ILB_0 to ILB_m. When the enable signal EN is input to the 0th to mth inverting loop prevention buffers ILB_0 to ILB_m, the XOR result values ​​XORout[0:m] may be input to the first adder 115. Through the 0th to mth inverting loop prevention buffers ILB_0 to ILB_m, the data encoding circuit 110a may prevent the (n+1)th inverted signal SIn+1 and the (n+1)th shift signal SSn+1 output by the XOR result value XORout[0:m] from being fed back due to the XOR result value XORout[0:m].

[0104] Each of the 0th coding clock gating AND operator 112_0 to the mth coding clock gating AND operator 112_m and the conversion clock gating AND operator 112_T may be operated as a clock gating circuit having the 0th XOR operator 113X_0 to the mth XOR operator 113X_m and the conversion XOR operator 113X_T of the first bit operator 113. The description of the 0th coding clock gating AND operator 112_0 to the mth coding clock gating AND operator 112_m, the conversion clock gating AND operator 112_T, the 0th XOR operator 113X_0 to the mth XOR operator 113X_m and the conversion XOR operator 113X_T may be as described for Figure 3 As provided by the 0_0th data clock gating circuit CG00.

[0105] For example, the 0th XOR operator 113X_0 may output the 0th XOR result value XORout[0] by receiving the (n+1_0)th data DPn+1[0] and the (n+0)th coded data Dn[0] as input data of the 0th coding flip-flop 111_0, and may provide the 0th XOR result value XORout[0] to the 0th coding clock gating AND operator 112_0. The 0th coding clock gating AND operator 112_0 may perform a clock gating operation on the clock of the 0th coding flip-flop 111_0 based on the clock signal clk and the 0th XOR result value XORout[0].

[0106] The second bit operator 114a may include 0th to mth XNOR operators 114XN_0 to 114XN_m. The 0th to mth XNOR operators 114XN_0 to 114XN_m may perform an XNOR bit operation on the nth coded data Dn[0:m] latched to the output terminals of the 0th to mth coding flip-flops 111_0 to 111_m and data cyclically shifted in the right direction by 1 bit with respect to the (n+1)th data DPn+1[0:m].

[0107] The 0th through mth XNOR operators 114XN_0 through 114XN_m may provide an XNOR result value XNORout[0:m] that is a result of the XNOR bit operation to the second adder 116 .

[0108] For example, the 0th XNOR operator 114XN_0 performs an XNOR operation on the (n_0)th coded data Dn[0] latched to the output terminal of the 0th coding flip-flop 111_0 and the (n+1_1)th data DPn+1[1] input to the input terminal of the first coding flip-flop 111_1, outputs the 0th XNOR result value XNORout[0], and provides the 0th XNOR result value XNORout[0] to the second adder 116. In addition, the mth XNOR operator 114XN_m may perform an XNOR operation on the (n_m)th coded data Dn[m] latched to the output terminal of the mth coding flip-flop 111_m and the (n+1_0)th data DPn+1[0] input to the input terminal of the 0th coding flip-flop 111_0, and may output and provide the mth XNOR result value XNORout[m] to the second adder 116.

[0109] The XNOR result values ​​XNORout[0:m] of the 0th XNOR operators 114XN_0 to the mth XNOR operators 114XN_m may be transmitted to the second adder 116 through the 0th shift loop prevention buffers SLB_0 to the mth shift loop prevention buffers SLB_m. When the enable signal EN is input to the 0th shift loop prevention buffers SLB_0 to the mth shift loop prevention buffers SLB_m, the XNOR result values ​​XNORout[0:m] may be input to the second adder 116. The data encoding circuit 110a may prevent the (n+1)th shift signal SSn+1 outputted from the XNOR result value XNORout[0:m] from being fed back to the XNOR result value XNORout[0:m] through the 0th shift loop prevention buffers SLB_0 to the mth shift loop prevention buffers SLB_m.

[0110] The first adder 115 may perform bit counting on the XOR result value XORout[0:m], generate a first sum value A, and provide the first sum value A to the first comparator 117 and the second comparator 118 .

[0111] The second adder 116 may perform bit counting on the XNOR result value XNORout[0:m], generate a second sum value B, and provide the second sum value B to the second comparator 118 .

[0112] In some embodiments, the first comparator 117 may output the (n+1)th inverted signal SIn+1 based on whether the following Equation 1 is satisfied, but the operation of the first comparator 117 is not limited thereto. The output (n+1)th inverted signal SIn+1 may be provided to the mask unit 110MU and the encoding control unit 119.

[0113] (Equation 1): In Equation 1, A represents the first sum value A, and M represents the number of bits of the (n+1)th data DPn+1[0:m]. Here, M may be m+1. In some embodiments, through the comparison operation of the first comparator 117, the data encoding circuit 110 performs an inversion operation on the (n+1)th data DPn+1[0:m] to predict the clock gating efficiency of the converted (n+1)th encoding signal Dn+1[0:m].

[0114] In some embodiments, the second comparator 118 may output the (n+1)th shift signal SSn+1 based on whether the following Equation 2 is satisfied, but the operation of the second comparator 118 is not limited thereto. The output (n+1)th shift signal SSn+1 may be provided to the mask unit 110MU and the encoding control unit 119.

[0115] (Equation 2): In Equation 2, A represents the first sum value A, B represents the second sum value B, and M is the number of bits of the (n+1)th data DPn+1[0:m]. Here, M may be m+1. The second comparator 118 performs calculation based on the first sum value A, the second sum value B, and the number of bits m+1 of the (n+1)th data DPn+1[0:m], thereby predicting the clock gating efficiency of the (n+1)th coded signal Dn+1[0:m] transformed by performing a cyclic shift operation on the (n+1)th data DPn+1[0:m].

[0116] In some embodiments, the encoding control unit 119 may receive the (n+1_0)th to (n+1_2)th data DPn+1[0:2], the (n+1)th inversion signal SIn+1, and the (n+1)th shift signal SSn+1, and may output an inversion enable signal IEn and a shift enable signal SEn and provide the inversion enable signal IEn and the shift enable signal SEn to the mask unit 110MU.

[0117] The encoding control unit 119 may include a burst counter 119B and a mode selector 119PS.

[0118] The burst counter 119B checks whether the data input / output mode of the master interface MI is the burst mode, and if it is the burst mode, sets the inversion enable signal IEn and the shift enable signal SEn to the on level, and provides the inversion enable signal IEn and the shift enable signal SEn at the on level to the mask unit 110MU. When the output of the (n+1)th data DPn+1[0:m] and the data output of the nth encoding signal Dn[0:m] are performed by different requests, the burst counter 119B may set the inversion enable signal IEn and the shift enable signal SEn to the off level.

[0119] In some embodiments, the mode selector 119PS receives the (n+1_0)th to (n+1_2)th data DPn+1[0:2], the (n+1)th inversion signal SIn+1, and the (n+1)th shift signal SSn+1, and may determine an encoding operation to be performed on the (n+1)th data DPn+1[0:m]. Based on the determination, the mode selector 119PS may set the inversion enable signal IEn and / or the shift enable signal SEn to an enable / disable level.

[0120] For example, the mode selector 119PS may perform an OR operation on the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1, and may output the inversion enable signal IEn and / or the shift enable signal SEn according to the mode of the (n+1_0)th data to the (n+1_2)th data DPn+1[0:2].

[0121] For example, when the value of the OR operation of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is "1", and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are different from each other, the mode selector 119PS may set the inversion enable signal IEn to an off level and the shift enable signal SEn to an on level. When the value of the OR operation of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is "1", and the (n+1_0)th data DPn+1[0], the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are all the same, the mode selector 119PS may set the inversion enable signal IEn to an on level and the shift enable signal SEn to an off level. When the OR operation value of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is "1", and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are the same and only the (n+1_0)th data DPn+1[0] is different, the mode selector 119PS can set both the inversion enable signal IEn and the shift enable signal SEn to the cut-off level.

[0122] This mode of output of the (n+1)th data DPn+1[0:m] and the inversion enable signal IEn and the shift enable signal SEn according to the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is described as an example, and the scope of the embodiments according to the present disclosure is not limited to this mode.

[0123] Reference Figures 9 to 12 And refer to Figure 7 The mode selector 129PS describes the mode selector 119PS in more detail.

[0124] Figure 6 The mode selector 119PS shown in FIG. 1 receives the (n+1_0)th data to the (n+1_2)th data DPn+1[0:2] among the (n+1)th data DPn+1[0:m], and outputs the inversion enable signal IEn and / or the shift enable signal SEn based on the received data. However, the input data to the mode selector 119PS among the (n+1)th data DPn+1[0:m] is not limited to this example.

[0125] In some embodiments, the mask unit 110MU may include first and second inverting AND operators Ian_1 and Ian_2, first and second shift AND operators San_1 and San_2, and a transform OR operator TsOR.

[0126] The first inverting AND operator Ian_1 and the second inverting AND operator Ian_2 may receive the inverting enable signal IEn and the (n+1)th inverting signal SIn+1. The first inverting AND operator Ian_1 may provide the AND operation result of the inverting enable signal IEn and the (n+1)th inverting signal SIn+1 to the data transformation unit 110DTa. The second inverting AND operator Ian_2 may provide the AND operation result of the inverting enable signal IEn and the (n+1)th inverting signal SIn+1 to the transformation OR operator TsOR. The first inverting AND operator Ian_1 may determine the activation of the (n+1)th inverting signal SIn+1 by using the AND operation of the inverting enable signal IEn. The first inverting AND operator Ian_1 may output the activated (n+1)th inverting signal SIn+1.

[0127] The first shift AND operator San_1 and the second shift AND operator San_2 may receive the shift enable signal SEn and the (n+1)th shift signal SSn+1. The first shift AND operator San_1 may provide the AND operation result of the shift enable signal SEn and the (n+1)th shift signal SSn+1 to the data transformation unit 110DTa. The second shift AND operator San_2 may provide the AND operation result of the shift enable signal SEn and the (n+1)th shift signal SSn+1 to the transformation OR operator TsOR. The first shift AND operator San_1 may determine the activation of the (n+1)th shift signal SSn+1 by using the AND operation of the shift enable signal SEn. The first shift AND operator San_1 may output the activated (n+1)th shift signal SSn+1.

[0128] The transformation OR operator TsOR can output the (n+1)th transformation signal Tsn+1 based on the operation results of the second inverting AND operator Ian_2 and the second shift AND operator San_2. The transformation OR operator TsOR can output the (n+1)th transformation signal Tsn+1 considering the activation of the (n+1)th inverted signal SIn+1 and the (n+1)th shift signal SSn+1 based on the operation results of the second inverting AND operator Ian_2 and the operation results of the second shift AND operator San_2.

[0129] The output (n+1)th conversion signal Tsn+1 may be 1 bit. Figure 2 ) may be 1, and thus the bandwidth output in parallel with the (n+1)th data DPn+1[0:m] of the present disclosure may be reduced.

[0130] In addition, the (n+1)th transformed signal Tsn+1 is a signal output from an OR operation of the activated (n+1)th inversion signal SIn+1 and the activated (n+1)th shift signal SSN+1, and when one of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSN+1 is activated, the (n+1)th transformed signal Tsn+1 may be activated. For example, when a value of one of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSN+1 is "1", the value of the (n+1)th transformed signal Tsn+1 may be "1". For example, the (n+1)th transformed signal Tsn+1 having a value of "1" may indicate an inversion operation or a cyclic shift operation (i.e., the encoding operation performed on the (n+1)th data DPn+1[0:m] is an inversion operation or a cyclic shift operation).

[0131] However, when both the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 are deactivated, the (n+1)th transformation signal Tsn+1 may be deactivated. For example, when the values ​​of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 are both "0", the value of the (n+1)th transformation signal Tsn+1 may be "0". For example, the (n+1)th transformation signal Tsn+1 having a value of "0" may indicate a maintenance operation (i.e., the encoding operation performed on the (n+1)th data DPn+1[0:m] is a maintenance operation).

[0132] The data transform unit 110DTa may perform any one of a maintenance operation, an inversion operation, and a cyclic shift operation encoding operation on the (n+1)th data DPn+1[0:m] based on the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1.

[0133] In some embodiments, the data transformation unit 110DTa may include 0th to mth transformation XOR operators TX_0 to TX_m and 0th to mth transformation multiplexers (MUX) TM_0 to TM_m. Each of the 0th to mth transformation XOR operators TX_0 to TX_m may receive the (n+1)th data DPn+1[0:m] and the output of the first inversion AND operator Ian_1 (e.g., the AND operation result of the inversion enable signal IEn and the (n+1)th inversion signal SIn+1) and perform an XOR bit operation.

[0134] For example, the 0th transformation XOR operator TX_0 may receive the (n+1_0)th data DPn+1[0] and the output of the first inverting AND operator Ian_1. When the received output of the first inverting AND operator Ian_1 is "0", the 0th transformation XOR operator TX_0 may output the (n+1_0)th data DPn+1[0] as is, and when the received output of the first inverting AND operator Ian_1 is "1", the 0th transformation XOR operator TX_0 may invert and output the (n+1_0)th data DPn+1[0]. In some embodiments, the value of the (n+1)th transformation signal Tsn+1 may be "1".

[0135] Each of the 0th transformation MUX TM_0 to the mth transformation MUX TM_m may receive the result value of each of the 0th transformation XOR operators TX_0 to the mth transformation XOR operators TX_m and each data cyclically shifted in the right direction by 1 bit for the (n+1)th data DPn+1[0:m], and may receive the output of the first shift AND operator San_1 (e.g., the AND operation result of the shift enable signal SEn and the (n+1)th shift signal SSn+1) as a selection signal. Each of the 0th transformation MUX TM_0 to the mth transformation MUX TM_m may output any one of the result value of each of the 0th transformation XOR operators TX_0 to the mth transformation XOR operators TX_m and the cyclically shifted data based on the output of the first shift AND operator San_1.

[0136] For example, the 0th transformation MUX TM_0 may receive the result value of the 0th transformation XOR operator TX_0 and the (n+1_1)th data DPn+1[1], and may receive the output of the first shift AND operator San_1 as a selection signal. When the received output of the first shift AND operator San_1 is "0", the 0th transformation MUX TM_0 outputs the result value of the 0th transformation XOR operator TX_0, and provides the output result value to the 0th encoding flip-flop 111_0. When the received output of the first shift AND operator San_1 is "1", the 0th transformation MUX TM_0 may output the (n+1_1)th data DPn+1[1], and provide the output data to the 0th encoding flip-flop 111_0.

[0137] In addition, the mth transformation MUX TM_m may receive the result value of the mth transformation XOR operator TX_m and the (n+1_0)th data DPn+1[0], and may receive the output of the first shift AND operator San_1 as a selection signal. When the output of the first shift AND operator San_1 is "0", the mth transformation MUX TM_m may output the result value of the mth transformation XOR operator TX_m, and provide the output result value to the mth encoding trigger 111_m. When the output of the first shift AND operator San_1 is "1", the mth transformation MUX TM_m may output the (n+1_0)th data DPn+1[0], and provide the output data to the mth encoding trigger 111_m.

[0138] The data transformation unit 110DTa outputs the (n+1)th coded data Dn+1[0:m] obtained by performing any one of a maintenance operation, an inversion operation, and a cyclic shift operation on the (n+1)th data DPn+1[0:m] based on the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1, and provides the output coded data to a plurality of coding flip-flops 111.

[0139] Therefore, the (n+1)th transformed signal Tsn+1 output based on the activated (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 may include encoding operation information for the (n+1)th data DPn+1[0:m]. The (n+1)th transformed signal Tsn+1 may indicate whether any one of the inversion operation and the cyclic shift operation for the (n+1)th data DPn+1[0:m] is performed.

[0140] In addition, the data transformation unit 110DTa may control the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 before performing the encoding operation, and provide the (n+1)th data DPn+1[0:m] to the input terminal of each of the 0th to mth encoding flip-flops 111_0 to 111_m. Before the encoding operation of the data transformation unit 110DTa, the first bit operator 113 may output an XOR result value XORout[0:m] based on the provided (n+1)th data DPn+1[0:m].

[0141] Figure 7 is a circuit diagram provided for description of a data decoding circuit according to some embodiments.

[0142] Figure 7 The data decoding circuit 120a is Figure 5 An example of the data decoding circuit 120. Figure 5 and Figure 7The data decoding circuit 120a may include a plurality of decoding triggers 121, a plurality of decoding clock gating circuits 122, a decoding control unit 129 and a data transformation logic 120DTa.

[0143] The plurality of decoding flip-flops 121 may include a 0th decoding flip-flop 121_0 to an mth decoding flip-flop 121_m. Each of the 0th decoding flip-flop 121_0 to the mth decoding flip-flop 121_m may receive a bit of the decoding data DDo[0:m] outputted by the data conversion logic 120DTa through an input terminal, and may latch the previous decoding data DDo-1[0:m] to an output terminal. For example, the 0th decoding flip-flop 121_0 may receive the 0th decoding data DDo[0] through an input terminal, and latch the 0th previous decoding data DDo-1[0] to an output terminal.

[0144] The plurality of decoding clock gating circuits 122 may include 0th to mth decoding clock gating AND operators 122A_0 to 122A_m and 0th to mth decoding clock gating XOR operators 122X_0 to 122X_m.

[0145] The 0th to mth decoding clock gating XOR operators 122X_0 to 122X_m may provide XOR operation result values ​​to the 0th to mth decoding clock gating AND operators 122A_0 to 122A_m based on the data at the input terminals of the 0th to mth decoding flip-flops 121_0 to 121_m and the latched data at the output terminals of the 0th to mth decoding flip-flops 121_0 to 121_m. The 0th to mth decoding clock gating AND operators 122A_0 to 122A_m may gate the XOR operation result values ​​and the clock signal clk by performing an AND operation and provide input as the clock of the 0th to mth decoding flip-flops 121_0 to 121_m.

[0146] For example, the 0th decoding clock gating XOR operator 122X_0 may provide the XOR operation result value to the 0th decoding gated AND operator 122A_0 based on the 0th decoding data DDo[0] and the 0th previous decoding data DDo-1[0] latched to the 0th decoding flip-flop 121_0. The 0th decoding gated AND operator 122A_0 may gate the XOR operation result value and the clock signal clk by performing an AND operation and provide an input as the clock of the 0th decoding flip-flop 121_0.

[0147] The plurality of decoding clock gating circuits 122 compare each decoding data DDo[0:m] with the previous decoding data DDo-1[0:m] latched to the 0th to mth decoding flip-flops 121_0 to 121_m, and may perform clock gating for the clock signal clk input to the 0th to mth decoding flip-flops 121_0 to 121_m.

[0148] The decoding control unit 129 can receive the 0th output coded data and the first output coded data Do[0:1] as adjacent bits in the output coded data Do[0:m] and the output transformation signal Tso, and can output the output inversion signal SIo and the output shift signal SSo based on the 0th output coded data and the first output coded data Do[0:1] and the output transformation signal Tso, and provide the output inversion signal SIo and the output shift signal SSo to the data transformation unit 120DTa.

[0149] The decoding control unit 129 may include a mode selector 129PS. The mode selector 129PS may determine a decoding operation to be performed on the output coded data Do[0:m] based on the 0th output coded data and the first output coded data Do[0:1] and the output transformation signal Tso. According to the determination, the mode selector 129PS may turn on / off the output inversion signal SIo and / or the output shift signal SSo.

[0150] For example, when the value of the output transformation signal Tso is "0", the mode selector 129PS turns off both the output inversion signal SIo and the output shift signal SSo, so that the decoding operation for the output coded data Do[0:m] can be determined as a maintenance operation. When the value of the output transformation signal Tso is "1" and the 0th output coded data and the first output coded data Do[0:1] are different from each other, the mode selector 129PS turns off the output inversion signal SIo and turns on the output shift signal SSo, so that the decoding operation for the output coded data Do[0:m] can be determined as a shift operation. When the value of the output transformation signal Tso is "1" and the 0th output coded data and the first output coded data Do[0:1] are equal to each other, the mode selector 129PS turns on the output inversion signal SIo and turns off the output shift signal SSo, so that the decoding operation for the output coded data Do[0:m] can be determined as an inversion operation.

[0151] Reference Figures 9 to 12 And refer to Figure 6 The operation of the mode selector 129PS is described in detail.

[0152] The mode selector 129PS may receive the 0th output coded data and the first output coded data Do[0:1] among the output coded data Do[0:m], and output an output inversion signal SIo and an output shift signal SSo based on the 0th output coded data and the first output coded data Do[0:1]. In some embodiments, the input data among the output coded data Do[0:m] is not limited to Do[0:1], but may be other data among the output coded data Do[0:m].

[0153] The data transform unit 120DTa may perform a decoding operation of any one of a maintenance operation, an inversion operation, and a cyclic shift operation on the output coded data Do[0:m] based on the output inversion signal SIo and the output shift signal SSo.

[0154] In some embodiments, the data transform unit 120DTa may include 0th to mth decoding XOR operators DX_0 to DX_m and 0th to mth decoding MUX DM_0 to DM_m. Each of the 0th to mth decoding XOR operators DX_0 to DX_m may receive the output coded data Do[0:m] and the output inversion signal SIo and perform an XOR bit operation.

[0155] For example, the 0th decoding XOR operator DX_0 may receive the 0th output coded data Do[0] and the output inversion signal SIo. When the output inversion signal SIo is "0", the 0th decoding XOR operator DX_0 outputs the 0th output coded data Do[0] as is, and when the output inversion signal SIo is "1", the 0th decoding XOR operator DX_0 may invert and output the 0th output coded data Do[0].

[0156] Each of the 0th to mth decoding MUX DM_0 may receive a result value of each of the 0th to mth decoding XOR operators DX_0 to DX_m and data cyclically shifted in the left direction by 1 bit for the output encoded data Do[0:m], and may receive an output shift signal SSo as a selection signal. Each of the 0th to mth decoding MUX DM_0 may output any one of the result values ​​of the 0th to mth decoding XOR operators DX_0 to DX_m and the cyclically shifted data based on the output shift signal SSo.

[0157] For example, the 0th decoding MUX DM_0 may receive the result value of the 0th decoding XOR operator DX_0 and the mth output coded data Do[m], and receive the output shift signal SSo as a selection signal. When the output shift signal SSo is "0", the 0th decoding MUX DM_0 may output the result value of the 0th decoding XOR operator DX_0 and provide it to the 0th decoding flip-flop 121_0. When the output shift signal SSo is "1", the 0th decoding MUX DM_0 may output the mth output coded data Do[m] and provide it to the 0th decoding flip-flop 121_0.

[0158] In addition, the first decoding MUX DM_1 can receive the result value of the first decoding XOR operator DX_1 and the 0th output coded data Do[0], and receive the output shift signal SSo as a selection signal. When the output shift signal SSo is "0", the first decoding MUX DM_1 outputs the result value of the first decoding XOR operator DX_1 and provides it to the first decoding flip-flop 121_1. When the output shift signal SSo is "1", the first decoding MUX DM_1 outputs the 0th output coded data Do[0] and provides it to the first decoding flip-flop 121_1.

[0159] The data transformation unit 120DTa can output the decoded data DDo[0:m] obtained by performing any one of a maintenance operation, an inversion operation and a circular shift operation on the output encoded data Do[0:m] based on the output inversion signal SIo and the output shift signal SSo, and provide the output decoded data DDo[0:m] to multiple decoding triggers 121.

[0160] Figure 8 A description of an example of encoding operations for a data encoding circuit according to some embodiments is provided. Figure 8 1 shows that when the inversion enable signal IEn and the shift enable signal SEn are set to the on level and the (n+1)th data DPn+1 [0:m] (where m is 7) is continuously input three times Figure 6 An example of the operation of the data encoding circuit 110a.

[0161] Reference Figure 6 and Figure 8 , the data encoding circuit 110 a may receive “11101011 (2)” for the first clock cycle clockcycle1 , receive “00001110 (2)” for the second clock cycle clockcycle2 , and receive “11101010 (2)” as the (n+1)th data DPn+1[0:7] for the third clock cycle clockcycle3 .

[0162] Since the nth coded data Dn[0:7] is not latched in the first clock cycle clockcycle1, the first bit operator 113 and the second bit operator 114a may abnormally output the XOR result value XORout[0:7] and the XNOR result value XNORout[0:7]. Therefore, "11101011 (2)" input to the input terminals of the plurality of coding flip-flops 111 before the transformation operation of the data transformation logic 110DTa may be latched to the output terminals of the plurality of coding flip-flops 111 based on the clock signal clk.

[0163] "11101011 (2)" may be latched as the nth encoded data Dn[0:7] to the output terminals of the plurality of encoding flip-flops 111 in the second clock cycle clockcycle2, and "00001110 (2)" may be input as the (n+1)th data DPn+1[0:7] to the input terminals of the plurality of encoding flip-flops 111. The XOR result value XORout[0:7] may be "11100101 (2)", and the XNOR result value XNORout[0:7] may be "00010011 (2)". Therefore, the first sum value A may be 5, and the second sum value B may be 3.

[0164] Therefore, the first comparator 117 can output by setting the (n+1)th inversion signal SIn+1 to the on level, and the second comparator 118 can output by setting the (n+1)th shift signal SSn+1 to the off level. Assuming that the inversion enable signal IEn and the shift enable signal SEn are set to the on level, the mask unit 110MU can output by setting the (n+1)th conversion signal Tsn+1 to the on level.

[0165] The data conversion logic 110DTa may perform an inversion operation on "00001110 (2)" in the second clock cycle clockcycle2, and may output "11110001 (2)" as the (n+1)th encoded data Dn+1[0:7]. The data conversion logic 110DTa may provide "11110001 (2)" to the input terminals of the plurality of encoding flip-flops 111. The "11110001 (2)" input to the input terminals of the plurality of encoding flip-flops 111 may be latched to the output terminals of the plurality of encoding flip-flops 111 based on the clock signal clk.

[0166] "11110001 (2)" may be latched into the output terminals of the plurality of encoding flip-flops 111 as the nth encoding data Dn[0:7] in the third clock cycle clockcycle3, and "11101010 (2)" may be input into the input terminals of the plurality of encoding flip-flops 111 as the (n+1)th data DPn+1[0:7]. The XOR result value XORout[0:7] may be "00011011 (2)", and the XNOR result value XNORout[0:7] may be "01111011 (2)". Therefore, the first sum value A may be 4, and the second sum value B may be 6.

[0167] Therefore, the first comparator 117 may turn off and output the (n+1)th inversion signal SIn+1, and the second comparator 118 may turn on and output the (n+1)th shift signal SSn+1. Assuming that the inversion enable signal IEn and the shift enable signal SEn are set to the on level, the mask unit 110MU may output by setting the (n+1)th conversion signal Tsn+1 to the on level.

[0168] In the third clock cycle clockcycle3, the data transformation logic 110DTa may perform a cyclic shift operation in the right direction by 1 bit with respect to "11101010 (2)", and may output "01110101 (2)" as the (n+1)th encoded data Dn+1[0:7]. The data transformation logic 110DTa may provide "01110101 (2)" to the input terminals of the plurality of encoding flip-flops 111. The "01110101 (2)" input to the input terminals of the plurality of encoding flip-flops 111 may be latched to the output terminals of the plurality of encoding flip-flops 111 based on the clock signal clk.

[0169] The data encoding circuit 110a may receive the (n+1)th data DPn+1[0:7] in the order of “11101011(2)”, “00001110(2)”, and “11101010(2)” in the first clock cycle clockcycle1 to the third clock cycle clockcycle3. The data encoding circuit 110a may output the (n+1)th data DPn+1[0:7] in the order of “11101011(2)”, “11110001(2)”, and “01110101(2)”, and may output the (n+1)th conversion signal Tsn+1 in the order of “0(2)”, “1(2)”, and “1(2)” in the first clock cycle clockcycle1 to the third clock cycle clockcycle3.

[0170] Figures 9 and 10 A description of an example of an encoding operation for a data encoding circuit is provided. Figures 9 and 10is provided for when the (n+1)th data DPn+1[0:m] (where m is 7) is input four times in succession Figure 6 Description of the operation of the data encoding circuit 110a.

[0171] Reference Figure 6 , Fig. 9 and Fig.10 , the data encoding circuit 110a can receive "01000001 (2)" in the first clock cycle clockcycle1, receive "10100010 (2)" in the second clock cycle clockcycle2, receive "11101111 (2)" in the third clock cycle clockcycle3, and receive "10100001 (2)" in the fourth clock cycle clockcycle4 as the (n+1)th data DPn+1[0:7].

[0172] In addition, as referenced Figure 6 As described, the mode selector 119PS performs an OR operation on the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1, and may output an inversion enable signal IEn and / or a shift enable signal SEn according to a pattern of the (n+1_0)th data to the (n+1_2)th data DPn+1[0:2].

[0173] In some embodiments, when the value of the OR operation of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is "1" and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are different from each other, the mode selector 119PS may turn off the inversion enable signal IEn and set the shift enable signal SEn to an on level. When the value of the OR operation of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is "1" and the (n+1_0)th data DPn+1[0], the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are all the same, the mode selector 119PS may set the inversion enable signal IEn to an on level and turn off the shift enable signal SEn. When the value of the OR operation of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is "1" and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are the same and only the (n+1_0)th data DPn+1[0] is different, the mode selector 119PS can turn off both the inversion enable signal IEn and the shift enable signal SEn.

[0174] Since the nth coded data Dn[0:7] is not latched in the first clock cycle clockcycle1, the first bit operator 113 and the second bit operator 114a may abnormally output the XOR result value XORout[0:7] and the XNOR result value XNORout[0:7]. Therefore, before the transformation operation of the data transformation logic 110DTa, "01000001 (2)" input to the input terminals of the plurality of coding flip-flops 111 may be latched to the output terminals of the plurality of coding flip-flops 111 based on the clock signal clk. Since the inversion operation and the cyclic shift operation are not performed in the data transformation logic 110DTa, the mask unit 110MU may be turned off (e.g., set to a turn-off level) and output the (n+1)th transformation signal Tsn+1.

[0175] "01000001 (2)" may be latched as the nth encoded data Dn[0:7] to the output terminals of the plurality of encoding flip-flops 111 in the second clock cycle clockcycle2, and "10100010 (2)" may be input as the (n+1)th data DPn+1[0:7] to the input terminals of the plurality of encoding flip-flops 111. The XOR result value XORout[0:7] may be "11100011 (2)", and the XNOR result value XNORout[0:7] may be "11101111 (2)". Therefore, the first sum value A may be 5, and the second sum value B may be 7.

[0176] Therefore, the first comparator 117 may set the (n+1)th inverted signal SIn+1 to an on level and output it, and the second comparator 118 may set the (n+1)th shift signal SSn+1 to an on level and output it. Since the OR operation result value of the (n+1)th inverted signal SIn+1 and the (n+1)th shift signal SSn+1 is "1", the value of the (n+1_1)th data DPn+1[1] is "1", and the value of the (n+1_2)th data DPn+1[2] is "0" (that is, they are different from each other), the mode selector 119PS may turn off the inverted enable signal IEn and may set the shift enable signal SEn to an on level. The mask unit 110MU may set the (n+1)th transformation signal Tsn+1 to an on level and output it.

[0177] In the second clock cycle clockcycle2, the data transformation logic 110DTa receives the activated (n+1)th shift signal SSn+1 and may output “01010001(2)” by cyclically shifting “10100010(2)” in the right direction by 1 bit. The data transformation logic 110DTa may provide “01010001(2)” to the input terminals of the plurality of encoding flip-flops 111. The “01010001(2)” input to the input terminals of the plurality of encoding flip-flops 111 may be latched to the output terminals of the plurality of encoding flip-flops 111 based on the clock signal clk.

[0178] In the third clock cycle clockcycle3, "01010001 (2)" may be latched as the nth encoded data Dn[0:7] to the output terminals of the plurality of encoding flip-flops 111, and "11101111 (2)" may be input as the (n+1)th data DPn+1[0:7] to the input terminals of the plurality of encoding flip-flops 111. The XOR result value XORout[0:7] may be "10111110 (2)", and the XNOR result value XNORout[0:7] may be "01011001 (2)". Therefore, the first sum value A may be 6, and the second sum value B may be 4.

[0179] Therefore, the first comparator 117 may set the (n+1)th inverted signal SIn+1 to an on level and output it, and the second comparator 118 may set the (n+1)th shift signal SSn+1 to an on level and output it. Since the OR operation result value of the (n+1)th inverted signal SIn+1 and the (n+1)th shift signal SSn+1 is "1", and the values ​​of the (n+1_0)th data DPn+1[0], the (n+1_1)th data DPn+1[1], and the (n+1_2)th data DPn+1[2] are equally "1", the mode selector 119PS may set the inverted enable signal IEn to an on level and turn off the shift enable signal SEn. The mask unit 110MU may set the (n+1)th transformation signal Tsn+1 to an on level and output it.

[0180] In the third clock cycle clockcycle3, the data conversion logic 110DTa receives the activated (n+1)th inversion signal SIn+1, and inverts "11101111 (2)" to "00010000 (2)" and outputs it. The data conversion logic 110DTa may provide "00010000 (2)" to the input terminals of the plurality of encoding flip-flops 111. The "00010000 (2)" input to the input terminals of the plurality of encoding flip-flops 111 may be latched to the output terminals of the plurality of encoding flip-flops 111 based on the clock signal clk.

[0181] In the fourth clock cycle clockcycle4, "00010000 (2)" may be latched as the nth encoded data Dn[0:7] to the output terminals of the plurality of encoding flip-flops 111, and "10100001 (2)" may be input as the (n+1)th data DPn+1[0:7] to the input terminals of the plurality of encoding flip-flops 111. The XOR result value XORout[0:7] may be "10110001 (2)", and the XNOR result value XNORout[0:7] may be "00111111 (2)". Therefore, the first sum value A may be 4, and the second sum value B may be 6.

[0182] Therefore, the first comparator 117 may turn off the (n+1)th inversion signal SIn+1 and output it, and the second comparator 118 may set the (n+1)th shift signal SSn+1 to the on level and output it. Since the OR operation result value of the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 is "1", and the values ​​of the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are equally "0", and the value of the (n+1_0)th data DPn+1[0] is "1", the value of the (n+1_0)th data DPn+1[0] is different. Therefore, the mode selector 119PS may turn off both the inversion enable signal IEn and the shift enable signal SEn. The mask unit 110MU may turn off the (n+1)th transformation signal Tsn+1 and output it.

[0183] In the fourth clock cycle clockcycle4, the data conversion logic 110DTa receives the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1 which are all deactivated, and can maintain and output "10100001 (2)" as it is. The data conversion logic 110DTa can provide "10100001 (2)" to the input terminals of the plurality of encoding flip-flops 111. The "10100001 (2)" input to the input terminals of the plurality of encoding flip-flops 111 can be latched to the output terminals of the plurality of encoding flip-flops 111 based on the clock signal clk.

[0184] exist Fig. 9 and Fig.10, the data encoding circuit 110 a may receive the (n+1)th data DPn+1[0:7] in the order of “01000001(2)”, “10100010(2)”, “11101111(2)”, and “10100001(2)” in the first clock cycle clockcycle1 to the fourth clock cycle clockcycle4. The data encoding circuit 110 a may output the (n+1)th data DPn+1[0:7] in the order of “01000001(2)”, “01010001(2)”, “00010000(2)”, and “10100001(2)” in the first clock cycle clockcycle1 to the fourth clock cycle clockcycle4. The data encoding circuit 110 a may output the (n+1)th conversion signal Tsn+1 in the order of “0(2)”, “1(2)”, “1(2)”, and “0(2)”.

[0185] Figure 11 to Figure 12 A description of an example of a decoding operation for a data decoding circuit is provided. Figure 11 to Figure 12 The following diagram shows the case where the coded data Do [0:m] (where m is 7) is input and output four times and the transformed signal Tso is output Figure 7 The operation of the data decoding circuit 120a.

[0186] Reference Figure 7 , Fig.11 and Fig.12 , the data decoding circuit 120a may receive "01000001 (2)" in the first clock cycle clockcycle1', "01010001 (2)" in the second clock cycle clockcycle2', "00010000 (2)" in the third clock cycle clockcycle3', and "10100001 (2)" in the fourth clock cycle clockcycle4' as the output coded data Do[0:7]. The data decoding circuit 120a may receive "0 (2)" in the first clock cycle clockcycle1', "1 (2)" in the second clock cycle clockcycle2', "1 (2)" in the third clock cycle clockcycle3', and "0 (2)" in the fourth clock cycle clockcycle4' as the output transformation signal Tso. The output coded data Do[0:7] and the output transformation signal Tso received in the first clock cycle clockcycle1' to the fourth clock cycle clockcycle4' may be combined with the output coded data Do[0:7] and the output transformation signal Tso received in the first clock cycle clockcycle1' to the fourth clock cycle clockcycle4'. Fig. 9 and Fig.10The (n+1)th encoded data Dn+1[0:7] output from the data encoding circuit 110 a in the first clock cycle clockcycle1 to the fourth clock cycle clockcycle4 match the (n+1)th converted signal Tsn+1.

[0187] In addition, as referenced Figure 7 As described, in some embodiments, the mode selector 129PS may cut off both the output inversion signal SIo and the output shift signal SSo when the value of the output transformation signal Tso is "0" to determine the decoding operation for the output coded data Do[0:m] as a maintenance operation. When the value of the output transformation signal Tso is "1" corresponding to the conduction level, and the 0th output coded data and the first output coded data Do[0:1] are different from each other, the mode selector 129PS cuts off the output inversion signal SIo and sets the output shift signal SSo to the conduction level, thereby determining the decoding operation for the output coded data Do[0:m] as a shift operation. When the value of the output transformation signal Tso is "1" and the 0th output coded data and the first output coded data Do[0:1] are equal to each other, the mode selector 129PS sets the output inversion signal SIo to the conduction level and cuts off the output shift signal SSo, thereby determining the decoding operation for the output coded data Do[0:m] as an inversion operation. However, the determination operation of the mode selector 129PS is an example, and implementations of the mode selector 129PS having other operations are within the scope of the present disclosure.

[0188] In the first clock cycle clockcycle1', the output conversion signal Tso received by the decoding control unit 129 is "0 (2)", and thus the mode selector 129PS may turn off and output both the output inversion signal SIo and the output shift signal SSo. The data conversion logic 120DTa may receive the output inversion signal SIo and the output shift signal SSo which are all turned off.

[0189] The data conversion logic 120DTa maintains "01000001 (2)" as the output coded data Do[0:7] as it is based on the turned-off output inversion signal SIo and the turned-off output shift signal SSo, and outputs "01000001 (2)", and provides it to the input terminals of the plurality of decoding flip-flops 121. The "01000001 (2)" input to the input terminals of the plurality of decoding flip-flops 121 can be latched to the output terminals of the plurality of decoding flip-flops 121 based on the clock signal clk.

[0190] In the second clock cycle clockcycle2', "01000001 (2)" is latched as the previous decoded data DDo-1[0:7] to the output terminals of the plurality of decode flip-flops 121, and "01010001 (2)" may be received as the output coded data Do[0:7]. The output conversion signal Tso received by the decoding control unit 129 is "1 (2)", the value of the 0th output coded data Do[0] is "1" and the value of the first output coded data Do[1] is "0" (they are different), the mode selector 129PS turns off the output inversion signal SIo, and sets the output shift signal SSo to the on level and outputs it.

[0191] The data conversion logic 120DTa performs a cyclic shift operation in a left direction by 1 bit on “01010001 (2)” based on the output shift signal SSo to output “10100010 (2)”, and outputs “10100010 (2)” at the input terminals of the plurality of decoding flip-flops 121. The “10100010 (2)” input to the input terminals of the plurality of decoding flip-flops 121 may be latched to the output terminals of the plurality of decoding flip-flops 121 based on the clock signal clk.

[0192] In the third clock cycle clockcycle3', "10100010 (2)" is latched as the previous decoded data DDo-1[0:7] to the output terminals of the plurality of decoding flip-flops 121, and the data decoding circuit 120 can receive "00010000 (2)" as the output coded data Do[0:7]. The output conversion signal Tso received at the decoding control unit 129 is "1 (2)", the value of the 0th output coded data Do[0] is "0", and the value of the first output coded data Do[1] is "0", so the 0th output coded data Do[0] and the first output coded data Do[1] have the same value. The mode selector 129PS can set the output inverted signal SIo to the on level and cut off the output shift signal SSo and output it.

[0193] The data conversion logic 120DTa performs an inversion operation on “00010000 (2)” as the output coded data Do[0:7] based on the output inversion signal SIo, and thus outputs “11101111 (2)” as the decoded data DDo[0:7], and provides it to the input terminals of the plurality of decoding flip-flops 121. The “11101111 (2)” input to the input terminals of the plurality of decoding flip-flops 121 may be latched to the output terminals of the plurality of decoding flip-flops 121 based on the clock signal clk.

[0194] In the fourth clock cycle clockcycle4', the output conversion signal Tso received at the decoding control unit 129 is "0 (2)", so the mode selector 129PS can turn off both the output inversion signal SIo and the output shift signal SSo and output them. The data conversion logic 120DTa can receive the output inversion signal SIo and the output shift signal SSo that are all turned off.

[0195] The data conversion logic 120DTa may maintain "10100001 (2)" as output coded data Do[0:7] as is based on the turned-off output inversion signal SIo and the turned-off output shift signal SSo, and output "10100001 (2)" as decoded data DDo[0:7]. The data conversion logic 120DTa may provide the decoded data DDo[0:7] to the input terminals of the plurality of decoding flip-flops 121. The "10100001 (2)" input to the input terminals of the plurality of decoding flip-flops 121 may be latched to the output terminals of the plurality of decoding flip-flops 121 based on the clock signal clk.

[0196] Refer to Figure 6 , Fig. 9 and Fig.10 , in the first clock cycle clockcycle1' to the fourth clock cycle clockcycle4', the decoded data DDo[0:7] output by the data conversion logic 120DTa is output in the order of "01000001 (2)", "10100010 (2)", "11101111 (2)" and "10100001 (2)", and the output order of the decoded data DDo[0:7] is equal to Fig. 9 and Fig.10 The input order of the (n+1)th data DPn+1[0:7].

[0197] exist Fig. 9 In the first clock cycle clockcycle1 of the data conversion logic 110DTa, the output “01000001 (2)” can be Fig.11 The first clock cycle clockcycle1′ in is decoded by performing a maintenance operation by the data transformation logic 120DTa.

[0198] exist Fig. 9 In the second clock cycle clockcycle2, the data conversion logic 110DTa shifts the bits rightward in units of 1 bit and outputs "01010001 (2)" which can be Fig.11In the second clock cycle clockcycle2', the data conversion logic 120DTa cyclically shifts the cyclic shift operation in units of 1 bit to the left and decodes the cyclic shift operation. However, the shift direction of the cyclic shift operation performed in the data conversion logic 110DTa and the shift direction of the cyclic shift operation performed in the data conversion logic 120DTa are different from each other.

[0199] exist Fig.10 The “00010000 (2)” inverted and output by the data conversion logic 110DTa in the third clock cycle clockcycle3 can be Fig.12 The third clock cycle clockcycle3' is inverted and decoded by the data conversion logic 120DTa.

[0200] exist Fig.10 The "10100001 (2)" output by the data conversion logic 110DTa performing the maintenance operation in the fourth clock cycle clockcycle4 can be Fig.12 The fourth clock cycle clockcycle4′ is decoded by performing a maintenance operation by the data transformation logic 120DTa.

[0201] By setting the determination operation of the mode selector 119PS of the data encoding circuit 110 and the mode selector 129PS of the data decoding circuit 120 , the reliability of the encoding / decoding operation of the data encoding circuit 110 and the data decoding circuit 120 can be improved.

[0202] Reference Figures 9 to 12 , the clock gating operation in the multiple encoding clock gating circuits 112 is performed 16 times on the (n+1)th encoded data Dn+1[0:m] in the first clock cycle clockcycle1 to the fourth clock cycle to clockcycle4, and the clock gating operation in the multiple decoding clock gating circuits 122 is performed 11 times on the decoded data DDo[0:m] in the first clock cycle clockcycle1' to the fourth clock cycle clockcycle4'.

[0203] The data encoding circuit 110 can reduce the number of data switching in a sequential circuit by performing encoding operations on data, and specifically, improve power consumption of transferring data by increasing the number of clock gating operations by increasing the efficiency of clock gating operations for continuously inputting / outputting data.

[0204] The data encoding circuit 110 can improve the clock signal transmitted by the data channel CW (refer to Figure 3 ) of all clock gate circuits CG00 to CGTx (refer to Figure 3 ) operational efficiency.

[0205] Fig.13 A description is provided for data encoding circuits according to some embodiments. Fig.13 For the purpose of describing a part of the data encoding circuit 110b. Figure 6 The data encoding circuit 110a compares the Fig.13 The data encoding circuit 110b will be described. Figure 6 The data conversion unit 110DTa is different from the data conversion unit 110DTb and Figure 6 The second bit operator 114a is different from the second bit operator 114b.

[0206] Reference Figure 6 and Fig.13 , the data transform unit 110DTb may include 0th to mth transform XOR operators TX_0 to TX_m and 0th to mth transform MUX TM′_0 to TM′_m.

[0207] Each of the 0th transformation MUX TM'_0 to the mth transformation MUX TM'_m may receive a result value of each of the 0th transformation XOR operators TX_0 to the mth transformation XOR operators TX_m and data cyclically shifted in the right direction by 2 bits for the (n+1)th data DPn+1[0:m], and may receive the (n+1)th shift signal SSn+1 as a selection signal. Each of the 0th transformation MUX TM'_0 to the mth transformation MUX TM'_m may output any one of the result value of each of the 0th transformation XOR operators TX_0 to the mth transformation XOR operators TX_m and the cyclically shifted data based on the (n+1)th shift signal SSn+1.

[0208] For example, the 0th transformation MUX TM'_0 may receive the result value of the 0th transformation XOR operator TX_0 and the (n+1_2)th data DPn+1[2], and may receive the (n+1)th shift signal SSn+1 as a selection signal. When the received (n+1)th shift signal SSn+1 is "0", the 0th transformation MUX TM'_0 outputs the result value of the 0th transformation XOR operator TX_0 and provides it to the 0th encoding flip-flop 111_0. When the received (n+1)th shift signal SSn+1 is "1", the 0th transformation MUX TM'_0 may output the (n+1_2)th data DPn+1[2] and provide it to the 0th encoding flip-flop 111_0.

[0209] In addition, the m-th transformation MUX TM'_m may receive the result value of the m-th transformation XOR operator TX_m and the (n+1_1)th data DPn+1[1], and receive the (n+1)th shift signal SSn+1 as a selection signal. When the (n+1)th shift signal SSn+1 is "0", the m-th transformation MUX TM'_m may output the result value of the m-th transformation XOR operator TX_m and provide it to the m-th encoding flip-flop 111_m. When the (n+1)th shift signal SSn+1 is "1", the m-th transformation MUX TM'_m may output the (n+1_1)th data DPn+1[1] and provide it to the m-th encoding flip-flop 111_m.

[0210] The data transform unit 110DTb may output the (n+1)th coded data Dn+1[0:m] obtained by performing any one of a maintenance operation, an inversion operation, and a cyclic shift operation on the (n+1)th data DPn+1[0:m] based on the (n+1)th inversion signal SIn+1 and the (n+1)th shift signal SSn+1, and provide the output coded data to the plurality of coding flip-flops 111. Specifically, the cyclic shift operation of the data transform unit 110DTb may shift in units of 2 bits.

[0211] The second bit operator 114b may include a 0th XNOR operator 114XN'_0 to an mth XNOR operator 114XN'_m. The 0th XNOR operator 114XN'_0 to the mth XNOR operator 114XN'_m may perform an XNOR bit operation on the nth coded data Dn[0:m] latched to the output terminals of the 0th coded flip-flops 111_0 to the mth coded flip-flops 111_m and data cyclically shifted in the right direction by 2 bits with respect to the (n+1)th data DPn+1[0:m].

[0212] For example, the 0th XNOR operator 114XN'_0 may perform an XNOR operation on the (n_0)th coded data Dn[0] latched to the 0th coding flip-flop 111_0 and the (n+1_2)th data DPn+1[2] input to the input terminal of the first coding flip-flop 111_1, and output and provide the 0th XNOR result value XNORout[0] to the second adder 116. In addition, the mth XNOR operator 114XN'_m may perform an XNOR operation on the (n_m)th coded data Dn[m] latched to the output terminal of the mth coding flip-flop 111_m and the (n+1_1)th data DPn+1[1] input to the input terminal of the first coding flip-flop 111_1, and output and provide the mth XNOR result value XNORout[m] to the second adder 116.

[0213] The XNOR result values ​​XNORout[0:m] of the 0th to mth XNOR operators 114XN′_0 to 114XN′_m may be transmitted to the second adder 116 through the 0th to mth shift loop prevention buffers SLB_0 to SLB_m. When the enable signal EN is input to the 0th to mth shift loop prevention buffers SLB_0 to SLB_m, the XNOR result values ​​XNORout[0:m] may be input to the second adder 116.

[0214] Fig.14 A description is provided for data decoding circuitry according to some embodiments. Fig.14 is provided for the description of the data decoding circuit 120b. For ease of description, Figure 7 The data decoding circuit 120a is compared to describe Fig.14 Specifically, the data decoding circuit 120b will be mainly described. Figure 7 The data transformation unit 120DTa is different from the data transformation unit 120DTb.

[0215] Reference Figure 7 and Fig.14 In some embodiments, the data transform unit 120DTb may include 0th to mth decoding XOR operators DX_0 to DX_m and 0th to mth decoding MUX DM'_0 to DM'_m.

[0216] Each of the 0th to mth decoding MUX DM'_0 may receive a result value of each of the 0th to mth decoding XOR operators DX_0 to DX_m and data cyclically shifted in a left direction by 2 bits with respect to the output coded data Do[0:m], and may receive an output shift signal SSo as a selection signal (for clarity, Fig.14 Some SSo connections are omitted). Each of the 0th to mth decoding MUX DM'_0 to DM'_m may output any one of a result value of each of the 0th to mth decoding XOR operators DX_0 to DX_m and cyclic shift data based on the output shift signal SSo.

[0217] For example, the 0th decoding MUX DM'_0 may receive the result value of the 0th decoding XOR operator DX_0 and the m-1th output coded data Do[m-1], and may receive the output shift signal SSo as a selection signal. When the output shift signal SSo is "0", the 0th decoding MUX DM'_0 may output the result value of the 0th decoding XOR operator DX_0 and provide it to the 0th decoding flip-flop 121_0. When the output shift signal SSo is "1", the 0th decoding MUX DM'_0 may output the m-1th output coded data Do[m-1] and provide it to the 0th decoding flip-flop 121_0.

[0218] In addition, the first decoding MUX DM'_1 may receive the result of the first decoding XOR operator DX_1 and the m-th output coded data Do[m], and may receive the output shift signal SSo as a selection signal. When the output shift signal SSo is "0", the first decoding MUX DM'_1 may output the result value of the first decoding XOR operator DX_1 and provide it to the first decoding flip-flop 121_1. When the output shift signal SSo is "1", the first decoding MUX DM'_1 may output the m-th output coded data Do[m] and provide it to the first decoding flip-flop 121_1.

[0219] Fig.15 A description is provided for data encoding circuits according to some embodiments. Fig.15 A description of the data conversion unit 110DTc provided for the data encoding circuit 110c is provided. Figure 6 The data conversion unit 110DTa is compared to describe Fig.15 The data transformation unit 110DTc.

[0220] The data transform unit 110DTc may include 0th transform MUX TM′_0 to mth transform MUX TM′_m.

[0221] Each of the 0th transformation MUX TM''_0 to the mth transformation MUX TM''_m can receive each bit of the (n+1)th data DPn+1[0:m], each bit of the (n+1)th inverted data DIn+1[0:m] for the (n+1_0)th data DPn+1[0], and each bit cyclically shifted in the right direction by 1 bit for each of the (n+1)th data DPn+1[0:m], and can receive the (n+1)th shift signal SSn+1 and the (n+1)th inverted signal SIn+1 as selection signals. Each of the 0th transformation MUX TM′′_0 to the mth transformation MUX TM′′_m can output any one of the (n+1)th data DPn+1[0:m], the (n+1)th inverted data DIn+1[0:m] and the cyclically shifted data based on a combination of the (n+1)th shift signal SSn+1 and the (n+1)th inverted signal SIn+1.

[0222] For example, the 0th transformation MUX TM''_0 may receive the (n+1_0)th data DPn+1[0], the (n+1)th inverted data DIn+1[0], and the (n+1_1)th data DPn+1[1], and may receive the (n+1)th shift signal SSn+1 and the (n+1)th inverted signal SIn+1 as selection signals. Through the combination of the (n+1)th shift signal SSn+1 and the (n+1)th inverted signal SIn+1, the 0th transformation MUX TM''_0 may output any one of the (n+1_0)th data DPn+1[0], the (n+1)th inverted data DIn+1[0], and the (n+1_1)th data DPn+1[1] as the (n+1_0)th coded data Dn+1[0].

[0223] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of possible claims. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in a specific combination, one or more features from the combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0224] Some examples have been described in detail above, but the scope of the present disclosure is not limited thereto, and many changes and improvements made by those of ordinary skill in the art using the concept of the present disclosure may also fall within the scope of the present disclosure.

Claims

1. A system on chip, comprising: a bus including a data channel through which data is sent in at least one direction; as well as The main interface is configured as: receiving first data from a data channel, performing a bit operation on first data and second data input before input of the first data, determining an encoding operation for the first data based on a result of the bit operation; performing an encoding operation on the first data to obtain encoded data; as well as The encoded data and a transform signal indicating the encoding operation are provided to the data channel.

2. The system on chip according to claim 1, wherein: The encoding operation includes a maintenance operation, an inversion operation, or a cyclic shift operation.

3. The system on chip according to claim 2, wherein: The conversion signal is 1 bit.

4. The system on chip according to claim 3, wherein: The master interface is configured to provide a first transform signal indicating an inversion operation and a second transform signal indicating a cyclic shift operation, and The first transformation signal and the second transformation signal are the same.

5. The system on chip according to claim 3, wherein: The master interface is configured to provide a first switching signal indicating an inverting operation and a second switching signal indicating a maintenance operation, and The first transformed signal and the second transformed signal are different from each other.

6. The system on chip according to claim 2, wherein: The cyclic shift operation includes shifting the first data in units of 2 bits.

7. The system on chip according to claim 1, wherein: The main interfaces include: a first bit operator that performs an XOR bit operation on the first data and the second data to output an XOR result value; and The second bit operator outputs an XNOR result value by performing an XNOR bit operation on the first shifted data and the second data obtained by performing the cyclic shift operation on the first data.

8. The system on chip according to claim 7, wherein: The main interfaces include: a first adder configured to output a first sum value by bit counting the XOR result value; a second adder configured to output a second sum value by bit counting the XNOR result value; a first comparator configured to output an inverted signal based on the first sum value and the number of bits of the first data; and The second comparator is configured to output a shift signal based on the first sum value, the second sum value, and the number of bits of the first data.

9. The system on chip according to claim 8, wherein: The first comparator is configured to output an inversion signal based on whether the first sum value is greater than a result obtained by dividing the number of bits of the first data by two.

10. The system on chip according to claim 8, wherein: The second comparator is configured to output a shift signal based on whether the second sum value is greater than a difference between the number of bits of the first data and the first sum value.

11. The system on chip according to any one of claims 1 to 10, wherein: The main interface includes: a control unit configured to receive the inversion signal, the shift signal and at least a part of the first data, The inversion signal and the shift signal are based on the result of the bit operation.

12. The system on chip according to claim 11, wherein: The control unit is configured to output an inversion enable signal for the inversion signal and a shift enable signal for the shift signal, and The main interface is configured as: receiving an inverting signal, a shifting signal, an inverting enabling signal and a shift enabling signal, Enables the inversion and shift signals, and The transformed signal is output.

13. The system on chip according to claim 12, wherein: The control unit is configured to turn off the inversion enable signal and the shift enable signal when the first data and the second data are not provided to the data channel in a burst mode.

14. A system on chip, comprising: a bus including a data channel through which data is sent in at least one direction; as well as From the interface, it is configured as: receiving coded data and a transform signal from a data channel, the transform signal indicating a coding operation performed to obtain the coded data, and A maintenance operation, an inversion operation, or a cyclic shift operation is performed on the encoded data based on at least a portion of the encoded data and based on the transformed signal.

15. The system on chip according to claim 14, wherein: The slave interface is configured to perform an inversion operation or a cyclic shift operation based on the conversion signal being 1 bit and being at an on level.

16. The system on chip according to claim 15, wherein: The slave interface is configured to perform the inversion operation based on the conversion signal being at an on level and based on the first bit of the encoded data and the second bit of the encoded data adjacent to each other being equal.

17. The system on chip according to claim 15, wherein: The slave interface is configured to perform a cyclic shift operation based on the conversion signal being at an on level and based on the first bit of the encoded data and the second bit of the encoded data being adjacent to each other being different.

18. A system on chip, comprising: a main interface configured to: perform a bit operation on first data and second data input before input of the first data, perform an encoding operation on the first data based on a result of the bit operation to obtain encoded data, and output the encoded data and a conversion signal indicating the encoding operation; A bus comprising: a data flip-flop configured to latch encoded data based on a clock signal, a clock gating circuit configured to clock-gate the clock signal, and a data channel configured to transmit the encoded data in at least one direction through the data flip-flop; as well as The slave interface is configured to receive the encoded data and the transformed signal from the bus, and perform a decoding operation on the encoded data based on at least a portion of the encoded data and based on the transformed signal.

19. The system on chip according to claim 18, wherein: The encoding operation is a first maintenance operation, and the decoding operation is a second maintenance operation, The encoding operation is a first inversion operation and the decoding operation is a second inversion operation, or The encoding operation is a first cyclic shift operation, and the decoding operation is a second cyclic shift operation.

20. The system on chip according to claim 19, wherein: the encoding operation is a first cyclic shift operation, and the decoding operation is a second cyclic shift operation, And wherein the shift direction in the encoding operation and the shift direction in the decoding operation are different from each other.

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