Timing analysis method, electronic device and storage medium based on abstract timing diagram

Abstract

The present invention relates to the technical field of EDA, and in particular to a timing analysis method, electronic device and storage medium based on an abstract timing diagram. The method establishes a basic timing diagram, wherein the basic timing diagram includes basic nodes and basic edges, wherein the basic nodes include top-level nodes, nodes between the starting point or the end point of a data path where a module boundary point is located, and when the starting point or the end point is a timing unit, nodes on a clock path formed by a clock input end of the timing unit and a clock input starting point; establishes an abstract timing diagram, wherein the abstract timing diagram includes abstract nodes and abstract edges, wherein the abstract nodes include top-level nodes, internal abstract nodes and module boundary points connected to the internal abstract nodes, wherein the internal abstract points are all starting points or end points of all data paths where the module boundary points connected to the internal abstract points are located in the basic timing diagram; and performs timing analysis according to the abstract timing diagram. The scheme reduces the analysis complexity and the memory occupied, and greatly improves the analysis speed.

Description

Technical Field

[0001] The present invention relates to the technical field of EDA, and in particular to a timing analysis method based on an abstract timing diagram, an electronic device and a storage medium. Background Art

[0002] Very large chip designs often have hundreds of millions of logic gates, registers and other circuit elements. In digital verification, this very large chip design needs to be divided into multiple FPGAs, and the division of FPGAs requires routing design. During the routing process, the optimal routing strategy is iteratively calculated based on the timing analysis results. Timing analysis based on FPGA blocks is a common optimization method. User designs are divided into multiple FPGAs, which causes the timing path to cross the FPGA boundary. The external delay between FPGAs is higher than the internal delay of the FPGA. In order to increase the operating frequency, the transmission time on these timing paths needs to be optimized. Therefore, a technology that can quickly provide timing results based on the delay of different external FPGA connection schemes is needed. The cross-FPGA timing path usually has multiple potential timing paths inside the FPGA. For example, when there is a cross-FPGA timing path between the first FPGA1 and the second FPGA2, the timing path connects an output port of FPGA1 and another input port of FPGA2, and there are m starting points inside FPGA1 that can reach the output port, and the output port inside FPGA2 can reach the end point of n timing paths, that is, there are actually m×n potential timing paths from the starting point to the end point of a cross-FPGA timing path. And because each path may contain different timing information, for example, the start and end registers of the timing path may be driven by multiple driving clocks and different timing constraints, the actual situation that needs to be analyzed will increase in compound growth. Assuming that there are an average of l types of timing information on each cross-FPGA timing path, it is actually necessary to analyze m×n×l situations that need to be analyzed. And there are many repeated situations, which will reduce the analysis efficiency. If the traditional block timing analysis model ILM is used, the graph structure in the ILM model is relatively complex, including more nodes and precise delay calculation, which leads to the model's insufficiency in memory usage and computational efficiency. If another traditional block timing analysis model ETM is used, when anomalies or constraints change, ETM needs to modify the existing constraints and apply them to new nodes, and also split the constraints into different modules (blocks). This process is not only cumbersome, but may also lead to model inconsistency and reduced analysis efficiency. Therefore, a timing analysis method that can reduce computational complexity and memory usage is urgently needed. Summary of the invention

[0003] In view of the above technical problems, the technical solution adopted by the present invention is: a timing analysis method based on an abstract timing diagram, characterized in that the method includes the following steps: establishing a basic timing diagram, the basic timing diagram includes basic nodes and basic edges, the basic nodes include top-level nodes, nodes between the starting point or end point of the data path where the module boundary point is located, and when the starting point or end point is a timing unit, the nodes on the clock path formed by the clock input end of the timing unit and the clock input starting point. Establishing an abstract timing diagram, the abstract timing diagram includes abstract nodes and abstract edges, the abstract nodes include top-level nodes, internal abstract nodes, and module boundary points connected to the internal abstract nodes, the internal abstract points represent all starting points or end points of all data paths where the module boundary points connected to the internal abstract points are located in the basic timing diagram. Performing timing analysis according to the abstract timing diagram.

[0004] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0005] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0006] The present invention has at least the following beneficial effects:

[0007] The timing analysis method, electronic device and storage medium based on the abstract timing graph provided by the embodiment of the present invention, the abstract nodes in the abstract timing graph are bound to the timing information of the basic nodes of the starting point or end point of the timing path, and the basic nodes in the basic timing graph do not include nodes on non-target timing paths and other nodes that are not traversed from the starting point or end point. Using the abstract timing graph to perform timing analysis in the verification system not only reduces the complexity of analysis, but also significantly improves the efficiency of analysis. In addition, the combination of the abstract timing graph and the basic timing graph greatly reduces the number of nodes and the timing information that needs to be stored compared to the traditional basic timing graph, thereby greatly reducing memory usage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A flow chart of a timing analysis method based on an abstract timing diagram provided by an embodiment of the present invention;

[0010] Figure 2 A schematic diagram of the gate-level netlist of a single module;

[0011] Figure 3 A schematic diagram of a basic timing diagram provided for an embodiment of the present invention;

[0012] Figure 4 A schematic diagram of an abstract timing diagram provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0014] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0015] See also Figure 1 , which shows a timing analysis method based on an abstract timing diagram, the method comprising the following steps:

[0016] S100, establish a basic timing diagram, which includes basic nodes and basic edges. The basic nodes include top-level nodes, nodes between the starting point or end point of the data path where the module boundary point is located, and nodes on the clock path formed by the clock input end of the timing unit and the clock input starting point when the starting point or end point is a timing unit.

[0017] Among them, the top-level node is the top-level port, which is the highest-level interface for the top-level module to interact with the outside world or other modules. It is used to receive signals or data from the outside and output the results of internal processing to the outside. The top-level port may be a data bus interface, a control signal line interface, or a clock signal line interface. The top-level module refers to a module that integrates all the components to be verified required for chip design verification into a whole. In one embodiment, the top-level module is the user's design under test (DUT).

[0018] In one embodiment, the module is a verification chip module to which the DUT is divided, for example, the verification chip is an FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit). In another embodiment, the module is a hierarchical module in a netlist, such as a module configured by Module in Verilog or a module configured by entity and architect in VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language). In another embodiment, the module is a group of circuit elements. Other types of modules also fall within the scope of protection of the present invention.

[0019] In one embodiment, the module boundary point is a port at the boundary of the verification chip module, or a boundary port of a hierarchical module, or a junction point where this group of components is connected to an external component by a wire. A portion of the chip ports in a verified chip are connected to the chip ports of other verification chips in the same top-level module, and the other portion is connected to the top-level port through an external interface. The top-level port may be connected to the chip ports of multiple verification chips through internal connections, such as buses, signal lines, etc.; the top-level port may also directly correspond to the chip port. In one embodiment, the module is a verification chip, wherein the verification chip is an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit) prototype verification chip or a hardware accelerator, and other types of chip types that need to optimize the critical path between cross-verification chips all fall within the scope of protection of the present invention. Other types of methods for establishing a model identical to the basic timing diagram through module division all fall within the scope of protection of the present invention.

[0020] Among them, a chip design usually needs to be divided into multiple verification chips, each verification chip contains a part of the chip design, and all verification chips are packaged as a whole to form a complete chip design.

[0021] Among them, see Figure 2 , Figure 2 A schematic diagram of the gate-level netlist of a single module is shown. In order to better illustrate the difference between the gate-level netlist traversed to build the basic timing diagram and the gate-level netlist traversed to build the traditional timing diagram, Figure 2All circuit elements and their connection relationships, that is, the circuit including the gray part, are the gate-level netlist traversed to establish the traditional timing diagram. After removing the gray part of the circuit, it is the gate-level netlist traversed to establish the basic timing diagram provided by the present invention. The module 100 includes a module boundary point 110 and a large number of circuit elements inside the module. Taking a timing path of the module boundary point 110 as an example, the steps of establishing the basic timing diagram include: starting from the module boundary point 110, traversing along the timing arcs of the circuit elements and the connection relationship between the elements, that is, traversing along the timing arc between the module boundary point 110 and the logic block 120, and stopping the traversal when traversing along the wire 150 to the register 130 of the data path, that is, the end point. Establish the basic nodes for the traversed pins respectively; then, starting from the driving clock pin of the register 130, traverse to the starting point clk1 of the clock path through the wire 160, and establish the basic nodes for the traversed pins; and establish the basic edges for the timing arcs between the traversed basic nodes. Each module boundary point and each timing path thereof are traversed to obtain a basic timing diagram. Therefore, compared with the traditional timing diagram, the basic timing diagram provided by the present invention greatly reduces the scale of the basic timing diagram.

[0022] Among them, see Figure 3 , Figure 3 The basic timing diagram of the top module is shown, which includes a top module 200, a plurality of top nodes 210 on the top module 200, three modules 100 inside the top module, and each module 100 includes a corresponding basic node inside. Figure 3 The timing path where the connection of the mid-span module is located is the target timing path. The target timing path may have a corresponding starting point (Startpoint) and a corresponding end point (Endpoint) in the two connected modules, that is, the starting point and the end point are located in different modules; it is also possible that there is no corresponding starting point or end point in the current module, but it passes through the current module, and its starting point or end point is in other modules. The starting point is a pin without a fan-in timing arc, or a clock pin of a timing unit, which is generally the location where the signal enters the data path, wherein the timing unit can be a latch or a register, and other types of timing units also fall within the protection scope of the present invention. The end point is a pin without a fan-out timing arc, or a specific pin where data must arrive at a certain time according to the inspection requirements in the timing model of the circuit element or the user timing constraints.

[0023] In one embodiment, the step of establishing the basic timing diagram includes: obtaining the module boundary point; traversing along the timing arcs of the circuit elements and the connection relationships between the elements with the module boundary point as the starting point, traversing to the starting point or end point of the data path, and establishing the basic nodes for the traversed pins respectively; when the starting point or end point is a timing unit, traversing to the starting point of the clock path with the driving clock pin of the timing unit as the starting point, and establishing the basic nodes for the traversed pins; establishing the path traversed between the basic nodes as the basic edge.

[0024] In another embodiment, the step of establishing the basic time sequence graph may be established during the traversal process, or may be performed by saving the corresponding basic nodes and basic edges during the traversal process, and establishing the basic time sequence graph uniformly after the traversal is completed.

[0025] In one implementation, the basic timing diagram further includes binding the current basic node and its timing information.

[0026] In one embodiment, the module boundary point is a basic node in the basic timing diagram. In another embodiment, the module boundary point is not a basic node in the basic timing diagram.

[0027] When obtaining the connection relationship from the module boundary point to the inside of the module, the circuit element pins directly connected to the module are obtained on the netlist through the netlist component elements corresponding to the module boundary points, and one or more basic nodes inside the module are obtained, so as to continue to obtain the connection relationship from these basic nodes to the inside of the module. For example, the netlist component elements corresponding to the module boundary points can be ports at the boundary of the module instance, wire connections (net), or pins of circuit elements in the module.

[0028] When obtaining the connection relationship between the module boundary point and the outside of the module, the top-level module port directly connected to the outside of the module is obtained on the netlist through the netlist component element corresponding to the module boundary point, and the connection relationship between the module boundary point and the top-level node is obtained; or, the netlist component element corresponding to the module boundary point is obtained on the netlist through the netlist component element corresponding to the module boundary point, and the connection relationship between the module boundary point and the module boundary points in other modules is obtained. The netlist includes the connection relationship between all pins, so all types of connection relationships can be obtained through the netlist.

[0029] In one implementation, the traversal search algorithm is a depth-first search algorithm (DFS) or a breadth-first search algorithm (BFS). Other algorithms for traversing and searching for sequential paths fall within the protection scope of the present invention.

[0030] When the module boundary point is an input port, a forward traversal search is performed, and when the module boundary point is an output port, a reverse traversal search is performed.

[0031] The circuit element may be a sequential logic unit, a combinational logic unit or other circuit modules. A sequential unit is a sequential logic circuit, a logic unit used to control the timing of signal transmission and synchronous operation, with a storage function, capable of maintaining a state and changing the output under certain conditions.

[0032] In one implementation, the sequential unit is a trigger or a latch, and the trigger is a D trigger, a JK trigger, or a T trigger. The latch is a D latch. Other types of sequential units also fall within the protection scope of the present invention.

[0033] The pins of the sequential unit at least include a clock input pin, a data input pin and a data output pin. Other types of pins of the sequential unit also fall within the protection scope of the present invention.

[0034] In one embodiment, the marked timing information includes a driving clock and a timing constraint. The driving clock is a clock that drives the timing unit to work, such as driving the timing unit to read or write data. The timing constraint is a user-input description of the timing behavior of the signal in the circuit design, which constrains the content of the timing analysis, such as defining the clock, clock characteristics, defining fixed logic condition analysis (case analysis), defining false paths (false paths), defining multi-clock paths (multicycle paths) and other special cases. Other types of marked timing information also fall within the scope of protection of the present invention.

[0035] Among them, the timing arc describes the relationship of the signal propagating from one point to another in the circuit, which is divided into a cell arc and a net arc. A cell arc is usually the signal propagation path from the input pin to the output pin of a combinational logic unit; or the signal from the clock input pin to the output pin of a sequential logic unit, or from the clock input pin to other input pins of a sequential unit. A net arc is the path between the output pin of one unit and the input pin of another unit.

[0036] In one embodiment, after the basic timing diagram is established, a preliminary timing analysis and timing information collection are performed. The preliminary timing analysis includes modifying the diagram, such as disconnecting certain basic edges in the diagram or making certain basic nodes unavailable according to fixed logic states (case values), initial values ​​of cells, and user constraints. The timing information collection includes collecting the driving clock of each register and the timing constraints actually met.

[0037] Among them, the basic timing diagram is different from the ordinary timing diagram. The ordinary timing diagram needs to establish a corresponding relationship for each circuit element. The nodes in the basic timing diagram provided by the embodiment of the present invention are not the pins of all circuit elements, but the pins and top-level nodes of all elements passed on the timing path across modules. Other pins are not in the basic timing diagram. On the basis of retaining the role of the ordinary timing diagram in the timing path optimization, it further reduces the objects that need to be processed, saves computing resources, and improves the speed of establishing and analyzing the basic timing diagram.

[0038] S200, establish an abstract timing diagram, the abstract timing diagram includes abstract nodes and abstract edges, the abstract nodes include top nodes, internal abstract nodes and module boundary points connected to the internal abstract nodes, the internal abstract points represent all starting points or end points of all data paths where the module boundary points connected to the internal abstract points are located in the basic timing diagram. Figure 4 , which shows Figure 3 The abstract timing diagram after abstraction only includes the top-level port 210, the module boundary point 110, and the internal abstract nodes 170 connected thereto. Figure 4 The abstract timing diagram shown is compared to Figure 3 The basic timing diagram greatly reduces the number of nodes. At the same time, since the timing information of the corresponding start and end points is bound to each internal abstract node, the abstract timing diagram can reduce the scale of the abstract timing diagram and the area of ​​​​storage space occupied while ensuring that the timing information that meets the requirements is provided. At the same time, due to the reduction in the number of nodes, the optimization efficiency of the timing path is improved.

[0039] The internal abstract node also includes the timing information of the launch clock and capture clock of all the timing paths. The launch clock is a driving clock signal for driving the timing unit at the signal transmitting end, for example, the timing unit is a trigger or a register. The trigger clock and the drive clock may be the same or related, or they may not be related. The capture clock is the driving clock signal of the timing unit at the signal receiving end.

[0040] In one embodiment, the step of establishing the abstract timing diagram includes: establishing the abstract nodes, the abstract nodes including the top-level nodes, the module boundary points and the internal abstract nodes; establishing the abstract edges connecting the abstract nodes, the abstract edges including the abstract edges connecting the internal abstract nodes and the module boundary points, the abstract edges connecting the module boundary points and the top-level nodes, and the abstract edges between the module boundary points. The abstract edges between the module boundary points include the abstract edges between the boundary points of different modules established according to the netlist, and the abstract edges within the module established according to the connection relationship obtained during traversal and passing through the input boundary points and output boundary points of the same module.

[0041] In one implementation, after the step of establishing the abstract timing diagram, the step further includes: merging the timing information of the starting point or the end point corresponding to the abstract node and binding it with the abstract node.

[0042] In one embodiment, the internal abstract node is bound to the basic node information, and the basic node information acquisition step includes: S210, traversing all basic nodes belonging to the module in the basic timing diagram from the module boundary point as the starting point, and taking the traversed starting point or end point as the basic node information. The binding of the basic node information is helpful for the subsequent update of the abstract timing diagram.

[0043] S300, performing timing analysis according to the abstract timing diagram.

[0044] Among them, in the abstract timing diagram, an internal abstract node is used to represent the basic nodes corresponding to all the starting points or end points of all timing paths where the corresponding module boundary points are located in the current module, and all basic nodes are bound to the abstract node. This method can further abstract the basic timing diagram and effectively reduce the number of billions of nodes that originally need to be processed to the order of millions or even hundreds of thousands, which can greatly reduce the order of magnitude of nodes to be analyzed in timing analysis, thereby greatly improving the analysis efficiency.

[0045] Among them, compared with the traditional abstract timing diagram, the abstract timing diagram has at least the following three advantages: First, since the internal nodes in the abstract timing diagram provided by the present invention are formed by merging multiple starting points or end points in the basic timing diagram, and do not include other nodes, the number of nodes is greatly reduced. The reduction in the number of nodes can greatly reduce the occupancy of memory space and improve the analysis efficiency. For example, the number of billion-level nodes that originally need to be processed is effectively reduced to the order of millions or even hundreds of thousands, thereby greatly improving the analysis efficiency, and the time required for a complete timing analysis is also reduced by several orders of magnitude. Second, since the internal abstract nodes corresponding to the same module boundary point in the abstract timing diagram provided by the embodiment of the present invention may correspond to multiple basic nodes, the repeated information on these multiple basic nodes is merged to further reduce the amount of information. Thirdly, since the basic timing diagram provides a complete and accurate representation of the circuit and can capture all relevant timing details, timing information is collected on the basic timing diagram, such as fixed logic state (case value), timing exceptions, constraints, clock and other timing information, to ensure the accuracy of timing analysis; since the abstract timing diagram is a simplified representation of the basic timing diagram and removes some unnecessary details, the propagation of arrival time and time margin (slack) are calculated on the abstract timing diagram, taking into account both efficiency and accuracy.

[0046] The abstract timing diagram may be optimized during or after its establishment. The following two implementations are optimizations performed at different stages.

[0047] In one embodiment, after establishing the abstract edge connecting the abstract nodes, the following optimization steps are also included: traversing the module in the basic timing diagram according to the module boundary point, and performing the following steps according to the result of the traversal: when the basic node inside the module that serves as the starting point or end point of the timing path does not exist, deleting the internal abstract node connected to the current module boundary point: when the abstract path obtained by traversal starts from the top-level node, passes through the module boundary point, and ends at the internal abstract node, or when the abstract path obtained by traversal is a path that will not introduce timing problems, deleting the abstract path.

[0048] In another embodiment, the process of establishing the internal abstract node also includes the following optimization steps: when traversing the interior of the module in the basic timing diagram according to the module boundary point, the following steps are performed according to the traversal result: when the basic node inside the module that serves as the starting point or end point of the timing path does not exist, the internal abstract node is not established for the module boundary point; when the abstract path obtained by traversal starts from the top-level node, passes through the module boundary point, and ends at the internal abstract node, or when the abstract path obtained by traversal is a path that will not introduce timing problems, the internal abstract node and the abstract path are not established.

[0049] In one implementation, the path that does not introduce timing problems is a path to which timing is disabled or an asynchronous clock belongs. Other types of paths that do not introduce timing problems also fall within the protection scope of the present invention.

[0050] In one implementation, the internal abstract node in the abstract timing diagram is bound to the timing information related to the starting point or the end point associated with the internal abstract node in the basic timing diagram.

[0051] In one embodiment, the method further includes: S400, after obtaining the abstract timing diagram, deleting the basic timing diagram and the timing information marked on its nodes, and only retaining the abstract timing diagram and the timing information marks on its nodes to save memory.

[0052] In one embodiment, when modifying the netlist, the abstract timing diagram is partially modified and updated through the optimization steps provided in S500, and the basic timing diagram and the information bound to its nodes are not deleted. The method further includes: S500, updating the abstract timing diagram, and the updating step includes:

[0053] S510, obtain the target timing path, the target timing path is a timing path across modules; when adding a new circuit element on the target timing path, add a new basic node and a basic edge in the basic timing diagram, and update the timing information bound to the basic node; when deleting the circuit element on the target timing path, delete the basic node corresponding to the circuit element in the basic timing diagram and the timing information bound to it, and modify the connection relationship after deletion; when there are multiple target timing paths, and modify the connection relationship of the circuit element on the target timing path, and after modification, it is still connected to the current target timing path or other target timing paths, update the connection relationship between the basic nodes in the basic timing diagram and its timing information; when modifying the connection relationship of the circuit element on the target timing path, and after modification, it is not connected to the target timing path, delete the basic node corresponding to the circuit element in the basic timing diagram and the timing information bound to it. Other types of modifications also fall within the scope of protection of the present invention. After modifying the basic timing diagram, update the module boundary abstract nodes and internal abstract nodes in the corresponding abstract timing diagram and the timing information bound to them.

[0054] The newly added types of newly added circuit elements include newly added types in which the newly added circuit elements are connected to the target path, and newly added types in which the elements that were not originally on the path are connected to the target path by modifying their connections.

[0055] When both end nodes of the wire of the circuit element are not on the target timing path, it indicates that the current modification does not affect the basic timing diagram.

[0056] In one embodiment, the step of determining whether to add a new circuit element to the target timing path includes:

[0057] S511, if the fan-in node of the input pin or the fan-out node of the output pin of the modified connection of the circuit element is on the target timing path, then determine that the current modification is to add a circuit element on the target timing path. In the step of modifying the netlist, only a small amount of modification can be made to the part of the graph that needs to be modified, thereby saving time to recreate the entire block graph.

[0058] In one implementation, since the modification is implemented based on the original basic timing diagram, if the number of modified nodes is of the same order of magnitude as the node size of the original basic timing diagram, the shortening of the running time will not be significant, and when the number is large, it may even be slower than the creation time of the entire basic timing diagram. Therefore, when the number of elements on the updated basic timing diagram reaches 1 / Q times of all elements, the basic timing diagram and the abstract timing diagram are cleared, and the basic timing diagram and the abstract timing diagram are re-established.

[0059] In one embodiment, the method further comprises a step of calculating a time margin:

[0060] S800, obtain the internal delay of the module and the external delay of the timing path across modules in the abstract timing diagram, and calculate the time margin (slack) according to the internal delay and the external delay. Among them, the internal delay of the module includes the delay between the internal abstract node of the module and the module boundary abstract node or the delay between the boundary input abstract node and the boundary output abstract node of the same module. The time margin is related to the clock cycle, the structure of the timing path and the delay across modules, and may also be related to the specific path of the basic node in the module. That is, for the scenario where wiring across modules needs to be performed by modifying the delay, it iteratively updates and modifies the external delay, modifies the required arrival time of the corresponding pin in the abstract timing diagram, recalculates the time margin, and iteratively repeats the optimization steps to obtain the optimal wiring solution, which can reduce the computational complexity and reduce memory usage.

[0061] In one implementation, the internal delay is a preset value, or is estimated based on the number of internal basic nodes. Other types of methods for obtaining the internal delay also fall within the protection scope of the present invention.

[0062] The abstract timing diagram provided by the embodiment of the present invention may also be used to iteratively update a netlist or other information that affects the timing diagram structure, or to update only delays, and optimization steps that require obtaining the latest time data.

[0063] In summary, the timing analysis method based on the abstract timing graph provided by the embodiment of the present invention has an abstract node in the abstract timing graph that binds the timing information of the basic node of the starting point or end point of the timing path, and the basic node in the basic timing graph does not include nodes on the non-target timing path and other nodes that are not traversed from the starting point or end point. Using the abstract timing graph to perform timing analysis in the verification system not only reduces the complexity of analysis, but also significantly improves the efficiency of analysis. In addition, by combining the abstract timing graph and the basic timing graph, the number of nodes and the timing information required to be stored are greatly reduced compared with the traditional basic timing graph, thereby greatly reducing the memory usage; compared with the traditional abstract timing graph, since the preliminary timing analysis is performed on the reduced basic timing graph, it is more accurate in the exception judgment and required time calculation, and only the arrival time and time margin (slack) calculation part is performed on the abstract timing graph, which reduces the calculation complexity.

[0064] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0065] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0066] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0067] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0068] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A timing analysis method based on an abstract timing diagram, characterized in that: The method comprises the following steps: Establish a basic timing diagram, wherein the basic timing diagram includes basic nodes and basic edges, wherein the basic nodes include top-level nodes, nodes between the starting point or the end point of the data path where the module boundary point is located, and nodes on the clock path formed by the clock input end of the timing unit and the clock input starting point when the starting point or the end point is a timing unit; wherein the top-level node is a top-level port; the module boundary point is a port for verifying the chip module boundary, or a boundary port of a hierarchical module, or a junction point where a group of components are connected to an external component by a wire; Establish an abstract timing graph, the abstract timing graph includes abstract nodes and abstract edges, the abstract nodes include top-level nodes, internal abstract nodes and module boundary points connected to the internal abstract nodes, each of the internal abstract nodes represents the basic nodes corresponding to all starting points or end points of all data paths where the corresponding module boundary point is located in the basic timing graph; Performing timing analysis according to the abstract timing diagram; The steps of establishing the basic timing diagram include: Obtaining the module boundary point; Taking the module boundary point as the starting point, traverse along the timing arcs of the circuit elements and the connection relationship between the elements to the starting point or end point of the data path, and establish the basic nodes for the traversed pins respectively; when the starting point or end point is a timing unit, take the driving clock pin of the timing unit as the starting point to traverse to the starting point of the clock path, and establish the basic nodes for the traversed pins; establish the path traversed between the basic nodes as the basic edge.

2. The method according to claim 1, characterized in that The steps of establishing the abstract timing diagram include: Establishing the abstract node, wherein the abstract node includes a top-level node, the module boundary point and the internal abstract node; The abstract edges connecting the abstract nodes are established, wherein the abstract edges include the abstract edges connecting the internal abstract nodes and the module boundary points, the abstract edges connecting the module boundary points and the top-level nodes, and the abstract edges between the module boundary points.

3. The method according to claim 2, characterized in that After establishing the abstract edges connecting the abstract nodes, the following optimization steps are also included: According to the module boundary point, the module in the basic timing diagram is traversed internally, and the following steps are performed according to the traversal result: When the basic node as the starting point or end point of the timing path inside the module does not exist, delete the internal abstract node connected to the current module boundary point: When the traversed abstract path starts from the top-level node, passes through the module boundary point, and ends at the internal abstract node, or when the traversed abstract path is a path that will not introduce timing problems, the abstract path is deleted.

4. The method according to claim 2, characterized in that: In the process of establishing the internal abstract node, the following optimization steps are also included: when traversing the module inside the basic timing diagram according to the module boundary point, the following steps are performed according to the traversal result: When the basic node in the module that is the starting point or the end point of the timing path does not exist, the internal abstract node is not established for the module boundary point: When the abstract path obtained by traversal starts from the top-level node, passes through the module boundary point, and ends at the internal abstract node, or when the abstract path obtained by traversal is a path that will not introduce timing problems, the internal abstract node and the abstract path are not established.

5. The method according to claim 1, characterized in that After the step of establishing the abstract timing diagram, the method further includes: merging the timing information of the starting point or the end point corresponding to the abstract node and binding it with the abstract node.

6. The method according to claim 1, characterized in that The method further includes: S500, updating the abstract timing diagram, the updating step including: Obtaining a target timing path, where the target timing path is a timing path across modules; When a circuit element is added to the target timing path, a basic node and a basic edge are added to the basic timing graph, and the timing information bound to the basic node is updated; When deleting a circuit element on the target timing path, deleting the basic node corresponding to the circuit element in the basic timing diagram and the timing information bound thereto, and modifying the connection relationship after the deletion; When there are multiple target timing paths, and the connection relationship of the circuit elements on the target timing path is modified, and the circuit elements are still connected to the current target timing path or other target timing paths after modification, the connection relationship between the basic nodes in the basic timing diagram and the timing information thereof are updated; When the connection relationship of the circuit element on the target timing path is modified and is no longer connected to the target timing path after the modification, the basic node corresponding to the circuit element in the basic timing diagram and the timing information bound thereto are deleted.

7. The method according to claim 1, characterized in that The step of performing timing analysis according to the abstract timing diagram includes: obtaining the internal delay of the module and the external delay of the timing path across the modules in the abstract timing diagram, and calculating the time margin according to the internal delay and the external delay.

8. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 7.

9. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 8.

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