Two-dimensional field-effect transistor model and construction method based on monolayer transition metal chalcogenides

Abstract

This invention relates to the field of semiconductor device design and simulation, and discloses a two-dimensional field-effect transistor (FET) model and construction method based on a single-layer transition metal dichalcogenide compound. The method includes: setting the source and drain terminals of the two-dimensional FET to ohmic contacts with the two-dimensional material to construct a charge model of the FET; constructing a capacitance model of the FET, including quantum capacitance and parasitic capacitance, based on the charge determined by the charge model according to the relationship between charge and capacitance; determining the parasitic capacitance between the layers of the two-dimensional FET, and transforming the circuit composed of parasitic capacitance into a static capacitance network, constructing a channel voltage model of the FET based on the relationship between capacitance and voltage; determining a general channel current model, and combining the voltage-capacitance-charge relationship determined by the channel voltage model with the general channel current model to obtain the final channel current model. This invention can improve the performance and efficiency of low-power electronic devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device design and simulation technology, and in particular to a two-dimensional field-effect transistor model and construction method based on a single-layer transition metal chalcogenide compound. Background Technology

[0002] With the development of two-dimensional material technology, monolayer transition metal dichalcogenides (TMDs) have attracted widespread attention due to their excellent electronic and physical properties. These materials are unique in that they can significantly improve the performance of field-effect transistors (FETs), especially in low-power applications. However, two-dimensional material transistors are ultimately intended for large-scale circuits and are currently only used in simple circuits with a small number of transistors. With continuous improvements in two-dimensional materials and transistor generation technology, large-scale circuit applications will soon become feasible. In this process, modeling the electrical characteristics of two-dimensional material transistors is essential, including device design optimization, performance prediction, and the exploration of low-power switching circuits.

[0003] Existing two-dimensional transistor models typically suffer from the following problems: 1. They fail to consider the unique quantum capacitance effect and anomalous charge carrier transport mechanisms inherent in two-dimensional materials. 2. They simply model the intrinsic characteristics of the device based on the capacitance network, meaning such models are not scalable. 3. They lack proper definitions and distinctions regarding drift and diffusion currents, chemical or Fermi potentials (or voltages), and electrostatic potentials, failing to comprehensively characterize the transistor. 4. They only consider intrinsic properties, making the models overly idealized.

[0004] The aforementioned problems limit the application of TMD in the design of novel two-dimensional semiconductor devices. Therefore, designing a model that can characterize the transistor effects and mechanisms of two-dimensional materials becomes particularly crucial. Summary of the Invention

[0005] To address the aforementioned problems, the purpose of this invention is to provide a two-dimensional field-effect transistor model and construction method based on a single-layer transition metal chalcogenide compound. This model can improve the performance and efficiency of low-power electronic devices by utilizing a single-layer transition metal chalcogenide compound, and can lay the foundation for subsequent design and simulation of complex circuits.

[0006] To achieve the above objectives, in a first aspect, the technical solution adopted by the present invention is as follows: a method for constructing a two-dimensional field-effect transistor model based on a single-layer transition metal chalcogenide compound, comprising: setting the source and drain terminals of the two-dimensional field-effect transistor to ohmic contact with the two-dimensional material, and constructing a charge model of the two-dimensional field-effect transistor; constructing a capacitance model of the two-dimensional field-effect transistor including quantum capacitance and parasitic capacitance based on the charge determined by the charge model according to the relationship between charge and capacitance; determining the parasitic capacitance between each layer of the two-dimensional transistor, and transforming the circuit composed of parasitic capacitance into a static capacitance network, and constructing a channel voltage model of the two-dimensional field-effect transistor according to the relationship between capacitance and voltage; determining a general channel current model, and combining the voltage, capacitance and charge relationship determined by the channel voltage model with the general channel current model to obtain the final channel current model.

[0007] Furthermore, a charge model for a two-dimensional field-effect transistor is constructed, including: defining the voltage drop V on the surface of the two-dimensional material in the L region. C and the Fermi-Dirac function f F (E), intermediate band E0 and effective mass D0 are simplified respectively; L is the length of the back gate oxide layer;

[0008] Based on the simplified parameters, the charge model is determined as follows:

[0009]

[0010] In the formula, Q c This is a charge model, where q is the electron charge, and DOS is... 2D (E) is the two-dimensional density of states function, f(E) F -E) is the Fermi-Dirac distribution function, E is the mid-bandgap of the semiconductor, E F It is the Fermi level.

[0011] Furthermore, based on the charge determined by the charge model, a capacitance model is constructed inside the two-dimensional field-effect transistor, including quantum capacitance and parasitic capacitance. This includes: differentiating the potential of the charge model according to the relationship between charge and capacitance to obtain the capacitance model; the capacitance model is:

[0012]

[0013] In the formula, C q For the capacitance model, C q,p For hole-dominated quantum capacitors, C q,n For electron-dominated quantum capacitance, k is the Boltzmann constant, T is room temperature, and m * For the effective mass of electrons, It is Planck's constant.

[0014] Furthermore, the parasitic capacitances between the layers of the two-dimensional transistor are determined, including: the top oxide capacitance is C. t Monolayer molybdenum disulfide quantum capacitors are C q The bottom oxide capacitor is C. b .

[0015] Furthermore, a channel voltage model for a two-dimensional field-effect transistor is constructed based on the relationship between capacitance and voltage. This includes: transforming the circuit composed of parasitic capacitances between the material layers of the two-dimensional transistor into a static capacitor network; directly deriving the voltage-capacitance relationship using Kirchhoff's voltage and current laws; and obtaining the channel voltage model based on this voltage-capacitance relationship, as follows:

[0016]

[0017] In the formula, V c (x) represents the channel voltage model, V gs -V gs0 and V bs -V Bs0 These are the overdrive voltages of the top-gate source voltage and the back-gate source voltage, respectively, V. gs V is the gate-source voltage. gs0 V is the top-gate flat-band voltage. Bs V is the back gate voltage. bs0 Back gate flat band voltage, Q n (V c The contribution of electrons is emphasized here as V. c The function, the same as Q n V n (x) represents the electron concentration, C t For the top oxide capacitor, C b The bottom oxide capacitor.

[0018] Furthermore, a general channel current model is determined, including: assuming that the internal structure of the two-dimensional transistor channel is a drift-diffusion transport mechanism, the general channel current model is determined as follows:

[0019]

[0020] In the formula, This is a general channel current model, where W is the gate width, μ is the effective hole mobility, and V... cd V is the drain voltage drop of the quantum capacitor. cs Q is the voltage drop at the source of the quantum capacitor. n V is the charge of an electron. c V represents the channel voltage. n (x) is the potential of the NMOS at channel x.

[0021] Furthermore, the relationship between voltage, capacitance, and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model. This includes: differentiating the channel voltage determined by the channel voltage model and combining it with the capacitance-charge relationship to obtain the final channel current model from the general channel current model.

[0022]

[0023] In the formula, I ds For the final channel current model, E g This refers to the bandwidth of the no-bandwidth area.

[0024] Secondly, the technical solution adopted by the present invention is: a two-dimensional field-effect transistor model based on a single-layer transition metal chalcogenide compound. The model is established based on the above-mentioned two-dimensional field-effect transistor model construction method based on a single-layer transition metal chalcogenide compound. The two-dimensional field-effect transistor model includes: a charge model, a capacitance model, a channel voltage model, and a channel current model.

[0025] The charge model is:

[0026]

[0027] The capacitance model is as follows:

[0028]

[0029] The channel voltage model is as follows:

[0030]

[0031] The channel current model is as follows:

[0032]

[0033] In the formula, Q c This is a charge model, where q is the electron charge, and DOS is... 2D (E) is the two-dimensional density of states function, f(E) F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F For the Fermi level, C q For the capacitance model, C q,p For hole-dominated quantum capacitors, C q,n For electron-dominated quantum capacitance, k is the Boltzmann constant, T is room temperature, and V is... c (x) represents the channel voltage model, V gs -V gs0 and V bs -V bs0 These are the overdrive voltages of the top-gate source voltage and the back-gate source voltage, respectively, V.gs V is the gate-source voltage. gs0 V is the top-gate flat-band voltage. bs V is the back gate voltage. bs0 Q is the bottom-gate flat-band voltage. n (V c ) represents the charge of an electron, and V c Related to V n (x) represents the potential of the NMOS at channel x, C t For the top oxide capacitor, C b For the bottom oxide capacitor, I ds For the final channel current model, E g This refers to the bandwidth of the no-bandwidth area.

[0034] Thirdly, the technical solution adopted by the present invention is: a computer-readable storage medium for storing one or more programs, characterized in that the one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform any of the methods described above.

[0035] Fourthly, the technical solution adopted by the present invention is as follows: a computing device, comprising: one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for performing any of the methods described above.

[0036] The present invention has the following advantages due to the adoption of the above technical solutions:

[0037] The compact physical model provided by this invention is applicable to field-effect transistors containing a single layer of two-dimensional material. This model integrates the unique properties of two-dimensional materials, such as their contribution to quantum capacitance and the effect of parasitic capacitance, and the resulting impact on the electrical characteristics of the device. It also employs a drift-diffusion mechanism to describe carrier transport behavior, thereby improving the performance and efficiency of low-power electronic devices. Attached Figure Description

[0038] Figure 1 This is a flowchart of the method for constructing a two-dimensional field-effect transistor model based on a single-layer transition metal chalcogenide in this invention.

[0039] Figure 2 This is a schematic diagram of a two-dimensional field-effect transistor model in an embodiment of the present invention;

[0040] Figure 3 This is a front view of the two-dimensional field-effect transistor model in an embodiment of the present invention;

[0041] Figure 4This is a diagram showing the main capacitance distribution of the two-dimensional field-effect transistor model in this embodiment of the invention;

[0042] Figure 5 This is a schematic diagram of the transformation of a circuit composed of parasitic capacitors into a static capacitor network in an embodiment of the present invention;

[0043] Figure 6 This is a current-voltage characteristic curve (IV curve) of a two-dimensional transistor in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0045] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0046] In one embodiment of the present invention, a method for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide is provided. This method utilizes monolayer transition metal chalcogenides such as MoS2 and WSe2 to improve the performance and efficiency of low-power electronic devices. In this embodiment, as... Figure 1 , Figure 2 As shown, the method for constructing this model includes the following steps:

[0047] 1) Assume that the source and drain terminals of the two-dimensional field-effect transistor are in ohmic contact with the two-dimensional material, and construct the charge model Q of the two-dimensional field-effect transistor. c ;

[0048] 2) Based on the relationship between charge and capacitance, construct quantum capacitance and parasitic capacitance models C inside a two-dimensional field-effect transistor using the charge model determined by the charge model. q ;

[0049] 3) Determine the parasitic capacitances between the layers of the two-dimensional transistor, and transform the circuit composed of parasitic capacitances into a static capacitor network. Construct the channel voltage model V of the two-dimensional field-effect transistor based on the relationship between capacitance and voltage. c (x);

[0050] 4) Determine a general channel current model, and combine the voltage-capacitance-charge relationship determined by the channel voltage model with the general channel current model to obtain the final channel current model I. ds .

[0051] In step 1) above, constructing the charge model of a two-dimensional field-effect transistor includes the following steps:

[0052] 1.1) Define the voltage drop V on the surface of a two-dimensional material in the interval L. C and the Fermi-Dirac function f F (E), intermediate band E0 and effective mass D0 are simplified respectively; L is the length of the back gate oxide layer;

[0053] 1.2) Based on the simplified parameters, the charge model is determined as follows:

[0054]

[0055] In the formula, Q c This is a charge model, where q is the electron charge, and DOS is... 2D (E) is the two-dimensional density of states function, f(E) F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F It is the Fermi level.

[0056] in:

[0057]

[0058] In this embodiment, specifically, the derivation and calculation of other models are based on the core physical and mathematical model of electric charge. For the charge model, the voltage drop V on the surface of a two-dimensional material in the L interval is first defined. C Distinguished from V ds ,as follows Figure 3 As shown.

[0059] Next, define f F (E) is the Fermi-Dirac function, E F =qV c It is the Fermi level, with the reference level being the middle bandgap of the semiconductor, E. g The band gap is for a single layer of molybdenum disulfide. Parameter V c C represents q The voltage drop or surface potential on the surface, D0 is the effective mass, q represents the electron charge, and C q This is a capacitance model. The following simplifications are made in the initial modeling stage:

[0060] (1) Simplified to

[0061] (2) The intermediate band is simplified to

[0062] (3) The Fermi-Dirac function simplifies to f F (E)~1.

[0063] In step 2) above, the capacitance model refers to the quantum capacitance C dominated by two-dimensional materials. q Since the above charge model is also based on quantum states and the Fermi-Dirac function, the relationship between capacitance, charge, and potential still holds. In this embodiment, this capacitance model differs from the capacitance equivalent network used in the voltage model proposed later. This capacitance model is a theoretical characterization of the quantum capacitance and parasitic capacitance inside a two-dimensional transistor, while the capacitance equivalent network described below is only based on the macroscopic parasitic capacitance between the layers of materials in the transistor.

[0064] Among them, the capacitance model of the two-dimensional field-effect transistor, which includes quantum capacitance and parasitic capacitance, is constructed based on the charge model. Specifically, the potential of the charge model is differentiated according to the relationship between charge and capacitance to obtain the capacitance model.

[0065] The relationship between charge and capacitance:

[0066]

[0067] By directly differentiating the potential of the above charge model, we obtain the capacitance model as follows:

[0068]

[0069] In the formula, C q For the capacitance model, C q,p For hole-dominated quantum capacitors, C q,n For electron-dominated quantum capacitance, k is the Boltzmann constant, and T is the room temperature.

[0070] In step 3) above, the parasitic capacitances between the layers of the two-dimensional transistor are determined, including: the topgate oxide capacitance is C. t Monolayer molybdenum disulfide (MoS2) quantum capacitors are C q The backgate oxide capacitance is C. b ,like Figure 4 As shown.

[0071] In step 3) above, the channel voltage model of the two-dimensional field-effect transistor is constructed based on the relationship between capacitance and voltage, including the following steps:

[0072] 3.1) Transforming the circuit composed of parasitic capacitances between the material layers of a two-dimensional transistor into a static capacitance network (e.g., Figure 5 As shown, using Kirchhoff's voltage and current laws, the relationship between voltage and capacitance can be directly derived;

[0073] 3.2) Based on the relationship between voltage and capacitance, the channel voltage model is obtained as follows:

[0074]

[0075] In the formula, V c (x) represents the channel voltage model, V gs -V gs0 and V bs -V bs0 These are the overdrive voltages of the top-gate source voltage and the back-gate source voltage, respectively, V. gs V is the gate-source voltage. gs0 V is the top-gate flat-band voltage. bs V is the back gate voltage. bs0 Q is the bottom-gate flat-band voltage. n (V c ) represents the charge of an electron, and V c Related to V n (x) represents the potential of the NMOS at channel x, C t For the top oxide capacitor, C b The bottom oxide capacitor.

[0076] The model includes the work function difference between the gate and the monolayer molybdenum disulfide, the final charged interface state of the monolayer molybdenum disulfide and oxide interface, and the intentional or unintentional doping of the monolayer molybdenum disulfide.

[0077] In step 4) above, the general channel current model is determined as follows:

[0078] Based on the modeling methods used for ordinary silicon field-effect transistors, assuming that the internal channel of a two-dimensional transistor follows a drift-diffusion transport mechanism, then:

[0079]

[0080] v = μF

[0081]

[0082] Where W is the gate width, v(x) is the hole drift velocity, F is the electric field, and μ is the effective hole mobility.

[0083] This model assumes independence from field, carrier density, or temperature. It applies when the channel length is much longer than the mean free path of holes. Combining these equations, we obtain a general channel current model:

[0084]

[0085] To obtain an explicit expression for the drain current, V is used. c Using Q as the integration variable to solve the integral n It is also represented as V c The function of the surface potential. Then, after redefining the boundary conditions for the surface potential, the general channel current model is obtained as:

[0086]

[0087] In the formula, This is a general channel current model, where W is the gate width, μ is the effective hole mobility, and V... cd V is the drain voltage drop of the quantum capacitor. cs Q is the voltage drop at the source of the quantum capacitor. n V is the electron charge. n (x) is the potential at channel x of the NMOS, V c This represents the channel voltage.

[0088] In this embodiment, the relationship between voltage, capacitance, and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model, specifically:

[0089] By differentiating the channel voltage determined by the channel voltage model:

[0090]

[0091] In addition to the capacitance and charge relationship, combining the general channel current model, we obtain the final channel current model as follows:

[0092]

[0093] In the formula, I ds This is the final channel current model.

[0094] in:

[0095]

[0096] In summary, taking the simulation of the current-voltage curves of the model of this invention as an example, firstly, the .sp file of the model is generated, in which the complete code is called (the model code is a .va file), generating the simulation environment of the model: the transistor gate is connected to 1V, the drain is connected to 1V, and the source is grounded (0V). DC simulation is then performed. The current-voltage characteristic curves (IV curves) of the two-dimensional transistor are obtained, as shown below. Figure 6As shown, the simulation results match the curves of conventional field-effect transistors well, and the model is calibrated by comparing it with experimental data. This model can be used to optimize the design of two-dimensional transistors, especially for low-power and high-performance applications, ultimately enabling designers to predict and optimize performance before design. This includes using the model to analyze and design low-power switching circuits and other high-performance electronic devices.

[0097] This invention includes a model of quantum effects and unique characteristics of two-dimensional transistors, enabling its application in future EDA (Electronic Design Automation) applications. Compared to other models, it can more comprehensively characterize the electrical characteristics and quantum effects of two-dimensional material transistors. The model includes the charge model Q. c Capacitor Model C q Channel voltage model V c (x) and channel current model I ds .

[0098] Furthermore, the model of this invention is scalable. By modifying the parameters, it is possible to predict the operation of transistors under other parameter conditions. The parameters of the model can be adjusted in reverse according to various results that appear in the simulation, or the formula expression of the model can be refined to achieve a current-voltage curve similar to that of conventional silicon field-effect transistors. In this way, there is no need to directly change the material or size or modify the parameters manually. The design and manufacturing process is close to that of conventional silicon transistor circuits.

[0099] Furthermore, compared to other two-dimensional transistor models, this invention can fully represent the relevant electrical characteristics of the model.

[0100] In one embodiment of the present invention, a two-dimensional field-effect transistor (FET) model based on a monolayer transition metal chalcogenide is provided. This model is established based on the two-dimensional FET model construction method based on a monolayer transition metal chalcogenide described in the above embodiments. In this embodiment, the two-dimensional FET model includes: a charge model, a capacitance model, a channel voltage model, and a channel current model. Wherein:

[0101] The charge model is:

[0102]

[0103] The capacitance model is as follows:

[0104]

[0105] The channel voltage model is as follows:

[0106]

[0107] The channel current model is as follows:

[0108]

[0109] In the formula, Q c This is a charge model, where q is the electron charge, and DOS is... 2D (E) is the two-dimensional density of states function, f(E) F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F For the Fermi level, C q For the capacitance model, C q,p For electron-dominated quantum capacitors, C q,n The quantum capacitance is dominated by holes, k is the Boltzmann constant, T is the room temperature, and V is the capacitance. c (x) represents the channel voltage model, V gs -V gs0 and V bs -V bs0 These are the overdrive voltages of the top-gate source voltage and the back-gate source voltage, respectively, V. gs V is the gate-source voltage. gs0 V is the top-gate flat-band voltage. bs V is the back gate voltage. bs0 V is the bottom-gate flat-band voltage. n (x) represents the potential of the NMOS at channel x, C t For the top oxide capacitor, C b For the bottom oxide capacitor, E g For the bandgap width, I ds This is the final channel current model.

[0110] The model provided in this embodiment is used to execute the above method embodiments. For specific processes and details, please refer to the above embodiments, which will not be repeated here.

[0111] A computing device, which can be a terminal, is provided in one embodiment of the present invention. This computing device may include a processor, a communication interface, memory, a display screen, and an input device. The processor, communication interface, and memory communicate with each other via a communication bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. When the computer programs are executed by the processor, they implement the methods described in the above embodiments. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface is used for wired or wireless communication with external terminals. Wireless communication can be achieved through Wi-Fi, a network management system, NFC (Near Field Communication), or other technologies. The display screen may be a liquid crystal display (LCD) or an e-ink display. The input device may be a touch layer covering the display screen, or buttons, a trackball, or a touchpad mounted on the casing of the computing device, or an external keyboard, touchpad, or mouse. The processor can call logical instructions stored in the memory.

[0112] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0113] In one embodiment of the present invention, a computer program product is provided, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to perform the methods provided in the above-described method embodiments.

[0114] In one embodiment of the present invention, a non-transitory computer-readable storage medium is provided, which stores server instructions that cause a computer to perform the methods provided in the above embodiments.

[0115] The computer-readable storage medium provided in the above embodiments has a similar implementation principle and technical effect to the above method embodiments, and will not be described again here.

[0116] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0117] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0118] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide compound, characterized in that, include: The source and drain terminals of the two-dimensional field-effect transistor are assumed to be in ohmic contact with the two-dimensional material, and a charge model of the two-dimensional field-effect transistor is constructed. Based on the relationship between charge and capacitance, a capacitance model including quantum capacitance and parasitic capacitance is constructed inside a two-dimensional field-effect transistor based on the charge determined by the charge model. The parasitic capacitances between the layers of a two-dimensional transistor are determined, and the circuit composed of parasitic capacitances is transformed into a static capacitor network. Based on the relationship between capacitance and voltage, a channel voltage model of a two-dimensional field-effect transistor is constructed. A general channel current model is determined, and the relationship between voltage, capacitance, and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model. Determine a general channel current model, including: Assuming that the channel of a two-dimensional transistor uses a drift-diffusion transport mechanism, the general channel current model is as follows: In the formula, This is a general channel current model, where W is the gate width, μ is the effective hole mobility, and V... cd V is the drain voltage drop of the quantum capacitor. cs Q is the voltage drop at the source of the quantum capacitor. n V is the charge of an electron. c V is the channel voltage. n (x) is the potential of the NMOS at channel x; The relationship between voltage, capacitance, and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model, including: By differentiating the channel voltage determined by the channel voltage model and considering the relationships between voltage, capacitance, and charge, and combining these with the general channel current model, the final channel current model is obtained as follows: In the formula, I ds For the final channel current model, E g Where is the band gap, k is the Boltzmann constant, T is the room temperature, q is the electron charge, E0 is the intermediate band, D0 is the effective mass, and C is the electron charge. t For the top oxide capacitor, C b The bottom oxide capacitor.

2. The method for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide as described in claim 1, characterized in that, Constructing a charge model for a two-dimensional field-effect transistor, including: Define the voltage drop V on the surface of a two-dimensional material in the L interval. C and the Fermi-Dirac function f F (E), intermediate band E0 and effective mass D0 are simplified respectively; L is the length of the back gate oxide layer; Based on the simplified parameters, the charge model is determined as follows: In the formula, Q c This is a charge model, where q is the electron charge, and DOS is... 2D (E) is the two-dimensional density of states function, f(E) F -E) is the Fermi-Dirac distribution function, E is the mid-bandgap of the semiconductor, E F It is the Fermi level.

3. The method for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide as described in claim 2, characterized in that, Based on the charge model, a capacitance model is constructed for the internal structure of a two-dimensional field-effect transistor, including quantum capacitance and parasitic capacitance, comprising: Based on the relationship between charge and capacitance, the potential of the charge model is differentiated to obtain the capacitance model; The capacitance model is: In the formula, C q For the capacitance model, C q,p For hole-dominated quantum capacitors, C q,n For electron-dominated quantum capacitance, k is the Boltzmann constant, T is room temperature, and m * For the effective mass of electrons, It is Planck's constant.

4. The method for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide as described in claim 1, characterized in that, Determine the parasitic capacitances between the layers of a two-dimensional transistor, including: the top oxide capacitance is C. t Monolayer molybdenum disulfide quantum capacitors are C q The bottom oxide capacitor is C. b .

5. The method for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide as described in claim 1, characterized in that, A channel voltage model for a two-dimensional field-effect transistor is constructed based on the relationship between capacitance and voltage, including: The circuit composed of parasitic capacitances between the layers of materials in a two-dimensional transistor is transformed into a static capacitor network. Kirchhoff's voltage and current laws are used to directly derive the relationship between voltage and capacitance. Based on the relationship between voltage and capacitance, the channel voltage model is obtained as follows: In the formula, V c (x) represents the channel voltage model, V gs -V gs0 and V bs -V bs0 These are the overdrive voltages of the top-gate source voltage and the back-gate source voltage, respectively, V. gs V is the gate-source voltage. gs0 V is the top-gate flat-band voltage. bs V is the back gate voltage. bs0 Back gate flat band voltage, C t For the top oxide capacitor, C b The bottom oxide capacitor.

6. A device for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide, wherein the model is established based on the method for constructing a two-dimensional field-effect transistor model based on a monolayer transition metal chalcogenide as described in any one of claims 1 to 5, characterized in that, The two-dimensional field-effect transistor model includes: a charge model, a capacitance model, a channel voltage model, and a channel current model; The charge model is: The capacitance model is as follows: The channel voltage model is as follows: The channel current model is as follows: In the formula, Q c This is a charge model, where q is the electron charge, and DOS is... 2D (E) is the two-dimensional density of states function, f(E) F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F For the Fermi level, C q For the capacitance model, C q,p For hole-dominated quantum capacitors, C q,n For electron-dominated quantum capacitance, k is the Boltzmann constant, T is room temperature, and V is... c (x) represents the channel voltage model, V gs -V gs0 and V bs -V bs0 These are the overdrive voltages of the top-gate source voltage and the back-gate source voltage, respectively, V. gs V is the gate-source voltage. gs0 V is the top-gate flat-band voltage. bs V is the back gate voltage. bs0 Q is the bottom-gate flat-band voltage. n (V c V represents the charge of an electron. n (x) represents the potential of the NMOS at channel x, C t For the top oxide capacitor, C b For the bottom oxide capacitor, I ds For the final channel current model, E g Where W is the bandgap width, μ is the effective hole mobility, and V is the gate width. cd V is the drain voltage drop of the quantum capacitor. cs This represents the voltage drop at the source of the quantum capacitor.

7. A computer-readable storage medium for storing one or more programs, characterized in that, The one or more programs include instructions that, when executed by a computing device, cause the computing device to perform any of the methods described in claims 1 to 5.

8. A computing device, characterized in that, include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods described in claims 1 to 5.

Images