Automated design layout and path planning method and system for double-sided and multi-layer printed circuit boards

Abstract

The present invention relates to the technical field of circuit board line planning, specifically to an automated design arrangement and path planning method and system for double-sided and multi-layer printed circuits; the method comprises: obtaining input parameters of the circuit board, parsing and generating the initial structure of a wiring grid diagram; abstracting the wiring problem into a graph model, extracting wiring topology and density distribution characteristics; using a deep reinforcement learning algorithm to optimize the generation of wiring paths, while considering factors such as wiring direction, layer selection and path length; on the basis of generating wiring paths, detecting and adjusting conflicts in optimized wiring design rules; establishing a comprehensive evaluation system for wiring path planning schemes, considering indicators such as wiring efficiency, density and inter-layer balance, meeting preset quality requirements through iterative optimization, and outputting optimized wiring paths. The present invention can adaptively learn and improve wiring strategies, improve the reliability, efficiency and quality of wiring planning.

Description

Technical Field

[0001] The present invention relates to the technical field of multilayer printed circuit design, and in particular to an automated design arrangement and path planning method and system for double-sided boards and multilayer printed circuits. Background Art

[0002] In the existing technology, there are many deficiencies in the design and layout of double-sided and multi-layer printed circuit boards and the planning of wiring paths. The traditional method mainly relies on the experience of designers for wiring and lacks systematic and intelligent auxiliary tools. This method is not only time-consuming and labor-intensive, but also prone to inefficiency and frequent errors due to increased design complexity.

[0003] Traditional wiring methods are difficult to effectively handle the multi-dimensional data structure and design rules involved in multi-layer board wiring when faced with complex circuit board designs. Especially when the wiring density is high or the design rules are strictly restricted, problems such as insufficient wiring spacing and excessive vias are prone to occur, leading to repeated design modifications.

[0004] Existing technologies lack automated support for routing optimization, and the optimization process mainly relies on manual adjustments. Manual optimization not only fails to guarantee the optimal path, but also easily misses possible design rule conflicts, resulting in a decrease in performance indicators such as signal integrity and thermal distribution.

[0005] Existing methods usually lack comprehensive evaluation methods for wiring performance. After the wiring scheme is completed, it is difficult to efficiently analyze the overall performance of the wiring, such as wiring length, density distribution balance, and signal integrity, which makes it difficult to ensure the design quality and increases the risk of problems in the production process.

[0006] Traditional routing methods are inefficient when dealing with iterative optimization. Feedback adjustments based on evaluation results often require manual redesign and optimization, which makes the entire design cycle lengthy and makes it impossible to fully utilize existing design data in multiple optimization iterations to improve design efficiency and accuracy.

[0007] In view of this, the present invention proposes an automated design arrangement and path planning method and system for double-sided and multi-layer printed circuit boards. Summary of the invention

[0008] To achieve the above-mentioned purpose, the present invention provides a method and system for automatic design, arrangement and path planning of double-sided and multi-layer printed circuits. The specific technical scheme is as follows: The method for automatic design, arrangement and path planning of double-sided and multi-layer printed circuits comprises:

[0009] Obtain the input parameters of the circuit board to be designed, including the circuit schematic, the length and width of the circuit board, the number of layers, and the component package size, and parse and generate the initial structure of the circuit board wiring grid diagram;

[0010] The wiring problem of the circuit board is abstracted into a graph model, with component pins as nodes and wiring paths as edges. The topological structure and wiring density distribution characteristics of the circuit board wiring are extracted based on the graph model.

[0011] Based on deep reinforcement learning algorithm, the circuit board routing path is optimized, including optimization of routing direction, layer selection and path length;

[0012] Based on the generated routing path, the design rule conflicts of the circuit board routing are detected, including insufficient routing spacing and excessive via number, and the routing path and parameters are adjusted and optimized to complete the routing path planning;

[0013] Evaluate the wiring path planning scheme of the circuit board. If the wiring scheme evaluation results meet the preset conditions, output the optimized wiring path file and performance evaluation report, otherwise continue to optimize the wiring.

[0014] Preferably, the input parameters of the circuit board to be designed are obtained, including the circuit schematic, the length and width of the circuit board, the number of layers, and the component packaging size;

[0015] Define the length of the circuit board as , the width is , the number of layers is ; Represent the circuit schematic as an undirected connected graph ,in For the device collection, is a set of connected relationships, each edge Connecting two device nodes and ;

[0016] According to the length and width of the circuit board and , divide the circuit board wiring grid, set along Direction and The grid line spacing in the direction is and ;

[0017] According to the component package size information, determine each component Placement and orientation in the routing grid;

[0018] Based on the input parameters of the circuit board to be designed, the initial structure of the circuit board wiring grid diagram is generated; the wiring grid diagram is defined as ,in is a set of grid nodes, is the mesh edge set; Each node in Corresponding grid line intersection coordinates , and record the component information covering the node; Each edge in Connect adjacent mesh nodes and , indicating potential routing paths.

[0019] Preferably, based on the generated circuit board wiring grid diagram , abstract the wiring problem of the circuit board into a graph model; define the wiring graph model as ,in is a set of component pin nodes, is the set of routing path edges;

[0020] According to the circuit diagram Extract component pin nodes, for each component , extract its pin set ,in For components Number of pins; pin In the wiring grid diagram Corresponding to a grid node , the coordinates are ; The pin nodes of all components constitute a collection : ;

[0021] Based on the circuit schematic The connection relationship set in , establish routing path edges between pin nodes; for each connection relationship , find the corresponding pin node pair , add a routing path edge between pin node pairs ;

[0022] Extracting Wiring Diagram Model The topological structure and wiring density distribution characteristics of the wiring path are defined. Length Two pin nodes connected and In the wiring grid diagram Manhattan distance in: ;

[0023] Introducing wiring density function Represents a grid node The wiring density on the initial ; For each routing path edge , passing through all the grid nodes The wiring density increases by 1: ;

[0024] Computational Wiring Diagram Model Total wiring length and average wiring density :

[0025]

[0026] Statistical Wiring Diagram Model The topological structure characteristics of the network include the number of connected subgraphs, the number of key nodes, and the number of loops.

[0027] Preferably, based on the wiring diagram model , using deep reinforcement learning algorithm to optimize the circuit board routing path; defining the state space of reinforcement learning , Action Space And the reward function ;

[0028] state Including the topology of the current wiring path, wiring density distribution and the number of wiring layers used; status Represented as a feature vector: ;in Indicates the wiring topology characteristics, Indicates the wiring density distribution characteristics, Indicates the usage of each wiring layer;

[0029] action Indicates the optimization operation of the current routing path; each action Represented as a multidimensional parameter vector: ;in and Indicated in and The amount of wiring displacement in the direction, Indicates the amount of wiring layer change, Indicates the reduction in wiring length;

[0030] Reward Function To evaluate actions Status The optimization objectives of the reward function include: minimizing the total wiring length, minimizing the wiring congestion level, and satisfying the wiring design rules; ;in , , and To balance the weight coefficients of each item, is the amount of wiring length reduction that minimizes the total wiring length, is the congestion penalty term in minimizing the routing congestion level, It is the design rule penalty item in the wiring design rules.

[0031] Preferably, the deep reinforcement learning model uses a deep Q network DQN model for training optimization; the DQN model includes an evaluation network and target network ,in and is the network parameter; the evaluation network is used to estimate the state-action value function , the target network is used to generate training labels;

[0032] In the training step, the agent in the deep reinforcement learning model is trained according to Strategy selection action , that is, The probability of randomly selecting an action is The probability of selecting the action with the largest Q value;

[0033] Agent performs actions , observe the next state and rewards received , and transfer the sample Store to experience replay buffer middle;

[0034] From the Experience Replay Buffer Randomly sample a batch of transfer samples , use the target network to generate the Q-value target: ;in is the discount factor;

[0035] Network parameters will be evaluated regularly Copy to target network parameters , repeat the training process and optimize the DQN model until the convergence condition is met or the maximum number of training steps is reached;

[0036] Apply the trained DQN model to optimize the routing path; from the initial routing state Start by selecting the best action , execute actions and update status to generate the optimal routing path.

[0037] Preferably, the wiring path and parameters are adjusted and optimized to complete the wiring path planning;

[0038] For wiring spacing conflicts, solve them by increasing the wiring spacing or changing the wiring layer; if the conflict occurs in the same wiring layer, insert additional line segments near the conflicting location to increase the wiring spacing to meet the design rule requirements;

[0039] If the conflict occurs in different wiring layers, change the conflicting wiring path to other wiring layers to eliminate the conflict;

[0040] For conflicts involving excessive via quantity, solve them by merging adjacent vias or optimizing the wiring topology; find adjacent redundant vias, and if the distance between the two vias is less than the threshold , and they are connected to the same pair of network nodes, they are merged into one via to reduce the number of vias;

[0041] If the limit on the number of vias is still not met after merging the redundant vias, the number of vias is reduced by optimizing the wiring topology and reducing the connections between wiring layers;

[0042] If the wiring length exceeds the limit, the problem can be solved by shortening the wiring path or increasing the number of wiring layers. If the wiring path is too long due to detours, a shorter wiring path can be found by optimizing the topology.

[0043] If insufficient routing space results in extra-long routing, more routing resources can be provided for the long routing path by increasing the number of routing layers.

[0044] Preferably, according to the generated wiring path planning, including path topology information, wiring density distribution and wiring layer usage;

[0045] Calculate the sum of the Manhattan distances of all routing paths to evaluate routing efficiency; analyze the routing density of each grid node, count the proportion of nodes that exceed the set threshold, and mark the congested areas; count the usage of each routing layer and evaluate the balance between layers;

[0046] Calculate the comprehensive score of the wiring and define the comprehensive performance scoring function:

[0047]

[0048] in, , , and Is the weight coefficient. If the comprehensive score If the preset standard is met, the unlimited path planning scheme is determined to be qualified. If the preset standard is not met, the path planning step is returned to and the path planning is performed again.

[0049] The automatic design arrangement and path planning system for double-sided and multi-layer printed circuits is used to implement the automatic design arrangement and path planning method for double-sided and multi-layer printed circuits, including: a data acquisition module, a graph model module, a wiring path generation module, a conflict detection module and a wiring route evaluation module;

[0050] The data acquisition module is used to obtain input parameters of the circuit board to be designed, including the circuit schematic, the length and width of the circuit board, the number of layers and the component packaging size, and parse and generate the initial structure of the circuit board wiring grid diagram;

[0051] The graph model module is used to abstract the wiring problem of the circuit board into a graph model, taking component pins as nodes and wiring paths as edges, and extracting the topological structure and wiring density distribution characteristics of the circuit board wiring based on the graph model;

[0052] The wiring path generation module optimizes and generates the circuit board wiring path based on the deep reinforcement learning algorithm, including optimizing the wiring direction, layer selection and path length;

[0053] The conflict detection module detects design rule conflicts of circuit board wiring based on the generated wiring path, including insufficient wiring spacing and excessive via number, adjusts and optimizes the wiring path and parameters, and completes wiring path planning;

[0054] The wiring route evaluation module evaluates the wiring path planning scheme of the circuit board. If the wiring scheme evaluation result meets the preset conditions, the optimized wiring path file and performance evaluation report are output, otherwise the wiring optimization is continued.

[0055] An electronic device comprises: a processor and a memory, wherein the memory stores a computer program that can be called by the processor; the processor executes the automatic design arrangement and path planning method of double-sided board and multi-layer board printed circuits by calling the computer program stored in the memory.

[0056] A computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the automatic design arrangement and path planning method for double-sided and multi-layer printed circuits.

[0057] Beneficial effects of the present invention: The present invention obtains key input parameters of the circuit board and parses and generates the initial structure of the wiring grid diagram, thereby providing a complete and accurate circuit board information basis for subsequent wiring path planning, which is beneficial to improving the reliability and efficiency of wiring planning.

[0058] The present invention abstracts the circuit board wiring problem into a graph model, extracts the wiring topology and density distribution characteristics, and transforms the complex wiring problem into a graph theory problem, laying a foundation for the application of intelligent optimization algorithms and facilitating the systematic analysis and optimization of wiring paths.

[0059] The present invention adopts a deep reinforcement learning algorithm to globally optimize the wiring path of the circuit board, while considering multiple optimization objectives such as wiring direction, layer selection and path length. It can adaptively learn and improve the wiring strategy to generate a more efficient and reasonable wiring path solution.

[0060] On the basis of generating a wiring path, the present invention further detects and adjusts the conflicts in the optimized wiring design rules, automatically solves the problems of insufficient wiring spacing and excessive via number, greatly reduces the workload of manual adjustment, and improves the feasibility and quality of the wiring scheme.

[0061] The present invention establishes a comprehensive evaluation system for circuit board wiring path planning schemes, taking into account multiple performance indicators such as wiring efficiency, wiring density and inter-layer balance, and meets preset wiring scheme quality requirements through iterative optimization to ensure the reliability and superiority of the output wiring scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A flow chart of the automatic design arrangement and path planning method for double-sided and multi-layer printed circuit boards provided by the present invention;

[0063] Figure 2 This is a structural diagram of the automatic design, arrangement and path planning system for double-sided and multi-layer printed circuit boards provided by the present invention. DETAILED DESCRIPTION

[0064] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0065] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0066] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0067] Example 1

[0068] Reference Figure 1 , which is the first embodiment of the present invention, provides an automated design layout and path planning method for double-sided and multi-layer printed circuit boards.

[0069] Step 1: Obtain the input parameters of the circuit board to be designed, including the circuit schematic, the length and width of the circuit board, the number of layers, and the component package size, and parse and generate the initial structure of the circuit board wiring grid diagram.

[0070] Obtain the input parameters of the circuit board to be designed, including the circuit schematic, circuit board length and width, number of layers, and component package size.

[0071] Define the length of the circuit board as , the width is , the number of layers is ; Represent the circuit schematic as an undirected connected graph ,in For the device collection, is a set of connected relationships, each edge Connecting two device nodes and .

[0072] According to the length and width of the circuit board and , divide the circuit board wiring grid, set along Direction and The grid line spacing in the direction is and , then the node coordinates of the circuit board routing grid are satisfy: ; ,in Represents the floor function.

[0073] According to the component package size information, determine each component Placement and orientation in the routing grid; set components The center coordinates of , the length is , the width is , then the corresponding grid node satisfy:

[0074] .

[0075] Based on the input parameters of the circuit board to be designed, the initial structure of the circuit board wiring grid diagram is generated; the wiring grid diagram is defined as ,in is a set of grid nodes, is the mesh edge set; Each node in Corresponding grid line intersection coordinates , and record the component information covering the node; Each edge in Connect adjacent mesh nodes and , indicating potential routing paths.

[0076] Step 1 Completed the PCB routing grid diagram Initial construction of It reflects the layout information and connection constraints of the circuit board, laying the foundation for subsequent wiring path planning.

[0077] Step 2: Abstract the wiring problem of the circuit board into a graph model, with component pins as nodes and wiring paths as edges, and extract the topological structure and wiring density distribution characteristics of the circuit board wiring based on the graph model.

[0078] Based on the generated circuit board wiring grid diagram , abstract the wiring problem of the circuit board into a graph model; define the wiring graph model as ,in is a set of component pin nodes, A collection of routing path edges.

[0079] According to the circuit diagram Extract component pin nodes, for each component , extract its pin set ,in For components Number of pins; pin In the wiring grid diagram Corresponding to a grid node , the coordinates are ; The pin nodes of all components constitute a collection : .

[0080] Based on the circuit schematic The connection relationship set in , establish routing path edges between pin nodes; for each connection relationship , find the corresponding pin node pair , add a routing path edge between pin node pairs .

[0081] It should be noted that this embodiment assumes that each pin pair is connected by one wiring path, and in practice there may be multiple wiring paths.

[0082] Extracting Wiring Diagram Model The topological structure and wiring density distribution characteristics of the wiring path are defined. Length Two pin nodes connected and In the wiring grid diagram Manhattan distance in: .

[0083] Introducing wiring density function Represents a grid node The wiring density on the initial ; For each routing path edge , passing through all the grid nodes The wiring density increases by 1: .

[0084] Computational Wiring Diagram Model Total wiring length and average wiring density :

[0085]

[0086] Statistical Wiring Diagram Model The topological structure characteristics of the circuit board include the number of connected subgraphs, the number of key nodes, and the number of loops. These characteristics reflect the complexity and reliability of circuit board wiring;

[0087] Step 2: Abstract the circuit board wiring problem into a graphical model , and extracted its topological structure and wiring density distribution characteristics; this provides important input information and evaluation indicators for subsequent wiring path optimization.

[0088] Step 3: Based on the deep reinforcement learning algorithm, optimize and generate the circuit board routing path, including optimizing the routing direction, layer selection and path length.

[0089] Based on wiring diagram model , using deep reinforcement learning algorithm to optimize the circuit board routing path; defining the state space of reinforcement learning , Action Space And the reward function .

[0090] state Including the topology of the current wiring path, wiring density distribution and the number of wiring layers used; status It can be represented as a feature vector: ;in Indicates the wiring topology characteristics, Indicates the wiring density distribution characteristics, Indicates the usage of each wiring layer.

[0091] action Indicates the optimization operation of the current wiring path, including adjusting the wiring direction, changing the wiring layer, and reducing the wiring length; each action Represented as a multidimensional parameter vector:

[0092]

[0093] in and Indicated in and The amount of wiring displacement in the direction, Indicates the amount of wiring layer change, Indicates the reduction in wiring length.

[0094] Reward Function To evaluate actions Status The optimization objectives of the reward function include: minimizing the total wiring length, minimizing the wiring congestion level, and satisfying the wiring design rules;

[0095]

[0096] in , , and To balance the weight coefficients of each item, is the amount of wiring length reduction that minimizes the total wiring length, is the congestion penalty term in minimizing the routing congestion level, It is the design rule penalty item in the wiring design rules.

[0097] Set the minimum total wiring length , wiring length reduction Can be used as a positive reward; set the minimum routing congestion level and introduce congestion penalty items , with wiring density exceeding the threshold The number of grid nodes is related to the number of grid nodes; set the wiring design rules and introduce the design rule penalty item , which is related to the number of routing paths that violate the design rules.

[0098] The deep reinforcement learning model uses the deep Q network DQN model for training and optimization; the DQN model includes an evaluation network and target network ,in and is the network parameter; the evaluation network is used to estimate the state-action value function , the target network is used to generate training labels.

[0099] In the training step, the agent in the deep reinforcement learning model is trained according to Strategy selection action , that is, The probability of randomly selecting an action is The probability of selecting the action with the largest Q value is

[0100] Agent performs actions , observe the next state and the rewards received , and transfer the sample Store to experience replay buffer middle.

[0101] From the Experience Replay Buffer Randomly sample a batch of transfer samples , use the target network to generate the Q-value target: ;in is the discount factor;

[0102] Use the mean square error loss function to optimize and evaluate network parameters :

[0103]

[0104] Network parameters will be evaluated regularly Copy to target network parameters , to maintain the stability of the target network; repeat the training process and optimize the DQN model until the convergence condition is met or the maximum number of training steps is reached.

[0105] Apply the trained DQN model to optimize the routing path; from the initial routing state Start by selecting the best action , execute actions and update status to generate the optimal routing path.

[0106] Step 4: Based on the generated routing path, detect the design rule conflicts of the circuit board routing, including insufficient routing spacing and excessive via number, adjust and optimize the routing path and parameters, and complete the routing path planning.

[0107] For wiring spacing conflicts, they can be resolved by increasing the wiring spacing or changing the wiring layer. If the conflict occurs in the same wiring layer, insert additional line segments near the conflicting position to increase the wiring spacing to meet the design rule requirements. Let the conflicting line segment be , whose endpoint coordinates are and , the coordinates of the inserted line segment endpoints are , then the parametric equation of the inserted line segment is:

[0108]

[0109]

[0110]

[0111]

[0112] Insertion Point The selection of needs to comprehensively consider factors such as wiring topology, wiring density distribution, etc., which can be solved by optimization algorithm.

[0113] If the conflict occurs in different wiring layers, change the conflicting wiring path to other wiring layers to eliminate the conflict.

[0114] For conflicts involving excessive via quantity, solve them by merging adjacent vias or optimizing the wiring topology; find adjacent redundant vias, and if the distance between the two vias is less than the threshold , and they are connected to the same pair of network nodes, they are merged into one via to reduce the number of vias; let the coordinates of the two redundant vias be , the coordinates of the merged vias satisfy:

[0115]

[0116] If the limit on the number of vias is still not met after merging redundant vias, the number of vias can be reduced by optimizing the wiring topology and reducing the connections between wiring layers. Some wiring paths can be concentrated in the same wiring layer to reduce the transition between layers, or some connections can be changed to same-layer connections to avoid the use of vias. The process of optimizing the topology can be assisted by graph theory algorithms and heuristic search methods.

[0117] For the conflict of excessive wiring length, the wiring path can be shortened or the number of wiring layers can be increased; if the wiring path is too long due to detour, a shorter wiring path can be found by optimizing the topology structure; let the excessive wiring path be ,in Represents the line segment on the path. The optimization goal is to find a routing path To minimize its total length:

[0118]

[0119] The optimization process can use the shortest path algorithm, such as Dijkstra algorithm or A algorithm;

[0120] If insufficient wiring space results in an overlong wiring, more wiring resources can be provided for the long wiring path by increasing the number of wiring layers. , which can be increased to :

[0121]

[0122] in The value of needs to balance the wiring length and manufacturing cost; after increasing the number of wiring layers, the wiring path needs to be replanned and optimized.

[0123] Through the above wiring path and parameter adjustment and optimization, design rule conflicts can be eliminated or reduced, and a wiring scheme that meets the design requirements can be generated; the entire adjustment and optimization process may require multiple iterations until all design rule conflicts are eliminated and the final wiring path planning results are obtained; the wiring path planning results include the starting and ending coordinates of each wiring path, wiring layer, line width, via position and other parameters, as well as the wiring density distribution, via distribution, key signal routing and other statistical information of the entire circuit board, providing a basis for subsequent circuit board manufacturing and performance evaluation.

[0124] Step 5: Evaluate the wiring path planning scheme of the circuit board. If the wiring scheme evaluation results meet the preset conditions, output the optimized wiring path file and performance evaluation report, otherwise continue to optimize the wiring.

[0125] Based on the generated wiring path planning, including path topology information, wiring density distribution and wiring layer usage.

[0126] Calculate the sum of the Manhattan distances of all routing paths to evaluate routing efficiency; analyze the routing density of each grid node, count the proportion of nodes that exceed the set threshold, and mark the congested areas; count the usage of each routing layer and evaluate the balance between layers.

[0127] Calculate the comprehensive score of the wiring and define the comprehensive performance scoring function:

[0128]

[0129] in, , , and Is the weight coefficient. If the comprehensive score If the preset standard is met, the unlimited path planning scheme is determined to be qualified. If the preset standard is not met, the path planning step is returned to and the path planning is performed again.

[0130] The technical solution of the present invention combines traditional wiring problems with deep reinforcement learning, providing an automated and intelligent circuit board design method with important application value.

[0131] Example 2

[0132] Reference Figure 2 , which is the second embodiment of the present invention, provides an automated design layout and path planning system for double-sided and multi-layer printed circuit boards.

[0133] The system comprises: a data acquisition module, a graph model module, a wiring path generation module, a conflict detection module and a wiring route evaluation module.

[0134] The data acquisition module is used to obtain input parameters of the circuit board to be designed, including the circuit schematic, the length and width of the circuit board, the number of layers and the component packaging size, and parse and generate the initial structure of the circuit board wiring grid diagram.

[0135] The graph model module is used to abstract the wiring problem of the circuit board into a graph model, with component pins as nodes and wiring paths as edges, and to extract the topological structure and wiring density distribution characteristics of the circuit board wiring based on the graph model.

[0136] The wiring path generation module optimizes and generates the circuit board wiring path based on a deep reinforcement learning algorithm, including optimizing the wiring direction, layer selection and path length.

[0137] The conflict detection module detects design rule conflicts of circuit board wiring based on the generated wiring path, including insufficient wiring spacing and excessive via number, adjusts and optimizes the wiring path and parameters, and completes wiring path planning.

[0138] The wiring route evaluation module evaluates the wiring path planning scheme of the circuit board. If the wiring scheme evaluation result meets the preset conditions, the optimized wiring path file and performance evaluation report are output, otherwise the wiring optimization is continued.

[0139] Example 3

[0140] The third embodiment of the present invention provides an electronic device, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0141] Example 4

[0142] A fourth embodiment of the present invention provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the aforementioned method when executed by a processor.

[0143] Those skilled in the art should understand that the embodiments of the present application may provide methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0144] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. The method for automatic design, arrangement and path planning of double-sided and multi-layer printed circuit boards is characterized in that: include: Obtain the input parameters of the circuit board to be designed, including the circuit schematic, the length and width of the circuit board, the number of layers, and the component package size, and parse and generate the initial structure of the circuit board wiring grid diagram; The wiring problem of the circuit board is abstracted into a graph model, with component pins as nodes and wiring paths as edges. The topological structure and wiring density distribution characteristics of the circuit board wiring are extracted based on the graph model. Based on deep reinforcement learning algorithm, the circuit board routing path is optimized, including optimization of routing direction, layer selection and path length; Based on wiring diagram model , using deep reinforcement learning algorithm to optimize the circuit board routing path; defining the state space of reinforcement learning , Action Space And the reward function ; state Including the topology of the current wiring path, wiring density distribution and the number of wiring layers used; status Represented as a feature vector: ;in Indicates the wiring topology characteristics, Indicates the wiring density distribution characteristics, Indicates the usage of each wiring layer; action Indicates the optimization operation of the current routing path; each action Represented as a multidimensional parameter vector: ;in and Indicated in and The amount of wiring displacement in the direction, Indicates the amount of wiring layer change, Indicates the reduction in wiring length; Reward Function To evaluate actions Status Optimization effect; The optimization objectives of the reward function include: minimizing the total length of wiring, minimizing the degree of wiring congestion, and satisfying wiring design rules; ;in , and To balance the weight coefficients of each item, is the amount of wiring length reduction that minimizes the total wiring length, is the congestion penalty term in minimizing the routing congestion level, It is the design rule penalty item in the wiring design rule; Based on the generated routing path, the design rule conflicts of the circuit board routing are detected, including insufficient routing spacing and excessive via number, and the routing path and parameters are adjusted and optimized to complete the routing path planning; Evaluate the wiring path planning scheme of the circuit board. If the wiring scheme evaluation results meet the preset conditions, output the optimized wiring path file and performance evaluation report, otherwise continue to optimize the wiring.

2. The method for automatic design, arrangement and path planning of double-sided and multi-layer printed circuit boards according to claim 1, characterized in that: Obtain input parameters of the circuit board to be designed, including circuit schematic, length and width of the circuit board, number of layers, and component package size; Define the length of the circuit board as , the width is , the number of layers is ; Represent the circuit schematic as an undirected connected graph ,in For the device collection, is a set of connected relationships, each edge Connecting two device nodes and ; According to the length and width of the circuit board and , divide the circuit board wiring grid, set along Direction and The grid line spacing in the direction is and ; According to the component package size information, determine each component Placement and orientation in the routing grid; Based on the input parameters of the circuit board to be designed, an initial structure of the circuit board wiring grid diagram is generated; Define the wiring grid diagram as ,in is a set of grid nodes, is the mesh edge set; Each node in Corresponding grid line intersection coordinates , and record the component information covering the node; Each edge in Connect adjacent mesh nodes and , indicating potential routing paths.

3. The method for automatic design, arrangement and path planning of double-sided and multi-layer printed circuit boards according to claim 2, characterized in that: Based on the generated circuit board wiring grid diagram ,abstract the wiring problem of the circuit board into a graphical model; Define the wiring diagram model as ,in is a set of component pin nodes, is the set of routing path edges; According to the circuit diagram Extract component pin nodes, for each component , extract its pin set ,in For components Number of pins; pin In the wiring grid diagram Corresponding to a grid node , the coordinates are ; The pin nodes of all components constitute a collection : ; Based on the circuit schematic The connection relationship set in , establish routing path edges between pin nodes; for each connection relationship , find the corresponding pin node pair , add a routing path edge between pin node pairs ; Extracting Wiring Diagram Model The topological structure and wiring density distribution characteristics of the wiring path are defined. Length Two pin nodes connected and In the wiring grid diagram Manhattan distance in: ; Introducing wiring density function Represents a grid node The wiring density on the initial ; For each routing path edge , passing through all the grid nodes The wiring density increases by 1: ; Computational Wiring Diagram Model Total wiring length and average wiring density : Statistical Wiring Diagram Model The topological structure characteristics of the network include the number of connected subgraphs, the number of key nodes, and the number of loops.

4. The method for automatic design, arrangement and path planning of double-sided and multi-layer printed circuit boards according to claim 3, characterized in that: The deep reinforcement learning model uses the deep Q network DQN model for training and optimization; the DQN model includes an evaluation network and target network ,in and is the network parameter; the evaluation network is used to estimate the state-action value function , the target network is used to generate training labels; In the training step, the agent in the deep reinforcement learning model is trained according to Strategy selection action , that is, The probability of randomly selecting an action is The probability of selecting the action with the largest Q value; Agent performs actions , observe the next state and rewards received , and transfer the sample Store to experience replay buffer middle; From the Experience Replay Buffer Randomly sample a batch of transfer samples , use the target network to generate the Q-value target: ;in is the discount factor; Network parameters will be evaluated regularly Copy to target network parameters , repeat the training process and optimize the DQN model until the convergence condition is met or the maximum number of training steps is reached; Apply the trained DQN model to optimize the routing path; from the initial routing state Start by selecting the best action , execute actions and update status to generate the optimal routing path.

5. The method for automatic design, arrangement and path planning of double-sided and multi-layer printed circuit boards according to claim 4, characterized in that: Adjust and optimize the wiring paths and parameters to complete the wiring path planning; For wiring spacing conflicts, solve them by increasing the wiring spacing or changing the wiring layer; If the conflict occurs on the same routing layer, insert additional line segments near the conflicting location to increase the routing spacing to meet the design rule requirements; If the conflict occurs in different wiring layers, change the conflicting wiring path to other wiring layers to eliminate the conflict; For conflicts where the number of vias exceeds the limit, solve them by merging adjacent vias or optimizing the wiring topology. Find adjacent redundant vias. If the distance between two vias is less than the threshold , and they are connected to the same pair of network nodes, they are merged into one via to reduce the number of vias; If the limit on the number of vias is still not met after merging the redundant vias, the number of vias is reduced by optimizing the wiring topology and reducing the connections between wiring layers; For wiring length exceeding limit conflicts, solve them by shortening the wiring path or increasing the number of wiring layers; If the routing path is too long due to detours, find a shorter routing path by optimizing the topology. If insufficient routing space results in extra-long routing, more routing resources can be provided for the long routing path by increasing the number of routing layers.

6. The method for automatic design, arrangement and path planning of double-sided and multi-layer printed circuit boards according to claim 5, characterized in that: Based on the generated routing path planning, including path topology information, routing density distribution and routing layer usage; Calculate the sum of Manhattan distances of all routing paths to evaluate routing efficiency; Analyze the wiring density of each grid node, count the proportion of nodes that exceed the set threshold, and mark the congested areas; Count the usage of each wiring layer and evaluate the balance between layers; Calculate the comprehensive score of the wiring and define the comprehensive performance scoring function: in, , , and Is the weight coefficient. If the comprehensive score If the preset standard is met, the unlimited path planning scheme is determined to be qualified. If the preset standard is not met, the path planning step is returned to and the path planning is performed again.

7. An automated design, arrangement and path planning system for double-sided and multi-layer printed circuits, which is used to implement the automated design, arrangement and path planning method for double-sided and multi-layer printed circuits as claimed in any one of claims 1 to 6, characterized in that: include: Data acquisition module, graph model module, wiring path generation module, conflict detection module and wiring route evaluation module; The data acquisition module is used to obtain input parameters of the circuit board to be designed, including the circuit schematic, the length and width of the circuit board, the number of layers and the component packaging size, and parse and generate the initial structure of the circuit board wiring grid diagram; The graph model module is used to abstract the wiring problem of the circuit board into a graph model, taking component pins as nodes and wiring paths as edges, and extracting the topological structure and wiring density distribution characteristics of the circuit board wiring based on the graph model; The wiring path generation module optimizes and generates the circuit board wiring path based on the deep reinforcement learning algorithm, including optimizing the wiring direction, layer selection and path length; The conflict detection module detects design rule conflicts of circuit board wiring based on the generated wiring path, including insufficient wiring spacing and excessive via number, adjusts and optimizes the wiring path and parameters, and completes wiring path planning; The wiring route evaluation module evaluates the wiring path planning scheme of the circuit board. If the wiring scheme evaluation result meets the preset conditions, the optimized wiring path file and performance evaluation report are output, otherwise the wiring optimization is continued.

8. An electronic device, characterized in that: include: A processor and a memory, wherein the memory stores a computer program that can be called by the processor; The processor executes the automatic design arrangement and path planning method for double-sided board and multi-layer board printed circuits as described in any one of claims 1 to 6 by calling the computer program stored in the memory.

9. A computer-readable storage medium, characterized in that: Instructions are stored, and when the instructions are run on a computer, the computer executes the automatic design, arrangement and path planning method for double-sided and multi-layer printed circuits as described in any one of claims 1 to 6.

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