An extension card timing management apparatus, method, and computer device and storage medium

Abstract

The application relates to an expansion card timing management device, method, computer equipment and storage medium. The device comprises an expansion chip module and a complex programmable logic device arranged on an expansion card module, the complex programmable logic device is connected with a mainboard through a bus, and a power supply module is further arranged on the expansion card module, the power supply module comprises a power supply output end, and the complex programmable logic device comprises a power supply input end, a reset signal output end, a debugging signal output end and a heartbeat signal input end; the expansion chip module comprises a heartbeat signal output end, a reset signal input end and a debugging signal input end. The method can reduce the use of hardware circuits, optimize layout space and complete logic timing control.

Description

Technical Field

[0001] This application relates to the field of chip timing control technology, and in particular to an expansion card timing management device, method, computer equipment, and storage medium. Background Technology

[0002] SAS (Serial Attached SCSI) is a disk connectivity technology. Expansion cards can connect multiple SAS devices to a limited number of host ports. In complex computer systems, servers, and embedded devices, expansion cards are key components for expanding interfaces and resources, typically used to connect and manage multiple peripheral devices. The expansion chip on the expansion card is the core control chip, and its power-on and management have specific timing requirements. Specifically, certain pins on the expansion chip have input / output requirements under specific timing conditions, such as the Reset signal and the DFT_IN pin. To meet the expansion chip's input / output timing requirements for these pins and signals, hardware delay circuits are added to achieve logical timing control.

[0003] However, the timing of the expansion card in this method cannot be freely adjusted, and additional peripheral circuitry is required, increasing costs and reducing PCB design space. Therefore, it is essential to provide a new logic timing management device for expansion cards to address the aforementioned shortcomings of existing technologies. Summary of the Invention

[0004] Therefore, it is necessary to provide an expansion card timing management device, method, computer equipment, and storage medium that can not only reduce hardware circuitry but also perform logic timing control, in order to address the above-mentioned technical problems.

[0005] On the one hand, an expansion card timing management device is provided, the device comprising:

[0006] An expansion card module and a complex programmable logic device (CPLD) are mounted on the expansion card module. The CPLD is connected to the motherboard via a bus. The expansion card module also includes a power module with a power output terminal. The CPLD includes a power input terminal, a reset signal output terminal, a debug signal output terminal, and a heartbeat signal input terminal. The expansion card module includes a heartbeat signal output terminal, a reset signal input terminal, and a debug signal input terminal.

[0007] Specifically, the power output terminal of the power module is connected to the power input terminal of the complex programmable logic device (CPLD), the reset signal output terminal of the CPLD is connected to the reset signal input terminal of the expansion chip module, the debug signal output terminal of the CPLD is connected to the signal input terminal of the expansion chip module, and the heartbeat signal output terminal of the expansion chip module is connected to the heartbeat signal input terminal of the CPLD.

[0008] In one embodiment, it further includes:

[0009] The motherboard is equipped with a baseboard management controller that is connected to the complex programmable logic device via the bus. The baseboard management controller is used to control the complex programmable logic device.

[0010] In one embodiment,

[0011] The expansion card module is equipped with an external crystal clock module. The output terminal of the external crystal clock module is connected to the clock signal input terminal of the complex programmable logic device. The complex programmable logic device is also equipped with a timer and a counter for measuring time.

[0012] In one embodiment, an expansion card timing management method for the expansion card timing management device is provided, the method comprising:

[0013] The power module sends a power good signal to the power input terminal of the complex programmable logic device through its output terminal;

[0014] After receiving a power good signal, the complex programmable logic device detects the power good signal and obtains a detection result, which includes: normal power-on and abnormal power-on.

[0015] In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on the first delay duration and the external crystal clock, and sends the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal of the complex programmable logic device.

[0016] A second delay duration is set. After the first signal is sent, a timer is started. The complex programmable logic device generates a debug signal based on the second delay duration and the external crystal clock. The debug signal is sent to the debug signal input terminal of the expansion chip module through the debug signal output terminal of the complex programmable logic device module. The second delay duration is longer than the first delay duration.

[0017] The extended chip module performs corresponding operations based on the received reset signal and debug signal.

[0018] In one embodiment, the method further includes: after receiving the power-good signal, the complex programmable logic device detects the power-good signal to obtain a detection result, the detection result including: power-on normal and power-on abnormal, including:

[0019] The complex programmable logic device initializes the counter and sets a threshold for the counter;

[0020] The complex programmable logic device periodically samples and detects the power-good signal, and records the detection result each time;

[0021] If the detection result indicates that the power-on is normal, the counter is incremented by one;

[0022] If the detection result indicates a power-on abnormality, the counter is reset to zero, and the detection process restarts.

[0023] If the detection result indicates that the power-on is normal and the value does not reach the threshold of the counter, then the next sampling is performed;

[0024] When the detection result indicating normal power-on reaches the threshold of the counter, the power supply good signal is stable power-on normal.

[0025] If the value of the detection result indicating normal power-on does not reach the threshold of the counter within a set time period, then the power good signal indicates abnormal power-on.

[0026] In one embodiment, in response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on a first delay duration and the external crystal clock, and sends the reset signal from the reset signal output terminal of the complex programmable logic device to the reset signal input terminal of the expansion chip module, including:

[0027] A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock.

[0028] The complex programmable logic device starts a timer to begin timing according to the clock signal, determines a first trigger time according to the first delay duration, and generates a reset signal in response to the timer time reaching the first trigger time.

[0029] The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

[0030] In one embodiment, the complex programmable logic device generates a debug signal based on a second delay duration and an external crystal clock, and sends the debug signal to the debug signal input terminal of the expansion chip module through the debug signal output terminal of the complex programmable logic device module, wherein the second delay duration is longer than the first delay duration, including:

[0031] A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock.

[0032] The complex programmable logic device starts a timer to begin timing according to the clock signal, and determines the second trigger time according to the second delay duration;

[0033] In response to the timer reaching the second trigger time, the complex programmable logic device generates a debug signal;

[0034] The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

[0035] In one embodiment, the extended chip module performs corresponding operations based on the received reset signal and debug signal, and further includes:

[0036] The baseboard management controller sends a detection command to the complex programmable logic device via the bus, wherein the detection command is to detect the operating status of the expansion chip module;

[0037] The complex programmable logic device determines the operating status of the extended chip module by receiving the heartbeat signal sent by the extended chip module, including: setting the firmware heartbeat signal frequency of the extended chip module to indicate the firmware working status of the extended chip module;

[0038] The hardware configuration heartbeat signal frequency of the extended chip module is set to indicate the hardware status of the extended chip module;

[0039] The operating mode heartbeat signal frequency of the extended chip module is set to indicate the current operating mode status of the extended chip module;

[0040] Set the abnormal frequency threshold range;

[0041] The frequency of each heartbeat signal is measured using the counter and the timer to determine whether it is within the abnormal frequency threshold range, and a comparison result is obtained.

[0042] If the firmware heartbeat signal frequency of the extended chip module exceeds the abnormal frequency threshold range, it indicates that there is a problem with the current firmware working state of the extended chip module.

[0043] In response to an anomaly occurring during the operation of the extended chip module, the complex programmable logic device reports the anomaly detection result to the baseboard management controller.

[0044] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0045] The power module sends a power good signal to the power input terminal of the complex programmable logic device through its output terminal;

[0046] After receiving a power good signal, the complex programmable logic device detects the power good signal and obtains a detection result, which includes: power-on normal and power-on abnormal.

[0047] In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on the delay logic and the external crystal clock, and sends the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal of the complex programmable logic device.

[0048] The complex programmable logic device generates a debugging signal based on the delay logic and the external crystal clock, and sends the debugging signal to the debugging signal input terminal of the expansion chip module through the debugging signal output terminal of the complex programmable logic device module;

[0049] The extended chip module performs corresponding operations based on the received reset signal and debug signal.

[0050] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0051] The power module sends a power good signal to the power input terminal of the complex programmable logic device through its output terminal;

[0052] After receiving a power good signal, the complex programmable logic device detects the power good signal and obtains a detection result, which includes: power-on normal and power-on abnormal.

[0053] In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on the delay logic and the external crystal clock, and sends the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal of the complex programmable logic device.

[0054] The complex programmable logic device generates a debugging signal based on the delay logic and the external crystal clock, and sends the debugging signal to the debugging signal input terminal of the expansion chip module through the debugging signal output terminal of the complex programmable logic device module;

[0055] The extended chip module performs corresponding operations based on the received reset signal and debug signal.

[0056] In the aforementioned expansion card timing management device, the reset signal output of the complex programmable logic device (CPL) is connected to the reset signal input of the expansion chip module, enabling the CPL to control the reset of the expansion chip module. The debug signal output of the CPL is connected to the debug signal input of the expansion chip module, allowing the CPL to control and diagnose the expansion chip module via debug signals. The CPL module and the expansion chip module have clearly defined roles on the expansion card: the CPL is responsible for control functions such as reset, debugging, and heartbeat monitoring, while the expansion chip module provides specific expansion functions. This modular design allows for flexible replacement or upgrades of the expansion chip module, adapting the expansion card to different application scenarios and improving system scalability and flexibility. Timing control is achieved by controlling the time sequence of the two signals. Reasonable port connections enable hardware integration and function sharing, reducing system cost and power consumption while improving system reliability, response speed, and maintainability. This optimized design is suitable for various application scenarios with high requirements for cost, energy efficiency, and reliability. Attached Figure Description

[0057] Figure 1 This is an application environment diagram of the expansion card timing management method in one embodiment;

[0058] Figure 2 This is a structural diagram of the expansion card timing management device in one embodiment;

[0059] Figure 3 This is a flowchart illustrating an expansion card timing management method in one embodiment;

[0060] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0062] In one embodiment, such as Figure 2As shown, an expansion card timing management device is provided, including: an expansion chip module and a complex programmable logic device (CPLD) disposed on an expansion card module. The CPLD is connected to the motherboard via a bus. The expansion card module also includes a power module, which includes a power output terminal. The CPLD includes a power input terminal, a reset signal output terminal, a debug signal output terminal, and a heartbeat signal input terminal. The expansion chip module includes a heartbeat signal output terminal, a reset signal input terminal, and a debug signal input terminal.

[0063] Specifically, the power output terminal of the power module is connected to the power input terminal of the complex programmable logic device (CPLD), the reset signal output terminal of the CPLD is connected to the reset signal input terminal of the expansion chip module, the debug signal output terminal of the CPLD is connected to the signal input terminal of the expansion chip module, and the heartbeat signal output terminal of the expansion chip module is connected to the heartbeat signal input terminal of the CPLD.

[0064] The power output terminal, power input terminal, reset signal output terminal, debug signal output terminal, heartbeat signal input terminal, heartbeat signal output terminal, reset signal input terminal, and debug signal input terminal are implemented through OD (Open-Drain) configuration. OD is used to drive and communicate input / output signals. Open-Drain is an output configuration type widely used in digital circuit design. In scenarios such as reset signals and heartbeat signals, it allows multiple devices to share a single signal line and pull the signal low when needed. In the high-impedance state, the OD output does not drive a level; the signal line is pulled high by an external pull-up resistor, allowing multiple devices to connect to this line and share the signal. When the OD output is pulled low, the OD configuration actively pulls the signal line low (output 0), driving the signal line to a low level, indicating a valid signal. OD allows devices to actively pull the signal low when needed and return to a high-impedance state when not needed, avoiding level conflicts caused by multiple devices simultaneously driving signals.

[0065] Specifically, by connecting various ports, functional integration and resource sharing are achieved, thereby reducing the use of hardware components. Functional reuse between modules is realized, further reducing the need for independent hardware components. Manufacturing costs are reduced while optimizing circuit layout space. Complex programmable logic devices can directly control reset, debug, and heartbeat signals through port connections, thus reducing design complexity. Hardware circuit design is simplified, reducing the dependence on hardware changes for various application requirements, making it suitable for multiple scenarios, reducing development and verification work, and lowering maintenance costs.

[0066] In the aforementioned expansion card timing management device, the reset signal output of the complex programmable logic device (CPL) is connected to the reset signal input of the expansion chip module, enabling the CPL to control the reset of the expansion chip module. The debug signal output of the CPL is connected to the debug signal input of the expansion chip module, allowing the CPL to control and diagnose the expansion chip module via debug signals. The CPL module and the expansion chip module have clearly defined roles on the expansion card: the CPL is responsible for control functions such as reset, debugging, and heartbeat monitoring, while the expansion chip module provides specific expansion functions. This modular design allows for flexible replacement or upgrades of the expansion chip module, adapting the expansion card to different application scenarios and improving system scalability and flexibility. Timing control is achieved by controlling the time sequence of the two signals. Reasonable port connections enable hardware integration and function sharing, reducing system cost and power consumption while improving system reliability, response speed, and maintainability. This optimized design is suitable for various application scenarios with high requirements for cost, energy efficiency, and reliability.

[0067] In one embodiment, the motherboard is provided with a baseboard management controller connected to the complex programmable logic device via the bus, and the baseboard management controller is used to control the complex programmable logic device.

[0068] Specifically, the motherboard connects to complex programmable logic devices (CPLs) via a baseboard management controller and a bus. The baseboard management controller can monitor the CPL status in real time via the bus, including power status, heartbeat signals, and reset signals. This allows system administrators to remotely obtain system operating information, greatly enhancing system controllability. The combination of the baseboard management controller and the CPLs not only simplifies hardware design and improves system integration but also significantly enhances system stability, maintainability, and adaptability.

[0069] In one embodiment, the expansion card module is provided with an external crystal clock module, the output terminal of which is connected to the clock signal input terminal of the complex programmable logic device. The complex programmable logic device is also provided with a timer and a counter for measuring time.

[0070] Specifically, by configuring an external crystal clock module on the expansion card module and connecting it to a complex programmable logic device (CPL), the timers and counters of the CPL become more accurate in time measurement, enabling precise time interval control. The system obtains a high-precision time base, significantly enhancing the system's time control accuracy, response speed, stability, and reliability. Furthermore, this design enhances the system's independence and scalability, making the expansion card module independent of the motherboard clock, suitable for scenarios requiring high precision and stability.

[0071] The expansion card timing management method based on an expansion card timing management device provided in this application can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. The complex programmable logic device (CLPD) detects the power-good signal sent by the power module. Upon receiving a normal power-on result, it generates reset and debug signals through delay logic and an external crystal clock signal, and sends these signals to the expansion chip. The expansion chip then performs corresponding operations based on the signals. Terminal 102 can be, but is not limited to, various personal computers and laptops, and server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0072] In one embodiment, an expansion card timing management method based on an expansion card timing management device includes:

[0073] Step 202: The power module sends a power good signal to the power input terminal of the complex programmable logic device through its output terminal.

[0074] Specifically, the power module generates a power-good signal upon power-up and transmits it to the complex programmable logic device (CPL). This signal indicates that the power supply has reached a stable operating state and signals to the CPL that the system can begin the startup process.

[0075] Step 204: After receiving the power good signal, the complex programmable logic device detects the power good signal and obtains the detection result, which includes: normal power-on and abnormal power-on.

[0076] Specifically, by detecting the power supply signal status, complex programmable logic devices (CPLs) can accurately determine whether the startup conditions are met. If the power supply is abnormal, such as unstable or too low a voltage, the CPL will prevent the startup process, avoiding potential risks. This detection step provides crucial fault protection for the system and improves startup safety.

[0077] Step 206: In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on the first delay duration and the external crystal oscillator clock, and sends the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal of the complex programmable logic device.

[0078] Specifically, when the complex programmable logic device (CPL) detects a normal power-on, it sets a waiting time value. Once this waiting time value is reached, indicating power signal stability, a reset signal is generated using delay logic and an external crystal oscillator clock. This ensures the system only resets the expansion chip module after power stability. The external crystal oscillator clock provides a high-precision time reference for the reset signal generation, ensuring accurate timing. Through the delay logic, the CPL can issue a reset signal only after a period of power stabilization, avoiding false resets caused by transient power fluctuations or unstable power rise. This mechanism significantly improves system startup stability, ensuring the expansion chip module enters the correct startup state.

[0079] Step 208: Set the second delay duration. After the first signal is sent, start the timer. The complex programmable logic device generates a debugging signal according to the second delay duration and the external crystal oscillator clock. The debugging signal is sent to the debugging signal input terminal of the expansion chip module through the debugging signal output terminal of the complex programmable logic device module. The second delay duration is longer than the first delay duration.

[0080] Specifically, after receiving the reset signal, the complex programmable logic device (CPL) generates a debug signal via delay logic and an external crystal oscillator clock. This debug signal instructs the expansion chip module to enter debug mode or perform initialization configuration. The generation of the debug signal is also precisely controlled by the crystal oscillator clock, ensuring that the module enters debug mode according to the set timing after reset, avoiding conflicts between reset and debug signals. This step guarantees that the expansion chip module receives the debug signal at the correct time to perform necessary initialization, configuration, and self-test operations, improving debugging effectiveness and the overall system startup success rate.

[0081] Step 210: The extended chip module performs corresponding operations based on the received reset signal and debug signal.

[0082] Specifically, the reset signal and the debug signal work together to enable the expansion chip module to complete the reset and initialization in sequence and enter the correct working state. The signal sequence ensures that the status of the expansion chip module is clear and the configuration is correct, reducing failures caused by operational confusion or initialization errors during the startup process, thereby improving the stability and reliability of the system.

[0083] Specifically, the complex programmable logic device (CPL) generates reset and debug signals based on delay logic and an external crystal oscillator clock. This timing mechanism ensures that control signals are sent only after the power supply is fully stable, effectively reducing the impact of power fluctuations or interference during startup and improving system stability. The reset and debug signals generated by the CPL undergo precise delay control, ensuring that the expansion chip module completes initialization according to the specified timing sequence. This design avoids initialization failures or anomalies caused by signal asynchrony or timing errors, ensuring that the expansion chip module can start correctly and enter the working state. Through power state detection and precise delay control, the correct signal timing is ensured, reducing the impact of power transient fluctuations on the system and thus improving the system's anti-interference capability. The external crystal oscillator provides a stable frequency reference, making the generation of reset and debug signals less susceptible to external interference, especially under complex electromagnetic environments, ensuring stable operation and improving the overall system reliability. The CPL automatically generates reset and debug signals without manual intervention, greatly reducing the complexity of daily maintenance and improving system usability and reliability.

[0084] This design, through real-time power status monitoring, precise control of delay logic, and synchronous signal transmission, makes the system more stable and reliable during startup and operation. The centralized management capabilities of complex programmable logic devices not only optimize signal transmission paths and reduce hardware requirements but also enhance the system's self-monitoring and automatic recovery capabilities, simplifying overall system maintenance.

[0085] In one embodiment, after receiving the power-good signal, the complex programmable logic device detects the power-good signal to obtain a detection result. The detection result includes: power-on normal and power-on abnormal, including:

[0086] The complex programmable logic device initializes the counter and sets a threshold for the counter;

[0087] The complex programmable logic device periodically samples and detects the power-good signal, and records the detection result each time;

[0088] If the detection result indicates that the power-on is normal, the counter is incremented by one;

[0089] If the detection result indicates a power-on abnormality, the counter is reset to zero, and the detection process restarts.

[0090] If the detection result indicates that the power-on is normal and the value does not reach the threshold of the counter, then the next sampling is performed;

[0091] When the detection result indicating normal power-on reaches the threshold of the counter, the power supply good signal is stable power-on normal.

[0092] If the value of the detection result indicating normal power-on does not reach the threshold of the counter within a set time period, then the power good signal indicates abnormal power-on.

[0093] Specifically, the counter threshold of the complex programmable logic device is set to 5, the sampling period is 10 milliseconds, and a 50-millisecond detection window is set for the system to detect the good power signal. The specific detection process is as follows:

[0094] Counter initialization: Upon receiving a power-good signal, the complex programmable logic device (CPLD) initializes the counter to 0 and sets the threshold to 5. Periodic sampling and detection: The CPLD samples the power-good signal every 10 milliseconds and records the sampling result each time.

[0095] Testing process:

[0096] First sampling: The test result shows that the power-on is normal, the counter increments by 1, and the counter value is 1.

[0097] Second sampling: The test result was a power-on abnormality, the counter was reset to zero, and the test started again.

[0098] Third sampling: The test result shows that the power-on is normal, the counter increments by 1, and the counter value is 1.

[0099] Sampling from the 4th to the 8th time: The detection result is always "normal power-on", and the counter increments sequentially until it reaches 5 (i.e., the threshold is reached).

[0100] Determining power status: When the counter value reaches the threshold, that is, when the sampling result is 5 consecutive times, the power-on is normal. The complex programmable logic device will determine the good power signal as a stable and normal power-on.

[0101] If the counter value fails to reach the threshold within the 50-millisecond detection period, the complex programmable logic device is determined to be a power-on abnormality.

[0102] By adjusting the counter threshold and sampling period, the stability requirements for power supply detection can be flexibly set according to specific system needs. For example, in environments with high stability requirements, a higher threshold and a longer detection duration can be set to enhance the stringency of power supply detection; in low-power systems, the requirements can be appropriately reduced to improve response speed. This flexibility makes the power supply detection design highly adaptable. Frequent misjudgments of the power-on state can lead to frequent triggering of reset signals, thus affecting the normal operation of the system. Through the above detection mechanism, complex programmable logic devices will not generate reset signals before confirming power supply stability, preventing frequent resets caused by brief fluctuations in power supply status and ensuring smooth system startup and stable operation.

[0103] In one embodiment, in response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on a first delay duration and the external crystal clock, and sends the reset signal from the reset signal output terminal of the complex programmable logic device to the reset signal input terminal of the expansion chip module, including:

[0104] A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock.

[0105] The complex programmable logic device starts a timer to begin timing according to the clock signal, determines a first trigger time according to the first delay duration, and generates a reset signal in response to the timer time reaching the first trigger time.

[0106] The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

[0107] Specifically, the following parameters are configured: the external crystal oscillator clock frequency is 10MHz (i.e., each clock cycle is 0.1 microseconds). The first timing duration is set to 50 milliseconds to wait for further power stabilization. Clock signal transmission: The external crystal oscillator generates a 10MHz high-precision clock signal, which is transmitted to the clock signal input of the complex programmable logic device (CPL) through its output terminal as the system time base. Timer start timing: When the CPL detects a good power signal (PG signal) and confirms that the power-on state is normal, the timer starts timing under the drive of the 10MHz clock signal. The timer's first timing end time is set to 50 milliseconds, meaning the timer needs to accumulate 500,000 clock cycles before reaching the set delay time. Timing completion and reset signal generation: When the timer reaches 50 milliseconds (accumulated 500,000 clock cycles), the CPL generates a reset signal to ensure that the power supply is completely stable before initiating the reset process of the expansion chip module. Sending the reset signal: The CPL transmits the reset signal to the reset signal input of the expansion chip module through its reset signal output terminal, thereby resetting and initializing the expansion chip module.

[0108] By employing a delayed reset design that combines an external crystal oscillator clock and a timer, this embodiment ensures that the extended chip module is reset after the power supply is fully stable. This improves the system's startup safety and anti-interference capabilities, optimizes the control precision of the reset timing, and offers good compatibility and maintainability, making it suitable for a variety of complex application scenarios.

[0109] In one embodiment, the complex programmable logic device generates a debug signal based on a second delay duration and an external crystal clock, and sends the debug signal to the debug signal input terminal of the expansion chip module through the debug signal output terminal of the complex programmable logic device module, wherein the second delay duration is longer than the first delay duration, including:

[0110] A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock.

[0111] The complex programmable logic device starts a timer to begin timing according to the clock signal, and determines the second trigger time according to the second delay duration;

[0112] In response to the timer reaching the second trigger time, the complex programmable logic device generates a debug signal;

[0113] The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

[0114] Specifically, it should be understood that the debugging signal generation step is the same as the reset signal generation step described above, so it will not be repeated here.

[0115] By delaying the generation of debugging signals, the system enters debugging mode only after completing power-on stability testing and reset. This delay logic avoids the impact of startup fluctuations on the debugging process, improving the stability and reliability of system debugging.

[0116] In one embodiment, the extended chip module performs corresponding operations based on the received reset signal and debug signal, further comprising:

[0117] The baseboard management controller sends a detection command to the complex programmable logic device via the bus, wherein the detection command is to detect the operating status of the expansion chip module;

[0118] The complex programmable logic device determines the operating status of the expansion chip module by receiving the heartbeat signal sent by the expansion chip module, including:

[0119] The firmware heartbeat signal frequency of the extended chip module is set to indicate the firmware working status of the extended chip module.

[0120] The hardware configuration heartbeat signal frequency of the extended chip module is set to indicate the hardware status of the extended chip module;

[0121] The operating mode heartbeat signal frequency of the extended chip module is set to indicate the current operating mode status of the extended chip module;

[0122] Set the abnormal frequency threshold range;

[0123] The frequency of each heartbeat signal is measured using the counter and the timer to determine whether it is within the abnormal frequency threshold range, and a comparison result is obtained.

[0124] If the firmware heartbeat signal frequency of the extended chip module exceeds the abnormal frequency threshold range, it indicates that there is a problem with the current firmware working state of the extended chip module.

[0125] In response to an anomaly occurring during the operation of the extended chip module, the complex programmable logic device reports the anomaly detection result to the baseboard management controller.

[0126] Specifically, the system is configured with the following heartbeat signal monitoring parameters:

[0127] Firmware heartbeat signal frequency: set to 10Hz, used to indicate the firmware running status of the extended chip.

[0128] Hardware configuration heartbeat signal frequency: set to 5Hz, indicating whether the expansion chip hardware configuration is normal.

[0129] Operating mode heartbeat signal frequency: set to 1Hz, indicating the current operating mode status of the expansion chip.

[0130] Abnormal frequency threshold range: allowable deviation of ±10% for each heartbeat signal.

[0131] During actual monitoring, the complex programmable logic device (CPL) performs the following steps: The baseboard management controller sends detection commands to the CPL via the bus, requesting monitoring of various operating states of the expansion chip. Heartbeat signal frequency measurement: During normal operation, the CPL receives various heartbeat signals periodically and measures the frequency of each heartbeat signal using counters and timers. For example, the firmware heartbeat signal should be close to 10Hz, and the CPL verifies that the received frequency is within the range of 9-11Hz. The hardware configuration heartbeat signal should be close to 5Hz, with a verification range of 4.5-5.5Hz. The operating mode heartbeat signal should be 1Hz, with a verification range of 0.9-1.1Hz. Frequency anomaly judgment: The CPL compares the actual frequency of each heartbeat signal with the set frequency range. For example, if the firmware heartbeat signal frequency is 8Hz (below the threshold range), the CPL identifies it as a firmware status anomaly. If the hardware configuration heartbeat signal frequency is abnormal (e.g., 3Hz), it is judged as a hardware configuration anomaly. Abnormal result reporting: When any heartbeat signal exceeds the set threshold range, the complex programmable logic device immediately reports the abnormal detection result to the board management controller so that the board management controller can respond in a timely manner and may take measures such as restarting or isolating the faulty chip.

[0132] By detecting the frequency of different types of heartbeat signals, multi-level status monitoring of firmware, hardware, and operating modes is achieved, significantly improving monitoring accuracy and enabling the system to quickly detect anomalies. Complex programmable logic devices (PLDs) can quickly identify firmware or hardware anomalies by monitoring heartbeat frequencies in real time, preventing potential faults from spreading further and ensuring the overall stable operation of the system. Real-time heartbeat detection provides early warnings through a feedback mechanism when a fault occurs, reducing the impact of interruptions caused by a system-wide restart and improving system continuity. The ability to adjust the frequency and threshold range of different heartbeat signals allows the monitoring solution to be extended to more types of expansion chip modules or other hardware units, enhancing system compatibility.

[0133] This embodiment utilizes complex programmable logic devices to monitor the frequency of the heartbeat signal from the extended chip module. Based on multi-level detection of firmware, hardware configuration, and operating modes, it provides a precise and real-time anomaly warning mechanism. This method not only improves system stability and reliability but also significantly reduces maintenance costs and operational risks, making it suitable for various complex system management scenarios.

[0134] In one embodiment, responding to the firmware heartbeat signal frequency of the extended chip module exceeding the abnormal frequency threshold range, indicating a problem with the current firmware operating state of the extended chip module, the method further includes:

[0135] In response to the complex programmable logic device detecting that the firmware heartbeat signal of the extended chip module exceeds the abnormal frequency threshold range;

[0136] The complex programmable logic device reports the abnormal situation to the baseboard management controller;

[0137] Specifically, when an anomaly is detected, the complex programmable logic device reports the anomaly to the baseboard management controller via the bus, notifying it that there is a problem with the firmware of the expansion chip module.

[0138] After receiving the report, the baseboard management controller sends a reset command to the complex programmable logic device via the bus, wherein the reset command is to perform a reset operation on the expansion chip;

[0139] Specifically, after receiving an anomaly report, the baseboard management controller sends a reset command to the complex programmable logic device via the bus, requesting a reset operation on the expansion chip module.

[0140] When the complex programmable logic device receives a reset command, it lowers the signal strength of the reset signal output from the reset signal output terminal of the complex programmable logic device, thereby triggering a reset operation.

[0141] Specifically, upon receiving a reset command, the complex programmable logic device (CPL) controls the strength of the reset signal at the reset signal output terminal, pulling it low to trigger the reset operation of the expansion chip. Through logic design, the CPL can control the reset signal to remain low for a period of time (e.g., several clock cycles), ensuring that the reset of the expansion chip module can be effectively triggered.

[0142] The complex programmable logic device releases the signal strength of the reset signal after a preset time has elapsed;

[0143] Specifically, the complex programmable logic device (CPL) waits for a preset period of time to ensure that the reset process of the expansion chip is complete. After the reset is complete, the CPL restores the reset pin to a high level or high impedance state, allowing the expansion chip to restart normally.

[0144] The complex programmable logic device re-detects the firmware heartbeat signal frequency of the extended chip module; and obtains the detection result, wherein the detection result includes: normal heartbeat signal and abnormal heartbeat signal;

[0145] In response to the detection result of the complex programmable logic device indicating a normal heartbeat signal, the system reports to the baseboard management controller.

[0146] In response to the detection result of the complex programmable logic device indicating an abnormal heartbeat signal, the error is recorded and reported to the substrate management controller.

[0147] Specifically, after the expansion chip resets, the complex programmable logic device (CPLD) restarts the heartbeat signal detection process, monitoring the frequency of its firmware heartbeat signal. If the detected heartbeat signal frequency returns to the normal range, the CPLD reports to the baseboard management controller that the reset was successful and the expansion chip has returned to normal. If the heartbeat signal is still abnormal, the CPLD records the error and reports the abnormal state to the baseboard management controller for further processing.

[0148] Through automatic detection and rapid recovery mechanisms, the system achieves rapid response and reset control for abnormal states, improving system reliability and automation. The complex programmable logic device (CLPD), as the core control unit, ensures the stable operation of the expansion chip module through monitoring the heartbeat signal, controlling the reset pin, and cooperating with the baseboard management controller.

[0149] It should be understood that, although Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0150] Specific limitations regarding the expansion card timing management device can be found in the limitations of the expansion card timing management method described above, and will not be repeated here. Each module in the aforementioned expansion card timing management device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0151] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 4As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores expansion card data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements an expansion card timing management method.

[0152] Those skilled in the art will understand that Figure 2 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0153] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0154] The power module sends a power good signal to the power input terminal of the complex programmable logic device through its output terminal;

[0155] After receiving a power good signal, the complex programmable logic device detects the power good signal and obtains a detection result, which includes: normal power-on and abnormal power-on.

[0156] In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on the first delay duration and the external crystal clock, and sends the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal of the complex programmable logic device.

[0157] The complex programmable logic device generates a debugging signal based on a second delay duration and an external crystal clock, and sends the debugging signal to the debugging signal input terminal of the expansion chip module through the debugging signal output terminal of the complex programmable logic device module, wherein the second delay duration is longer than the first delay duration;

[0158] The extended chip module performs corresponding operations based on the received reset signal and debug signal.

[0159] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0160] The complex programmable logic device initializes the counter and sets a threshold for the counter;

[0161] The complex programmable logic device periodically samples and detects the power-good signal, and records the detection result each time;

[0162] If the detection result indicates that the power-on is normal, the counter is incremented by one;

[0163] If the detection result indicates a power-on abnormality, the counter is reset to zero, and the detection process restarts.

[0164] If the detection result indicates that the power-on is normal and the value does not reach the threshold of the counter, then the next sampling is performed;

[0165] When the detection result indicating normal power-on reaches the threshold of the counter, the power supply good signal is stable power-on normal.

[0166] If the value of the detection result indicating normal power-on does not reach the threshold of the counter within a set time period, then the power good signal indicates abnormal power-on.

[0167] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0168] A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock.

[0169] The complex programmable logic device starts a timer according to the clock signal to start timing, sets a first timing end time, and obtains a first timing duration;

[0170] In response to the timer reaching the first timer end time, the complex programmable logic device generates a reset signal according to the first timer duration;

[0171] The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

[0172] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0173] The power module sends a power good signal to the power input terminal of the complex programmable logic device through its output terminal;

[0174] After receiving a power good signal, the complex programmable logic device detects the power good signal and obtains a detection result, which includes: normal power-on and abnormal power-on.

[0175] In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on the first delay duration and the external crystal clock, and sends the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal of the complex programmable logic device.

[0176] The complex programmable logic device generates a debugging signal based on a second delay duration and an external crystal clock, and sends the debugging signal to the debugging signal input terminal of the expansion chip module through the debugging signal output terminal of the complex programmable logic device module, wherein the second delay duration is longer than the first delay duration;

[0177] The extended chip module performs corresponding operations based on the received reset signal and debug signal.

[0178] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0179] A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock.

[0180] The complex programmable logic device starts a timer according to the clock signal to start timing, sets a second timing end time, and obtains a second timing duration, wherein the second timing duration is greater than the first timing duration;

[0181] In response to the timer reaching the second timing end time, the complex programmable logic device generates a debug signal according to the second timing duration;

[0182] The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

[0183] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0184] The baseboard management controller sends a detection command to the complex programmable logic device via the bus, wherein the detection command is to detect the operating status of the expansion chip module;

[0185] The complex programmable logic device determines the operating status of the extended chip module by receiving the heartbeat signal sent by the extended chip module, including: setting the firmware heartbeat signal frequency of the extended chip module to indicate the firmware working status of the extended chip module;

[0186] The hardware configuration heartbeat signal frequency of the extended chip module is set to indicate the hardware status of the extended chip module;

[0187] The operating mode heartbeat signal frequency of the extended chip module is set to indicate the current operating mode status of the extended chip module;

[0188] Set the abnormal frequency threshold range;

[0189] The frequency of each heartbeat signal is measured using the counter and the timer to determine whether it is within the abnormal frequency threshold range, and a comparison result is obtained.

[0190] If the firmware heartbeat signal frequency of the extended chip module exceeds the abnormal frequency threshold range, it indicates that there is a problem with the current firmware working state of the extended chip module.

[0191] In response to an anomaly occurring during the operation of the extended chip module, the complex programmable logic device reports the anomaly detection result to the baseboard management controller.

[0192] In one embodiment, when a computer program is executed by a processor, it further performs the following steps: the computer program may be stored in a non-volatile computer-readable storage medium, and when executed, the computer program may include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0193] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A timing management device for an expansion card, characterized in that, include: An expansion card module and a complex programmable logic device (CPLD) are mounted on the expansion card module. The CPLD is connected to the motherboard via a bus. The expansion card module also includes a power module with a power output terminal. The CPLD includes a power input terminal, a reset signal output terminal, a debug signal output terminal, and a heartbeat signal input terminal. The expansion card module includes a heartbeat signal output terminal, a reset signal input terminal, and a debug signal input terminal. Wherein, the power output terminal of the power module is connected to the power input terminal of the complex programmable logic device, the reset signal output terminal of the complex programmable logic device is connected to the reset signal input terminal of the expansion chip module, the debug signal output terminal of the complex programmable logic device is connected to the signal input terminal of the expansion chip module, and the heartbeat signal output terminal of the expansion chip module is connected to the heartbeat signal input terminal of the complex programmable logic device; The extended chip module performs corresponding operations based on the received reset signal and debug signal, including: The baseboard management controller sends a detection command to the complex programmable logic device via the bus, wherein the detection command is to detect the operating status of the expansion chip module; The complex programmable logic device determines the operating status of the extended chip module by receiving the heartbeat signal sent by the extended chip module, including: setting the firmware heartbeat signal frequency of the extended chip module to indicate the firmware working status of the extended chip module; The hardware configuration heartbeat signal frequency of the extended chip module is set to indicate the hardware status of the extended chip module; The operating mode heartbeat signal frequency of the extended chip module is set to indicate the current operating mode status of the extended chip module; Set the abnormal frequency threshold range; The frequency of each heartbeat signal is measured using a counter and a timer to determine whether it falls within the abnormal frequency threshold range, and the comparison results are obtained. If the firmware heartbeat signal frequency of the extended chip module exceeds the abnormal frequency threshold range, it indicates that there is a problem with the current firmware working state of the extended chip module. In response to an anomaly occurring during the operation of the extended chip module, the complex programmable logic device reports the anomaly detection result to the baseboard management controller.

2. The expansion card timing management device according to claim 1, characterized in that, include: The motherboard is equipped with a baseboard management controller that is connected to the complex programmable logic device via the bus. The baseboard management controller is used to control the complex programmable logic device.

3. The expansion card timing management device according to claim 1, characterized in that, include: The expansion card module is equipped with an external crystal clock module. The output terminal of the external crystal clock module is connected to the clock signal input terminal of the complex programmable logic device. The complex programmable logic device is also equipped with a timer and a counter for measuring time.

4. A method for managing the timing of an expansion card in the expansion card timing management device according to any one of claims 1-3, characterized in that, include: The power module sends a power good signal to the power input terminal of the complex programmable logic device through its output terminal; After receiving a power good signal, the complex programmable logic device detects the power good signal and obtains a detection result, which includes: normal power-on and abnormal power-on. In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on the first delay duration and the external crystal clock, and sends the reset signal to the reset signal input terminal of the expansion chip module through the reset signal output terminal of the complex programmable logic device. A second delay duration is set. After the reset signal is sent, the timer is started. The complex programmable logic device generates a debug signal based on the second delay duration and the external crystal clock. The debug signal is sent to the debug signal input terminal of the expansion chip module through the debug signal output terminal of the complex programmable logic device module. The second delay duration is longer than the first delay duration. The extended chip module performs corresponding operations based on the received reset signal and debug signal.

5. The expansion card timing management method according to claim 4, characterized in that, After receiving the power-good signal, the complex programmable logic device detects the power-good signal and obtains a detection result. The detection result includes: normal power-on and abnormal power-on, including: The complex programmable logic device initializes the counter and sets a threshold for the counter; The complex programmable logic device periodically samples and detects the power-good signal, and records the detection result each time; If the detection result indicates that the power-on is normal, the counter is incremented by one; If the detection result indicates a power-on abnormality, the counter is reset to zero, and the detection process restarts. If the detection result indicates that the power-on is normal and the value does not reach the threshold of the counter, then the next sampling is performed; When the detection result indicating normal power-on reaches the threshold of the counter, the power supply good signal is stable power-on normal. If the value of the detection result indicating normal power-on does not reach the threshold of the counter within a set time period, then the power good signal indicates abnormal power-on.

6. The expansion card timing management method according to claim 5, characterized in that, In response to the detection result indicating normal power-on, the complex programmable logic device generates a reset signal based on a first delay duration and the external crystal oscillator clock, and sends the reset signal from the reset signal output terminal of the complex programmable logic device to the reset signal input terminal of the expansion chip module, including: A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock. The complex programmable logic device starts a timer to begin timing according to the clock signal, determines a first trigger time according to the first delay duration, and generates a reset signal in response to the timer time reaching the first trigger time. The reset signal output terminal of the complex programmable logic device sends a reset signal to the reset signal input terminal of the expansion chip.

7. The expansion card timing management method according to claim 6, characterized in that, The complex programmable logic device generates a debug signal based on a second delay duration and an external crystal clock, and sends the debug signal to the debug signal input terminal of the expansion chip module through the debug signal output terminal of the complex programmable logic device module, wherein the second delay duration is longer than the first delay duration, including: A clock signal is sent to the clock signal input terminal of the complex programmable logic device through the output terminal of the external crystal oscillator clock. The complex programmable logic device starts a timer to begin timing according to the clock signal, and determines the second trigger time according to the second delay duration; In response to the timer reaching the second trigger time, the complex programmable logic device generates a debug signal; The debug signal output terminal of the complex programmable logic device sends a debug signal to the debug signal input terminal of the expansion chip.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 4 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 4 to 7.

Images