Operation method of memory controller, memory controller and memory system

Abstract

The invention provides an operation method of a memory controller, the memory controller and a memory system, and relates to the technical field of semiconductor chips. The operation method comprises the following steps: in response to a data writing instruction, determining a first storage unit block of to-be-written data; determining whether the target parameter of the first storage unit block is greater than a first threshold; and in response to that the target parameter of the first storage unit block is not greater than the first threshold, writing data into the first storage unit block. According to the application, when the target parameters of part of the programming blocks are not greater than the preset first threshold value, that is, the unprogrammed memory cell pages are less affected, the execution of erased page detection is omitted, and the data is written into the first memory cell block. Therefore, the time consumed for executing erase page detection is saved, the time consumed for programming part of programming blocks is shortened, and the programming time of the memory is shortened.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor chip technology, and in particular, relates to an operating method of a memory controller, a memory controller and a memory system. Background Art

[0002] As a non-volatile memory, NAND memory has the advantages of low cost, high capacity, fast rewrite speed, etc. In NAND memory, peripheral circuits usually supply power to the storage unit to implement various logic operations, such as read operation, program operation and erase operation. Summary of the invention

[0003] The embodiments disclosed in the present application provide an operating method of a memory controller, a memory controller and a memory system, which are used to reduce the programming time of a memory.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a method for operating a memory controller is provided, the method comprising: in response to a data write instruction, determining a first storage unit block to which data is to be written; determining whether a target parameter of the first storage unit block is greater than a first threshold; and in response to the target parameter of the first storage unit block being not greater than the first threshold, writing data to the first storage unit block.

[0006] The present application reflects the impact on the unprogrammed memory cell page according to the target parameters of the partial programming block. When the target parameters of the partial programming block meet the requirement of not being greater than the preset first threshold value, the unprogrammed memory cell page is less affected, so the execution of the erase page detection can be omitted, and data can be written to the first memory cell block. This saves the time required for executing the erase page detection, reduces the time required for programming the partial programming block, and reduces the programming time of the memory.

[0007] In some embodiments, the operation method further includes: in response to the target parameter of the first storage cell block being greater than the first threshold, performing an erase page detection on the first storage cell block; in response to the first storage cell block passing the erase page detection, writing data to the first storage cell block. The erase page detection can indicate that the unprogrammed storage cell page is in an erased state, that is, it has not been affected by various factors and data bit flipping has occurred. Therefore, the peripheral circuit in the memory can ensure the accuracy of the written data when writing data to any unprogrammed storage cell page in the first storage cell block.

[0008] In some embodiments, the target parameter of the first storage cell block includes the number of data reads of the first storage cell block. Each time data is read from a programmed storage cell page, read interference is generated on the unprogrammed storage cell page, resulting in weak programming. When the number of data reads is greater than the preset number, the accumulated read interference may cause data bit flipping of the unprogrammed storage cell page, affecting the accuracy of subsequent programming of the unprogrammed storage cell page. Or, the target parameter of the first storage cell block includes the placement time of the first storage cell block, and the placement time of the first storage cell block is the time difference between the current moment and the moment when the erase operation was last performed on the first storage cell block. When the placement time is greater than the preset time, the accumulated migrated charge page may affect the accuracy of subsequent programming of the unprogrammed storage cell page. Therefore, the present application can reflect whether the unprogrammed storage cell page can meet the programming conditions to a certain extent through the number of data reads of the first storage cell block or the placement time of the first storage cell block.

[0009] In some embodiments, the operating method further includes: determining a first threshold value based on the number of erase times of the first storage cell block. As the number of erase times of the storage cell block increases, the tunneling layer between the floating gate (or charge well) and the channel is worn more and more seriously, and read interference and charge migration are more likely to affect the storage cell. In other words, the first storage cell blocks with different erase times face different impacts when facing the same number of data reads (or placement times). Therefore, the present application determines the first threshold value by the number of erase times of the first storage cell block, and can more accurately judge the impact on the first storage cell block based on the number of data reads (or placement times).

[0010] In some embodiments, for an unprogrammed memory cell page, the more times the erase is performed, the easier it is for data bit flipping to occur. Therefore, based on the number of erases of the first memory cell block, a first threshold is determined; specifically, the method includes: determining whether the number of erases of the first memory cell block is greater than a second threshold; in response to the number of erases of the first memory cell block being greater than the second threshold, determining the first threshold to be threshold a; in response to the number of erases of the first memory cell block being not greater than the second threshold, determining the first threshold to be threshold b; threshold a is less than threshold b.

[0011] In some embodiments, the operation method further includes: in response to the first storage cell block failing to pass the erase page detection, determining whether the number of first word lines coupled to the programmed storage cell pages in the first storage cell block is greater than a third threshold value; in response to the number of first word lines not being greater than the third threshold value, writing data to the unprogrammed storage cell pages coupled to the second word line in the first storage cell block, the second word line being not adjacent to the first word line; in response to the number of first word lines being greater than the third threshold value, determining the second storage cell block to be written with data. Since the read disturbance mainly affects the storage cells adjacent to the read storage cells, it has less impact on the storage cell pages in the second word line. Therefore, when the first storage cell block fails to pass the erase page detection, if the number of first word lines is not greater than the third threshold value, by writing data to the storage cell pages in the second word line, the storage space of the first storage cell block (partially programmed block) can be better utilized under the premise of ensuring programming accuracy, thereby improving the storage space utilization rate of the first storage cell block. If the number of first word lines is greater than the third threshold value, more data has been written into the first storage cell block, and the storage space is limited, so the second storage cell block is determined to write data to the second storage cell block.

[0012] In some embodiments, the operation method further includes: in response to the number of the first word lines being not greater than a third threshold, writing invalid data to an unprogrammed memory cell page located between the programmed memory cell page and the unprogrammed memory cell page coupled to the second word line, thereby reducing the threshold voltage difference between adjacent memory cell pages, reducing charge migration, and improving data retention of the first memory cell block.

[0013] In some embodiments, the operation method further includes: in response to the number of the first word lines being greater than a third threshold, writing invalid data to an unprogrammed memory cell page in the first memory cell block, thereby making the first memory cell block a fully programmed memory cell block, reducing the threshold voltage difference between two adjacent memory cell pages coupled to different word lines, thereby reducing charge migration and improving data retention of the first memory cell block.

[0014] In some embodiments, before performing erase page detection on the first storage cell block, it also includes: determining a read voltage according to the number of erases of the first storage cell block, the number of data reads of the first storage cell block, and the placement time of the first storage cell block. Since a small increase in the threshold voltage of the storage cell in the unprogrammed storage cell page is acceptable (i.e., it is not considered to affect the accuracy of programming), adjusting the read voltage according to the number of erases, the number of data reads, and the placement time can maximize the use of the storage space of the first storage cell block while ensuring the accuracy of programming, thereby improving the space utilization of the first storage cell block.

[0015] In a second aspect, a memory controller is provided, the memory controller comprising a processor and a cache, the cache being configured to store a target parameter of a first storage unit block; the processor being configured to: determine a first storage unit block to which data is to be written in response to a data write instruction; determine whether the target parameter of the first storage unit block is greater than a first threshold; and write data to the first storage unit block in response to the target parameter of the first storage unit block being not greater than the first threshold.

[0016] In some embodiments, the processor is further configured to: in response to a target parameter of the first storage cell block being greater than a first threshold, perform erase page detection on the first storage cell block; in response to the first storage cell block passing the erase page detection, write data to the first storage cell block.

[0017] In some embodiments, the target parameter of the first storage unit block includes the number of data reads of the first storage unit block, or the target parameter of the first storage unit block includes the placement duration of the first storage unit block, and the placement duration of the first storage unit block is the time difference between the current moment and the moment when the erase operation was last performed on the first storage unit block; the cache is specifically configured to: store the number of data reads of the first storage unit block, and / or, store the placement duration of the first storage unit block.

[0018] In some embodiments, the processor is further configured to determine a first threshold based on the number of erase times of the first storage unit block.

[0019] In some embodiments, the processor determines a first threshold based on the number of times the first storage cell block is erased; and is specifically configured to: determine whether the number of times the first storage cell block is erased is greater than a second threshold; in response to the number of times the first storage cell block is erased being greater than the second threshold, determine the first threshold to be threshold a; in response to the number of times the first storage cell block is erased being not greater than the second threshold, determine the first threshold to be threshold b; threshold a is less than threshold b.

[0020] In some embodiments, the processor is further configured to: in response to the first storage cell block failing the erase page detection, determine whether the number of first word lines coupled to the programmed storage cell pages in the first storage cell block is greater than a third threshold; in response to the number of first word lines not being greater than the third threshold, write data to the unprogrammed storage cell pages coupled to the second word line in the first storage cell block; the second word line is not adjacent to the first word line; in response to the number of first word lines being greater than the third threshold, determine a second storage cell block to which data is to be written.

[0021] In some embodiments, the processor is further configured to: in response to the number of first word lines being not greater than a third threshold, write invalid data to an unprogrammed memory cell page between the programmed memory cell page and an unprogrammed memory cell page coupled to the second word line.

[0022] In some embodiments, the processor is further configured to: in response to the number of first word lines being greater than a third threshold, write invalid data to an unprogrammed memory cell page in the first memory cell block.

[0023] In some embodiments, before performing erase page detection on the first storage unit block, the processor is further configured to:

[0024] The read voltage is determined according to the number of times the first memory cell block is erased, the number of times data of the first memory cell block is read, and the placement time of the first memory cell block.

[0025] According to a third aspect, a memory system is provided, comprising a memory and a memory controller coupled to the memory; wherein the memory controller is configured to: determine a first storage unit block to which data is to be written in response to a data write instruction; determine whether a target parameter of the first storage unit block is greater than a first threshold value; in response to the target parameter of the first storage unit block being not greater than the first threshold value, send a first write command to the memory, the first write command instructing the memory to write data to the first storage unit block; the memory is configured to: write data to the first storage unit block in response to the first write command.

[0026] In some embodiments, the memory controller is further configured to: in response to a target parameter of the first storage cell block being greater than a first threshold, send a detection command to the memory, the detection command instructing the memory to perform an erase page detection on the first storage cell block; receive the detection result sent by the memory, and determine whether the first storage cell block passes the erase page detection; in response to the first storage cell block passing the erase page detection, send a first write command to the memory; the memory is also configured to: in response to the detection command, perform an erase page detection on the first storage cell block, and send the detection result to the memory controller.

[0027] In some embodiments, the memory controller is further configured to: in response to the first memory cell block failing the erase page detection, determine whether the number of first word lines coupled to the programmed memory cell pages in the first memory cell block is greater than a third threshold; in response to the number of first word lines not being greater than the third threshold, send a second write command to the memory, the second write command instructing to write data to an unprogrammed memory cell page coupled to a second word line in the first memory cell block, the second word line being not adjacent to the first word line; the memory is further configured to: in response to the second write command, write data to an unprogrammed memory cell page coupled to the second word line in the first memory cell block.

[0028] In some embodiments, the memory controller is further configured to: in response to the number of the first word lines being greater than a third threshold, determine a second storage cell block to be written with data, and send a third write command to the memory, the third write command instructing to write invalid data to an unprogrammed storage cell page in the first storage cell block; the memory is further configured to: in response to the third write command, write invalid data to an unprogrammed storage cell page in the first storage cell block

[0029] In some embodiments, the second write command also instructs writing invalid data to an unprogrammed memory cell page located between the programmed memory cell page and the unprogrammed memory cell page coupled to the second word line; the memory is also configured to: in response to the second write command, write invalid data to the unprogrammed memory cell page located between the programmed memory cells and the unprogrammed memory cell page coupled to the second word line.

[0030] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented.

[0031] In a fifth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the first aspect can be implemented.

[0032] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 A schematic diagram of the structure of a possible storage unit block provided in an embodiment of the present application;

[0035] Figure 2 A partial cross-sectional view of a possible cross-section of a memory cell string provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of the structure of another possible storage unit block provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of applying voltages to a word line and a select line for performing a read operation on a memory cell;

[0038] Figure 5 A schematic diagram of determining a reading result of performing a read operation on a storage unit;

[0039] Figure 6 A schematic diagram of a possible memory system provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the structure of a memory and peripheral circuits provided in an embodiment of the present application;

[0041] Figure 8 A schematic flow chart of a memory controller operating method in a memory system provided by an embodiment of the present application;

[0042] Fig. 9 A schematic diagram of a process of a memory in a memory system responding to a first write command provided in an embodiment of the present application;

[0043] Fig.10 A possible programming result comparison diagram of a memory in response to a first write command is provided for an embodiment of the present application;

[0044] Fig.11 Another possible programming result comparison diagram of the memory in response to the first write command is provided for the embodiment of the present application;

[0045] Fig.12 A schematic diagram of a process of a memory in a memory system according to an embodiment of the present application responding to a second write command;

[0046] Fig.13 A possible programming result comparison diagram of a memory in response to a second write command is provided for an embodiment of the present application;

[0047] Fig.14 Another programming result comparison diagram of the memory in response to the second write command is provided for the embodiment of the present application;

[0048] Fig.15 A schematic diagram of a process of a memory in a memory system according to an embodiment of the present application responding to a third write command;

[0049] Fig.16 A possible programming result comparison diagram of the memory in response to the third write command is provided for the embodiment of the present application;

[0050] Fig.17 A schematic diagram of a flow chart of a memory response detection command in a memory system provided in an embodiment of the present application;

[0051] Fig.18 A schematic diagram of the structure of a memory controller provided in an embodiment of the present application.

[0052] Figure numerals: 100, memory cell block; 110, memory cell slice; 111, memory cell string; 112, top selection transistor; 113, dummy memory cell; 114, memory cell; 115, bottom selection transistor; 216, memory cell page; 210, memory stack layer; 211, gate conductive layer; 212, dielectric layer; 220, substrate; 230, top selection line; 240, word line; 250, bottom selection line; 300, memory system; 310, memory controller; 320, memory; 400, peripheral circuit; 410, I / O interface; 420, control logic unit; 430, row decoder; 340, voltage generator; 450, page buffer; 360, column decoder; 470, data bus; 480, register; 500, memory cell array; 600, processor; 700, cache. DETAILED DESCRIPTION

[0053] The following will be combined Figure 1-Figure 18 , the technical solutions in some embodiments of the present application are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0056] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0057] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0058] Flash memory is a non-volatile memory that can be electrically erased and reprogrammed. It can include memories of both NOR and NAND architectures. This application uses NAND flash memory as an example for further explanation. A three-dimensional (3D) NAND flash memory cell array can include multiple memory cell blocks. Among them, a memory cell block in which all memory cell pages (pages) in the memory cell block have been programmed (programmed) is called a fully programmed block (close block); a memory cell block in which only the memory cell pages corresponding to some word lines in the memory cell block have been programmed (the remaining memory cell pages are not programmed) is called a partially programmed block (open block).

[0059] like Figure 1 As shown, the memory cell block 100 may include a plurality of memory cell strings 111 (strings), N memory cell strings 111 are arranged along the X-axis to form a memory cell slice 110 (also referred to as a memory cell group), and M memory cell slices 110 are arranged along the Y-axis to form a memory cell block 100; illustratively, N=5, M=4. Each memory cell string 111 may include a top select transistor 112 (top select gate, TSG), a dummy (dummy, DMY) memory cell 113, a plurality of memory cells 114, and a bottom select transistor 115 (bottom select gate, BSG) sequentially stacked in series along the Z-axis. The X-axis, the Y-axis, and the Z-axis are respectively the horizontal axis, the vertical axis, and the vertical axis of the spatial rectangular coordinate system.

[0060] In the embodiment of the present application, the storage unit 114 in the NAND flash memory may be a device capable of storing data, such as a floating gate transistor or a charge trap field effect transistor.

[0061] Figure 2A partial cross-sectional schematic diagram of a possible memory cell string 111 of the present application is shown. The memory cell string 111 may extend vertically through the memory stack layer 210 above the substrate 220. The substrate 220 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0062] The memory stack layer 210 may include alternating gate conductive layers 211 and dielectric layers 212 . The number of gate conductive layers 211 and dielectric layers 212 in the memory stack layer 210 may determine the number of memory cells 114 in the memory cell string 111 .

[0063] The gate conductive layer 211 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 211 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 211 includes a doped polysilicon layer. Each gate conductive layer 211 may include a control gate surrounding the memory cell 114, and the gate conductive layer 211 at the top of the memory stack layer 210 may extend laterally as a top select line 230 (string select line, SSL), the gate conductive layer 211 at the bottom of the memory stack layer 210 may extend laterally as a bottom select line 250 (ground select line, GSL), or the gate conductive layer 211 between the top select line 230 and the bottom select line 250 may extend laterally as a word line 240 (word line, WL).

[0064] It should be understood that although Figure 2 Not shown, but additional components of the memory cell string 111 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0065] like Figure 1 and Figure 3 As shown, for the M memory cell strings 111 in the same memory cell slice 110, the gate of the top selection transistor 112 in each memory cell string 111 is coupled to the same top selection line; the gate of the bottom selection transistor 115 in each memory cell string 111 is coupled to the same bottom selection line.

[0066] The M memory cell strings 111 in the memory cell slice 110 are coupled to the M bit lines (BL) in a one-to-one correspondence, for example, the drain of the top selection transistor 112 in the memory cell string 111 is coupled to the bit line. In order to reduce the number of bit lines, the memory cell strings 111 in the N memory cell slices 110 can share M bit lines, that is, the memory cell string 111 in any memory cell slice 110 is coupled to the same bit line as the memory cell strings 111 at corresponding positions in the other (N-1) memory cell slices 110.

[0067] For the N*M memory cell strings 111 in the N memory cell slices 110, the control gate of the memory cell 114 in any memory cell string 111 is coupled to the same word line as the control gate of the memory cell 114 at the corresponding position in the other (N*M-1) memory cell strings 111. Also, the control gate of the dummy memory cell 113 in any memory cell string 111 is coupled to the same dummy word line (DWL) as the control gate of the dummy memory cell 113 at the corresponding position in the other (N*M-1) memory cell strings 111. Among them, the memory cells 114 coupled to the same word line in a memory cell slice 110 can be referred to as a memory cell page 216 (physical page).

[0068] The sources of the bottom selection transistors 115 in the N*M memory cell strings 111 can be coupled to a common source line (CSL), which can also be called an array common source (ACS). It should be noted that the drawings of the present application only illustrate the structure of the memory 320 of some embodiments, but in practice, the structure of the memory 320 can also be in other ways. For example, the sources of the bottom selection transistors 115 in the N*M memory cell strings 111 can be similar to the drain, and the memory cell strings 111 in the N memory cell slices 110 can share M source lines, that is, the memory cell strings 111 in any memory cell slice 110 are coupled to the same source line as the memory cell strings 111 in the corresponding positions in the other (N-1) memory cell slices 110.

[0069] The memory cell page 216 is the smallest read / write unit in the memory cell block 100. Performing a read operation on the memory cell page 216 is to measure the threshold voltage Vt of all memory cells in the memory cell page 216. Because it is not easy to directly measure the threshold voltage Vt of a memory cell, and the output current of the memory cell is related to the gate voltage and the threshold voltage Vt, the threshold voltage Vt of the memory cell is determined by measuring the current.

[0070] like Figure 4As shown, when performing a read operation, the bitline (BL) coupled to the memory cell string where the memory cell to be read is located and the sensing node (SO) in the corresponding page buffer are first charged. Then, a turn-on voltage Von is applied to the selection line (e.g., SSL1, GSL1) of the memory cell string where the memory cell to be read is located, a read voltage Vread is applied to the selected word line (selected WL) coupled to the memory cell to be read, and a pass voltage Vpass is applied to the unselected word lines (unselected WL) other than the selected word line.

[0071] like Figure 5 As shown, after the sensing time Tsense, by comparing the voltage V SO The relationship between the magnitude of the sensing node Vtrip and the threshold voltage Vtrip is used to obtain the state of the storage cell. SO If the voltage Vt of the sensing node is greater than the threshold voltage Vtrip, it means that the storage cell to be read is turned off (the discharge circuit of the sensing node is turned off and the sensing node cannot discharge), that is, the threshold voltage Vt is greater than the read voltage Vread. At this time, the data "0" is read from the storage cell to be read. SO If it is smaller than the threshold voltage Vtrip, it means that the memory cell to be read is turned on (the discharge loop of the sensing node is turned on, and the sensing node is discharged), that is, the threshold voltage Vt is smaller than the read voltage Vread. At this time, data "1" is read from the memory cell to be read.

[0072] In the read operation, a strong electric field is formed between the gate and the channel of the memory cell coupled to the non-selected word line through the voltage Vpass. This electric field has a certain probability of causing the charge to enter the floating gate (or charge well) of the memory cell, thereby causing read interference (increasing the threshold voltage of the memory cell), causing the effect of weak programming on the memory cell coupled to the non-selected word line, and the accumulated weak programming may cause the data bit of the memory cell to flip. Thereby affecting the accuracy of subsequent programming of the unprogrammed memory cell page. Therefore, when programming a part of the programming block, the erase page detection can be used to determine whether the part of the programming block meets the programming conditions, and the unprogrammed memory cell page in the part of the programming block is programmed (data is written) when the programming conditions are met. However, it takes time to perform erase page detection on the part of the programming block, so it takes a long time to program the part of the programming block.

[0073] The embodiment of the present application determines the degree of influence of the interference on the unprogrammed memory cell page in the partial programming block according to the size relationship between the target parameter of the partial programming block and the preset first threshold value. When the target parameter of the partial programming block satisfies not greater than the preset first threshold value, the unprogrammed memory cell page is less affected, so that the execution of the erase page detection can be omitted and data can be written to the first memory cell block. The time required for executing the erase page detection is saved, and the time required for programming the partial programming block is reduced, so as to reduce the programming time of the memory.

[0074] like Figure 6 As shown, the embodiment of the present application provides a memory system 300, including a memory controller 310 and a memory 320, wherein the memory controller 310 is used to store data in the memory 320 or read data from the memory 320. The memory system 300 can be applied to and packaged in different types of electronic devices, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, servers, and any other electronic devices that can store data.

[0075] Of course, the memory controller 310 may also perform any other suitable functions, such as formatting the memory 320; for example, the memory controller 310 may communicate with an external device (e.g., a host) through at least one of various interface protocols. The interface protocol may include at least one of a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0076] Specifically, Figure 7As shown, the memory 320 includes a memory cell array 500 and a peripheral circuit 400 coupled to the memory cell array 500, wherein the peripheral circuit 400 is used to control the memory cell array 500; wherein the memory cell array 500 may include a plurality of Figure 1 The memory cell block 100 is shown in FIG.

[0077] like Figure 7 As shown, the peripheral circuit 400 may include an I / O interface 410, a control logic unit 420, a row decoder 430, a voltage generator 440, a page buffer 450, a column decoder 460, a data bus 470, and a register 480. It should be understood that in some examples, the peripheral circuit 400 may also include Figure 7 The memory cell array 500 may be coupled to the peripheral circuit 400 through bit lines, common source lines, top selection lines, word lines, bottom selection lines, etc.; for example, the bit lines are coupled to the page buffer 450 and the word lines are coupled to the row decoder 430.

[0078] The I / O interface 410 may be coupled to the control logic unit 420 and act as a control buffer to buffer the data from the memory controller 310 (eg, Figure 6 The I / O interface 410 may receive control commands received from the memory controller 310 in the memory cell array 500 and relay them to the control logic unit 420, and buffer status information received from the control logic unit 420 and relay them to the memory controller 310. The I / O interface 410 may also be coupled to the page buffer 450 via the data bus 470, and act as a data I / O interface 410 and a data buffer to buffer data and relay them to or from the memory cell array 500.

[0079] The control logic unit 420 may be coupled to the voltage generator 440, the page buffer 450, the column decoder 460, the row decoder 430, the I / O interface 410, etc., and is configured to control the operation of each peripheral circuit 400. The control logic unit 420 may generate an operation signal to control the operation of the row decoder 430, the column decoder 460, the page buffer 450, and the voltage generator 440 in response to a command (CMD) or a control signal from the memory controller 310; wherein the command may be a program command, a read command, etc.

[0080] The voltage generator 440 can use an external power supply voltage or an internal power supply voltage to generate various voltages for performing operations such as erasing, programming, reading and verifying on the memory cell array 500, such as a programming voltage Vpgm, a pass voltage Vpass, a read voltage Vread and a verification voltage Vvfy applied to the word line, and a programming inhibit voltage Vinhibit, a programming select voltage Vss, etc. applied to the bit line, and their combinations.

[0081] The row decoder 430 may supply the word line voltage generated from the voltage generator 440 to the selected word lines and the unselected word lines of the memory cell array 500 in response to the operation signal of the control logic unit 420. As described in detail below, the row decoder 430 is configured to perform a program operation on the memory 320 cells coupled to one or more selected word lines in the memory cell array 500.

[0082] The column decoder 460 may select one or more memory cell strings 111 in the memory cell array 500 in response to an operation signal of the control logic unit 420 .

[0083] The page buffer 450 may read data from the memory cell array 500 and program (write) data to the memory cell array 500 according to an operation signal from the control logic unit 420. In one example, the page buffer 450 may store program data (write data) to be programmed into the memory cell array 500. In another example, the page buffer 450 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 114 coupled to the selected word line. In yet another example, the page buffer 450 may also detect a low-power signal from a bit line representing a data bit stored in the memory cell 114, and amplify the small voltage to a recognizable logic level in a read operation.

[0084] The register 480 may be coupled to the control logic unit 420 and include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 400 .

[0085] Those skilled in the art should understand that the operations performed by the row decoder 430, the page buffer 450, the control logic unit 420, and the voltage generator 440 described in the present application may be performed by a processing circuit. The processing circuit may include but is not limited to hardware of a logic circuit or a hardware / software combination of a processor that executes software.

[0086] Specifically, as one implementation of the memory system of the present application, Figure 8 As shown, steps S110-S190 are executed as follows:

[0087] S110 . In response to a data write instruction sent by the host, the memory controller determines a first storage unit block into which data is to be written, that is, allocates a physical address for the data to be written.

[0088] Specifically, when the memory controller 310 performs programming operations on the memory 320, it is inevitable that a partial programming block will appear, and the partial programming block includes a programmed memory cell page and an unprogrammed memory cell page. There is almost no stored charge in the floating gates (or charge wells) of all the memory cells 114 in the unprogrammed memory cell page, and the threshold voltage is low. Therefore, in a read operation, when a pass voltage Vpass is applied to a non-selected word line, it is easier for the charge to enter the floating gate (or charge well) of the memory cell 114 in the unprogrammed memory cell page. In addition, since the charge migration occurring in the floating gate (or charge well) is an important physical mechanism that affects the stability of the data stored in the memory 320; among them, the greater the difference in the threshold voltages of two adjacent memory cells 114 in the memory cell string 111, the more serious the charge migration. Therefore, for a partially programmed block, adjacent programmed memory cell pages (high threshold voltage) and unprogrammed memory cell pages (low threshold voltage) in the same memory cell slice 110 will face more serious charge migration, resulting in poor data retention of programmed memory cell pages adjacent to unprogrammed memory cell pages. In other words, compared with a fully programmed block, a partially programmed block has worse data retention and is more susceptible to read disturbance. Thus, when determining the first memory cell block to be written with data, the memory controller 310 will prioritize the partially programmed block as the first memory cell block.

[0089] S120: The memory controller determines whether a target parameter of the first storage unit block is greater than a first threshold.

[0090] Among them, the target parameter of the first storage cell block may include the number of data reads of the first storage cell block. The memory controller 310 may send a read command to the memory 320 to read data from the programmed storage cell page in the memory 320. Each time data is read from a programmed storage cell page, read interference is generated on the unprogrammed storage cell page. When the number of data reads is greater than the preset number, the accumulated read interference may cause the data bit of the unprogrammed storage cell page to flip (for example, data "1" becomes data "0"), affecting the accuracy of subsequent programming of the unprogrammed storage cell page.

[0091] The target parameters of the first storage cell block may also include the placement duration of the first storage cell block, and the placement duration of the first storage cell block is the time difference between the current moment and the moment when the erase operation was last performed on the first storage cell block. For an unprogrammed storage cell page, charges (such as holes) migrate out of the floating gate (or charge well) of the storage cell in the unprogrammed storage cell page, which can increase the threshold voltage of the storage cell in the unprogrammed storage cell page. When the placement duration is greater than the preset duration, the accumulated amount of migrated charge may cause data bit flipping of the unprogrammed storage cell page, affecting the accuracy of subsequent programming of the unprogrammed storage cell page.

[0092] It should be understood that the present application may use any one of the data read times or the placement time (or a combination of the two) as the target parameter of the first storage unit block. That is, when the data read times is greater than a preset number of times or the placement time is greater than a preset time, it can be considered that the target parameter of the first storage unit block is greater than the first threshold.

[0093] In addition, as the number of erase times of the memory cell block 100 increases, the tunneling layer between the floating gate (or charge well) and the channel is worn more and more seriously, and the control of the charge in the floating gate (or charge well) becomes more and more difficult (i.e., read disturbance and charge migration are more likely to affect the memory cell). For an unprogrammed memory cell page, the more times it is erased, the more likely it is that data bit flipping will occur.

[0094] Therefore, in the present application, the memory controller 310 also determines the first threshold value based on the number of erase times of the first memory cell block.

[0095] Specifically, the memory controller 310 may be configured with a correspondence between the number of erasures and the first threshold value (e.g., a mapping table, a query table, or a mapping function, etc.). The greater the number of erasures, the smaller the first threshold value; illustratively, when the number of erasures of the first storage unit block is greater than the second threshold value, the memory controller 310 determines the first threshold value to be threshold value a; when the number of erasures of the first storage unit block is not greater than the second threshold value, the memory controller 310 determines the first threshold value to be threshold value b, and threshold value a is less than threshold value b.

[0096] S130: If the target parameter of the first storage unit block is not greater than the first threshold, the memory controller sends a first write command to the memory.

[0097] Among them, the first write command instructs the peripheral circuit 400 in the memory 320 to write data to the first storage cell block. That is to say, when the target parameter of the first storage cell block is not greater than the preset number of times (or the placement time of the first storage cell block is not greater than the preset time), it can be explained that the read interference (or charge migration) has little effect on the unprogrammed storage cell page, and the unprogrammed storage cell page can still meet the programming conditions; the peripheral circuit 400 in the memory 320 can ensure the accuracy of the written data when writing data to any unprogrammed storage cell page in the first storage cell block.

[0098] When writing data to a memory cell block, there may be multiple programming methods, such as programming by word line (by WL) and programming by string. The so-called programming by word line means programming the memory cell page coupled to the current word line first and then programming the memory cell page coupled to the next word line; the so-called programming by string means programming the memory cell page in the current memory cell slice 110 first and then programming the memory cell page in the next memory cell slice 110.

[0099] Take a memory cell block including two memory cell slices 110 (group 0 and group 1) and three word lines (WL0, WL1 and WL2) as an example. This example includes six memory cell pages, and each memory cell page and the corresponding number are shown in the following table:

[0100] Storage unit page Corresponding number The memory cell page in group 0 coupled to WL0 WL0 group 0 The memory cell page in group 1 coupled to WL1 WL0 group 1 The memory cell page in group 0 coupled to WL0 WL1 group 0 The memory cell page in group 1 coupled to WL1 WL1 group 1 The memory cell page in group 0 coupled to WL2 WL2 group 0 The memory cell page in group 1 coupled to WL2 WL2 group 1

[0101] The programming order of programming by word line is: WL0 group 0, WL0 group 1, WL1 group 0, WL1group1, WL2 group 0, WL2 group 1. That is, when programming by word line, if WL0 group 0 is a programmed memory cell page, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed memory cell page starting from WL0group 1. If WL0 group 0 and WL0 group 1 are programmed memory cell pages, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed memory cell page starting from WL1 group0.

[0102] The programming sequence of the string programming is: WL0 group 0, WL1 group 0, WL2 group 0, WL0 group 1, WL1 group 1, WL2 group 1. That is, when programming by string, if WL0 group 0 is a programmed memory cell page, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed memory cell page starting from WL1 group 0. If WL0 group 0 and WL1 group 0 are programmed memory cell pages, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed memory cell page starting from WL2 group 0.

[0103] This application does not limit the programming method of programming the storage unit block.

[0104] S140 . In response to a target parameter of the first storage unit block being greater than a first threshold, the memory controller sends a detection command to the memory.

[0105] Among them, the detection command instructs the peripheral circuit 400 in the memory 320 to perform an erase page detection on the first memory cell block. That is, the peripheral circuit 400 is instructed to read the data of the unprogrammed memory cell page in the first memory cell block, and the peripheral circuit 400 sends the read data (i.e., the detection result) to the memory controller 310. Under normal circumstances (unprogrammed memory cell pages meet programming conditions), all memory cells in the unprogrammed memory cell page should be in an erased state, and the data read by the peripheral circuit 400 are all data "1". Under abnormal circumstances (unprogrammed memory cell pages do not meet programming conditions), there are memory cells in the unprogrammed memory cell page that are in a programmed state, and the data read by the peripheral circuit 400 are all data "0".

[0106] S150, receiving a test result sent by the memory, and determining whether the first storage unit block passes the erase page test.

[0107] Specifically, the memory controller 310 may decode (eg, use a low density parity-check code (LDPC)) the detection result read data sent by the peripheral circuit 400, and determine whether the first storage unit block passes the erase page detection based on the result of the decoding verification.

[0108] In order to reduce the time required for erase page detection, the peripheral circuit 400 usually reads the unprogrammed memory cell page adjacent to the programmed memory cell page. That is, when programming by word line, if WL0 group 0 is a programmed memory cell page, the peripheral circuit 400 reads the data of WL0 group 1. If WL0 group 0 and WL0 group 1 are programmed memory cell pages, the peripheral circuit 400 reads the data of WL1 group 0.

[0109] Further, in other embodiments, the memory controller 310 can also determine the read voltage according to the number of erase times of the first storage cell block, the number of data read times of the first storage cell block, and the placement time of the first storage cell block. The read voltage is applied to the selection word line when performing erase page detection on the first storage cell block to read the data of the unprogrammed storage cell page in the selection word line. Specifically, the memory controller 310 is also configured with a query table for querying the read voltage. The placement time of the first storage cell block is used as an input of the query table to query the read voltage, the number of data read times of the first storage cell block can also be used as an input of the query table to query the read voltage, and the number of erase times of the first storage cell block, the number of data read times of the first storage cell block, and the placement time of the first storage cell block can also be combined as an input of the query table to query the read voltage.

[0110] S160: If the first storage unit block passes the erase page detection, the memory controller sends a first write command to the memory.

[0111] That is, the erase page detection can indicate that the unprogrammed memory cell page is in the erased state; thus, the peripheral circuit 400 in the memory 320 can ensure the accuracy of the written data when writing data to any unprogrammed memory cell page in the first memory cell block.

[0112] S170: If the first memory cell block fails the erase page detection, determine whether the number of first word lines coupled to programmed memory cell pages in the first memory cell block is greater than a third threshold.

[0113] Since when reading data, read disturbance mainly affects the memory cells in the unselected word line (with pass voltage Vpass applied) adjacent to the selected word line (with read voltage Vread applied), that is, when the unprogrammed memory cell page coupled to the third word line adjacent to the first word line fails to meet the programming condition due to data bit flipping caused by multiple read disturbances, the unprogrammed memory cell page coupled to the second word line not adjacent to the first word line can often still meet the programming condition.

[0114] S180: If the number of the first word lines is not greater than the third threshold, the memory controller sends a second write command to the memory.

[0115] The second write command instructs the peripheral circuit 400 in the memory 320 to: write data to the unprogrammed memory cell page coupled to the second word line not adjacent to the first word line; and write invalid data to the unprogrammed memory cell page located between the programmed memory cell page and the unprogrammed memory cell page coupled to the second word line. Thus, the storage space utilization rate of the first memory cell block (partially programmed block) can be improved to a certain extent, and the threshold voltage difference between adjacent memory cell pages can be reduced, charge migration can be reduced, and the data retention of the first memory cell block can be improved.

[0116] S190: If the number of the first word lines is greater than the first threshold, the memory controller determines a second storage unit block to which data is to be written, and sends a third write command to the memory.

[0117] The second storage cell block may be a completely unprogrammed storage cell block or a partially programmed block. When the second storage cell block is a partially programmed block, the process returns to step S110; when the second storage cell block is a completely unprogrammed storage cell block, the memory controller 310 may control the peripheral circuit 400 in the memory 320 to write data to the second storage cell block.

[0118] In addition, the third write command instructs the peripheral circuit 400 in the memory 320 to write invalid data to the unprogrammed memory cell page in the first memory cell block, thereby making the first memory cell block a completely programmed block (close block), reducing the threshold voltage difference between two adjacent memory cell pages, thereby reducing charge migration and improving the data retention of the first memory cell block.

[0119] like Fig. 9 As shown, the memory system provided in the embodiment of the present application further includes executing step S210.

[0120] S210 . In response to a first write command sent by a memory controller, a peripheral circuit in the memory writes data to an unprogrammed memory cell page in a first memory cell block.

[0121] Specifically, the first write command is used to instruct to write data to the unprogrammed memory cells that are also adjacent to the programmed memory cells. That is, in response to the first write command sent by the memory controller, the peripheral circuit in the memory can start writing data from the unprogrammed memory cell page that is also adjacent to the programmed memory cells in the first memory cell block.

[0122] For example, Fig.10As shown, the memory cell pages coupled to the first word line and the second word line from the bottom to the top in the first memory cell block to be programmed are all programmed memory cell pages, the memory cell pages coupled to the third word line include programmed memory cell pages and unprogrammed memory cell pages, and the memory cell pages coupled to the fourth word line and the fifth word line are all unprogrammed memory cell pages. At this time, in response to the first write command, the peripheral circuit 400 in the memory 320 writes data to the unprogrammed memory cell page coupled to the third word line, and writes data to the unprogrammed memory cell page coupled to the fourth word line.

[0123] like Fig.11 As shown, the memory cell pages coupled to the first word line from the bottom to the top in the first memory cell block to be programmed are all programmed memory cell pages, and the memory cell pages coupled to the second word line, the third word line, the fourth word line and the fifth word line are all unprogrammed memory cell pages. At this time, in response to the first write command, the peripheral circuit 400 of the memory 120 writes data to the unprogrammed memory cell page coupled to the second word line.

[0124] like Fig.12 As shown, the memory system provided in the embodiment of the present application further includes executing step S220.

[0125] S220. In response to a second write command sent by the memory controller, the peripheral circuit in the memory writes data to an unprogrammed memory cell page coupled to a second word line in the first memory cell block; and, the peripheral circuit in the memory also writes invalid data to an unprogrammed memory cell page located between the programmed memory cell page and the unprogrammed memory cell page coupled to the second word line.

[0126] Specifically, the second word line is not adjacent to the first word line; that is, at least one third word line is spaced between the first word line and the second word line, and the number of third word lines spaced between the second word line and the first word line can be configured in advance. Exemplarily, there may be one third word line spaced between the second word line and the first word line, or there may be two third word lines spaced between the second word line and the first word line. Among the multiple memory cell pages coupled to the first word line, there is at least one programmed memory cell page; the multiple memory cell pages coupled to the second word line are all unprogrammed memory cell pages; and the multiple memory cell pages coupled to the third word line are all unprogrammed memory cell pages.

[0127] That is, among the plurality of memory cell pages coupled to the first word line, all memory cell pages may be programmed memory cell pages. Fig.13As shown, the first word line from bottom to top in the first memory cell block to be programmed is the first word line, the second word line is the third word line, and the third, fourth and fifth word lines are the second word lines. Among them, all memory cell pages coupled to the first word line are programmed memory cell pages. At this time, in response to the second write command, the peripheral circuit 400 in the memory 320 writes invalid data to the memory cell page coupled to the third word line to which no data is written, and writes data to the memory cell page coupled to the second word line to which no data is written.

[0128] like Fig.14 As shown, among the multiple memory cell pages to which the first word line is coupled, some memory cell pages may be programmed memory cell pages. Fig.13 In the embodiment, the memory cell page coupled to the first word line includes a programmed memory cell page and an unprogrammed memory cell page. At this time, in response to the second write command, the peripheral circuit 400 in the memory 320 writes invalid data to the memory cell page coupled to the first word line without data written therein and to the memory cell page coupled to the third word line without data written therein, and writes data to the memory cell page coupled to the second word line without data written therein.

[0129] like Fig.15 As shown, the memory system provided in the embodiment of the present application further includes executing step S230.

[0130] S230 . In response to the third write command sent by the memory controller, the peripheral circuit in the memory writes invalid data to the unprogrammed memory cell page in the first memory cell block.

[0131] like Fig.16 As shown, the first memory cell block becomes a completely programmed block (close block), so that the threshold voltage difference between two adjacent memory cell pages is reduced, thereby reducing charge migration and improving the data retention of the first memory cell block.

[0132] like Fig.17 As shown, the memory system provided in the embodiment of the present application further includes executing step S240.

[0133] S240 . In response to the detection command, perform an erase page detection on the first storage unit block, and send the detection result to the memory controller.

[0134] It should be understood that the writing of data to the unprogrammed memory cell page coupled to the first word line (or the second word line) described in the present application is intended to indicate the starting memory cell page for writing data, and does not mean writing data only to the unprogrammed memory cell page of the first word line (or the second word line). When the data to be written requires multiple memory cell pages, the memory 320 can write data to other unprogrammed memory cell pages according to a variety of programming methods (for example, by word line programming or by string programming). Exemplarily, after all the unprogrammed memory cell pages coupled to the first word line are written with data, data can be continued to be written to the unprogrammed memory cell pages coupled to the third word line and the second word line (or after all the unprogrammed memory cell pages in the current memory cell slice 110 are written with data, data can be written to all the unprogrammed memory cell pages in the next memory cell slice 110), and data can even be continued to be written to the next memory cell block (for example, the second memory cell block).

[0135] like Fig.18 As shown, the embodiment of the present application provides a memory controller, and the memory controller 310 includes a processor 600 and a cache 700. The cache 700 can be used to cache the number of erases, the number of data reads, the placement time, and the number of first word lines of the first storage unit block. Among them, the processor 600 can perform the above steps S110-S190.

[0136] The present application also provides a computer-readable storage medium, which stores computer-executable instructions. After the computer-executable instructions are executed, each step in the above method embodiment can be implemented, such as executing Figure 8 The method shown.

[0137] The present application embodiment provides a computer device, including a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions. When the executable instructions are executed by the processor, the various steps in the above method embodiment can be implemented, such as executing Figure 8 The method shown.

[0138] The embodiments of the present application provide an operating method of a memory controller, a memory controller, and a memory system. When the target parameters of a part of the programming blocks meet a preset first threshold value or less, that is, when the unprogrammed memory cell page is less affected, the erase page detection is omitted and data is written to the first memory cell block. This saves the time required for performing the erase page detection, reduces the time required for programming the part of the programming blocks, and reduces the programming time of the memory.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and for the parts not described in detail in a certain embodiment, reference can be made to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0140] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0141] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0142] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for operating a memory controller, characterized in that: include: In response to a data write instruction, determining a first storage unit block into which data is to be written; determining whether a target parameter of the first storage unit block is greater than a first threshold; In response to the target parameter of the first storage unit block being not greater than the first threshold, writing data to the first storage unit block.

2. The operating method according to claim 1, characterized in that: The operation method also includes: In response to the target parameter of the first storage cell block being greater than the first threshold, performing erase page detection on the first storage cell block; In response to the first memory cell block passing the erase page detection, the data is written to the first memory cell block.

3. The operating method according to claim 2, characterized in that: The target parameter of the first storage unit block includes the number of data reads of the first storage unit block; or, The target parameter of the first storage unit block includes a placement duration of the first storage unit block, where the placement duration of the first storage unit block is a time difference between a current moment and a moment when an erase operation is last performed on the first storage unit block.

4. The operating method according to claim 3, characterized in that: The operation method also includes: The first threshold is determined based on the number of times the first storage unit block is erased.

5. The operating method according to claim 4, characterized in that: The determining the first threshold based on the number of times the first storage unit block is erased includes: determining whether the number of erasures of the first storage unit block is greater than a second threshold; In response to the number of erasures of the first storage unit block being greater than the second threshold, determining the first threshold to be threshold a; In response to the number of times the first storage unit block is erased being not greater than the second threshold, determining the first threshold to be a threshold b; The threshold a is smaller than the threshold b.

6. The operating method according to claim 2, characterized in that: The operation method also includes: In response to the first memory cell block failing the erase page detection, determining whether the number of first word lines coupled to programmed memory cell pages in the first memory cell block is greater than a third threshold; In response to the number of the first word lines being not greater than the third threshold, writing data to an unprogrammed memory cell page coupled to a second word line in the first memory cell block, the second word line being not adjacent to the first word line; In response to the number of the first word lines being greater than the third threshold, a second memory cell block to which data is to be written is determined.

7. The operating method according to claim 6, characterized in that: The operation method also includes: In response to the number of the first word lines being not greater than the third threshold, invalid data is written to an unprogrammed memory cell page between the programmed memory cell page and an unprogrammed memory cell page coupled to the second word line.

8. The operating method according to claim 6, characterized in that: The operation method also includes: In response to the number of the first word lines being greater than the third threshold, invalid data is written to an unprogrammed memory cell page in the first memory cell block.

9. The operating method according to any one of claims 2 to 8, characterized in that: Before performing erase page detection on the first storage unit block, the method further includes: A read voltage is determined according to the number of times the first memory cell block is erased, the number of times data of the first memory cell block is read, and the placement time of the first memory cell block.

10. A memory controller, characterized in that: The memory controller includes a processor and a cache, wherein the cache is configured to store a target parameter of a first storage unit block; and the processor is configured to: In response to a data write instruction, determining a first storage unit block into which data is to be written; determining whether a target parameter of the first storage unit block is greater than a first threshold; In response to the target parameter of the first storage unit block being not greater than the first threshold, writing data to the first storage unit block.

11. The memory controller according to claim 10, characterized in that: The processor is further configured to: In response to the target parameter of the first storage cell block being greater than the first threshold, performing erase page detection on the first storage cell block; In response to the first memory cell block passing the erase page detection, the data is written to the first memory cell block.

12. The memory controller according to claim 11, wherein: The target parameter of the first storage unit block includes the number of data reads of the first storage unit block, or the target parameter of the first storage unit block includes the placement duration of the first storage unit block, and the placement duration of the first storage unit block is the time difference between the current moment and the moment when the erase operation was last performed on the first storage unit block; the cache is configured as: The number of data reads of the first storage unit block is stored, and / or the placement time of the first storage unit block is stored.

13. The memory controller according to claim 12, wherein: The processor is further configured to: The first threshold is determined based on the number of times the first storage unit block is erased.

14. The memory controller according to claim 13, wherein: The processor determines the first threshold based on the number of erasures of the first storage unit block; and is configured to: determining whether the number of erasures of the first storage unit block is greater than a second threshold; In response to the number of erasures of the first storage unit block being greater than the second threshold, determining the first threshold to be threshold a; In response to the number of times the first storage unit block is erased being not greater than the second threshold, determining the first threshold to be a threshold b; The threshold a is smaller than the threshold b.

15. The memory controller according to claim 11, wherein: The processor is further configured to: In response to the first memory cell block failing the erase page detection, determining whether the number of first word lines coupled to programmed memory cell pages in the first memory cell block is greater than a third threshold; In response to the number of the first word lines being not greater than the third threshold, writing data to an unprogrammed memory cell page coupled to a second word line in the first memory cell block; The second word line is not adjacent to the first word line; In response to the number of the first word lines being greater than the third threshold, a second memory cell block to which data is to be written is determined.

16. The memory controller according to claim 15, characterized in that: The processor is further configured to: In response to the number of the first word lines being not greater than the third threshold, invalid data is written to an unprogrammed memory cell page between the programmed memory cell page and an unprogrammed memory cell page coupled to the second word line.

17. The memory controller according to claim 15, wherein: The processor is further configured to: In response to the number of the first word lines being greater than the third threshold, invalid data is written to an unprogrammed memory cell page in the first memory cell block.

18. The memory controller according to any one of claims 11 to 17, characterized in that: Before performing erase page detection on the first storage unit block, the processor is further configured to: A read voltage is determined according to the number of times the first memory cell block is erased, the number of times data of the first memory cell block is read, and the placement time of the first memory cell block.

19. A memory system, characterized in that: The invention comprises a memory and a memory controller coupled to the memory; wherein the memory controller is configured to: In response to a data write instruction, determining a first storage unit block into which data is to be written; determining whether a target parameter of the first storage unit block is greater than a first threshold; In response to the target parameter of the first storage unit block being not greater than the first threshold, sending a first write command to the memory, wherein the first write command instructs the memory to write data to the first storage unit block; The memory is configured as: In response to the first write command, the data is written to the first storage unit block.

20. The memory system according to claim 19, wherein: The memory controller is further configured to: In response to the target parameter of the first storage unit block being greater than the first threshold, sending a detection command to the memory, the detection command instructing the memory to perform an erase page detection on the first storage unit block; receiving a detection result sent by the memory, and determining whether the first storage unit block passes the erase page detection; In response to the first storage unit block passing the erase page detection, sending the first write command to the memory; The memory is further configured to: In response to the detection command, an erase page detection is performed on the first storage unit block, and the detection result is sent to the memory controller.

21. The memory system according to claim 20, characterized in that: The memory controller is further configured to: In response to the first memory cell block failing the erase page detection, determining whether the number of first word lines coupled to programmed memory cell pages in the first memory cell block is greater than a third threshold; In response to the number of the first word lines being not greater than the third threshold, sending a second write command to the memory, the second write command instructing to write data to an unprogrammed memory cell page coupled to a second word line in the first memory cell block, the second word line being not adjacent to the first word line; The memory is further configured to: In response to the second write command, data is written to an unprogrammed memory cell page coupled to a second word line in the first memory cell block.

22. The memory system according to claim 21, characterized in that: The memory controller is further configured to: In response to the number of the first word lines being greater than the third threshold, determining a second storage cell block to which data is to be written, and sending a third write command to the memory, wherein the third write command instructs writing invalid data to an unprogrammed storage cell page in the first storage cell block; The memory is further configured to: In response to the third write command, invalid data is written to an unprogrammed memory cell page in the first memory cell block.

23. The memory system according to claim 21, wherein: The second write command further instructs writing invalid data to an unprogrammed memory cell page located between the programmed memory cell page and the unprogrammed memory cell page coupled to the second word line; the memory is further configured to: In response to the second write command, invalid data is written to an unprogrammed memory cell page located between the programmed memory cell page and an unprogrammed memory cell page coupled to the second word line.

24. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method described in any one of claims 1 to 9 can be implemented.

25. A computer device, characterized in that: The invention comprises a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, the method according to any one of claims 1 to 9 can be implemented.

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