Operation method of memory controller, memory controller and memory system

Abstract

The invention provides an operation method of a memory controller, the memory controller and a memory system, and relates to the technical field of semiconductor chips. The operation method comprises the following steps: in response to a data writing instruction, determining a first storage unit block of to-be-written data; the first memory block comprises a programmed first memory cell page and an unprogrammed second memory cell page; determining that the first storage unit block meets a first condition, wherein the first condition is related to the reading frequency of the first storage unit page; in response to the first memory cell block satisfying a first condition, determining that the number of first word lines coupled to the first memory cell page is greater than a first threshold; in response to the fact that the number of the first word lines is not larger than a first threshold value, writing data into a second memory cell page coupled to a second word line in the first memory cell block; the second word line is not adjacent to the first word line. According to the invention, the utilization rate of the storage space of the memory can be improved on the premise of ensuring the programming accuracy.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor chip technology, and in particular, relates to an operating method of a memory controller, a memory controller and a memory system. Background Art

[0002] Non-volatile memory (such as NAND flash memory) has the advantages of low cost, high capacity and fast rewrite speed. During the use of NAND flash memory, invalid data (dummy data) will inevitably be programmed (written) into the NAND flash memory, thereby reducing the available space in the NAND flash memory. Summary of the invention

[0003] The embodiments disclosed in the present application provide an operating method of a memory controller, a memory controller and a memory system, which are used to improve the utilization rate of memory storage space.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a method for operating a memory controller is provided, the method comprising: in response to a data write instruction, determining a first storage cell block to which data is to be written; the first storage cell block comprises a programmed first storage cell page and an unprogrammed second storage cell page; determining that the first storage cell block satisfies a first condition, the first condition being related to the number of reads of the first storage cell page; in response to the first storage cell block satisfying the first condition, determining that the number of first word lines coupled to the first storage cell page is greater than a first threshold; in response to the number of first word lines being not greater than the first threshold, starting to write data from a second storage cell page coupled to a second word line in the first storage cell block; the second word line is not adjacent to the first word line.

[0006] The present application writes data to the unprogrammed memory cell page coupled to the second word line when the number of read times of the first memory cell block meets the first condition and the number of first word lines coupled to the programmed memory cell page is less than the first threshold value; the second word line is not adjacent to the first word line. Since read disturbance (read disturb) mainly affects the memory cells adjacent to the read memory cell, it has less impact on the memory cell page in the second word line. Therefore, when read disturbance has a greater impact on the second memory cell page coupled to the word line adjacent to the first word line, writing data to the memory cell page in the second word line can better utilize the storage space of the first memory cell block (partial programming block) under the premise of ensuring programming accuracy, improve the storage space utilization rate of the first memory cell block, and thus improve the storage space utilization rate of the memory.

[0007] In some embodiments, the operation method further includes: in response to the first storage cell block not satisfying the first condition, writing data to the second storage cell page. When the first storage cell block does not satisfy the first condition, the read disturbance has a small impact on all the second storage cell pages, and writing data to all the second storage cell pages in the first storage cell block can also ensure programming accuracy.

[0008] In some embodiments, the operation method further includes: in response to the number of the first word lines being greater than a first threshold, determining a second storage cell block to be written with data. When the number of the first word lines is greater than the first threshold, the first storage cell block is no longer suitable for writing data, and therefore determining a second storage cell block to write data to the second storage cell block.

[0009] In some embodiments, the method further includes: writing invalid data to a memory cell page located between a first memory cell page coupled to a first word line and a second memory cell page coupled to a second word line, thereby reducing the threshold voltage difference between adjacent memory cell pages, reducing charge migration, and improving data retention of the first memory cell block.

[0010] In some embodiments, the method further includes: writing invalid data to the second memory cell page in the first memory cell block, so that the first memory cell block becomes a fully programmed block, and the threshold voltage difference between the first memory cell page and the adjacent memory cell page is reduced, thereby reducing charge migration and improving data retention of the first memory cell block.

[0011] In some embodiments, determining that the first storage cell block satisfies the first condition specifically includes: obtaining the number of reads of each first word line, the number of reads of each first word line being the sum of the number of reads of multiple first storage cell pages coupled to the first word line; and determining that there is at least one first word line with a number of reads greater than a second threshold. Determining the number of reads of each first word line individually, to a certain extent, avoids the first storage cell page in a single first word line from being read multiple times, while the second storage cell page coupled to the word line adjacent to the first word line is weakly programmed multiple times, causing the second storage cell data bit to flip.

[0012] In some embodiments, determining that the first storage cell block satisfies the first condition specifically includes: obtaining the number of reads of the first storage cell block; obtaining an average number of reads of the first word line in the first storage cell block according to the number of reads of the first storage cell block, and determining that the average number of reads is greater than a second threshold. Since there are multiple first word lines in the first storage cell block, the cost and complexity of recording the number of reads of each first word line is lower than recording the number of reads of each first word line separately.

[0013] In some embodiments, the method further includes: determining that the number of reads of the first storage cell block is greater than a third threshold; in response to the number of reads of the first storage cell block being not greater than the third threshold, writing data to the second storage cell page; in response to the number of reads of the first storage cell block being greater than the third threshold, determining that the first storage cell block satisfies the first condition. When the number of reads of the first storage cell block is not greater than the third threshold, the read disturbance has only a minimal effect on all the second storage cell pages, and at this time, writing data to all the second storage cell pages in the first storage cell block can also ensure programming accuracy.

[0014] In a second aspect, a memory controller is provided, the memory controller comprising a processor and a back-end interface coupled to the processor; the processor is configured to: determine a first storage cell block to which data is to be written in response to a data write instruction; the first storage block comprises a programmed first storage cell page and an unprogrammed second storage cell page; determine that the first storage cell block satisfies a first condition, the first condition being related to the number of reads of the first storage cell page; in response to the first storage cell block satisfying the first condition, determine that the number of first word lines coupled to the first storage cell page is greater than a first threshold; in response to the number of first word lines not being greater than the first threshold, control the back-end interface to send a write command to the memory, instructing to start writing data from a second storage cell page coupled to a second word line in the first storage cell block; the second word line is not adjacent to the first word line.

[0015] In some embodiments, the processor is further configured to: in response to the first storage unit block not satisfying the first condition, control the back-end interface to send a second write command to the memory, instructing to write data to the second storage unit page.

[0016] In some embodiments, the processor is further configured to: in response to the number of the first word lines being greater than a first threshold, determine a second storage cell block to which data is to be written.

[0017] In some embodiments, the processor is configured to control the back-end interface to send the first write command to the memory, and also instruct to write invalid data to a storage cell page located between a first storage cell page coupled to a first word line and a second storage cell page coupled to a second word line.

[0018] In some embodiments, the processor is configured to determine a second storage unit block to which data is to be written, and further includes: controlling the back-end interface to send a third write command to the memory, instructing to write invalid data to the second storage unit page in the first storage unit block.

[0019] In some embodiments, the memory controller also includes a first cache unit, which is used to cache the number of reads of each first word line, and the number of reads of the first word line is the sum of the number of reads of multiple first storage cell pages coupled to the first word line; to determine that the first storage cell block satisfies the first condition, the processor is configured to: obtain the number of reads of each first word line from the first cache unit; and determine that there is at least one first word line with a read count greater than a second threshold.

[0020] In some embodiments, the memory controller also includes a second cache unit, which is used to cache the number of read times of the first storage cell block; when it is determined that the first storage cell block satisfies the first condition, the processor is configured to: obtain the number of read times of the first storage cell block from the second cache unit; average the number of read times of the first storage cell block to a single first word line, obtain an average number of read times in the first storage cell block, and determine that the average number of read times is greater than a second threshold.

[0021] In some embodiments, the processor is further configured to: in response to a data write instruction, determine that the number of read times of the first storage cell block is greater than a third threshold; in response to the number of read times of the first storage cell block being not greater than the third threshold, start writing data to the storage cells coupled to the first word line to which no data has been written; in response to the number of read times of the first storage cell block being greater than the third threshold, determine that the first storage cell block satisfies the first condition.

[0022] According to a third aspect, a memory system is provided, comprising a memory and a memory controller, wherein the memory controller is coupled to the memory; the memory controller is configured to: determine a first storage cell block to which data is to be written in response to a data write instruction; the first storage block comprises a programmed first storage cell page and an unprogrammed second storage cell page; determine that the first storage cell block satisfies a first condition, wherein the first condition is related to the number of reads of the first storage cell page; in response to the first storage cell block satisfying the first condition, determine that the number of first word lines coupled to the first storage cell page is greater than a first threshold; in response to the number of first word lines not being greater than the first threshold, send a first write command to the memory, wherein the first write command indicates that data is to be written starting from a second storage cell page coupled to a second word line in the first storage cell block; the second word line is not adjacent to the first word line; the memory is configured to: write data starting from a second storage cell page coupled to a second word line in the first storage cell block in response to the first write command.

[0023] In some embodiments, the memory is further configured to: in response to the first write command, write invalid data to a memory cell page located between a first memory cell page coupled to the first word line and a second memory cell page coupled to the second word line.

[0024] In some embodiments, the memory controller is configured to: in response to the first storage unit block not satisfying the first condition, send a second write command to the memory, the second write command instructing to write data to the second storage unit page; the memory is also configured to: in response to the second write command, write data to the second storage unit page.

[0025] In some embodiments, the memory controller is further configured to: in response to the number of first word lines being greater than a first threshold, determine a second storage cell block to which data is to be written, and send a third write command to the memory, the third write command instructing to write invalid data to the second storage cell page in the first storage cell block; the memory is also configured to: in response to the third write command, write invalid data to the second storage cell page in the first storage cell block.

[0026] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented.

[0027] In a fifth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the first aspect can be implemented.

[0028] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1 A schematic diagram of the structure of a possible storage unit block provided in an embodiment of the present application;

[0031] Figure 2 A partial cross-sectional view of a possible cross-section of a memory cell string provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the structure of another possible storage unit block provided in an embodiment of the present application;

[0033] Figure 4A schematic diagram of applying voltages to a word line and a select line for performing a read operation on a memory cell;

[0034] Figure 5 A schematic diagram of determining a reading result of performing a read operation on a storage unit;

[0035] Figure 6 A schematic diagram of a memory system provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of a memory and peripheral circuits provided in an embodiment of the present application;

[0037] Figure 8 A schematic flow chart of a memory controller operation method in a memory system provided by an embodiment of the present application;

[0038] Fig. 9 A specific flow chart of step S120 provided in an embodiment of the present application;

[0039] Fig.10 Another specific flow chart of step S120 provided in the embodiment of the present application;

[0040] Fig.11 A schematic flow chart of another memory controller operation method in the memory system provided by an embodiment of the present application;

[0041] Fig.12 A schematic diagram of a process of a memory in a memory system responding to a first write command provided in an embodiment of the present application;

[0042] Fig.13 A programming result comparison diagram of a memory in response to a first write command is provided for an embodiment of the present application;

[0043] Fig.14 Another programming result comparison diagram of a memory in response to a first write command is provided for an embodiment of the present application;

[0044] Fig.15 A schematic diagram of a process of a memory in a memory system according to an embodiment of the present application responding to a second write command;

[0045] Fig.16 A programming result comparison diagram of a memory in response to a second write command is provided for an embodiment of the present application;

[0046] Fig.17 Another programming result comparison diagram of the memory in response to the second write command is provided for the embodiment of the present application;

[0047] Fig.18A schematic diagram of a process of a memory in a memory system according to an embodiment of the present application responding to a third write command;

[0048] Fig.19 A programming result comparison diagram of a memory in response to a third write command is provided for an embodiment of the present application;

[0049] Fig. 20 A schematic diagram of the structure of a memory controller provided in an embodiment of the present application.

[0050] 1. Reference numerals: 100, memory cell block; 110, memory cell slice; 111, memory cell string; 112, top selection transistor; 113, dummy memory cell; 114, memory cell; 115, bottom selection transistor; 210, memory stack layer; 211, gate conductive layer; 212, dielectric layer; 220, substrate; 230, top selection line; 240, word line; 250, bottom selection 300, memory system; 310, memory controller; 320, memory; 400, peripheral circuit; 410, I / O interface; 420, control logic unit; 430, row decoder; 440, voltage generator; 450, page buffer; 460, column decoder; 470, data bus; 480, register; 500, memory cell array; 600, processor; 700, back-end interface; 800, cache module; 810, first cache unit; 820, second cache unit. DETAILED DESCRIPTION

[0051] The following will be combined Figure 1-Figure 20 , the technical solutions in some embodiments of the present application are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Flash memory is a non-volatile memory that can be electrically erased and reprogrammed. It can include memories of both NOR and NAND architectures. This application uses NAND flash memory as an example for further explanation. The memory cell array of a three-dimensional (3D) NAND flash memory may include multiple memory cell blocks. A memory cell block in which all memory cell pages (pages) in the memory cell block have been programmed (programmed) is called a fully programmed block (closeblock); a memory cell block in which only the memory cell pages corresponding to some word lines in the memory cell block have been programmed (the remaining memory cell pages have not been programmed) is called a partially programmed block (open block).

[0057] like Figure 1 As shown, the memory cell block 100 may include a plurality of memory cell strings 111 (strings), N memory cell strings 111 are arranged along the X-axis to form a memory cell slice 110 (also referred to as a memory cell group), and M memory cell slices 110 are arranged along the Y-axis to form a memory cell block 100; illustratively, N=5, M=4. Each memory cell string 111 may include a top select transistor 112 (top select gate, TSG), a dummy (dummy, DMY) memory cell 113, a plurality of memory cells 114, and a bottom select transistor 115 (bottom select gate, BSG) sequentially stacked in series along the Z-axis. The X-axis, the Y-axis, and the Z-axis are respectively the horizontal axis, the vertical axis, and the vertical axis of the spatial rectangular coordinate system.

[0058] In the embodiment of the present application, the storage unit in the NAND flash memory may be a floating gate transistor or a charge trap field effect transistor or the like that can store data.

[0059] Figure 2 A partial cross-sectional schematic diagram of a possible memory cell string 111 of the present application is shown. The memory cell string 111 may extend vertically through the memory stack layer 210 above the substrate 220. The substrate 220 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0060] The memory stack layer 210 may include alternating gate conductive layers 211 and dielectric layers 212 . The number of gate conductive layers 211 and dielectric layers 212 in the memory stack layer 210 may determine the number of memory cells 114 in the memory cell string 111 .

[0061] The gate conductive layer 211 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 211 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 211 includes a doped polysilicon layer. Each gate conductive layer 211 may include a control gate surrounding the memory cell 114, and the gate conductive layer 211 at the top of the memory stack layer 210 may extend laterally as a top select line 230 (string select line, SSL), the gate conductive layer 211 at the bottom of the memory stack layer 210 may extend laterally as a bottom select line 250 (ground select line, GSL), or the gate conductive layer 211 between the top select line 230 and the bottom select line 250 may extend laterally as a word line 240 (word line, WL).

[0062] It should be understood that although Figure 2 Not shown, but additional components of the memory cell array 500 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0063] like Figure 1 and Figure 3As shown, for the M memory cell strings 111 in the same memory cell slice 110, the gate of the top selection transistor 112 in each memory cell string 111 is coupled to the same top selection line; the gate of the bottom selection transistor 115 in each memory cell string 111 is coupled to the same bottom selection line.

[0064] The M memory cell strings 111 in the memory cell slice 110 are coupled to the M bit lines (BL) in a one-to-one correspondence, for example, the drain of the top selection transistor 112 in the memory cell string 111 is coupled to the bit line. In order to reduce the number of bit lines, the memory cell strings 111 in the N memory cell slices 110 can share M bit lines, that is, the memory cell string 111 in any memory cell slice 110 is coupled to the same bit line as the memory cell strings 111 at corresponding positions in the other (N-1) memory cell slices 110.

[0065] For the N*M memory cell strings 111 in the N memory cell slices 110, the control gate of the memory cell 114 in any memory cell string 111 is coupled to the same word line as the control gate of the memory cell 114 at the corresponding position in the other (N*M-1) memory cell strings 111. Also, the control gate of the dummy memory cell 113 in any memory cell string 111 is coupled to the same dummy word line (DWL) as the control gate of the dummy memory cell 113 at the corresponding position in the other (N*M-1) memory cell strings 111. Among them, the memory cells 114 coupled to the same word line in a memory cell slice 110 can be referred to as a memory cell page 216 (physical page).

[0066] The source of the bottom selection transistor 115 in the N*M memory cell strings 111 can be coupled to a common source line (CSL), which can also be called an array common source (ACS). It should be noted that the drawings of the present application only illustrate the structure of the memory of some embodiments, but in practice, the structure of the memory can also be other ways. For example, the source of the bottom selection transistor 115 in the N*M memory cell strings 111 can be similar to the drain, and the memory cell strings 111 in the N memory cell slices 110 can share M source lines, that is, the memory cell string 111 in any memory cell slice 110 is coupled to the same source line as the memory cell string 111 in the corresponding position in the other (N-1) memory cell slices 110.

[0067] The memory cell page is the smallest unit of read / write in the memory cell block 100.

[0068] The (read) operation is to measure the threshold voltage Vt of all memory cells 114 in the memory cell page. Because it is not easy to directly measure the threshold voltage Vt of the memory cell, and the output current of the memory cell is related to the gate voltage and the threshold voltage Vt, the threshold voltage Vt of the memory cell is determined by measuring the current.

[0069] like Figure 4 As shown, when performing a read operation, the bitline (BL) coupled to the memory cell string where the memory cell to be read is located and the sensing node (SO) in the corresponding page buffer are first charged. Then, a turn-on voltage Von is applied to the selection line of the memory cell string where the memory cell to be read is located, a read voltage Vread is applied to the selected word line (selected WL) coupled to the memory cell to be read, and a pass voltage Vpass is applied to the unselected word lines (unselected WL) other than the selected word line.

[0070] like Figure 5 As shown, after the sensing time Tsense, by comparing the voltage V SO The relationship between the magnitude of the threshold voltage Vtrip and the state of the memory cell can be obtained. For example, if the voltage V SO If the voltage Vt of the sensing node is greater than the threshold voltage Vtrip, it means that the storage cell to be read is turned off (the discharge circuit of the sensing node is turned off and the sensing node cannot discharge), that is, the threshold voltage Vt is greater than the read voltage Vread. At this time, the data "0" is read from the storage cell to be read. SO If it is smaller than the threshold voltage Vtrip, it means that the memory cell to be read is turned on (the discharge loop of the sensing node is turned on, and the sensing node is discharged), that is, the threshold voltage Vt is smaller than the read voltage Vread. At this time, data "1" is read from the memory cell to be read.

[0071] When a partial programming block is read, a strong electric field is formed between the gate and the channel of the memory cell coupled to the non-selected word line through the voltage Vpass. This electric field has a certain probability of causing the charge to enter the floating gate (or charge well) of the memory cell, thereby causing read interference (increasing the threshold voltage of the memory cell), causing a weak programming effect on the memory cell coupled to the non-selected word line, and the accumulated weak programming may cause the data bit of the memory cell to flip. Thereby affecting the accuracy of subsequent programming of the unprogrammed memory cell page. Therefore, when programming a partial programming block, it can be determined by a read operation whether the currently unprogrammed memory cell page meets the programming conditions; when it is found that the programming conditions are not met, invalid data (dummy date) is programmed (written) to the unprogrammed memory cell page in the entire partial programming block. However, programming invalid data to the unprogrammed memory cell page in the entire partial programming block reduces the low storage space utilization of the partial programming block to a certain extent.

[0072] The embodiment of the present application reflects the influence of read interference on the unprogrammed memory cell page according to the number of reads of the partially programmed block. When the number of reads of the partially programmed block meets the first condition and the number of first word lines coupled to the programmed memory cell page is less than the first threshold, data is written to the unprogrammed memory cell page coupled to the second word line; the second word line is not adjacent to the first word line. Since the read interference mainly affects the memory cells adjacent to the read memory cell. Therefore, when the currently unprogrammed memory cell page does not meet the programming condition, writing data to the memory cell page in the second word line that is not adjacent to the first word line can better utilize the storage space of the partially programmed block while ensuring the programming accuracy, thereby improving the storage space utilization rate of the partially programmed block and thus improving the storage space utilization rate of the memory.

[0073] like Figure 6 As shown, the embodiment of the present application provides a memory system 300, including a memory controller 310 and a memory 320, wherein the memory controller 310 is used to store data in the memory 320 or read data from the memory 320. The memory system 300 can be applied to and packaged in different types of electronic devices, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, servers, and any other electronic devices that can store data.

[0074] Of course, the memory controller 310 may also perform any other suitable functions, such as formatting the memory 320; for example, the memory controller 310 may communicate with an external device (e.g., a host) through at least one of various interface protocols. The interface protocol may include at least one of a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0075] Specifically, Figure 7 As shown, the memory 320 includes a memory cell array 500 and a peripheral circuit 400 coupled to the memory cell array 500, wherein the peripheral circuit 400 is used to control the memory cell array 500; wherein the memory cell array 500 may include Figure 1 A plurality of memory cell blocks 100 are shown.

[0076] like Figure 7 As shown, the peripheral circuit 400 may include an I / O interface 410, a control logic unit 420, a row decoder 430, a voltage generator 440, a page buffer 450, a column decoder 460, a data bus 470, and a register 480. It should be understood that in some examples, the peripheral circuit 400 may also include Figure 7 The memory cell array 500 may be coupled to the peripheral circuit 400 through bit lines, common source lines, top selection lines, word lines, bottom selection lines, etc.; for example, the bit lines are coupled to the page buffer 450 and the word lines are coupled to the row decoder 430.

[0077] The I / O interface 410 may be coupled to the control logic unit 420 and act as a control buffer to buffer the data from the memory controller 310 (eg, Figure 6The I / O interface 410 may receive control commands received from the memory controller 310 in the memory cell array 500 and relay them to the control logic unit 420, and buffer status information received from the control logic unit 420 and relay them to the memory controller 310. The I / O interface 410 may also be coupled to the page buffer 450 via the data bus 470, and act as a data I / O interface 410 and a data buffer to buffer data and relay them to or from the memory cell array 500.

[0078] The control logic unit 420 may be coupled to the voltage generator 440, the page buffer 450, the column decoder 460, the row decoder 430, the I / O interface 410, etc., and is configured to control the operation of each peripheral circuit 400. The control logic unit 420 may generate an operation signal to control the operation of the row decoder 430, the column decoder 460, the page buffer 450, and the voltage generator 440 in response to a command (CMD) or a control signal from the memory controller 310; wherein the command may be a program command, a read command, etc.

[0079] The voltage generator 440 can use an external power supply voltage or an internal power supply voltage to generate various voltages for performing operations such as erasing, programming, reading and verifying on the memory cell array 500, such as a programming voltage Vpgm, a pass voltage Vpass, a read voltage Vread and a verification voltage Vvfy applied to the word line, and a programming inhibit voltage Vinhibit, a programming select voltage Vss, etc. applied to the bit line, and their combinations.

[0080] The row decoder 430 may supply the word line voltage generated from the voltage generator 440 to the selected word lines and the unselected word lines of the memory cell array 500 in response to the operation signal of the control logic unit 420. As described in detail below, the row decoder 430 is configured to perform a program operation on the memory 320 cells coupled to one or more selected word lines in the memory cell array 500.

[0081] The column decoder 460 may select one or more memory cell strings 111 in the memory cell array 500 in response to an operation signal of the control logic unit 420 .

[0082] The page buffer 450 may read data from the memory cell array 500 and program (write) data to the memory cell array 500 according to an operation signal from the control logic unit 420. In one example, the page buffer 450 may store program data (write data) to be programmed into the memory cell array 500. In another example, the page buffer 450 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 114 coupled to the selected word line. In yet another example, the page buffer 450 may also detect a low-power signal from a bit line representing a data bit stored in the memory cell 114, and amplify the small voltage to a recognizable logic level in a read operation.

[0083] The register 480 may be coupled to the control logic unit 420 and include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 400 .

[0084] Those skilled in the art should understand that the operations performed by the row decoder 430, the page buffer 450, the control logic unit 420, and the voltage generator 440 described in the present application may be performed by a processing circuit. The processing circuit may include but is not limited to hardware of a logic circuit or a hardware / software combination of a processor that executes software.

[0085] Specifically, as one implementation of the memory system of the present application, Figure 8 As shown, steps S110-S160 are executed as follows.

[0086] S110 . In response to a data write instruction sent by the host, the memory controller determines a first storage unit block into which data is to be written, that is, allocates a physical address for the data to be written.

[0087] Specifically, when the memory controller 310 performs programming operations on the memory 320, a partial programming block will inevitably appear, and the partial programming block includes a programmed first memory cell page and an unprogrammed second memory cell page. There is almost no stored charge in the floating gates (or charge wells) of all memory cells 114 in the unprogrammed second memory cell page, and the threshold voltage is low. Therefore, in a read operation, when a pass voltage Vpass is applied to a non-selected word line, it is easier for the charge to enter the floating gate (or charge well) of the memory cell 114 in the unprogrammed second memory cell page. In addition, since the charge migration occurring in the floating gate (or charge well) is an important physical mechanism that affects the stability of the data stored in the memory 320; wherein, the greater the difference in the threshold voltages of two adjacent memory cells 114 in the memory cell string 111, the more serious the charge migration. Therefore, for a partially programmed block, the adjacent programmed first memory cell page (high threshold voltage) and the unprogrammed second memory cell page (low threshold voltage) in the same memory cell slice 110 will face more serious charge migration, making the data retention of the programmed first memory cell page adjacent to the unprogrammed second memory cell page poor. In other words, compared with a fully programmed block, the data retention of the partially programmed block is worse and more susceptible to read disturbance. Therefore, when determining the first memory cell block to be written with data, the memory controller 310 will give priority to the partially programmed block as the first memory cell block.

[0088] S120: The memory controller determines whether the first storage unit block satisfies a first condition.

[0089] It should be understood that the memory controller 310 can send a read command to the memory 320 to read data from the programmed first memory cell page in the memory 320. In addition, each time data is read from the programmed first memory cell page, read interference will be generated. The read interference will weakly program the unprogrammed second memory cell page, affecting the accuracy of subsequent programming of the unprogrammed second memory cell page. Therefore, after determining the first memory cell block, the memory controller 310 needs to determine whether the first memory cell block meets the first condition; wherein the first condition is related to the number of reads of the programmed first memory cell page, and the more reads, the more serious the weak programming caused by the read interference. When the unprogrammed second memory cell page has data bit flipping due to multiple weak programming, programming the unprogrammed second memory cell page cannot guarantee the accuracy of programming. Fig. 9 and Fig.10 As shown, the present application exemplarily provides two methods to determine whether the first storage unit block satisfies the first condition, that is, executing step S320 may include executing sub-steps S121-S122 or executing sub-steps S123-S125.

[0090] S121 . The memory controller obtains the number of reads of each first word line.

[0091] Specifically, in a logical to physical address mapping table (hereinafter referred to as "L2P table"), the physical address generally includes the number of the storage cell block 100 and the number of the storage cell page in the storage cell block 100. When recording the number of reads of each first word line, the memory controller 310 converts the number of reads of the programmed first storage cell page into the number of reads of multiple programmed first storage cell pages coupled to the first word line according to the L2P table, that is, the number of reads of each first word line is the sum of the number of reads of multiple programmed first storage cell pages coupled to the first word line.

[0092] S122: The memory controller determines whether there is at least one first word line whose number of read times is greater than a second threshold.

[0093] Specifically, there may be multiple first word lines in the first storage cell block, and the memory controller 310 separately records the number of read times of each first word line. As long as there is at least one first word line with a read time greater than the second threshold, it can be considered that the first storage cell block meets the first condition; wherein, the second threshold can be configured according to the product model of the memory 320 and historical experience.

[0094] S123: The memory controller obtains the number of read times of the first storage unit block.

[0095] That is, the memory controller 310 records the number of reads of the first storage unit block as a whole.

[0096] S124. The memory controller obtains an average number of read times of the first word line according to the number of read times of the first storage unit block.

[0097] S125: The memory controller determines that the average number of read times is greater than a second threshold.

[0098] When the average number of read times is greater than the second threshold, it can be considered that the first storage unit block meets the first condition.

[0099] It should be noted that in the above sub-steps S121-S122 and sub-steps S123-S125, whether the first storage cell block meets the first condition is determined based on the number of reads of the first word line coupled to multiple programmed first storage cell pages. It should be understood that for a memory 320 of a certain model, the number of storage cell pages coupled on each word line is determined. Therefore, the memory controller 310 can also determine whether the first storage cell block meets the first condition based on the number of reads of the programmed first storage cell page. In other words, the memory controller 310 can average the number of reads of the first storage cell block to the average value of a single programmed first storage cell page as the number of reads of the programmed first storage cell page; or, the memory controller 310 can also record the number of reads of a single programmed first storage cell page. The memory controller 310 determines whether the first storage cell block meets the first condition by judging the relationship between the number of reads of the programmed first storage cell page and the preset threshold.

[0100] S130: If the first storage unit block does not satisfy the first condition, the memory controller sends a second write command to the memory.

[0101] That is, when the first storage cell block does not meet the first condition, it can be explained that the number of reads of the first word line coupled to the plurality of programmed first storage cell pages (or the number of reads of the programmed first storage cell page) is small, and the influence of the read disturbance on the unprogrammed second storage cell page is not enough to make the unprogrammed second storage cell page fail to meet the programming condition. The second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed second storage cell page.

[0102] When writing data to a memory cell block 100, there may be multiple programming methods, such as programming by word line (by WL) and programming by string. The so-called programming by word line means programming the memory cell page coupled to the current word line first and then programming the memory cell page coupled to the next word line; the so-called programming by string means programming the memory cell page in the current memory cell slice 110 first and then programming the memory cell page in the next memory cell slice 110.

[0103] Take a memory cell block 100 including two memory cell slices 110 (group 0 and group 1) and three word lines (WL0, WL1 and WL2) as an example. This example includes six memory cell pages, and each memory cell page and the corresponding number are shown in the following table:

[0104] Storage unit page Corresponding number The memory cell page in group 0 coupled to WL0 WL0 group 0 The memory cell page in group 1 coupled to WL1 WL0 group 1 The memory cell page in group 0 coupled to WL0 WL1 group 0 The memory cell page in group 1 coupled to WL1 WL1 group 1 The memory cell page in group 0 coupled to WL2 WL2 group 0 The memory cell page in group 1 coupled to WL2 WL2 group 1

[0105] The programming order of programming by word line is: WL0 group 0, WL0 group 1, WL1 group 0, WL1group1, WL2 group 0, WL2 group 1. That is, when programming by word line, if WL0 group 0 is the programmed first memory cell page, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed second memory cell page starting from WL0 group 1. If WL0 group 0 and WL0group 1 are the programmed first memory cell pages, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed second memory cell page starting from WL1 group 0.

[0106] The programming sequence of the string programming is: WL0 group 0, WL1 group 0, WL2 group 0, WL0 group1, WL1 group 1, WL2 group 1. That is, when programming by string, if WL0 group 0 is the programmed first memory cell page, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed second memory cell page starting from WL1 group 0. If WL0 group 0 and WL1 group0 are the programmed first memory cell pages, the second write command instructs the peripheral circuit 400 in the memory 320 to write data to the unprogrammed second memory cell page starting from WL2 group 0.

[0107] The present application does not limit the programming method of programming the memory cell block 100 .

[0108] S140: If the first storage unit block meets the first condition, the memory controller determines whether the number of first word lines is greater than a first threshold.

[0109] That is, if the number of reads of the first word lines coupled to the plurality of programmed first memory cell pages is greater than the read number threshold, the memory controller 310 determines whether the number of first word lines coupled to the programmed first memory cell pages is greater than the first threshold. The first threshold can be configured according to the product model of the memory 320 combined with historical experience.

[0110] S150: If the number of the first word lines is not greater than the first threshold, the memory controller sends a first write command to the memory.

[0111] Among them, the first write command instructs the peripheral circuit 400 in the memory 320 to write data from the second storage cell page coupled to the second word line not adjacent to the first word line, and writes invalid data to the storage cell page located between the first storage cell page coupled to the first word line and the second storage cell page coupled to the second word line. Because when reading data, the read interference mainly affects the storage cells in the unselected word line (applying the pass voltage Vpass) adjacent to the selected word line (applying the read voltage Vread). That is to say, when the second storage cell page coupled to the third word line adjacent to the first word line does not meet the programming condition due to multiple read interferences, the second storage cell page coupled to the second word line not adjacent to the first word line can often still meet the programming condition. Therefore, the storage space utilization rate of the first storage cell block (partial programming block) can be improved to a certain extent, thereby improving the utilization rate of the storage space of the memory. At the same time, the threshold voltage difference between adjacent storage cell pages can be reduced, the charge migration can be reduced, and the data retention of the first storage cell block can be improved.

[0112] S160: If the number of the first word lines is greater than the first threshold, the memory controller determines a second storage unit block to which data is to be written, and sends a third write command to the memory.

[0113] The second storage cell block may be a storage cell block to which no data is written, or may be a partially programmed block. When the second storage cell block is a partially programmed block, the process returns to step S110; when the second storage cell block is a storage cell block to which no data is written, the memory controller 310 may control the peripheral circuit 400 in the memory 320 to write data to the second storage cell block.

[0114] In addition, the third write command instructs the peripheral circuit 400 in the memory 320 to write invalid data to the second memory cell page in the first memory cell block, thereby making the first memory cell block a completely programmed block (close block), reducing the threshold voltage difference between the first memory cell page and the adjacent memory cell page, thereby reducing charge migration and improving the data retention of the first memory cell block.

[0115] like Fig.11 As shown, the embodiment of the present application provides another method for operating a memory controller, and the method may include steps S210-S280. Among them, step S210 and Figure 8 The step S110 is the same as shown, and the steps S240-S280 are the same as Figure 8 The steps S120-S160 shown are the same and will not be described in detail in this application.

[0116] S220: The memory controller determines whether the number of read times of the first storage unit block is greater than a third threshold.

[0117] The third threshold value may be configured according to the product model of the memory 320 in combination with historical experience.

[0118] S230: If the number of read times of the first storage unit block is not greater than a third threshold, the memory controller sends a second write command to the memory.

[0119] Similarly, when the number of reads of the first memory cell block is not greater than the third threshold, the effect of the read disturbance on the second memory cell page is far from sufficient to make the second memory cell page fail to meet the programming condition. Therefore, the memory controller 310 can send a second write command to the memory 320 to instruct the peripheral circuit 400 in the memory 320 to write data to the unprogrammed second memory cell page.

[0120] like Fig.12 As shown, the memory system provided in the embodiment of the present application further includes executing step S310.

[0121] S310. In response to a first write command sent by a memory controller, the peripheral circuit in the memory starts writing data from an unprogrammed second memory cell page coupled to a second word line in a first memory cell block; and, the peripheral circuit in the memory also writes invalid data to a memory cell page located between the unprogrammed first memory cell page coupled to the first word line and the unprogrammed second memory cell page coupled to the second word line.

[0122] Specifically, the second word line is not adjacent to the first word line, that is, at least one third word line is spaced between the first word line and the second word line, and the number of third word lines spaced between the second word line and the first word line can be configured in advance. Exemplarily, there may be one third word line spaced between the second word line and the first word line, or there may be two third word lines spaced between the second word line and the first word line. Among the multiple memory cell pages coupled to the first word line, there is at least one programmed first memory cell page; the multiple memory cell pages coupled to the second word line are all unprogrammed second memory cell pages; and the multiple memory cell pages coupled to the third word line are all unprogrammed second memory cell pages.

[0123] like Fig.13 As shown, that is, among the multiple memory cell pages coupled to the first word line, all memory cell pages may be the first memory cell page that has been programmed. At this time, in response to the first write command, the peripheral circuit 400 in the memory 320 writes invalid data to the second memory cell page coupled to the third word line and to which no data has been written.

[0124] like Fig.14As shown, among the multiple memory cell pages coupled to the first word line, some memory cell pages may be the first memory cell page that has been programmed. At this time, in response to the first write command, the peripheral circuit 400 in the memory 320 writes invalid data to the second memory cell page coupled to the first word line without data written therein, and to the second memory cell page coupled to the third word line without data written therein.

[0125] like Fig.15 As shown, the memory system provided in the embodiment of the present application further includes executing step S320.

[0126] S320: In response to a second write command sent by the memory controller, the peripheral circuit in the memory writes data to the unprogrammed second memory cell page.

[0127] Fig.16 It is exemplarily shown that there are three first word lines in the first storage unit block, and the number of the first word lines is greater than the first threshold. Fig.16 As shown, at this time, in response to the second write command, the peripheral circuit 400 in the memory 320 writes to the third ( Fig.16 Data is written into an unprogrammed second memory cell page coupled to the (from bottom to top) word line and the fourth word line.

[0128] Fig.17 It is exemplarily shown that there is one first word line in the first storage unit block, and the number of the first word lines is less than the first threshold. Fig.17 As shown, at this time, in response to the second write command, the peripheral circuit 400 in the memory 320 writes to the first ( Fig.17 Data is written into an unprogrammed second memory cell page coupled to a word line (from bottom to top) and a second word line.

[0129] like Fig.18 As shown, the memory system provided in the embodiment of the present application further includes executing step S330.

[0130] S330 , in response to the third write command sent by the memory controller, the peripheral circuit in the memory writes invalid data to the unprogrammed second memory cell page in the first memory cell block.

[0131] like Fig.19 As shown, the first memory cell block becomes a completely programmed block (close block), so that the threshold voltage difference between the first memory cell page and the adjacent memory cell page is reduced, thereby reducing charge migration and improving the data retention of the first memory cell block.

[0132] It should be understood that the writing of data to the unprogrammed second storage cell page coupled to the first word line (or the second word line) described in the present application is intended to indicate the starting storage cell page for writing data, and does not mean writing data only to the unprogrammed second storage cell page of the first word line (or the second word line). When the data to be written requires multiple storage cell pages, the memory 320 can write data to the unprogrammed second storage cell pages on other word lines according to a variety of programming methods (for example, by word line programming or by string programming). That is to say, after the unprogrammed second storage cell pages coupled to the first word line are all written with data, data can continue to be written to the unprogrammed second storage cell pages coupled to the third word line and the second word line, and data can even continue to be written to the next storage cell block (for example, the second storage cell block).

[0133] like Fig. 20 As shown, the embodiment of the present application provides a memory controller 310, which includes a processor 600, a back-end interface 700, and a cache module 800. The cache module 800 may include a first cache unit 810 for caching the number of reads of a single first word line and / or a second cache unit 820 for caching the number of reads of a first storage unit block.

[0134] Among them, the processor 600 can execute the above-mentioned steps S210 (step S110), step S220, step S240 (step S120), step S260 (step S140) and step S280 (step S160); and control the back-end interface 700 to execute steps 230, step S250 (step S130), step S270 (step S150), and S280 (step S160).

[0135] It should be understood that each module of the memory controller 310 described herein may be a software module running on a processor 600 (e.g., a microcontroller unit (MCU)) that is part of the memory controller 310, or may be a hardware module of a finite state machine (FSM) (e.g., an integrated circuit (IC, such as an application specific IC (ASIC), a field programmable gate array (FPGA), etc.)), or may be a combination of software modules and hardware modules.

[0136] The present application also provides a computer-readable storage medium, which stores computer-executable instructions. After the computer-executable instructions are executed, each step in the above method embodiment can be implemented, such as executing Figure 8-Figure 12 , Fig.15 and Fig.18 The method shown.

[0137] The present application embodiment provides a computer device, including a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions. When the executable instructions are executed by the processor, the various steps in the above method embodiment can be implemented, such as executing Figure 8-Figure 12 , Fig.15 and Fig.18 The method shown.

[0138] The embodiment of the present application provides an operation method of a memory controller, a memory controller and a memory system, which writes data to an unprogrammed memory cell page coupled to a second word line when the number of reads of a first memory cell block meets a first condition and the number of first word lines coupled to a programmed memory cell page is less than a first threshold value; the second word line is not adjacent to the first word line. Under the premise of ensuring programming accuracy, the storage space of a part of the programming block can be better utilized, the storage space utilization rate of the part of the programming block can be improved, and thus the storage space utilization rate of the memory can be improved.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and for the parts not described in detail in a certain embodiment, reference can be made to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0140] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0141] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0142] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for operating a memory controller, characterized in that: include: In response to a data write instruction, determining a first storage unit block into which data is to be written; The first memory block includes a programmed first memory cell page and an unprogrammed second memory cell page; Determining that the first storage unit block satisfies a first condition, wherein the first condition is related to a number of read times of the first storage unit page; In response to the first memory cell block satisfying the first condition, determining that the number of first word lines coupled to the first memory cell page is greater than a first threshold; In response to the number of the first word lines being not greater than the first threshold, starting to write data from the second memory cell page coupled to the second word line in the first memory cell block; The second word line is not adjacent to the first word line.

2. The operating method according to claim 1, characterized in that: The operation method also includes: In response to the first memory cell block not satisfying the first condition, data is written to the second memory cell page.

3. The operating method according to claim 2, characterized in that: The operation method also includes: In response to the number of the first word lines being greater than the first threshold, a second memory cell block to which data is to be written is determined.

4. The operating method according to claim 1, characterized in that: Also includes: Invalid data is written to a memory cell page located between the first memory cell page coupled to the first word line and the second memory cell page coupled to the second word line.

5. The operating method according to claim 3, characterized in that: Also includes: Invalid data is written to the second memory cell page in the first memory cell block.

6. The operating method according to any one of claims 1 to 5, characterized in that: The determining that the first storage unit block satisfies a first condition includes: Acquire a reading number of each first word line, where the reading number of each first word line is the sum of the reading numbers of a plurality of first memory cell pages coupled to the first word line; It is determined that there is at least one first word line whose number of read times is greater than a second threshold.

7. The operating method according to any one of claims 1 to 5, characterized in that: The determining that the first storage unit block satisfies the first condition specifically includes: Obtaining the number of reads of the first storage unit block; According to the number of reads of the first storage unit block, an average number of reads of the first word line in the first storage unit block is obtained, and it is determined that the average number of reads is greater than a second threshold.

8. The operating method according to claim 7, characterized in that: Also includes: Determining that the number of reads of the first storage unit block is greater than a third threshold; In response to the number of reads of the first storage unit block being not greater than the third threshold, writing data to the second storage unit page; In response to the number of read times of the first storage unit block being greater than the third threshold, it is determined that the first storage unit block satisfies a first condition.

9. A memory controller, characterized in that: The memory controller includes a processor and a backend interface coupled to the processor; the processor is configured to: In response to a data write instruction, determining a first storage cell block to which data is to be written; the first storage block includes a programmed first storage cell page and an unprogrammed second storage cell page; Determining that the first storage unit block satisfies a first condition, wherein the first condition is related to a number of read times of the first storage unit page; In response to the first memory cell block satisfying the first condition, determining that the number of first word lines coupled to the first memory cell page is greater than a first threshold; In response to the number of the first word lines being not greater than the first threshold, controlling the back-end interface to send a first write command to the memory, instructing to start writing data from the second memory cell page coupled to the second word line in the first memory cell block; The second word line is not adjacent to the first word line.

10. The memory controller according to claim 9, characterized in that: The processor is further configured to: In response to the first storage unit block not satisfying the first condition, the back-end interface is controlled to send a second write command to the memory, instructing to write data to the second storage unit page.

11. The memory controller according to claim 10, characterized in that: The processor is further configured to: In response to the number of the first word lines being greater than the first threshold, a second memory cell block to which data is to be written is determined.

12. The memory controller according to claim 9, wherein: The processor is configured to: The back-end interface is controlled to send the first write command to the memory, and invalid data is also instructed to be written to a memory cell page located between the first memory cell page coupled to the first word line and the second memory cell page coupled to the second word line.

13. The memory controller according to claim 11, wherein: The processor is configured to, the determining of the second storage unit block to which data is to be written, further comprising: The back-end interface is controlled to send a third write command to the memory, instructing to write invalid data to the second storage unit page in the first storage unit block.

14. The memory controller according to any one of claims 9 to 13, characterized in that: The memory controller further includes a first cache unit, the first cache unit being used to cache the number of reads of each first word line, the number of reads of each first word line being the sum of the number of reads of a plurality of first storage unit pages coupled to the first word line; the processor being configured to: Acquire the number of reads of each first word line from the first cache unit; It is determined that there is at least one first word line whose number of read times is greater than a second threshold.

15. The memory controller according to any one of claims 10 to 13, characterized in that: The memory controller further includes a second cache unit, the second cache unit being used to cache the number of times the first storage unit block is read; and in determining that the first storage unit block satisfies the first condition, the processor is configured to: Acquire the number of reads of the first storage unit block from the second cache unit; According to the number of reads of the first storage unit block, an average number of reads of the first word line in the first storage unit block is obtained, and it is determined that the average number of reads is greater than a second threshold.

16. The memory controller according to claim 15, characterized in that: The processor is further configured to: In response to the data write instruction, determining that the number of reads of the first storage unit block is greater than a third threshold; In response to the number of reads of the first memory cell block being not greater than the third threshold, starting to write data into memory cells coupled to the first word line and to which no data is written; In response to the number of read times of the first storage unit block being greater than the third threshold, it is determined that the first storage unit block satisfies a first condition.

17. A memory system, characterized in that: include: a memory and a memory controller, the memory controller being coupled to the memory; The memory controller is configured to: In response to a data write instruction, determining a first storage cell block to which data is to be written; the first storage block includes a programmed first storage cell page and an unprogrammed second storage cell page; Determining that the first storage unit block satisfies a first condition, wherein the first condition is related to a number of read times of the first storage unit page; In response to the first memory cell block satisfying the first condition, determining that the number of first word lines coupled to the first memory cell page is greater than a first threshold; In response to the number of the first word lines being not greater than the first threshold, sending a first write command to the memory, the first write command instructing to write data starting from the second memory cell page coupled to the second word line in the first memory cell block; The second word line is not adjacent to the first word line; The memory is configured as: In response to the first write command, data is written starting from the second memory cell page coupled to the second word line in the first memory cell block.

18. A memory system according to claim 17, characterized in that: The memory is further configured to: In response to the first write command, invalid data is written to a memory cell page located between the first memory cell page coupled to the first word line and the second memory cell page coupled to the second word line.

19. A memory system according to claim 18, characterized in that: The memory controller is configured to: In response to the first storage unit block not satisfying the first condition, sending a second write command to the memory, wherein the second write command instructs writing data to the second storage unit page; The memory is further configured to: In response to the second write command, data is written to the second memory cell page.

20. The memory system according to claim 19, characterized in that: The memory controller is further configured to: In response to the number of the first word lines being greater than the first threshold, determining a second storage cell block to which data is to be written, and sending a third write command to the memory, wherein the third write command instructs writing invalid data to the second storage cell page in the first storage cell block; The memory is further configured to: In response to the third write command, invalid data is written to the second memory cell page in the first memory cell block.

21. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method provided in any one of claims 1 to 8 can be implemented.

22. A computer device, characterized in that: The invention comprises a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, the method according to any one of claims 1 to 8 can be implemented.

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