Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes forming a conductive pillar over and connected to a conductive pad, dispensing a first polymer layer, where the first polymer layer contacts a lower portion of a sidewall of the conductive pillar, curing the first polymer layer, and dispensing a second polymer layer on the first polymer layer. The second polymer layer contacts an upper portion of the sidewall of the conductive pillar. The second polymer layer is then cured. The embodiment of the invention also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] In the formation of an integrated circuit, an integrated circuit device such as a transistor is formed at the surface of a semiconductor substrate in a wafer. An interconnect structure is then formed above the integrated circuit device. A metal pad is formed above the interconnect structure and electrically coupled to the metal pad. A passivation layer and a first polymer layer are formed above the metal pad, and the metal pad is exposed through openings in the passivation layer and the first polymer layer. The first polymer layer has a function of buffering stress.

[0003] A metal pillar may then be formed to connect to the top surface of the metal pad, followed by forming a second polymer layer over the redistribution line. Summary of the invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, the method comprising: forming a first conductive column above a conductive pad, and the first conductive column is connected to the conductive pad; dispensing a first polymer layer, wherein the first polymer layer contacts a lower portion of a side wall of the first conductive column; curing the first polymer layer; dispensing a second polymer layer on the first polymer layer, wherein the second polymer layer contacts an upper portion of a side wall of the first conductive column; and curing the second polymer layer.

[0005] Other embodiments of the present disclosure provide a semiconductor structure, which includes: a conductive pad; a passivation layer partially covering the conductive pad; a conductive column including: a first portion located in the passivation layer and in contact with the conductive pad; and a second portion located above the passivation layer, wherein the second portion includes a sidewall; a first polymer layer located above the passivation layer, wherein the first polymer layer contacts a lower portion of the sidewall; and a second polymer layer located above the first polymer layer and in contact with the first polymer layer, wherein the second polymer layer contacts an upper portion of the sidewall.

[0006] Another embodiment of the present disclosure provides a semiconductor structure, which includes: a device die, including: a conductive pillar including a sidewall; a first polymer layer, contacting the sidewall of the conductive pillar; and a second polymer layer, located above the first polymer layer, wherein the second polymer layer contacts the sidewall of the conductive pillar; a gap filling material, surrounding the device die, wherein the gap filling material contacts both the first polymer layer and the second polymer layer; a dielectric layer, located above both the gap filling material and the second polymer layer, and contacts both the gap filling material and the second polymer layer; and a redistribution line, including a portion located in the dielectric layer to contact the conductive pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 8 A cross-sectional view of an intermediate stage in forming a device die is shown in accordance with some embodiments.

[0009] Figures 9 to 16 A cross-sectional view of an intermediate stage in forming a package including a device die is shown in accordance with some embodiments.

[0010] Fig.17 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] An integrated circuit package and a method for forming the same are provided. According to some embodiments of the present disclosure, a device die is formed, the device die including a metal through hole (also referred to as a metal pillar or a metal bump). A first polymer layer is dispensed and cured. The first polymer layer contacts the sidewall of the lower portion of the metal through hole. A second polymer layer is then dispensed on the first polymer layer, and the second polymer layer contacts the first polymer layer. The second polymer layer may contact the sidewall of the upper portion of the metal through hole. By forming multiple polymer layers, delamination between the polymer layer and underlying components such as a passivation layer is eliminated.

[0014] The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate the modifications that may be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, identical reference numerals are used to represent identical elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] Figures 1 to 16 1 shows a cross-sectional view of an intermediate stage of forming a package according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.17 The process flow shown.

[0016] Figure 1 A cross-sectional view of a (integrated circuit) device 20 is shown. According to some embodiments of the present disclosure, the device 20 is or includes a device wafer, which includes active devices and possible passive devices, which are represented as integrated circuit devices 26. A plurality of chips (device dies) 20' may be included in the device 20, of which one of the dies 20' is shown. According to an optional embodiment of the present disclosure, the device 20 is an interposer wafer, which does not contain active devices and may or may not include passive devices. According to another optional embodiment of the present disclosure, the device 20 is or includes a package substrate strip, which includes a coreless package substrate or a cored package substrate having a core therein. In the subsequent discussion, the device wafer is used as an example of the device 20, and the device 20 may also be referred to as a wafer 20. The embodiments of the present disclosure may also be applied to interposer wafers, package substrates, packages, and the like.

[0017] According to some embodiments of the present disclosure, the wafer 20 includes a semiconductor substrate 24 and components formed at a top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or III-V compound semiconductors (such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc.). A shallow trench isolation (STI) region (not shown) may be formed in the semiconductor substrate 24 to isolate active regions in the semiconductor substrate 24.

[0018] According to some embodiments of the present disclosure, wafer 20 includes integrated circuit devices 26 formed on a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not described herein. According to an optional embodiment, wafer 20 is used to form an interposer (which does not contain active devices).

[0019] An interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the spaces between the gate stacks of transistors (not shown) in the integrated circuit device 26. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present disclosure, the ILD 28 may also be formed using deposition methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0020] The contact plug 30 is formed in the ILD 28 and is used to electrically connect the integrated circuit device 26 to the metal lines and vias above. According to some embodiments of the present disclosure, the contact plug 30 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys and / or their multilayers, or the contact plug 30 includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, their alloys and / or their multilayers. The formation of the contact plug 30 may include forming a contact opening in the ILD 28, filling the conductive material into the contact opening, and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of the contact plug 30 flush with the top surface of the ILD 28.

[0021] An interconnect structure 32 is formed over the integrated circuit device 26. The interconnect structure 32 includes metal lines 34 and vias 36, which are formed in a dielectric layer 38 (also referred to as an intermetallic dielectric (IMD)) and an etch stop layer (not shown). Metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments of the present disclosure, the interconnect structure 32 includes a plurality of metal layers, and the plurality of metal layers include metal lines 34 interconnected by vias 36. The metal lines 34 and vias 36 may be formed of copper or a copper alloy, and may also be formed of other metals.

[0022] According to some embodiments of the present disclosure, dielectric layer 38 is formed of a low-k dielectric material. The dielectric constant (k value) of the low-k dielectric material may be, for example, lower than about 3.5. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. An etch stop layer is formed below the corresponding dielectric layer 38, and the etch stop layer may be formed of aluminum nitride, aluminum oxide, silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, etc., or a multilayer thereof, or the etch stop layer may include aluminum nitride, aluminum oxide, silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, etc., or a multilayer thereof.

[0023] The formation of metal line 34 and via 36 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming a metal line or via, a trench or via opening is first formed in one dielectric layer of dielectric layer 38, and then the trench or via opening is filled with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portion of the conductive material above the top surface of the dielectric layer, thereby leaving a metal line or via in the corresponding trench or via opening. In a dual damascene process, both a trench and a via opening are formed in the dielectric layer, and the via opening is located below the trench and connected to the trench. Then a conductive material is filled into the trench and the via opening to form a metal line and a via, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0024] Metal lines 34 include top conductive (metal) features (denoted as 34T), such as metal lines, metal pads, or vias, located in a top dielectric layer (denoted as dielectric layer 38T), which is a top layer of dielectric layer 38. According to some embodiments, dielectric layer 38T is formed of a low-k dielectric material similar to the material of the lower dielectric layers of dielectric layer 38. Metal features 34T in top dielectric layer 38T may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

[0025] According to some embodiments, an etch stop layer (not shown) may be deposited on the top dielectric layer 38T and the top metal layer. The etch stop layer may be formed of silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, etc., or the etch stop layer may include silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, etc.

[0026] Passivation layer 42 (sometimes referred to as passivation-1 or pass-1) may be formed over metal feature 34T and top dielectric layer 38T. According to some embodiments, passivation layer 42 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. Passivation layer 42 may be formed of or include an inorganic dielectric material, which may include, but is not limited to, a material selected from the following: undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), etc., combinations thereof, and / or multilayers thereof. According to some embodiments, the top surfaces of top dielectric layer 38T and metal line 34T are flush with each other. Accordingly, passivation layer 42 may be a planar layer.

[0027] According to some embodiments, vias 44 are formed in passivation layer 42 to electrically connect to the underlying top metal feature 34T. Metal pads 46 are further formed above vias 44. The corresponding process is shown as follows: Fig.17 Process 202 is shown in process flow 200. According to some embodiments, metal pad 46 includes aluminum, aluminum copper, copper, or the like.

[0028] According to some embodiments, via 44 and metal pad 46 are formed in the same process. The formation process may include etching passivation layer 42 to form an opening, depositing a metal layer including a first portion extending into the opening and a second portion located above passivation layer 42, and patterning the metal layer to form via 44 and metal pad 46. According to an optional embodiment, the formation process may include depositing a metal seed layer, forming a patterned plating mask, and plating a metal layer over the metal seed layer and extending into the opening. The patterned plating mask is then removed, followed by etching the portion of the metal seed layer previously covered by the plating mask. According to yet another optional embodiment, via 44 and metal pad 46 are formed separately, wherein via 44 is formed in a single damascene process, and metal pad 46 is formed by deposition and patterning.

[0029] Next, if Figure 2 As shown, a passivation layer 50 (sometimes referred to as passivation-2 or pass-2) is formed. The corresponding process is shown as follows Fig.17 Process 204 in process flow 200 is shown. According to some embodiments, passivation layer 50 is formed of or includes an inorganic dielectric material, which may include a nitride-based dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, etc. According to alternative embodiments, passivation layer 50 may include an oxide-based dielectric material, such as undoped silicate glass (USG), spin-on glass (SOG), silicon oxide, etc.

[0030] According to yet another optional embodiment, the passivation layer 50 may have a multilayer structure including a plurality of layers. For example, the passivation layer 50 may include a silicon nitride layer and a silicon oxide layer located above the silicon nitride layer. There may or may not be an additional silicon nitride layer above the silicon oxide layer. The passivation layer 50 and the sublayers in the passivation layer 50 (if any) may be formed by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0031] According to yet another optional embodiment, the passivation layer 50 is formed of an organic dielectric material (such as a polymer), the organic dielectric material is dispensed in a flowable form, and then the organic dielectric material is cured into a solid. According to these embodiments, the passivation layer 50 may be formed of a photosensitive polymer (such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), etc.) or a non-photosensitive polymer.

[0032] After the passivation layer 50 is deposited, a patterning process may be performed by an anisotropic etching process so that a via opening is formed in the passivation layer 50, wherein the metal pad 46 below is exposed. The patterning process may include forming a photoresist layer, and performing an exposure process and a development process on the photoresist layer. Undesirable portions of the photoresist layer are thus removed, and the passivation layer 50 is etched using the patterned photoresist layer as an etching mask so that an opening is formed in the passivation layer 50. After patterning of the passivation layer 50, the etching mask is removed.

[0033] See also Figure 3 , a polymer buffer layer 54 is selectively formed on some but not all metal pads 46. The corresponding process is shown as Fig.17 Process 206 in process flow 200 is shown. According to some embodiments, polymer buffer layer 54 may be formed of a polymer. The polymer may be photosensitive or non-photosensitive. Polymer buffer layer 54 may be formed by a dispensing process, such as by spin coating. Polymer buffer layer 54 may include polyimide, PBO, BCB, etc. After dispensing, polymer buffer layer 54 is patterned. According to some embodiments, the thickness of polymer buffer layer 54 may be in a range between about 3 μm and about 8 μm.

[0034] According to some embodiments where the polymer buffer layer 54 is photosensitive, patterning may include baking the polymer buffer layer 54 after dispensing, performing an exposure process (using a photolithography mask), and developing the exposed polymer buffer layer 54, so that undesired portions of the polymer buffer layer 54 are removed. A post-bake process may then be performed so that the polymer buffer layer 54 is cross-linked and is not further patterned by subsequent exposure and development processes.

[0035] According to an alternative embodiment in which the polymer buffer layer 54 is not photosensitive, the formation of the polymer buffer layer 54 may include dispensing the polymer buffer layer 54, and curing the polymer buffer layer 54 into a solid. An etching mask such as a photoresist layer may then be formed over the polymer buffer layer 54, and then the polymer buffer layer 54 is etched using the photoresist layer as an etching mask. The etching mask is then removed.

[0036] Next, refer to Figure 4 For example, according to some embodiments, the metal seed layer 51 is formed by physical vapor deposition (PVD). The corresponding process is shown as follows: Fig.17 Process 208 is shown in process flow 200. The metal seed layer may include a titanium layer and a copper layer located above the titanium layer.

[0037] Further references Figure 4 , a plating mask 52 is formed on the metal seed layer 51, and the plating mask 52 is patterned to form an opening overlapping the metal pad 46. The corresponding process is shown as follows Fig.17 The process 210 in the process flow 200 shown in FIG. Then the metal material is plated. The corresponding process is shown as follows Fig.17 Process 212 in process flow 200 is shown. According to some embodiments, deposition is performed by electrochemical plating. The metal material may include copper, nickel, tungsten, cobalt, etc., combinations thereof, and / or multilayers thereof.

[0038] According to some embodiments, the entire plated metal material 53 is formed of a homogeneous material such as copper, tungsten, cobalt, etc. According to an optional embodiment, the plated metal material 53 includes a lower layer (such as a copper layer) 53A and an upper layer (such as a nickel layer or a solder layer) 53B located above the lower layer.

[0039] The plating mask 52 is then removed. The corresponding process is shown as Fig.17 In the process 214 of the process flow 200 shown in FIG. 214 , some portions of the metal seed layer 51 are exposed. The exposed portions of the metal seed layer 51 are then removed by etching, wherein the metal material is used as an etching mask. The corresponding process is shown as follows: Fig.17 The process 216 in the process flow 200 is shown. The plated metal material 53 and the remaining portion of the metal seed layer 51 are collectively referred to as metal vias (or metal pillars and metal bumps) 56. Figure 5 According to some embodiments, metal via 56 has vertical or substantially vertical sidewalls, for example, with a tilt angle ranging from about 87 degrees to about 93 degrees.

[0040] Since polymer buffer layer 54 is selectively formed on some metal pads 46, polymer buffer layer 54 is selectively formed under some metal vias 56 (such as larger metal vias 56) but not under other metal vias 56 (such as narrower metal vias 56). For example, metal vias 56 may include metal vias 56A and 56B. Width (or length) W2 of via 56B may be greater than width W1 of via 56A. Ratio W2 / W1 may be greater than about 1.2 and may be in a range between about 1.2 and about 5. Figure 5 In FIG. 5 , dashed lines are used to indicate where the edge of through hole 56B may be when through hole 56A is narrower than through hole 56A.

[0041] According to an alternative embodiment, width W2 of through hole 56B may be equal to or greater than width W1 of through hole 56A. According to some embodiments, width W1 may be in a range between about 10 μm and about 20 μm, and width W2 may be in a range between about 24 μm and about 60 μm. Immediately adjacent polymer buffer layers 54 separated from each other may have a spacing of less than about 200 μm.

[0042] Likewise, the openings of metal vias 56A and 56B portions in passivation layer 50 may have widths W3 and W4, respectively, where width W4 is greater than width W3. Ratio W4 / W3 may be greater than about 1.2, and may be in a range between about 1.2 and about 5. According to some embodiments, width W3 may be in a range between about 6 μm and about 12 μm, and width W4 may be in a range between about 10 μm and about 35 μm. The height of narrower via 56A may be greater than the height of wider via 56B.

[0043] refer to Figure 6 , dispensing polymer layer 58. The corresponding process is shown as Fig.17 Process 218 in process flow 200 is shown. According to some embodiments, polymer layer 58 includes a polymer that is dispensed in a flowable form. Polymer layer 58 may include polyimide, PBO, BCB, etc. Dispensing may include spin coating. The amount of polymer layer 58 is controlled so that when spin coating is completed, polymer layer 58 is a thin layer covering passivation layer 50. According to some embodiments, the entire exposed surface of passivation layer 50 is covered.

[0044] Polymer layer 58 contacts the lower portion of the sidewall of metal via 56, while the upper portion and the top surface of the sidewall of metal via 56 are exposed. According to some embodiments, an exposure process is not performed on polymer layer 58, and a development process is not performed on polymer layer 58. The selective formation of polymer layer 58 on the lower portion of the sidewall of metal via 56 is due to spin coating and control of the amount of polymer layer 58. According to some embodiments, a thickness T1 of polymer layer 58 may be in a range between about 3% and about 2 / 3 of a height H1 of metal via 56. According to some embodiments, thickness T1 is less than about 15 μm, and may be in a range between about 1 μm and about 15 μm.

[0045] The polymer layer 58 is cured in the curing process 60 and thus solidifies. The corresponding process is shown as follows: Fig.17 Process 220 in process flow 200 is shown. According to some embodiments, curing process 60 includes a soft baking process, and curing process 60 does not include a hard baking process. According to some embodiments, the soft baking process is performed at a temperature within a first temperature range between about 90° C. and about 110° C. The duration of the soft baking process may be within a range between about 1 minute and about 5 minutes. The solvent in polymer layer 58 is driven out by the soft baking process.

[0046] According to some embodiments, after the soft bake process, the hard bake process is not performed, and the process proceeds to the dispensing polymer layer 62. According to an optional embodiment, after the soft bake process, the hard bake process is performed at a second temperature higher than the first temperature used for the soft bake process. For example, the second temperature may be in a range between about 140° C. and about 250° C. The duration of the hard bake process may be in a range between about 5 minutes and about 1 hour.

[0047] According to some embodiments, the curing process 60 causes the polymer layer 58 to be completely solidified. According to an optional embodiment, the curing process 60 causes the polymer layer 58 to be partially cured, wherein the cured polymer layer 58 is solid, but softer than if a hard baking process is performed. Optionally, the partially cured polymer layer 58 can also be considered to be flowable, but less fluid than when it is dispensed. The parameter "imidization ratio" can be used to measure the degree of curing. The higher the imidization ratio, the higher the mechanical strength that the polymer material will have, and the harder the corresponding polymer layer 58. Accordingly, the partially cured polymer layer 58 has a first imidization ratio that is lower than a second imidization ratio after it is fully cured (such as after a hard baking process).

[0048] refer to Figure 7 , dispensing polymer layer 62. The corresponding process is shown as Fig.17Process 222 in process flow 200 is shown. According to some embodiments, polymer layer 62 includes a polymer dispensed in a flowable form. For example, polymer layer 62 may include polyimide, PBO, BCB, etc. The material of polymer layer 62 may be the same as or different from the material of polymer buffer layer 54. Dispensing may include spin coating. According to some embodiments, polymer layer 62 completely fills the gap between adjacent metal vias 56, wherein metal vias 56 are covered by polymer layer 62. The overlapping portion may have a thickness greater than about 3 μm.

[0049] Polymer layer 62 contacts the top surface and upper portions of the sidewalls of metal via 56. According to some embodiments, a thickness T2 of polymer layer 62 is greater than a thickness T1 of polymer layer 58. According to some embodiments, thickness T2 is greater than about 10 μm, and may be in a range between about 10 μm and about 50 μm. According to some embodiments, an exposure process and a development process are not performed on polymer layer 62.

[0050] The polymer layer 62 is cured in a curing process 64. The corresponding process is shown as Fig.17 Process 224 in process flow 200 is shown. According to some embodiments, curing process 64 includes a soft baking process. According to some embodiments, the soft baking process is performed at a first temperature within a first temperature range (e.g., between about 90° C. and about 110° C.). The duration of the soft baking process may be in a range between about 1 minute and about 5 minutes. The solvent in polymer layer 62 is driven off by the soft baking process.

[0051] The curing process 64 may also include a hard baking process after the soft baking process. The hard baking process is performed at a second temperature higher than the first temperature for the soft baking process. For example, the second temperature may be in the range of about 140° C. to about 250° C. The duration of the hard baking process may be in the range of about 5 minutes to about 1 hour.

[0052] According to some embodiments, polymer layer 62 is a homogeneous layer formed of a homogeneous polymer. According to an optional embodiment, polymer layer 62 includes multiple sub-layers, such as sub-layers 62A and 62B. More sub-layers may be included in polymer layer 62. The lowest level of the interface between the sub-layers (if any) is lower than the top surface of metal via 56. For example, Figure 7 Sublayers 62A and 62B and the interface between sublayers 62A and 62B are schematically shown. Adjacent sublayers may be formed of the same or different polymers, and the materials of the sublayers are selected from the same set of candidate materials as polymer layers 58 and 62. In addition, each sublayer is followed by a soft bake process before the next sublayer is assigned. Each sublayer may or may not be followed by a hard bake process before the next sublayer is assigned.

[0053] According to some embodiments, a planarization process is performed to planarize the top surface of polymer layer 62. The remaining planar top surface of polymer layer 62 may be higher than or flush with the top surface of metal via 56. According to alternative embodiments, the planarization process is not performed.

[0054] refer to Figure 8 , the wafer 20 is singulated, for example, sawed, into a plurality of discrete device dies 20'. The corresponding process is shown as follows Fig.17 The process flow 200 is shown as process 226. During the sawing process, the wafer 20 may be fixed on a dicing tape (not shown), which is further fixed on a frame (not shown).

[0055] See also Fig. 9 , a carrier 70 is provided, on which a release film 72 is coated. The carrier 70 may be a glass carrier, a silicon wafer, an organic carrier, etc. The release film 72 may be formed of a polymer-based material and / or an epoxy-based thermal release material (such as a LTHC material).

[0056] The device die 20' is placed and attached to the carrier 70 via a die attach film 74 (which is an adhesive film). The corresponding process is shown as follows Fig.17 Process 228 of process flow 200 is shown. Although two device dies 20 ′ are shown as a group, there may be multiple groups of device dies 20 ′ attached to carrier 70 .

[0057] Next, the device die 20' is encapsulated in an encapsulant 78, such as Fig.10 The corresponding process is shown as Fig.17 Process 230 in the process flow 200 shown. The sealant 78 (also referred to as a gap filling material) fills the gap between adjacent device dies 20'. The sealant 78 may include a molding compound, a molding bottom filler, an epoxy resin and / or a resin. Optionally, the sealant 78 may include an inorganic dielectric layer, such as a silicon nitride layer, a silicon oxide layer located above the silicon nitride layer, etc. The top surface of the sealant 78 is higher than the top of the metal via 56. When a molding compound is used, the molding compound may include a base material and filling particles (not shown) located in the base material, and the base material may be a polymer, a resin, an epoxy resin, etc. The filling particles may be dielectric particles of SiO2, Al2O3, quartz, etc., and the filling particles may have a spherical shape. Similarly, the spherical filling particles may have the same or different diameters.

[0058] like Fig.11 As shown, a planarization process, such as a CMP process or a mechanical grinding process, is performed to thin the sealant 78 and the polymer layer 62 until the metal via 56 is fully exposed. The corresponding process is shown as Fig.17 Process 232 in process flow 200 is shown.

[0059] Figure 12 to Figure 14 The formation of the front side redistribution structure 86 is shown, and the front side redistribution structure 86 includes the dielectric layer 80 and the RDL 82. The corresponding process is shown as Fig.17 The process 234 in the process flow 200 is shown. Fig.12 , forming a first dielectric layer 80. According to some embodiments, the dielectric layer 80 may be formed of a polymer, such as PBO, polyimide, etc. The formation of the dielectric layer 80 may include coating the dielectric layer 80 in a flowable form, and then curing the dielectric layer 80. According to an optional embodiment of the present disclosure, the dielectric layer 80 is formed of an inorganic dielectric material (such as silicon nitride, silicon oxide, etc.). The formation method may include CVD, ALD, plasma enhanced chemical vapor deposition (PECVD) or other applicable deposition methods. The dielectric layer 80 is patterned to form an opening 81, through which the metal via 56 is exposed.

[0060] According to some embodiments, all topmost portions of polymer layer 58 are spaced apart from dielectric layer 80 by polymer layer 62. According to alternative embodiments, due to process variations, some topmost portions of polymer layer 58 are spaced apart from dielectric layer 80, while some other topmost portions of polymer layer 58 are in contact with the bottom surface of dielectric layer 80. For example, metal via 56B may have polymer 54 underneath that raises the height of polymer layer 58, and thus polymer layer 58 on some or all of metal vias 56 may extend to and be in contact with the bottom surface of dielectric layer 80. According to these embodiments, dashed line 79 is shown to represent the interface between polymer layers 58 and 62.

[0061] See also Fig.13 , forming RDL 82 to electrically connect to device die 20'. Each RDL 82 includes a through-hole portion formed in the corresponding underlying dielectric layer 80, and a trace portion (metal line) located above the corresponding dielectric layer 80. According to some embodiments of the present disclosure, RDL 82 is formed by the following process, including depositing a metal seed layer (not shown), forming and patterning a photoresist (not shown) above the metal seed layer, and plating a metal material (such as copper, tungsten, nickel, etc.) above the metal seed layer. The patterned photoresist is then removed, and then the portion of the metal seed layer previously covered by the patterned photoresist is etched.

[0062] Fig.14 The formation of further dielectric layers 80 and RDL 82 is shown. The formation process may be similar to Fig.12 The dielectric layer 80 and Fig.13The number of dielectric layers 80 and RDLs 82 is selected based on the routing requirements. A redistribution structure 86 is thus formed.

[0063] refer to Fig.15 , forming an electrical connection 88. The corresponding process is shown as Fig.17 Process 236 in the process flow 200 shown. The formation of the electrical connector 88 may include patterning the top dielectric layer 80 to form an opening, placing a solder ball on the exposed portion of the RDL 82, and then reflowing the solder ball. The resulting electrical connector 88 includes a solder area. According to an optional embodiment of the present disclosure, the formation of the electrical connector 88 includes performing a plating step to form a solder layer above the RDL 82, and then reflowing the solder layer. The electrical connector 88 may also include a non-solder metal column, and there may or may not be a solder cap above the non-solder metal column. Throughout the description, the structure above the release film 72 is referred to as the reconstructed wafer 100.

[0064] Fig.15 Also shown is the bonding of device 90 to redistribution structure 86. According to some embodiments, device 90 includes a local silicon interconnect (LSI) die that acts as a bridge die to electrically interconnect device die 20'. According to some embodiments, device 90 may be connected to underlying structures through Under-Bump Metallurgies (UBM) 93.

[0065] Next, the reconstructed wafer 100 can be turned upside down and placed on a dicing tape (not shown) attached to a frame (not shown). According to some embodiments of the present disclosure, the electrical connector 88 is in contact with the tape. Next, the reconstructed wafer 100 is debonded from the carrier 70. The corresponding process is shown as follows Fig.17 Process 238 in process flow 200 is shown. In the debonding process, a light beam is projected onto the LTHC coating material 72, and the light beam penetrates the transparent carrier 70 to decompose the LTHC coating material 72. According to some embodiments, the light beam is a laser beam, and the laser beam scans the entire LTHC coating material 72.

[0066] Because of the exposure (such as laser scanning), the carrier 70 may be peeled off from the LTHC coating material 72 , and thus the reconstructed wafer 100 is debonded (detached) from the carrier 70 . Fig.16 The resulting reconstructed wafer 100 is shown. According to some embodiments, Fig.16 As shown, dashed lines are shown to show possible locations of the edges of via 56A, which is narrower than via 56B. According to some embodiments, polymer buffer layer 54 extends directly under wider via 56B, but does not extend directly under narrower via 56A.

[0067] According to an optional embodiment, through-holes 56A and 56B have the same width, and polymer buffer layer 54 still extends directly under some through-holes (such as through-hole 56B), but not directly under some other through-holes (such as through-hole 56A). According to another optional embodiment, through-hole 56B is wider than through-hole 56A, but polymer buffer layer 54 extends directly under through-hole 56B, but not directly under through-hole 56A. This may occur when the wider through-hole 56B is subjected to higher stress than the narrower through-hole 56A, for example, when the wider through-hole 56B is a corner through-hole located at a corner of the corresponding package 100', and the narrower through-hole 56A is farther away from the corner of the corresponding package 100' than the wider through-hole 56B.

[0068] In the subsequent process, Fig.16 As shown, the reconstructed wafer 100 is sawn into a plurality of packages 100'. The corresponding process is shown as follows Fig.17 Process 240 in process flow 200 is shown.

[0069] In the embodiments shown above, some processes and components are discussed to form a three-dimensional (3D) package according to some embodiments of the present disclosure. Other components and processes may also be included. For example, a test structure may be included to assist in the verification test of a 3D package or a 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the testing of a 3D package or a 3DIC, the use of a probe and / or a probe card, etc. Verification tests may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that combines intermediate verification of known good dies to increase yield and reduce costs.

[0070] Embodiments of the present disclosure have several advantageous features. As the lateral dimensions and spacing of the through-holes become smaller and smaller, polymers are not suitable for formation under very small through-holes. However, the lack of polymer allows the encapsulation polymer to be in direct contact with the underlying passivation layer. Experimental results show that delamination occurs between the encapsulation polymer and the underlying passivation layer, and the delamination rate can be as high as 100% of the through-hole samples. With the formation of multiple polymer layers, delamination is eliminated and no delamination is found in the samples.

[0071] According to some embodiments of the present disclosure, a method includes: forming a first conductive column above a conductive pad, and the first conductive column is connected to the conductive pad; dispensing a first polymer layer, wherein the first polymer layer contacts a lower portion of a sidewall of the first conductive column; curing the first polymer layer; dispensing a second polymer layer on the first polymer layer, wherein the second polymer layer contacts an upper portion of a sidewall of the first conductive column; and curing the second polymer layer. In an embodiment, dispensing the first polymer layer is performed by spin coating. In an embodiment, the first polymer layer and the second polymer layer include the same polymer material.

[0072] In an embodiment, the first polymer layer and the second polymer layer include different polymer materials. In an embodiment, the first polymer layer is fully cured before dispensing the second polymer layer. In an embodiment, the first polymer layer is partially cured before dispensing the second polymer layer. In an embodiment, the method further includes, after curing the second polymer layer, performing a planarization process to make the first top surface of the first conductive pillar flush with the second top surface of the second polymer layer. In an embodiment, one of dispensing the first polymer layer and dispensing the second polymer layer includes dispensing polyimide.

[0073] In an embodiment, the method further comprises forming a second conductive pillar, wherein the first polymer layer continuously extends from the first conductive pillar to the second conductive pillar. In an embodiment, the method further comprises forming a passivation layer, the passivation layer comprising a portion located on the conductive pad; depositing a polymer buffer layer on the passivation layer; and patterning the polymer buffer layer to form an opening, wherein the first conductive pillar comprises a portion located in the opening to contact the conductive pad.

[0074] According to some embodiments of the present disclosure, a structure includes a conductive pad; a passivation layer partially covering the conductive pad; a conductive pillar, the conductive pillar including a first portion located in the passivation layer and in contact with the conductive pad; and a second portion located above the passivation layer, wherein the second portion includes a sidewall; a first polymer layer located above the passivation layer, wherein the first polymer layer contacts a lower portion of the sidewall; and a second polymer layer located above the first polymer layer and in contact with the first polymer layer, wherein the second polymer layer contacts an upper portion of the sidewall. In an embodiment, the topmost end of the first polymer layer is lower than a top surface of the conductive pillar.

[0075] In an embodiment, the first polymer layer and the second polymer layer include the same polymer material. In an embodiment, the first polymer layer and the second polymer layer include different polymer materials. In an embodiment, the first polymer layer includes a non-flat top surface. In an embodiment, the first polymer layer and the second polymer layer are subdivisions of a device die, and the structure further includes a molding compound that contacts the sidewalls of the device die; and a dielectric layer that is located above and contacts both the second polymer layer and the molding compound. In an embodiment, the structure further includes a polymer buffer layer, the polymer buffer layer including a subdivision located directly below the second portion of the conductive pillar, wherein the first polymer layer includes a first subdivision located above and contacting the polymer buffer layer; and a second subdivision located above and contacting the passivation layer.

[0076] According to some embodiments of the present disclosure, a structure includes a device die, the device die including a conductive pillar, the conductive pillar including a sidewall; a first polymer layer contacting the sidewall of the conductive pillar; and a second polymer layer located above the first polymer layer, wherein the second polymer layer contacts the sidewall of the conductive pillar; a gap filling material surrounding the device die, wherein the gap filling material contacts both the first polymer layer and the second polymer layer; a dielectric layer located above and contacting both the gap filling material and the second polymer layer; and a redistribution line including a portion located in the dielectric layer to contact the conductive pillar.

[0077] In an embodiment, the second polymer layer completely separates the first polymer layer from the dielectric layer. In an embodiment, the first polymer layer and the second polymer layer comprise different polymer materials.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first conductive pillar over the conductive pad, and the first conductive pillar is connected to the conductive pad; dispensing a first polymer layer, wherein the first polymer layer contacts a lower portion of a sidewall of the first conductive pillar; curing the first polymer layer; dispensing a second polymer layer on the first polymer layer, wherein the second polymer layer contacts an upper portion of the sidewall of the first conductive pillar; and The second polymer layer is cured.

2. The method according to claim 1, wherein: Dispensing the first polymer layer is performed by spin coating.

3. The method according to claim 1, wherein: The first polymer layer and the second polymer layer include the same polymer material.

4. The method according to claim 1, wherein: The first polymer layer and the second polymer layer include different polymer materials.

5. The method according to claim 1, wherein: The first polymer layer is fully cured prior to dispensing the second polymer layer.

6. The method according to claim 1, wherein: Prior to dispensing the second polymer layer, the first polymer layer is partially cured.

7. The method according to claim 1, further comprising: After curing the second polymer layer, a planarization process is performed to make the first top surface of the first conductive pillar flush with the second top surface of the second polymer layer.

8. The method according to claim 1, wherein: One of dispensing the first polymer layer and dispensing the second polymer layer includes dispensing polyimide.

9. A semiconductor structure comprising: Conductive pads; a passivation layer partially covering the conductive pad; Conductive column, comprising: a first portion located in the passivation layer and in contact with the conductive pad; and a second portion located above the passivation layer, wherein the second portion includes a sidewall; a first polymer layer located above the passivation layer, wherein the first polymer layer contacts a lower portion of the sidewall; and A second polymer layer is located above the first polymer layer and contacts the first polymer layer, wherein the second polymer layer contacts an upper portion of the sidewall.

10. A semiconductor structure comprising: Device die, including: a conductive column including a sidewall; a first polymer layer contacting the sidewalls of the conductive pillars; and a second polymer layer, located above the first polymer layer, wherein the second polymer layer contacts the sidewall of the conductive pillar; a gap-fill material surrounding the device die, wherein the gap-fill material contacts both the first polymer layer and the second polymer layer; a dielectric layer over and in contact with both the gap-fill material and the second polymer layer; and The redistribution line includes a portion located in the dielectric layer to contact the conductive pillar.

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