DC circulating current suppression method and system for parallel operation of inverters, and electronic equipment

Abstract

The invention relates to a direct-current circulating current suppression method and system for parallel operation of inverters and electronic equipment. The method comprises the following steps: acquiring a first current of a balance bridge circuit in an inverter, a second current output by a bus midpoint and a three-phase current direct-current component output by a three-phase bridge circuit based on a carrier cycle synchronized with a host; based on the first current and the second current, a first adjusting signal is generated to act on an upper bridge arm circuit and a lower bridge arm circuit of the balance bridge circuit, fluctuation interference currents in the first current and the second current are adjusted to offset each other, and therefore direct-current circulation between output zero lines caused by voltage difference between different parallel inverter buses is restrained; and based on the direct current component of each phase of current, generating a corresponding second adjusting signal to act on the three-phase bridge circuit, and adjusting the corresponding direct current component to suppress direct current circulation between output zero lines of each inverter caused by the direct current component of the three-phase current.

Description

Technical Field

[0001] The present application relates to the technical field of inverters, and in particular to a method, system and electronic equipment for suppressing direct current circulating current of inverters operating in parallel. Background Art

[0002] In the prior art, inverter paralleling refers to a system configuration in which multiple inverters are connected together and run in parallel. The main purpose of inverter paralleling is to improve the total power output and reliability of the system. Inverter paralleling can be divided into two modes: series paralleling and parallel paralleling.

[0003] Among them, series parallel connection is to connect multiple inverters together in series and share the load. Under series parallel connection, the output DC voltage of each inverter will pass through other inverters in turn and finally output to the load. Series parallel connection can increase the DC voltage of the system and is suitable for application scenarios that require higher DC voltage. Parallel parallel connection is to connect multiple inverters together in parallel and share the load. Each inverter independently converts DC power into AC power and outputs it to the load. Parallel parallel connection can increase the total power output of the system and is suitable for application scenarios that require higher power output.

[0004] When two or more inverters are connected in parallel, DC circulating current problems may occur due to direct connection of the bus midpoint, voltage deviation between the upper and lower buses, and the presence of a DC component in the output voltage. Summary of the invention

[0005] Based on this, it is necessary to provide a DC circulating current suppression method, system and electronic device for parallel operation of inverters, which can suppress the output DC circulating current between parallel inverters by carrier synchronization fine-tuning the deviation value of the DC side bus voltage of different inverters.

[0006] In a first aspect, in one embodiment, a method for suppressing DC circulating current in parallel operation of inverters is provided, wherein a plurality of inverters are connected in parallel and communicate with a host through a CAN bus, and the host sends a carrier signal to each of the inverters at fixed intervals; the inverter comprises a bus, and a balanced bridge circuit and a three-phase bridge circuit connected in parallel to the bus; the balanced bridge circuit comprises an upper bridge arm circuit, a lower bridge arm circuit and a balanced inductor, the upper bridge arm circuit is connected in series with the lower bridge arm circuit, one end of the balanced inductor is connected to the midpoint of the upper bridge arm circuit and the lower bridge arm circuit, and the other end of the balanced inductor is connected to the midpoint of the bus and the output end of the three-phase bridge circuit to form an output neutral line of the inverter; the output neutral lines of each of the inverters are short-circuited, and the method comprises:

[0007] Based on the fixed period of the carrier signal, a first current on the balanced inductor of the balanced bridge circuit, a second current output at the bus midpoint, and a three-phase current DC component at the output end of the three-phase bridge circuit are collected; the second current includes a fluctuating interference current generated by a voltage difference between different inverter buses;

[0008] Based on the first current and the second current, a first regulating signal is generated; and the first regulating signal is controlled to act on the upper bridge arm circuit and the lower bridge arm circuit to adjust the first current and the fluctuating interference current to offset each other, so as to suppress the DC circulating current between the output neutral lines of each inverter caused by the voltage difference between the busbars of the different inverters;

[0009] Based on the DC component of the current of each phase, a corresponding second adjustment signal is generated; and the second adjustment signal is controlled to act on the three-phase bridge circuit to adjust the corresponding DC component of the current to suppress the DC circulating current between the output neutral lines of each inverter caused by the DC component of the three-phase current.

[0010] In one embodiment, generating a first adjustment signal based on the first current and the second current includes:

[0011] According to the carrier period of the carrier signal, calculating a first current average value of the first current collected within the carrier period;

[0012] Obtaining a first deviation between the first current average value and a preset current reference value, and performing proportional-integral adjustment on the first deviation to obtain a balanced bridge current average value loop;

[0013] According to the first current and the second current, voltage and current dual closed-loop regulation is performed on the balance bridge current average value loop to generate the first regulation signal.

[0014] In one embodiment, performing voltage and current dual closed-loop regulation on the average current loop of the balanced bridge current to generate the first regulation signal includes:

[0015] According to the second current, obtaining a voltage difference between midpoints of the buses of different inverters;

[0016] Obtaining a second deviation between the voltage difference between the average current loop of the balancing bridge and the midpoint of the busbar, and performing proportional-integral regulation on the second deviation to obtain a voltage closed-loop regulation output value;

[0017] A third deviation between the voltage closed-loop regulation output value and the first current is obtained, and proportional-integral regulation is performed on the third deviation to obtain the first regulation signal.

[0018] In one embodiment, the upper bridge arm circuit includes a first switch tube, the lower bridge arm circuit includes a second switch tube, and the first switch tube and the second switch tube are complementary to each other; controlling the first adjustment signal to act on the upper bridge arm circuit or the lower bridge arm circuit to adjust the first current value and the fluctuating interference current to offset each other includes:

[0019] When the first current is less than the preset current reference value, the first regulating signal is controlled to close and turn on the first switch tube and to turn off and cut off the second switch tube, so as to adjust the first current to gradually increase and offset the fluctuating interference current;

[0020] When the first current is greater than the preset current reference value, the first regulating signal is controlled to turn off the first switch tube and turn on the second switch tube, so that the first current is gradually reduced to offset the fluctuating interference current.

[0021] In one embodiment, generating a corresponding second adjustment signal based on each of the current DC components includes:

[0022] According to the carrier cycle of the carrier signal, for the DC components of the current of each phase collected within the carrier cycle, an average value of the DC components of each phase is calculated;

[0023] Obtaining a fourth deviation between the average value of the DC component of each phase and a preset current reference value, and performing proportional-integral adjustment on the fourth deviation to obtain an average value loop of the DC component of each phase;

[0024] Obtaining a reference voltage instantaneous value loop of the three-phase bridge circuit;

[0025] The DC component average value loop and the reference voltage instantaneous value loop of each phase are respectively added and summed to generate each corresponding second adjustment signal in the three-phase bridge circuit.

[0026] In one embodiment, before collecting the first current on the balanced inductor of the balanced bridge circuit, the second current output at the bus midpoint, and the three-phase current DC component at the output end of the three-phase bridge circuit, the method further includes:

[0027] Receiving a carrier signal sent by the host;

[0028] The carrier signal is parsed to extract the corresponding host carrier phase, and the host carrier phase is synchronized to the carrier phase of each inverter.

[0029] In a second aspect, a DC circulating current suppression system for inverters in parallel operation is provided, the system comprising a plurality of inverters and a host, the plurality of inverters being connected in parallel and communicating with the host via a CAN bus, the host sending a carrier signal to each of the inverters at fixed intervals, the inverter comprising a bus, a balanced bridge circuit connected in parallel to the bus, a three-phase bridge circuit, and a controller; the balanced bridge circuit comprising an upper bridge arm circuit, a lower bridge arm circuit and a balanced inductor, the upper bridge arm circuit being connected in series with the lower bridge arm circuit, one end of the balanced inductor being connected to the midpoint of the upper bridge arm circuit and the lower bridge arm circuit, the other end of the balanced inductor being connected to the midpoint of the bus and the output end of the three-phase bridge circuit, constituting an output neutral line of the inverter; the output neutral lines of the inverters being short-circuited to each other; the controller being used for:

[0030] Collecting a first current on the balanced inductor of the balanced bridge circuit, a second current output at the bus midpoint, and a three-phase current DC component at the output end of the three-phase bridge; the second current includes a fluctuating interference current generated by a voltage difference between different inverter buses;

[0031] Based on the first current and the second current, a first regulating signal is generated; the first regulating signal acts on the upper bridge arm circuit and the lower bridge arm circuit to adjust the first current and the fluctuating interference current to offset each other, so as to suppress the DC circulating current between the output neutral lines of each inverter caused by the voltage difference between the busbars of different inverters;

[0032] Based on the DC component of the current of each phase, a corresponding second adjustment signal is generated; and the second adjustment signal is controlled to act on the three-phase bridge circuit to adjust the corresponding DC component of the current to suppress the DC circulating current between the output neutral lines of each inverter caused by the DC component of the three-phase current.

[0033] In one embodiment, the controller is also used to obtain a first current average value for the first current collected within the carrier period according to the carrier period of the carrier signal; obtain a first deviation between the first current average value and a preset current reference value, perform proportional-integral adjustment on the first deviation, and obtain a balanced bridge current average value loop; perform voltage-current dual closed-loop adjustment on the balanced bridge current average value loop according to the first current and the second current, and generate the first adjustment signal.

[0034] In one embodiment, the controller is also used to: calculate the average value of the DC component of each phase for the DC component of the current of each phase collected within the carrier period according to the carrier period of the carrier signal; obtain a fourth deviation between the average value of the DC component of each phase and the preset current reference value, and perform proportional integral adjustment on the fourth deviation to obtain an average value loop of the DC component of each phase; obtain an instantaneous value loop of the reference voltage of the three-phase bridge circuit; and respectively add and sum the average value loop of the DC component of each phase and the instantaneous value loop of the reference voltage to generate a second adjustment signal corresponding to each phase in the three-phase bridge circuit.

[0035] In a third aspect, an electronic device is provided, comprising a DC circulating current suppression system for inverters operating in parallel as described in the second aspect.

[0036] The DC circulating current suppression method, system and electronic device for the above-mentioned inverters operating in parallel control each inverter to generate a first adjustment signal and a second adjustment signal according to the carrier cycle of the host to act on the balancing bridge circuit and the three-phase bridge circuit, thereby suppressing the DC circulating current on the output neutral line caused by the DC current output by the balancing bridge circuit, the bus midpoint and the three-phase bridge circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A structural block diagram of a DC circulating current suppression system for inverters operating in parallel according to an embodiment;

[0039] Figure 2 A flowchart of a method for suppressing DC circulating current when inverters are operated in parallel according to an embodiment;

[0040] Figure 3 A flowchart of generating a first adjustment signal according to an embodiment;

[0041] Figure 4 A flowchart of generating a first adjustment signal according to another embodiment;

[0042] Figure 5 A flowchart of generating a second adjustment signal according to an embodiment;

[0043] Figure 6 FIG. 4 is a circuit diagram of a parallel inverter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0047] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0048] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least part of an element” means part or all of an element.

[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0050] like Figure 1 As shown, a DC circulating current suppression system for inverters in parallel operation is provided, the system comprises a plurality of inverters 1 and a host, the plurality of inverters are connected in parallel and communicate with the host via a CAN bus, the host sends a carrier signal to each of the inverters at fixed intervals. The inverter 1 comprises a bus 10, a balancing bridge circuit 11 connected in parallel to the bus, a three-phase bridge circuit 12, and a controller 13.

[0051] The balanced bridge circuit 11 includes an upper bridge arm circuit 110, a lower bridge arm circuit 111 and a balanced inductor L1. The upper bridge arm circuit 110 and the lower bridge arm circuit 111 are connected in series. One end of the balanced inductor L1 is connected to the midpoint of the upper bridge arm circuit 110 and the lower bridge arm circuit 111. The other end of the balanced inductor L1 is connected to the midpoint of the busbar and the output end of the three-phase bridge circuit 12 to form an output neutral line N of the inverter. The output neutral lines N of each inverter are short-circuited.

[0052] The controller 13 of each inverter is used to collect the first current i on the balancing inductor L1 of the balancing bridge circuit 11. L , the second current i output from the bus midpoint C , the U / V / W three-phase current DC component i at the output end of the three-phase bridge circuit doa 、i dob 、i doc The second current value i C The voltage difference between the first inverter bus and the second inverter bus includes the fluctuating interference current generated by the voltage difference between the first inverter bus and the second inverter bus; based on the first current i L and the second current i C , generating a first regulating signal duty; the first regulating signal acts on the upper bridge arm circuit 110 and the lower bridge arm circuit 111, regulating the first current value and the fluctuating interference current to offset each other, so as to suppress the DC circulating current between the output neutral lines of each inverter caused by the bus voltage difference; based on the DC component i of each phase current doa 、i dob 、i doc , generating a corresponding second adjustment signal U AC-refa , U AC-refb , U AC-refc and controlling the second regulating signal to act on the three-phase bridge circuit 12 to adjust the corresponding DC component of the current to suppress the DC circulating current between the output neutral lines of each inverter caused by the DC component of the three-phase current.

[0053] In one embodiment, the controller 13 is further configured to: based on the carrier period of the carrier signal, generate a first current i collected within the carrier period. L Calculate the first current average value; obtain the first deviation between the first current average value and the preset current reference value, perform proportional integral adjustment on the first deviation, and obtain the balanced bridge current average value loop; according to the first current i L and the second current i C , perform voltage and current dual closed-loop regulation on the average current loop of the balanced bridge to generate the first regulation signal duty.

[0054] In one embodiment, the controller 13 is further configured to: according to the carrier period of the carrier signal, calculate the DC component i of each phase current collected in the carrier period. doa 、i dob 、i doc , calculate the average value of the DC component of each phase; obtain the fourth deviation between the average value of the DC component of each phase and the preset current reference value, perform proportional integral adjustment on the fourth deviation, and obtain the average value loop of the DC component of each phase; obtain the instantaneous value loop of the reference voltage of the three-phase bridge circuit; respectively add and sum the average value loop of the DC component of each phase and the instantaneous value loop of the reference voltage to generate a second adjustment signal U corresponding to each phase in the three-phase bridge circuit AC-refa , U AC-refb , U AC-refc .

[0055] like Figure 2 As shown, a DC circulating current suppression method for inverters in parallel operation is provided, which is applied to Figure 1 The system shown, taking the controller of each inverter as an example, specifically includes the following steps 201 to 203.

[0056] Step 201: based on the fixed period of the carrier signal, collect the first current i on the balanced inductor of the balanced bridge circuit. L , the second current i output from the bus midpoint C , the three-phase current DC component i at the output end of the three-phase bridge circuit doa 、i dob 、i doc The second current value includes the fluctuating interference current caused by the voltage difference between different inverter bus bars.

[0057] Step 202, based on the first current and the second current, generate a first adjustment signal; and control the first adjustment signal to act on the upper bridge arm circuit and the lower bridge arm circuit, adjust the first current value and the fluctuating interference current to offset each other, so as to suppress the voltage difference between the different inverter bus bars from causing the DC circulating current between the output neutral lines of each inverter.

[0058] Step 203, based on the DC component of the current of each phase, generate a corresponding second adjustment signal; and control the second adjustment signal to act on the three-phase bridge circuit to adjust the corresponding DC component of the current to suppress the DC circulating current between the output neutral lines of each inverter caused by the DC component of the three-phase current.

[0059] Since the output neutral lines N are all short-circuited when the inverters are connected in parallel, that is, the bus midpoints of each inverter are connected together, the zero-sequence impedance in the entire parallel loop is very small, and when the working power of each inverter is different, there are differences between the buses of different inverters, which can easily cause a large DC loop between the output neutral lines N and damage the device. In order to reduce the DC loop, the conventional practice in the prior art is to control the voltage between the upper and lower buses of multiple inverters to be the same, but this is not guaranteed in actual operation, and the current on the output neutral line N cannot be sampled.

[0060] Therefore, the present application sends a carrier signal to the controller of each inverter at a fixed period through the host, and the controller of each inverter fine-tunes its own carrier period according to the carrier signal to achieve carrier synchronization of different inverters and reduce the high-frequency circulating current in the DC circulating current. Then the controller collects the first current output by the balanced bridge circuit in each period according to the synchronized carrier period, and the second current i output at the midpoint of the busbar C , the three-phase current DC component i at the output end of the three-phase bridge circuit doa 、i dob 、i doc , a first regulating signal is generated according to the first current and the second current. The first regulating signal adjusts the magnitude of the first current by controlling the conduction state of the upper bridge arm circuit and the lower bridge arm circuit in the balanced bridge circuit, so that the first current and the fluctuating interference current in the second current cancel each other out, thereby suppressing the voltage difference between different inverter buses from causing low-frequency DC circulating current between the output neutral lines of each inverter. In addition to the DC circulating current between the upper and lower buses, since the output neutral line N is also connected to the output end of the three-phase bridge circuit, if there is a voltage difference between the output end voltage of the three-phase AC of the inverter and the 220V mains, then the three-phase output end of the three-phase bridge circuit will generate a corresponding current DC component, thereby generating a low-frequency DC circulating current on the output neutral line N. Therefore, the present application is also based on the three-phase current DC component i at the output end of the three-phase bridge circuit. doa 、i dob 、i doc , respectively generate each corresponding second adjustment signal to control the output terminal voltage of the three-phase bridge circuit to be close to 220V AC power, thereby adjusting the corresponding DC component of the current to approach 0, so as to suppress the DC circulation between the output neutral lines of each inverter caused by the DC component of the three-phase current.

[0061] In this embodiment, each inverter is controlled to generate a first adjustment signal and a second adjustment signal according to the carrier period of the host to act on the balancing bridge circuit and the three-phase bridge circuit, thereby reducing the DC circulating current on the output neutral line caused by the DC current output by the balancing bridge circuit, the bus midpoint, and the three-phase bridge circuit.

[0062] In one embodiment, Figure 3As shown, step 202 generates a first adjustment signal based on the first current and the second current, and specifically includes the following steps 301 to 303.

[0063] Step 301: according to the carrier period of the carrier signal, obtain a first current average value of the first current collected within the carrier period.

[0064] Step 302: Obtain a first deviation between the first current average value and a preset current reference value, and perform proportional-integral adjustment on the first deviation to obtain a balanced bridge current average value loop.

[0065] Step 303: Perform voltage and current double closed-loop regulation on the balanced bridge current average value loop according to the first current and the second current to generate the first regulation signal.

[0066] Specifically, the first current is sampled in each carrier cycle, and the average value of multiple first current values ​​sampled in the carrier cycle is calculated to obtain the first current average value i L-average If it is necessary to suppress the DC circulating current between the output neutral lines N of each parallel inverter, it is necessary to ensure that the average value of the first current on each inverter is i L-average is near 0A. However, due to busbar differences, the first current average value i L-average will deviate from 0A, therefore, the preset current reference value is set to 0. Calculate the first deviation between the first current average value and the preset current reference value, and use the PI regulator to perform proportional integral regulation on the first deviation to obtain the balanced bridge current average value loop V ref Then, according to the first current i L The sampling value of the second current i output at the midpoint of the different inverter buses C The average value of the balanced bridge current loop V ref A PI regulator is used to perform dual closed-loop regulation of voltage and current to generate the first regulation signal duty.

[0067] In this embodiment, by performing proportional integral regulation and voltage-current dual closed-loop regulation on the average value of the first current within the carrier period, a first regulation signal is generated to act on the upper and lower bridge arm circuits of the balanced bridge circuit, thereby regulating the first current i outputted from the balanced circuit. L With the second current i C The fluctuating interference currents in the inverter cancel each other out and gradually return to near 0A, suppressing the DC circulating current caused by the bus voltage difference between the upper and lower inverters.

[0068] In one embodiment, if Figure 4 As shown, step 303 performs voltage and current dual closed-loop regulation on the average current loop of the balanced bridge current according to the first current and the second current to generate the first regulation signal, which specifically includes the following steps 401 to 403.

[0069] Step 401: Obtain the voltage difference between the bus midpoints of different inverters according to the second current.

[0070] Step 402, obtaining a second deviation between the balancing bridge current average value loop and the bus voltage difference, performing proportional-integral regulation on the second deviation, and obtaining a voltage closed-loop regulation output value.

[0071] Step 403: Obtain a third deviation between the voltage closed-loop regulation output value and the first current, and perform proportional-integral regulation on the third deviation to obtain the first regulation signal.

[0072] Specifically, according to the second current i C The size of the busbar midpoints of the upper and lower inverters determines the voltage difference V diff . Calculate the average value of the balanced bridge current ring V ref The second deviation between the voltage difference at the midpoint of the busbar and the voltage difference at the midpoint of the busbar is adjusted proportionally and integrally by a PI regulator to realize voltage loop control and obtain a voltage closed-loop regulation output value i L-ref Finally, the voltage closed-loop regulation output value i is calculated L-ref The first current i L The third deviation is adjusted by proportional-integral adjustment using a PI regulator to implement current loop control, and a first adjustment signal duty is output.

[0073] In this embodiment, the first adjustment signal is generated by performing voltage and current dual closed-loop adjustment on the average value loop of the balanced bridge current, thereby improving the accuracy of the first adjustment signal.

[0074] In one embodiment, Figure 5 As shown, step 203 generates a corresponding second adjustment signal based on each of the current DC components, specifically including the following steps 501 to 504:

[0075] Step 501 , according to the carrier cycle of the carrier signal, for the DC components of the current of each phase collected within the carrier cycle, an average value of the DC components of each phase is calculated.

[0076] Step 502 , obtaining a fourth deviation between the average value of the DC component of each phase and a preset current reference value, and performing proportional-integral adjustment on the fourth deviation to obtain a DC component average value loop of each phase.

[0077] Step 503, obtaining the instantaneous value loop of the reference voltage of the three-phase bridge circuit.

[0078] Step 504 , respectively add and sum the DC component average value loop and the reference voltage instantaneous value loop of each phase to generate a corresponding second adjustment signal in the three-phase bridge circuit.

[0079] Specifically, according to each carrier cycle, the DC component i of each phase current is doa 、i dob 、i doc Sampling is performed, and the DC component i of each phase current sampled within the carrier period is doa 、i dob 、i doc The average value of multiple values ​​is calculated to obtain the average value of the DC component of each phase i doa-average 、i dob-average 、i doc-average Calculate the fourth deviation between the average value of the DC component of each phase and the preset current reference value 0A, and use the PI regulator to perform proportional integral regulation on the fourth deviation to obtain the average value of the DC component of each phase. f . Obtain the instantaneous value loop of the reference voltage of the three-phase bridge circuit, wherein the instantaneous value loop of the reference voltage is the current DC component average value loop V f The voltage difference between the 220V AC mains is calculated by dividing the average value of the DC component of each phase by V f The instantaneous value of the reference voltage is added and summed to generate a second adjustment signal U corresponding to each of the three-phase bridge circuits. AC-refa , U AC-refb , U AC-refc .

[0080] In one embodiment, Figure 6 As shown, a circuit structure diagram of a parallel inverter is provided, wherein the upper arm circuit 110 of the balanced bridge circuit 11 includes a first switch tube Q1, and the lower arm circuit 111 includes a second switch tube Q2, and the first switch tube Q1 and the second switch tube Q2 are complementary and conductive. The three-phase bridge circuit 12 includes three parallel phase-controlled circuits 121, and each phase-controlled circuit 121 includes a third switch tube Q3, a third switch tube Q4, a phase inductor L2, and a phase capacitor C1 connected in series. The third switch tube Q3 and the fourth switch tube Q4 are connected in series and complementary and conductive, one end of the phase inductor L2 is connected to the midpoint of the third switch tube and the fourth switch tube, and the other end is connected to one end of the phase capacitor C1, and the other end of the phase capacitor C1 is connected to the other end of the balanced inductor L1 as the output end of the three-phase bridge circuit, forming the output neutral line N of the inverter.

[0081] It should be noted that the function of the balancing inductor L1 and each phase inductor L2 is to slowly increase or slowly decrease the current passing therethrough.

[0082] Preferably, step 202 controls the first adjustment signal to act on the upper bridge arm circuit or the lower bridge arm circuit to adjust the first current value and the fluctuating interference current to offset each other, which specifically includes the following contents:

[0083] When the first current i L When the first current i is less than the preset current reference value, the first regulating signal duty is controlled to close and turn on the first switch tube Q1 and turn off and turn off the second switch tube Q2, so as to regulate the first current i L The first current i gradually increases to near the preset current reference value of 0A, and cancels out the fluctuating interference current. L When it is greater than the preset current reference value, the first adjustment signal duty is controlled to turn off the first switch tube Q1 and turn on the second switch tube Q2, so as to gradually reduce the first current to near the preset current reference value of 0A, thereby offsetting the fluctuating interference current.

[0084] Preferably, step 203 controls the second regulating signal to act on the three-phase bridge circuit to regulate the corresponding DC component of the current, so that the second regulating signal U AC-refa For example, the specific contents include:

[0085] When the DC component of the current on the phase inductor L2 is doa When the current is less than the preset reference value 0A, the second regulating signal U AC-refa The third switch tube Q3 is closed and turned on, and the fourth switch tube Q4 is turned off and turned off, so as to adjust the DC component i doa The current gradually increases to near the preset current reference value of 0A. doa When the current is greater than the preset reference value 0A, the second regulating signal U AC-refa The third switch tube Q3 is turned off and the fourth switch tube Q4 is turned on to adjust the DC component i doa Gradually decrease to near the preset current reference value of 0A.

[0086] In this embodiment, the conduction state of the switch tube is controlled by the first adjustment signal and the second adjustment signal, so as to control the DC current on the output neutral line N to approach 0A, suppress the DC circulating current generated after the output neutral lines of multiple inverters are short-circuited, protect and maintain the normal operation of each inverter, and avoid damage to the inverter.

[0087] In one embodiment, before collecting the first current on the balanced inductor of the balanced bridge circuit, the second current output at the bus midpoint, and the three-phase current DC component at the output end of the three-phase bridge circuit in step 201, the method further includes:

[0088] Receive a carrier signal sent by the host; parse the carrier signal, extract the corresponding host carrier phase, and synchronize the host carrier phase to the carrier phase of each inverter.

[0089] Specifically, the controller of each inverter analyzes the carrier signal sent by the host to obtain the carrier phase, that is, the carrier period, of the host, thereby achieving carrier synchronization of each parallel inverter.

[0090] In a preferred embodiment, a method for suppressing DC circulating current in parallel operation of inverters is provided, which is applied to the controllers of each inverter in the DC circulating current suppression system in parallel operation of inverters shown in 1, wherein the circuit diagram of each inverter connected in parallel is as shown in Figure 5 As shown, the specific steps include:

[0091] Step 1: Receive the carrier signal sent by the host, and adjust the carrier period of each controller to synchronize with the host according to the carrier period of the host.

[0092] Step 2: According to the carrier period, collect the first current i on the balanced inductor L1 of the balanced bridge circuit 11 L , the second current i output from the bus midpoint C , the U / V / W three-phase current DC component i at the output end of the three-phase bridge circuit doa 、i dob 、i doc .

[0093] Step 3: According to the carrier period of the carrier signal, the first current i collected in the carrier period is L Calculate the first current average value i L-average . Get the first current average value i L-average The first deviation from the preset current reference value 0A is proportionally and integrally adjusted to obtain the average current loop V of the balanced bridge current. ref According to the second current i C The size of the busbar midpoints of the upper and lower inverters determines the voltage difference V diff . Calculate the average value of the balanced bridge current loop V ref The second deviation between the voltage difference at the midpoint of the busbar and the voltage difference at the midpoint of the busbar is proportionally and integrally regulated by a PI regulator to obtain a voltage closed-loop regulation output value i L-ref . Calculate the voltage closed-loop regulation output value i L-ref The first current i L The third deviation is adjusted by a PI regulator to perform proportional-integral adjustment on the third deviation, and a first adjustment signal duty is outputted.

[0094] Step 4: According to the carrier period, the DC component i of each phase current is doa 、idob 、i doc Sampling is performed, and the DC component i of each phase current sampled within the carrier period is doa 、i dob 、i doc The average value of multiple values ​​is calculated to obtain the average value of the DC component of each phase i doa-average 、i dob-average 、i doc-average Calculate the fourth deviation between the average value of the DC component of each phase and the preset current reference value 0A, and use the PI regulator to perform proportional integral regulation on the fourth deviation to obtain the average value of the DC component of each phase. f . Get the current DC component average value of each phase f The voltage difference between the 220V AC mains is calculated by dividing the average value of the DC component of each phase by V f The voltage difference is added and summed to generate a second adjustment signal U corresponding to each of the three-phase bridge circuits. AC-refa , U AC-refb , U AC-refc .

[0095] Step 5: When the first current i in the carrier cycle L When it is less than 0A, the first regulating signal duty turns on the first switch tube Q1 and turns off the second switch tube Q2, controlling the first current i flowing through the balancing inductor L1. L Gradually increases to near the preset current reference value of 0A. When the first current i L When it is greater than 0A, the first regulation signal duty controls the first switch tube Q1 to be turned off and the second switch tube Q2 to be turned on, so as to control the first current flowing through the balancing inductor L1 to gradually decrease to near 0A.

[0096] Step 6: When the DC component i of the current in the carrier cycle doa 、i dob 、i doc When it is less than 0A, the second adjustment signal U AC-refa , U AC-refb , U AC-refc The third switch tube Q3 in the corresponding phase-controlled circuit is closed and turned on, and the fourth switch tube Q4 is turned off and cut off, so as to adjust the DC component i doa 、i dob 、i doc Gradually increases to near 0A. When the DC component of the current i doa 、i dob 、i doc When it is greater than 0A, the second adjustment signal U AC-refa , U AC-refb , U AC-refcThe third switch tube Q3 in the corresponding phase-controlled circuit is turned off and the fourth switch tube Q4 is turned on to adjust the DC component i doa Gradually decreases to near 0A.

[0097] In this preferred embodiment, by carrier synchronously fine-tuning the deviation value of the upper and lower bus voltages of the DC side parallel inverters and the DC component of each phase current, the DC circulating current on the output neutral line of multiple parallel inverters with different working powers is suppressed, thereby ensuring the safe operation of the circuit.

[0098] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0099] In one embodiment, an electronic device is provided, the electronic device comprising the DC circulating current suppression system for inverters in parallel operation as described in the above embodiments. The electronic device can control the DC circulating current suppression system for inverters in parallel operation to perform the functions described in the above embodiments when in operation.

[0100] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for suppressing DC circulating current when inverters are operated in parallel, wherein: A plurality of inverters are connected in parallel and communicate with a host through a CAN bus, and the host sends a carrier signal to each of the inverters at fixed intervals; the inverter includes a bus, and a balanced bridge circuit and a three-phase bridge circuit connected in parallel to the bus; the balanced bridge circuit includes an upper bridge arm circuit, a lower bridge arm circuit and a balanced inductor, the upper bridge arm circuit is connected in series with the lower bridge arm circuit, one end of the balanced inductor is connected to the midpoint of the upper bridge arm circuit and the lower bridge arm circuit, and the other end of the balanced inductor is connected to the midpoint of the bus and the output end of the three-phase bridge circuit to form an output neutral line of the inverter; the output neutral lines of each inverter are short-circuited; the method comprises: Based on the fixed period of the carrier signal, a first current on the balanced inductor of the balanced bridge circuit, a second current output at the bus midpoint, and a three-phase current DC component at the output end of the three-phase bridge circuit are collected; the second current includes a fluctuating interference current generated by a voltage difference between different inverter buses; Based on the first current and the second current, a first regulating signal is generated; and the first regulating signal is controlled to act on the upper bridge arm circuit and the lower bridge arm circuit to adjust the first current and the fluctuating interference current to offset each other, so as to suppress the DC circulating current between the output neutral lines of each inverter caused by the voltage difference between the busbars of the different inverters; Based on the DC component of the current of each phase, a corresponding second adjustment signal is generated; and the second adjustment signal is controlled to act on the three-phase bridge circuit to adjust the corresponding DC component of the current to suppress the DC circulating current between the output neutral lines of each inverter caused by the DC component of the three-phase current.

2. The method for suppressing DC circulating current in parallel operation of inverters according to claim 1, characterized in that: The generating a first adjustment signal based on the first current and the second current includes: According to the carrier period of the carrier signal, calculating a first current average value of the first current collected within the carrier period; Obtaining a first deviation between the first current average value and a preset current reference value, and performing proportional-integral adjustment on the first deviation to obtain a balanced bridge current average value loop; According to the first current and the second current, voltage and current dual closed-loop regulation is performed on the balance bridge current average value loop to generate the first regulation signal.

3. The method for suppressing DC circulating current in parallel operation of inverters according to claim 2, characterized in that: The performing voltage and current double closed-loop regulation on the average current loop of the balanced bridge current to generate the first regulation signal includes: According to the second current, obtaining a voltage difference between midpoints of the buses of different inverters; Obtaining a second deviation between the voltage difference between the average current loop of the balancing bridge and the midpoint of the busbar, and performing proportional-integral regulation on the second deviation to obtain a voltage closed-loop regulation output value; A third deviation between the voltage closed-loop regulation output value and the first current is obtained, and proportional-integral regulation is performed on the third deviation to obtain the first regulation signal.

4. The method for suppressing DC circulating current in parallel operation of inverters according to claim 3, characterized in that: The upper bridge arm circuit includes a first switch tube, the lower bridge arm circuit includes a second switch tube, and the first switch tube and the second switch tube are complementary and conductive; controlling the first adjustment signal to act on the upper bridge arm circuit and the lower bridge arm circuit to adjust the first current and the fluctuating interference current to offset each other includes: When the first current is less than the preset current reference value, the first regulating signal is controlled to close and turn on the first switch tube and to turn off and cut off the second switch tube, so as to adjust the first current to gradually increase and offset the fluctuating interference current; When the first current is greater than the preset current reference value, the first regulating signal is controlled to turn off the first switch tube and turn on the second switch tube, so that the first current is gradually reduced to offset the fluctuating interference current.

5. The method for suppressing DC circulating current in parallel operation of inverters according to claim 1, characterized in that: The generating a corresponding second adjustment signal based on each of the current DC components includes: According to the carrier cycle of the carrier signal, for the DC components of the current of each phase collected within the carrier cycle, an average value of the DC components of each phase is calculated; Obtaining a fourth deviation between the average value of the DC component of each phase and a preset current reference value, and performing proportional-integral adjustment on the fourth deviation to obtain an average value loop of the DC component of each phase; Obtaining a reference voltage instantaneous value loop of the three-phase bridge circuit; The DC component average value loop and the reference voltage instantaneous value loop of each phase are respectively added and summed to generate each corresponding second adjustment signal in the three-phase bridge circuit.

6. The method for suppressing DC circulating current in parallel operation of inverters according to claim 1, characterized in that: Before collecting the first current on the balanced inductor of the balanced bridge circuit, the second current output at the bus midpoint, and the three-phase current DC component at the output end of the three-phase bridge circuit, the method further includes: Receiving a carrier signal sent by the host; The carrier signal is parsed to extract the corresponding host carrier phase, and the host carrier phase is synchronized to the carrier phase of each inverter.

7. A DC circulating current suppression system for inverters in parallel operation, characterized in that: The system includes a plurality of inverters and a host. The plurality of inverters are connected in parallel and communicate with the host through a CAN bus. The host sends a carrier signal to each of the inverters at fixed intervals. The inverter includes a bus, a balanced bridge circuit connected in parallel to the bus, a three-phase bridge circuit, and a controller. The balanced bridge circuit includes an upper bridge arm circuit, a lower bridge arm circuit, and a balanced inductor. The upper bridge arm circuit is connected in series with the lower bridge arm circuit. One end of the balanced inductor is connected to the midpoint of the upper bridge arm circuit and the lower bridge arm circuit. The other end of the balanced inductor is connected to the midpoint of the bus and the output end of the three-phase bridge circuit to form the output neutral line of the inverter. The output neutral lines of each inverter are short-circuited. The controller is used to: Collecting a first current on the balanced inductor of the balanced bridge circuit, a second current output at the bus midpoint, and a three-phase current DC component at the output end of the three-phase bridge; the second current value includes a fluctuating interference current generated by a voltage difference between different inverter buses; generating a first adjustment signal based on the first current and the second current; The first regulating signal acts on the upper bridge arm circuit and the lower bridge arm circuit to regulate the first current and the fluctuating interference current to offset each other, so as to suppress the DC circulating current between the output neutral lines of each inverter caused by the voltage difference between the busbars of different inverters; Based on the DC component of the current of each phase, a corresponding second adjustment signal is generated; and the second adjustment signal is controlled to act on the three-phase bridge circuit to adjust the corresponding DC component of the current to suppress the DC circulating current between the output neutral lines of each inverter caused by the DC component of the three-phase current.

8. The DC circulating current suppression system for inverters in parallel operation according to claim 7, characterized in that: The controller is also used to obtain a first current average value for the first current collected within the carrier period according to the carrier period of the carrier signal; obtain a first deviation between the first current average value and a preset current reference value, perform proportional-integral adjustment on the first deviation, and obtain a balanced bridge current average value loop; perform voltage-current dual closed-loop adjustment on the balanced bridge current average value loop according to the first current and the second current, and generate the first adjustment signal.

9. The DC circulating current suppression system for inverters in parallel operation according to claim 8, characterized in that: The controller is also used to: calculate the average value of the DC component of each phase for the DC component of the current of each phase collected within the carrier period according to the carrier period of the carrier signal; obtain a fourth deviation between the average value of the DC component of each phase and the preset current reference value, and perform proportional-integral adjustment on the fourth deviation to obtain an average value loop of the DC component of each phase; obtain an instantaneous value loop of the reference voltage of the three-phase bridge circuit; and respectively add and sum the average value loop of the DC component of each phase and the instantaneous value loop of the reference voltage to generate a second adjustment signal corresponding to each phase in the three-phase bridge circuit.

10. An electronic device, characterized in that: A DC circulating current suppression system comprising inverters operating in parallel as described in any one of claims 7 to 9.

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