Semiconductor power module packaging structure

Abstract

The invention belongs to the technical field of power module packaging, and particularly relates to a semiconductor power module packaging structure which comprises an insulating substrate, a metal copper layer, a power terminal, a signal terminal and a power chip. The metal copper layer is arranged on the surface of the insulating substrate, and the power terminal, the signal terminal and the power chip are all arranged on the insulating substrate and are electrically connected with the metal copper layer. According to the invention, in a power loop, a copper clamp connection mode is adopted to replace a traditional bonding wire mode, so that the thermal reliability of the module under high-temperature work can be improved; the source electrode of the power chip in the upper bridge is electrically connected with the alternating current terminal busbar by adopting an upper bridge chip connecting copper clamp; the mode that the power chip is directly and electrically connected with the direct-current negative terminal busbar through the lower bridge chip connecting copper clamp is adopted, and the problems of overhigh voltage caused by overhigh parasitic parameters of the semiconductor power module and thermal reliability under high-temperature work are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power module packaging, and in particular relates to a semiconductor power module packaging structure. Background Art

[0002] The application scope of power devices is becoming more and more extensive with the development of technology, such as electric vehicles, photovoltaic power generation, and aerospace. In recent years, wide-bandgap semiconductor power devices with excellent performance in switching speed and loss have attracted people's attention. Silicon carbide (SiC) material is a new type of semiconductor material with excellent switching frequency, thermal conductivity and switching loss. Power modules using SiC devices often use multi-chip parallel connection to increase power scale, which poses a huge challenge to the reliability of power modules.

[0003] Bonding wire connections are widely used for surface electrical connections in power modules due to their low cost, high maturity, and high flexibility. However, bonding wires introduce excessive parasitic parameters, which lead to increased voltage spikes and switching losses, especially in silicon carbide module applications. In addition, the expansion of the working temperature of the bonding wire under long-term high-current working conditions increases the thermomechanical stress, which may lead to failure problems such as shedding and breaking of the bonding wire. Therefore, the development of new packaging structures and connection methods is the primary issue to improve the reliability of power modules. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a semiconductor power module packaging structure to solve the problem of excessive voltage caused by excessively high parasitic parameters of the power module and the thermal reliability problem under high temperature operation.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A semiconductor power module packaging structure, comprising an insulating substrate, a metal copper layer, a power terminal, a signal terminal and a power chip; the metal copper layer is arranged on the surface of the insulating substrate, and the power terminal, the signal terminal and the power chip are all arranged on the insulating substrate and electrically connected to the metal copper layer;

[0007] The power chip comprises an upper bridge chip and a lower bridge chip, wherein the lower bridge chips are arranged in an array in the middle area of ​​the insulating substrate, and the upper bridge chips are symmetrically distributed on both sides of the lower bridge chip;

[0008] The power terminal comprises a first DC positive terminal, a second DC positive terminal, a DC negative terminal and an AC terminal, wherein the first DC positive terminal and the second DC positive terminal are respectively located on both sides of the DC negative terminal;

[0009] The first DC positive terminal is connected to the drain of one chip on one side of the upper bridge chip, the second DC positive terminal is connected to the drain of the other chip on the upper bridge chip, and the AC terminal is electrically connected to the source of all chips in the upper bridge chip, thereby forming a power loop from the DC positive terminal to the AC terminal;

[0010] The AC terminal is electrically connected to the drains of all chips in the lower bridge chip, and the DC negative terminal is electrically connected to the sources of all chips in the lower bridge chip, thereby forming a power loop from the AC terminal to the DC negative terminal.

[0011] Further, the power terminal includes a first drain lead terminal, a first gate drive signal lead terminal and a first Kelvin source lead terminal arranged on one side of the AC terminal, and a second gate drive signal lead terminal and a second Kelvin source lead terminal arranged on the other side of the AC terminal;

[0012] The first drain lead terminal is electrically connected to the drain of the upper bridge chip, the first gate drive signal lead terminal is electrically connected to the gate of the upper bridge chip, and the first Kelvin source lead terminal is electrically connected to the source of the upper bridge chip; the first gate drive signal lead terminal is electrically connected to the gate of the lower bridge chip, and the second Kelvin source lead terminal is electrically connected to the source of the lower bridge chip.

[0013] Furthermore, it also includes an AC terminal busbar, a DC negative terminal busbar, a DC positive terminal busbar, a first gate drive signal busbar, a second gate drive signal busbar and a Kelvin source busbar;

[0014] The drain of the upper bridge chip is electrically connected to the first DC positive terminal, the second DC positive terminal and the first drain lead terminal through the DC positive terminal busbar, the source of the upper bridge chip is electrically connected to the AC terminal and the first Kelvin source lead terminal through the AC terminal busbar, and the gate of the upper bridge chip is electrically connected to the first gate drive signal lead terminal through the first gate drive signal busbar;

[0015] The drain of the lower bridge chip is electrically connected to the AC terminal through the AC terminal busbar, the source of the lower bridge chip is electrically connected to the DC negative terminal through the DC negative terminal busbar, and is electrically connected to the second Kelvin source lead-out terminal through the Kelvin source busbar, and the gate of the lower bridge chip is electrically connected to the second gate drive signal lead-out terminal through the second gate drive signal busbar.

[0016] Furthermore, the second gate drive signal busbar and the Kelvin source busbar are both arranged in the middle area of ​​the AC terminal busbar, and are electrically connected to the gate and source of the lower bridge chip through bonding wires, and are electrically connected to the second Kelvin source lead terminal and the second gate drive signal lead terminal through bonding wires.

[0017] Furthermore, the first gate drive signal busbar is arranged around the edge of the insulating substrate and is electrically connected to the gate of the upper bridge chip and the first gate drive signal lead-out terminal respectively through bonding wires.

[0018] Furthermore, it also includes a temperature-sensing resistor arranged on the insulating substrate and electrically connected to the metal copper layer, and the power terminal also includes a first temperature-sensing pin and a second temperature-sensing pin electrically connected to the temperature-sensing resistor.

[0019] The beneficial effects of the present invention are:

[0020] The present invention provides a semiconductor power module packaging structure, in which the power chip layout is axially symmetrically distributed, ensuring that the currents of the upper and lower bridge arms of the power circuit are equal, thereby achieving a more uniform current distribution effect; in the power circuit, a connecting copper clip method is used instead of a traditional bonding wire method to improve the thermal reliability of the module under high-temperature operation; an upper bridge chip connecting copper clip is used to electrically connect the source of the power chip in the upper bridge with an AC terminal busbar, thereby reducing the parasitic parameters introduced compared to the bonding wire; a lower bridge chip connecting copper clip is used to directly electrically connect the power chip with a DC negative terminal busbar, thereby reducing the parasitic parameters of the circuit through the circuit cancellation principle, thereby solving the problem of excessive voltage caused by excessively high parasitic parameters of the semiconductor power module and the thermal reliability problem under high-temperature operation.

[0021] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 is an internal schematic diagram of a semiconductor power module packaging structure in an embodiment;

[0024] Figure 2 Schematic diagram of the structure of the upper bridge chip connection copper clip in the embodiment;

[0025] Figure 3 This is a schematic diagram of the structure of the copper clip connecting the lower bridge chip in the embodiment;

[0026] Figure 4 It is an overall schematic diagram of a semiconductor power module packaging structure in an embodiment.

[0027] Figure markings: 1-first DC positive terminal; 2-DC negative terminal; 3-second DC positive terminal; 4-insulating substrate; 5-power chip; 6-Kelvin source busbar; 7-second gate drive signal busbar; 8-first drain lead terminal; 9-first gate drive signal lead terminal; 10-first Kelvin source lead terminal; 11-AC terminal; 12-second Kelvin source lead terminal; 13-second gate drive signal lead terminal; 14-first temperature sensing pin; 15-second temperature sensing pin; 16-temperature sensing resistor; 17-first gate drive signal busbar; 18-gate drive resistor; 19-lower bridge chip connecting copper clip; 20-upper bridge chip connecting copper clip; 21-AC terminal busbar; 22-DC negative terminal busbar; 23-DC positive terminal busbar. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0029] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0030] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0031] The present invention proposes a semiconductor power module packaging structure, which includes an insulating substrate, a plurality of power chips, and a metal terminal. A metal copper layer is provided on the surface of the insulating substrate, and the metal terminal is electrically connected to the metal copper layer. The plurality of power chips are all located on the insulating substrate and are electrically connected to the metal copper layer, wherein a portion of the power chips are connected in parallel to form a lower bridge of the semiconductor power module, and another portion of the power chips are connected in parallel to form an upper bridge of the semiconductor power module, and the number of power chips in the upper bridge and the lower bridge is the same. In addition, the power chips in the upper bridge and the lower bridge are arranged in an array, and the power chips in the upper bridge are symmetrically distributed on both sides of the power chips in the lower bridge.

[0032] Through this setting method, since the upper bridges and lower bridges in the layout of multiple power chips are arranged in an array, the current imbalance can be reduced, avoiding the situation where the current of individual power chips is too large and the local temperature is too high.

[0033] It should be noted that the power chip can be a switch chip, specifically a MOS tube, a triode, etc., and multiple power chips form a single-phase half-bridge structure. In addition, the present invention does not limit the material and number of power chips. For example, the power chip can be a silicon carbide chip, and the number of power chips can be 10, 16 or 20.

[0034] See also Figure 1 to Figure 4 , is a semiconductor power module packaging structure proposed in one embodiment of the present invention. In this embodiment, the power chip 5 is a MOS tube, the number of MOS tubes is 16, and the upper bridge and the lower bridge each have 8 MOS tubes. Among them, the 8 MOS tubes of the lower bridge are arrayed in the middle area of ​​the insulating substrate 4, and the 8 MOS tubes of the upper bridge are symmetrically distributed on both sides of the lower bridge, with 4 MOS tubes on each side. Through the symmetrical and mirror-image arrangement of the upper bridge and the lower bridge parallel power chips, the imbalance of the current can be reduced, and the current of individual chips can be avoided to be too large. At the same time, it is also convenient to lead out the bonding wires of the chip, which is convenient for installation.

[0035] In this embodiment, the outer structure of the power module is rectangular. The metal terminal includes a power terminal and a signal terminal, wherein the power terminal includes a DC negative terminal 2, an AC terminal 11 and two DC positive terminals, the two DC positive terminals are respectively a first DC positive terminal 1 and a second DC positive terminal 3, wherein the DC negative terminal 2 and the two DC positive terminals are arranged on the same side of the power module, and the module positive pole and the module negative pole are led out in parallel, and the two DC positive terminals are respectively located on both sides of the DC negative terminal 2, and the two DC positive terminals are symmetrically arranged. By symmetrically arranging the two DC positive terminals, the parasitic inductance of the entire power circuit can be reduced, and the turn-off voltage spike and switch oscillation can be further reduced, thereby improving the performance of the power module. The AC terminal 9 and the signal terminal are located on the other side of the power module, and for the portability of the connection and the miniaturization of the power module as a whole, the signal terminal is divided into two parts, and the two signal terminals are respectively located on both sides of the AC terminal 9.

[0036] Specifically, the signal terminal includes a first drain lead terminal 8, a first gate drive signal lead terminal 9, a first Kelvin source lead terminal 10, a second Kelvin source lead terminal 12, a second gate drive signal lead terminal 13, a first temperature sensing pin 14, and a second temperature sensing pin 15. Among them, the first drain lead terminal 8, the first gate drive signal lead terminal 9, and the first Kelvin source lead terminal 10 are located on one side of the AC terminal 11, and the second Kelvin source lead terminal 12, the second gate drive signal lead terminal 13, the first temperature sensing pin 14, and the second temperature sensing pin 15 are located on the other side of the AC terminal 11.

[0037] In this embodiment, the selected chip 5 is a MOS tube, the drain of the power chip in the upper bridge is electrically connected to the DC positive terminal, the drain of the chip in the lower bridge is electrically connected to the AC terminal 11, the source of the upper bridge chip is electrically connected to the AC terminal (AC terminal busbar 21) through the upper bridge chip connecting copper clip 20, and the source of the lower bridge chip is electrically connected to the DC negative terminal (DC negative terminal busbar 22) through the lower bridge chip connecting copper clip 19. Figure 4 As shown, the drain of the upper bridge chip on one side is connected to the first DC positive terminal 1 through the DC positive terminal busbar 23, and the source is connected to the AC terminal 9, and the drain of the upper bridge chip on the other side is connected to the second DC positive terminal, and the source is connected to the AC terminal 9 (AC terminal busbar 21) through the upper bridge chip connecting copper clip 20, forming a symmetrical power loop flowing from the DC positive terminal to the AC terminal; and the drain of the chip of the lower bridge is connected to the AC terminal 9, and the source is connected to the DC negative terminal 2 (DC negative terminal busbar 22) through the lower bridge chip connecting copper clip 19, forming a power loop flowing from the AC terminal to the DC negative terminal.

[0038] In this way, the power chip 5 is connected to the metal copper layer on the insulating substrate 4 by connecting the copper clips to form a power loop. The power loop is short and symmetrically distributed, so that the power loop has a lower parasitic inductance, and the parasitic parameters are further reduced by connecting the copper clips. At the same time, the 16 power chips 5 are evenly distributed on the insulating substrate, and the heat generated by the chips can be evenly dissipated, which can avoid excessive thermal coupling between chips and improve the reliability of the power module.

[0039] In this embodiment, in order to reduce the interference between the power circuit and the drive circuit and improve the switching efficiency of the power chip 5, a Kelvin source connection method is adopted when connecting the power chip 5.

[0040] The packaging structure also includes an AC terminal busbar 21 and a Kelvin source busbar 6. The first Kelvin source lead-out terminal 10 is located on the AC terminal busbar 21 to realize electrical connection with the source of the upper bridge chip. The second Kelvin source lead-out terminal 12 is connected to the Kelvin source busbar 6 through a bonding wire to realize electrical connection with the source of the lower bridge chip.

[0041] The packaging structure also includes a first gate drive signal bus bar 17 and a second gate drive signal bus bar 7. Bonding wires are used to lead all the gates of the upper bridge chip to the first gate drive signal bus bar 17 to achieve electrical connection. The gate of the lower bridge chip is electrically connected to the second gate drive signal bus bar 7 through bonding wires, and the second gate drive signal bus bar 7 is then electrically connected to the second gate drive signal lead-out terminal 13 through bonding wires.

[0042] Optionally, the first gate drive signal busbar 17 or the second gate drive signal busbar 7 is located on the upper side and left and right sides of the upper bridge or lower bridge chip loop, that is, the upper end and left and right edges of the insulating substrate; by connecting to the first gate drive signal lead-out terminal 9, a surround integrated structure is finally formed.

[0043] Furthermore, the packaging structure also includes a DC negative terminal busbar 22 and a DC positive terminal busbar 23, the DC negative terminal busbar 22 is respectively connected to the DC negative terminal 2 and the lower bridge chip connecting copper clip 19, and the DC positive terminal busbar 23 is respectively connected to the first DC positive terminal 1, the second DC positive terminal 3 and the first drain lead-out terminal 8, so that the drain of the upper bridge chip is respectively connected to the first DC positive terminal 1, the second DC positive terminal 3 and the first drain lead-out terminal 8 through the DC positive terminal busbar 23.

[0044] In addition, in order to detect the temperature of the power chip 5 in real time, the power module is also provided with a temperature-sensing resistor 16, which can be a platinum resistance temperature sensor, and the temperature-sensing resistor 16 is arranged at the side of the power module to facilitate the layout of the entire module and make it close to the chip to achieve real-time monitoring of the module working temperature. A temperature measurement output terminal is correspondingly arranged in the metal terminal, and the temperature measurement output terminal includes a first temperature sensing pin 14 and a second temperature sensing pin 15. The temperature sensing resistor 16 is electrically connected to the first temperature sensing pin 14 and the second temperature sensing pin 15 respectively, so that the junction temperature of the power chip 5 can be accurately estimated.

[0045] Optionally, the connecting copper clip includes an upper bridge chip connecting copper clip 20 and a lower bridge chip connecting copper clip 19, the number of the upper bridge chip connecting copper clips 20 is the same as the number of the upper bridge power chips, and the upper bridge power chip is electrically connected to the AC terminal busbar 22, and then electrically connected to the first Kelvin source lead terminal 10, and the lower bridge chip connecting copper clip 19 simultaneously electrically connects all the lower bridge chips to the DC negative terminal busbar 22, and then electrically connected to the DC negative terminal 2.

[0046] Optionally, the packaging structure also includes multiple gate drive resistors 18, which can be soldered to the first gate drive signal bus 17 and the second gate drive signal bus 7 by spot tinning, and the number of gate drive resistors 18 is the same as the number of power chips 5 and corresponds one to one, and is electrically connected to the power chip 5 by bonding. In this way, integrating the gate drive resistors 18 can realize functions such as controlling the charging and discharging speed of the power chip 5 and preventing gate signal oscillation.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A semiconductor power module packaging structure, characterized in that: It comprises an insulating substrate, a metal copper layer, a power terminal, a signal terminal and a power chip; the metal copper layer is arranged on the surface of the insulating substrate, and the power terminal, the signal terminal and the power chip are all arranged on the insulating substrate and electrically connected to the metal copper layer; The power chip comprises an upper bridge chip and a lower bridge chip, wherein the lower bridge chips are arranged in an array in the middle area of ​​the insulating substrate, and the upper bridge chips are symmetrically distributed on both sides of the lower bridge chip; The power terminal comprises a first DC positive terminal, a second DC positive terminal, a DC negative terminal and an AC terminal, wherein the first DC positive terminal and the second DC positive terminal are respectively located on both sides of the DC negative terminal; The first DC positive terminal is connected to the drain of one chip on one side of the upper bridge chip, the second DC positive terminal is connected to the drain of the other chip on the upper bridge chip, and the AC terminal is electrically connected to the source of all chips in the upper bridge chip through the upper bridge chip connecting copper clip, thereby forming a power loop from the DC positive terminal to the AC terminal; The AC terminal is electrically connected to the drain of all chips in the lower bridge chip, and the DC negative terminal is electrically connected to the source of all chips in the lower bridge chip through the lower bridge chip connecting copper clip, thereby forming a power loop from the AC terminal to the DC negative terminal.

2. The semiconductor power module packaging structure according to claim 1, characterized in that: The power terminal includes a first drain lead terminal, a first gate drive signal lead terminal and a first Kelvin source lead terminal arranged on one side of the AC terminal, and a second gate drive signal lead terminal and a second Kelvin source lead terminal arranged on the other side of the AC terminal; The first drain lead terminal is electrically connected to the drain of the upper bridge chip, the first gate drive signal lead terminal is electrically connected to the gate of the upper bridge chip, and the first Kelvin source lead terminal is electrically connected to the source of the upper bridge chip; the first gate drive signal lead terminal is electrically connected to the gate of the lower bridge chip, and the second Kelvin source lead terminal is electrically connected to the source of the lower bridge chip.

3. The semiconductor power module according to claim 2, characterized in that: Also includes an AC terminal busbar, a DC negative terminal busbar, a DC positive terminal busbar, a first gate drive signal busbar, a second gate drive signal busbar, and a Kelvin source busbar; The drain of the upper bridge chip is electrically connected to the first DC positive terminal, the second DC positive terminal and the first drain lead terminal through the DC positive terminal busbar, the source of the upper bridge chip is electrically connected to the AC terminal and the first Kelvin source lead terminal through the AC terminal busbar, and the gate of the upper bridge chip is electrically connected to the first gate drive signal lead terminal through the first gate drive signal busbar; The drain of the lower bridge chip is electrically connected to the AC terminal through the AC terminal busbar, the source of the lower bridge chip is electrically connected to the DC negative terminal through the DC negative terminal busbar, and is electrically connected to the second Kelvin source lead-out terminal through the Kelvin source busbar, and the gate of the lower bridge chip is electrically connected to the second gate drive signal lead-out terminal through the second gate drive signal busbar.

4. The semiconductor power module according to claim 3, characterized in that: The second gate drive signal busbar and the Kelvin source busbar are both arranged in the middle area of ​​the AC terminal busbar, and are electrically connected to the gate and source of the lower bridge chip through bonding wires, and are electrically connected to the second Kelvin source lead terminal and the second gate drive signal lead terminal through bonding wires.

5. The semiconductor power module according to claim 3, characterized in that: The first gate drive signal busbar is arranged around the edge of the insulating substrate and is electrically connected to the gate of the upper bridge chip and the first gate drive signal lead-out terminal through bonding wires.

6. The semiconductor power module according to any one of claims 1 to 5, characterized in that: It also includes a temperature sensing resistor arranged on the insulating substrate and electrically connected to the metal copper layer, and the power terminal also includes a first temperature sensing pin and a second temperature sensing pin electrically connected to the temperature sensing resistor.

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