Source / drain structure dopant cluster design

Abstract

The invention relates to a source / drain structure dopant cluster design. The present disclosure describes a semiconductor device having a source / drain structure with dopant clusters. The semiconductor device includes a channel structure on a substrate, and a source / drain structure on the substrate and adjacent to the channel structure. The source / drain structure includes a first epitaxial layer on the substrate, sidewalls of the channel structure and a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The second epitaxial layer includes clusters of dopants extending in a direction of the channel structure.

Description

Technical Field

[0001] The present disclosure relates to source / drain structure dopant cluster design. Background Art

[0002] As semiconductor technology advances, there is a growing demand for greater storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This shrinkage increases the complexity of semiconductor manufacturing processes and increases the difficulty of process control of semiconductor devices. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a channel structure located on a substrate; and an epitaxial structure located on the substrate and adjacent to the channel structure, wherein the epitaxial structure comprises: a first epitaxial layer located on a sidewall of the channel structure, wherein the first epitaxial layer comprises a cluster of dopants extending in a direction of the channel structure; and a second epitaxial layer located on the first epitaxial layer.

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first channel structure and a second channel structure, located on a substrate; and a source / drain (S / D) structure, located between the first channel structure and the second channel structure, wherein the S / D structure comprises: a first epitaxial layer, located on side walls of the first channel structure and the second channel structure, wherein the first epitaxial layer comprises a first cluster of dopants extending from the first channel structure to the second channel structure; and a second epitaxial layer, located on the first epitaxial layer.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a channel structure on a substrate; forming a first epitaxial layer on a sidewall of the channel structure and the substrate, wherein the first epitaxial layer comprises a cluster of dopants extending in a direction of the channel structure; and forming a second epitaxial layer on the first epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 An isometric view of a semiconductor device having a source / drain structure with dopant clusters is shown in accordance with some embodiments.

[0008] Figure 2A and Figure 2BA cross-sectional view of a semiconductor device having a source / drain structure with dopant clusters is shown in accordance with some embodiments.

[0009] Figure 3 A cross-sectional view of a semiconductor device having a source / drain structure with horizontal and tilted dopant clusters is shown in accordance with some embodiments.

[0010] Figure 4A-4D Various shapes of dopant clusters in source / drain structures are shown according to some embodiments.

[0011] Figure 5A-5C Various shapes of channel structures in semiconductor devices according to some embodiments are shown.

[0012] Figure 6 is a flow chart of a method of fabricating a semiconductor device having a source / drain structure with dopant clusters according to some embodiments.

[0013] Figure 7-22B Isometric and cross-sectional views of a semiconductor device having a source / drain structure with dopant clusters at various stages of its fabrication are shown in accordance with some embodiments.

[0014] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. In addition, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] Note that references to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0018] It will be understood that the phraseology or terminology herein is used for the purpose of description rather than limitation, and thus the phraseology or terminology of the specification will be understood by those skilled in the relevant technical field(s) based on the teachings herein.

[0019] In some embodiments, the terms "about" and "substantially" may mean that the value of a given amount varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to percentages of these values ​​as understood by a person skilled in the relevant art(s) based on the teachings herein.

[0020] As the demand for lower power consumption, higher performance and smaller semiconductor devices continues to increase, the size of semiconductor devices continues to shrink. The continued reduction in device size and the continued improvement in device performance requirements may require various process and material improvements, which may have multiple challenges. For example, nanostructured transistors can utilize channels in stacked nanosheets / nanowire configurations to improve device performance. Nanostructured transistors may include finFETs, gate-all-around field effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. However, during the sheet formation process of the channel, the source / drain (S / D) structure of the nanostructured transistor will also be etched, and a gate-S / D short circuit defect will subsequently be formed. The gate-S / D short circuit defect can cause device failure and yield loss.

[0021] Various embodiments in the present disclosure provide example methods for forming an S / D structure with a dopant cluster in a semiconductor device (e.g., a nanostructure transistor) and / or other semiconductor devices in an integrated circuit (IC). In some embodiments, a channel structure may be formed on a substrate. The S / D structure may be formed on the substrate and adjacent to the channel structure. In some embodiments, the S / D structure may include a first epitaxial layer on the substrate, a sidewall of the channel structure and a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. In some embodiments, the second epitaxial layer may include a cluster of dopants extending along the direction of the channel structure. In some embodiments, the first concentration of the dopant in the cluster may be about ten times or more of the concentration of the dopant in the second epitaxial layer. In some embodiments, the cluster of dopants may extend along the intersection of the (111) growth plane of the second epitaxial layer. In some embodiments, the second epitaxial layer may include an additional cluster of dopants along the (111) growth plane of the second epitaxial layer. The cluster of dopants may reduce etching damage to the S / D structure, reduce gate-S / D short defects, and improve device performance and yield.

[0022] Figure 1 An isometric view of a semiconductor device 100 having a source / drain structure with dopant clusters is shown in accordance with some embodiments. Figure 2A and Figure 2B The semiconductor device 100 according to some embodiments is shown in FIG. Figure 1 Partial cross-sectional views along lines AA and BB are shown. Figure 3 A partial cross-sectional view of a semiconductor device 100 having a source / drain structure with horizontal and tilted dopant clusters is shown in accordance with some embodiments. Figure 4A-4D Various shapes of dopant clusters in source / drain structures are shown according to some embodiments. Figure 5A-5C Various shapes of the channel structure in the semiconductor device 100 according to some embodiments are shown.

[0023] In some embodiments, the semiconductor device 100 may include transistors 102A-102C, such as Figure 1As shown. In some embodiments, transistors 102A-102C may include nanostructure transistors. Nanostructure transistors may include finFETs, GAAFETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. Nanostructure transistors may provide channels in a stacked nanosheet / nanowire configuration. In some embodiments, transistors 102A-102C may be n-type field effect transistors (NFETs). In some embodiments, transistors 102A-102C may be p-type field effect transistors (PFETs). In some embodiments, any one of transistors 102A-102C may be an NFET or a PFET. In some embodiments, transistor 102A may be an NFET and transistors 102B and 102C may be PFETs. Although Figure 1 Three transistors are shown, but semiconductor device 100 can have any number of transistors. In addition, semiconductor device 100 can be incorporated into an IC by using other structural elements (e.g., conductive vias, conductive lines, dielectric layers, passivation layers, and interconnects), which are not shown for simplicity. Discussions of elements with the same annotations in transistors 102A-102C apply to each other unless otherwise noted. In addition, the same reference numerals generally represent identical, functionally similar, and / or structurally similar elements.

[0024] refer to Figure 1 5 , a semiconductor device 100 having transistors 102A-102C may be formed on a substrate 104 and may be isolated by a shallow trench isolation (STI) region 106. Each of the transistors 102A-102C may include a fin structure 108, a sidewall spacer 109, a gate dielectric layer 124, a gate structure 112, a gate spacer 114, an inner spacer 121, an S / D structure 110, an etch stop layer (ESL) 116, and an interlayer dielectric (ILD) layer 118. In some embodiments, as shown in FIG. 2 , the transistors 102A-102C may have nanostructures 122-1, 122-2, and 122-3 (collectively referred to as “nanostructures 122”) on the fin structure 108.

[0025] refer to Figure 1-Figure 3, the substrate 104 may include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a silicon wafer). In some embodiments, the substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and / or gallium aluminum arsenide; or (iv) a combination thereof. In addition, the substrate 104 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0026] STI regions 106 can provide electrical isolation between transistors 102A-102C, and with adjacent transistors (not shown) on substrate 104 and / or adjacent active and passive components (not shown) integrated with substrate 104 or deposited on substrate 104. STI regions 106 can be made of dielectric materials. In some embodiments, STI regions 106 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In some embodiments, STI regions 106 can include a multilayer structure.

[0027] refer to Figure 1-Figure 3 , the nanostructure 122 and the fin structure 108 can be formed on the patterned portion of the substrate 104. The embodiments of the nanostructures and fin structures disclosed herein can be patterned by any suitable method. For example, the nanostructures and fin structures can be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. The double patterning process or the multi-patterning process can combine the photolithography process and the self-alignment process to form a pattern with a smaller spacing than that obtainable using a single direct photolithography process, for example. For example, a sacrificial layer is formed on the substrate and patterned using a photolithography process. A self-alignment process can be used to form a spacer next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the nanostructures and the fin structure.

[0028] like Figure 1-Figure 3As shown, the nanostructure 122 and the fin structure 108 may extend along the X-axis of the transistor 102A-102C. In some embodiments, the nanostructure 122 and the fin structure 108 may be disposed on the substrate 104. The nanostructure 122 may include a stack of nanostructures 122-1, 122-2, and 122-3, which may be in the form of nanosheets, nanowires, or nanoribbons. Each nanostructure 122 may serve as a channel structure and form a channel region under the gate structure 112 of the transistor 102A-102C. In some embodiments, the nanostructure 122 and the fin structure 108 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon germanium. The semiconductor material of the nanostructure 122 and the fin structure 108 may be undoped, or may be in-situ doped during its formation process. In some embodiments, as Figure 2A and Figure 3 As shown, the nanostructure 122 below the gate structure 112 may form a channel region of the semiconductor device 100 and represent a current-carrying channel structure of the semiconductor device 100. Figure 2A and Figure 3 Three layers of nanostructures 122 are shown, but transistors 102A- 102C may have any number of nanostructures 122 .

[0029] In some embodiments, the thickness of the nanostructures 122 along the Z axis may be in the range of about 5 nm to about 8 nm. In some embodiments, the width of the nanostructures 122 along the Y axis may be in the range of about 15 nm to about 50 nm. In some embodiments, the spacing between adjacent nanostructures 122 along the Z axis may be in the range of about 8 nm to about 12 nm. In some embodiments, as Figure 5A As shown, nanostructures 122 may have square ends. Figure 5B As shown, the nanostructure 122 may have a protruding end. Figure 5C As shown, the nanostructures 122 may have concave ends.

[0030] refer to Figure 1-Figure 3, the gate dielectric layer 124 may be formed on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer and a high-k dielectric layer that are in direct contact with the nanostructure 122. In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the thickness of the interface layer may be in the range of about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0031] In some embodiments, Figure 1-Figure 3 As shown, the gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and a metal filler. The one or more work function metal layers may include a work function metal to adjust the threshold voltage (V t ). In some embodiments, the gate structures 112 of the NFET and PFET devices may have substantially the same work function metal. In some embodiments, the gate structures 112 of the NFET and PFET devices may have different work function metals. In some embodiments, as Figure 2A and Figure 3 As shown, each nanostructure 122 may be surrounded by a gate structure 112, and thus the gate structure 112 may be referred to as a "gate all around (GAA) structure", and the transistors 102A-102C may also be referred to as "GAA FETs 102A-102C". One or more work function metal layers may surround the nanostructure 122, and may include work function metal to adjust the V t In some embodiments, transistors 102A-102C may include any number of work function metal layers for V t Adjustment (e.g., ultra-low V t , Low V t and standard V t ).

[0032] In some embodiments, the NFETs 102A-102C may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium silicon nitride, or other suitable work function metals. In some embodiments, the PFETs 102A-102C may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbon nitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a stack of metal layers. The metal layer stack may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0033] refer to Figure 1-Figure 3 According to some embodiments, the gate spacer 114 may be disposed on the sidewall of the gate structure 112 and in contact with the gate dielectric layer 124. The sidewall spacer 109 may be disposed on the sidewall of the fin structure 108. The internal spacer 121 may be disposed adjacent to the end of the nanostructure 122 and between the S / D structure 110 and the gate structure 112. The gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, low-k material, and combinations thereof. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include different insulating materials. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include a single insulating layer or a stack of insulating layers. In some embodiments, the gate spacers 114 , the sidewall spacers 109 , and the inner spacers 121 may have a low-k material having a dielectric constant less than about 3.9 (eg, about 3.5, about 3.0, or about 2.8).

[0034] The S / D structure 110 may be disposed on the fin structure 108 and on the opposite side of the gate structure 112. The S / D structure 110 may be used as an S / D region of the transistors 102A-102C. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, a cone, a diamond, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material different from the material of the substrate 104, such as silicon germanium, and strain may be applied to the channel region below the gate structure 112. Since the lattice constant of such an epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is strained to improve the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include (i) semiconductor materials, such as germanium and silicon; (ii) compound semiconductor materials, such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys, such as silicon germanium and gallium arsenide phosphide.

[0035] In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped with n-type dopants (e.g., phosphorus and arsenic) during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors may be used, such as phosphine, arsine, and other n-type doping precursors. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped with p-type dopants (e.g., boron, indium, and gallium) during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors may be used, such as diborane (B 2 H 6 ), Boron trifluoride (BF 3 ) and other p-type doping precursors.

[0036] In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. Figure 1-Figure 3 As shown, the S / D structure 110 may include an epitaxially grown first epitaxial layer 110-1, a second epitaxial layer 110-2, and a third epitaxial layer 110-3. The first epitaxial layer 110-1 may be epitaxially grown on the partially recessed portion of the substrate 104, the second epitaxial layer 110-2 may be epitaxially grown on the sidewalls of the nanostructure 122 and the first epitaxial layer 110-1, and the third epitaxial layer 110-3 may be epitaxially grown on the second epitaxial layer 110-2. Figure 1 3 show three epitaxial layers of the S / D structure 110 , but the S / D structure 110 may have one or more epitaxial layers, and each epitaxial layer may have a different composition.

[0037] In some embodiments, each of the first epitaxial layer 110-1, the second epitaxial layer 110-2, and the third epitaxial layer 110-3 may include Si and be different from each other based on, for example, dopant concentration and / or epitaxial growth process conditions. In some embodiments, each of the first epitaxial layer 110-1, the second epitaxial layer 110-2, and the third epitaxial layer 110-3 may include silicon germanium and be different from each other based on, for example, dopant concentration, epitaxial growth process conditions, and / or relative concentrations of germanium relative to silicon. For example, the atomic percentage of germanium in the first epitaxial layer 110-1 may be less than the atomic percentage of germanium in the second epitaxial layer 110-2 and the third epitaxial layer 110-3. In some embodiments, the first epitaxial layer 110-1 may include silicon without germanium. In some embodiments, the second epitaxial layer 110-2 may include germanium in the range of about 0 atomic percentage to about 50 atomic percentages, the third epitaxial layer 110-3 may include germanium in the range of about 50 atomic percentages to about 80 atomic percentages, and the remaining atomic percentages are Si.

[0038] In some embodiments, the first epitaxial layer 110-1, the second epitaxial layer 110-2, and the third epitaxial layer 110-3 may have different dopant concentrations from each other. For example, the dopant concentration of the first epitaxial layer 110-1 may be lower than the dopant concentrations of the second epitaxial layer 110-2 and the third epitaxial layer 110-3. The dopant concentration of the second epitaxial layer 110-2 may be lower than the dopant concentration of the third epitaxial layer 110-3. In some embodiments, the first epitaxial layer 110-1 may be undoped. The second epitaxial layer 110-2 may be doped with a concentration less than about 5×10 20 Atom / cm 3 of boron, for example, about 1×10 20 About 5×10 20 Atom / cm 3 The third epitaxial layer 110 - 3 may be doped with a concentration of about 5×10 20 About 2×10 21 Atom / cm 3 The higher dopant concentration in the third epitaxial layer 110 - 3 can reduce the contact resistance between the S / D structure 110 and the S / D contact structure 130 .

[0039] In some embodiments, the second epitaxial layer 110-2 may include one or more dopant clusters. Figure 2AAs shown, the second epitaxial layer 110-2 may include horizontal dopant clusters 113h1, 113h2, and 113h3 (collectively referred to as "horizontal dopant clusters 113h"). The horizontal dopant clusters 113h may extend between adjacent nanostructure 122 stacks along the direction of the nanostructure 122. In some embodiments, the horizontal dopant clusters 113h may extend from the nanostructure 122 to the third epitaxial layer 110-3. In some embodiments, the dopants in the second epitaxial layer 110-2 may be gathered on the (111) growth plane of the second epitaxial layer 110-2, and the horizontal dopant clusters 113h may be formed along the intersection of the (111) growth plane. In some embodiments, the angle 110α between the (111) growth plane and the horizontal direction along the nanostructure 110 may be in the range of about 40 degrees to about 70 degrees.

[0040] In some embodiments, the concentration of the dopant in the horizontal dopant cluster 113h may be more than ten times the concentration of the dopant in the second epitaxial layer 110-2 and the dopant on other planes (e.g., the (001) plane) of the second epitaxial layer 110-2. For example, the horizontal dopant cluster 113h may include a collection of boron dopants with a concentration of about 5×10 20 About 5×10 21 Atom / cm 3 In some embodiments, the high dopant concentration in the horizontal dopant cluster 113h can improve the etching resistance of the S / D structure 110 and / or the inner spacer 121 during the sheet formation process of the nanostructure 122. Therefore, the horizontal dopant cluster 113h can reduce etching damage to the S / D structure 110, reduce gate-S / D short defects, and improve the device performance and yield of the semiconductor device 100. If the dopant concentration in the horizontal dopant cluster 113h is less than about 5×10 20 Atom / cm 3 , the etching damage to the S / D structure 110 may not be reduced. If the dopant concentration in the horizontal dopant cluster 113h is greater than about 5×10 21 Atom / cm 3 , more dopants may diffuse into the nanostructure 122 and may increase the device leakage current.

[0041] refer to Figure 4A-4D , the horizontal dopant clusters 113h may have different shapes. Figure 4A As shown, the horizontal dopant cluster 113h may have an elliptical shape, with a length 113l ranging from about 0 nm to about 10 nm and a width 113w ranging from about 0 nm to about 4 nm. Figure 4BAs shown, the horizontal dopant cluster 113h may have a rectangular shape with a length 113l ranging from about 0 nm to about 10 nm and a width 113w ranging from about 0 nm to about 4 nm. Figure 4C As shown, the horizontal dopant cluster 113h may have a fan shape, with a length 113l ranging from about 0 nm to about 10 nm and an angle 113α ranging from about 0 degrees to about 60 degrees. Figure 4D As shown, the horizontal dopant cluster 113h may include a plurality of circles along a line having a length 1131 in the range of about 0 nm to about 10 nm and a circle diameter 113d in the range of about 0 nm to about 2 nm.

[0042] In some embodiments, the horizontal dopant clusters 113h adjacent to the top, middle, and bottom nanostructures 122-1, 122-2, and 122-3 may have different sizes. In some embodiments, the size (e.g., width 113w and / or length 113l) of the horizontal dopant cluster 113h-1 adjacent to the top nanostructure 122-1 may be larger than the size of the horizontal dopant cluster 113h-2 adjacent to the middle nanostructure 122-2. In some embodiments, the size (e.g., width 113w and / or length 113l) of the horizontal dopant cluster 113h-2 adjacent to the middle nanostructure 122-2 may be larger than the size of the horizontal dopant cluster 113h-3 adjacent to the bottom nanostructure 122-3.

[0043] In some embodiments, Figure 3 As shown, the second epitaxial layer 110-2 may include a horizontal dopant cluster 113h and tilted dopant clusters 113s1, 113s2, and 113s3 (collectively referred to as "tilted dopant clusters 113s"). In some embodiments, the dopants in the second epitaxial layer 110-2 may be gathered on the (111) growth plane of the second epitaxial layer 110-2 and form tilted dopant clusters 113s. In some embodiments, the tilted dopant clusters 113s may extend along the (111) growth plane of the second epitaxial layer 110-2 and intersect with the horizontal dopant clusters 113h. In some embodiments, the (111) growth plane of the second epitaxial layer 110-2 may contact the third epitaxial layer 110-3. Therefore, the tilted dopant clusters 113s may extend along the interface between the second epitaxial layer 110-2 and the third epitaxial layer 110-3. In some embodiments, the angle between the tilted dopant clusters 113s and the horizontal dopant clusters 113h may be substantially the same as the angle 110α and may be in a range of about 40 degrees to about 70 degrees. In some embodiments, the tilted dopant clusters 113s may extend along the (111) growth plane to the inner spacer 121 and may contact the inner spacer 121.

[0044] In some embodiments, the concentration of the dopant in the tilted dopant cluster 113s may be more than ten times the concentration of the dopant in the second epitaxial layer 110-2 and the dopant on other planes (e.g., (001) plane) of the second epitaxial layer 110-2. For example, the tilted dopant cluster 113s may include a concentration of boron dopants with a concentration of about 5×10 20 About 5×10 21 Atom / cm 3 . In some embodiments, the dopant concentration in the horizontal dopant cluster 113h can be greater than the dopant concentration in the tilted dopant cluster 113s. In some embodiments, the high dopant concentration in both the horizontal dopant cluster 113h and the tilted dopant cluster 113s can further improve the etching resistance of the S / D structure 110 and / or the inner spacer 121 during the sheet formation process of the nanostructure 122. Therefore, the horizontal dopant cluster 113h and the tilted dopant cluster 113s can further reduce etching damage to the S / D structure 110, reduce gate-S / D short defects, and improve the device performance and yield of the semiconductor device 100.

[0045] In some embodiments, similar to the horizontal dopant clusters 113h described above, the tilted dopant clusters 113s may have different shapes and sizes, such as Figure 4A-4D As shown. In some embodiments, the tilted dopant clusters 113s adjacent to the top, middle, and bottom nanostructures 122-1, 122-2, and 122-3 may have different sizes, similar to the horizontal dopant cluster 113h. In some embodiments, the size (e.g., width 113w and / or length 113l) of the tilted dopant cluster 113s-1 adjacent to the top nanostructure 122-1 may be larger than the tilted dopant cluster 113s-2 adjacent to the middle nanostructure 122-2. In some embodiments, the size (e.g., width 113w and / or length 113l) of the tilted dopant cluster 113s-2 adjacent to the middle nanostructure 122-2 may be larger than the tilted dopant cluster 113s-3 adjacent to the bottom nanostructure 122-3.

[0046] The ESL 116 may be disposed on the STI region 106, the S / D structure 110, and the sidewalls of the gate spacer 114 and the sidewall spacer 109. The ESL 116 may be configured to protect the STI region 106, the S / D structure 110, and the gate structure 112 during the formation of the S / D contact structure 130 on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination thereof.

[0047] The ILD layer 118 may be disposed on the ESL 116 above the S / D structure 110 and the STI region 106. The ILD layer 118 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material. For example, flowable silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may include silicon oxide.

[0048] In some embodiments, Figure 1-Figure 3 As shown, the semiconductor device 100 may further include an S / D contact structure 130. In some embodiments, the S / D contact structure 130 may be disposed on the S / D structure 110. In some embodiments, the S / D contact structure 130 may include a silicide layer and a metal contact. In some embodiments, the silicide layer may include a metal silicide and may provide a low resistance interface between the metal contact and the S / D structure 110. Examples of metals for forming metal silicide include cobalt, titanium, and nickel. In some embodiments, the metal contact may include a conductive material, such as tungsten, aluminum, and cobalt. In some embodiments, as Figure 1-Figure 3 As shown, the S / D contact structure 130 can extend into the S / D structure 110 and can contact the horizontal dopant cluster 113h and / or the tilted dopant cluster 113s. In some embodiments, the high dopant concentration in the horizontal dopant cluster 113h and the tilted dopant cluster 113s can further reduce the contact resistance between the S / D contact structure 130 and the S / D structure 110.

[0049] In some embodiments, the horizontal dopant clusters 113h and the tilted dopant clusters 113s may include hydrogen, chlorine, carbon, fluorine, oxygen, and / or titanium due to the materials used during the process flow. For example, during the epitaxial growth of the S / D structure using a hydrogen chloride-containing gas, hydrogen and chlorine may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s. During the deposition process of the ESL 116 and / or the ILD layer 118, carbon and oxygen in the dielectric material may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s. During the sheet formation process of the nanostructure 122, fluorine in a fluorine-based etchant may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s. During the formation of the S / D contact structure, titanium in the silicide layer may diffuse into the horizontal dopant clusters 113h and the tilted dopant clusters 113s.

[0050] Figure 6is a flow chart of a method 600 of manufacturing a semiconductor device 100 having an S / D structure with dopant clusters according to some embodiments. The method 600 may not be limited to nanostructured transistor devices and may be applicable to other devices that benefit from an S / D structure with dopant clusters. Additional manufacturing operations may be performed between various operations of the method 600 and may be omitted solely for clarity and ease of description. Additional processing may be provided before, during, and / or after the method 600; one or more of these additional processes will be briefly described herein. Furthermore, not all operations are required to perform the disclosure provided herein. Furthermore, some operations may be performed simultaneously or in different order than the method 600. Figure 6 In some embodiments, one or more other operations may be performed in addition to or in place of the operations described.

[0051] For illustrative purposes, reference will be made to Figure 7-22B An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Figure 6 The operation shown. Figure 7-22B Partial isometric and partial cross-sectional views of a semiconductor device 100 having an S / D structure with dopant clusters at various stages of its fabrication are shown in accordance with some embodiments. Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 and Fig.21 Shown are partial isometric views of a semiconductor device 100 at various stages of its fabrication in accordance with some embodiments. Fig. 8A , Fig. 10A , Fig. 12A , Fig.14A , Fig.16A , Fig.18A , Fig. 20A and Fig.22A The semiconductor device 100 is shown in various stages of its manufacture according to some embodiments. Figure 1 A partial cross-sectional view along line AA is shown. Figure 8B , Fig. 10B , Fig. 12B , Fig. 14B , Fig. 16B , Fig.18B , Fig. 20B and Fig. 22B The semiconductor device 100 is shown in various stages of its manufacture according to some embodiments. Figure 1 A partial cross-sectional view along line BB is shown. Figure 7-22B With Figure 1 - Elements with the same reference numerals as those in FIG. 5 are as described above.

[0052] refer to Figure 6 , method 600 begins with operation 610 and a process of forming a channel structure on a substrate. Figure 7 , Fig. 8A and Figure 8B As shown, nanostructures 122 and 822 may be formed on substrate 104. In some embodiments, nanostructures 122 and 822 may be stacked in another configuration. In some embodiments, nanostructures 122 and 822 may be epitaxially grown on substrate 104 and then patterned to form a stack of nanostructures 122 and 822. In some embodiments, nanostructures 122 and 822 may be in the form of nanosheets, nanowires, and nanobelts. In some embodiments, nanostructures 122 and 822 may include semiconductor materials similar to or different from substrate 104. In some embodiments, nanostructures 122 and 822 may include different semiconductor materials. For example, nanostructure 122 may include silicon, and nanostructure 822 may include silicon germanium, wherein the atomic percentage of germanium is about 10% to about 40%.

[0053] Embodiments of the nanostructures 122 and 822 disclosed herein can be patterned by any suitable method. For example, the nanostructures can be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. The double patterning process or the multi-patterning process can combine a photolithography process and a self-alignment process to form a pattern having, for example, a smaller spacing than that obtainable using a single direct photolithography process. For example, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-alignment process can be used to form a spacer next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the nanostructure.

[0054] After forming the nanostructures 122, STI regions 106 may be formed between the stacks of adjacent nanostructures 122 and 822, sacrificial gate structures 712 may be formed on the nanostructures 122, gate spacers 114 and 718 may be formed on the sidewalls of the sacrificial gate structures 712, nanostructures 122 and 822 may be recessed, and an internal spacer layer 721 may be deposited in the recesses, as shown. Figure 7 , Fig. 8A and Figure 8B For the sake of clarity, these processes are not described in detail.

[0055] In some embodiments, after depositing the inner spacer layer 721, an etching process may be performed to form the inner spacer 121, such as Fig. 9 , Fig. 10A and Fig. 10B In some embodiments, the etching process may be a directional etching process to remove the inner spacer layer 721 located on the sidewalls of the nanostructure 122 and the top surface of the fin structure 108 .

[0056] refer to Figure 6 In operation 620, a first epitaxial layer is formed on the substrate adjacent to the channel structure. Fig.11 , Fig. 12A and Fig. 12B As shown, the first epitaxial layer 110-1 can be formed on the substrate 104 adjacent to the nanostructure 122. In some embodiments, the first epitaxial layer 110-1 can be epitaxially grown on the fin structure 108 above the substrate 104 using a bottom-up growth method. In some embodiments, the first epitaxial layer 110-1 can include intrinsic silicon without dopants. In some embodiments, the first epitaxial layer 110-1 can be formed on the fin structure 108 of the transistor 102A-102C. In some embodiments, the first epitaxial layer 110-1 can be formed on the n-type transistor, and the p-type transistor is blocked by the hard mask layer.

[0057] In some embodiments, the n-type S / D structure (eg, S / D structure 110A) may be formed before the p-type S / D structure (eg, S / D structure 110B). Fig.13 , Fig.14A and Fig. 14B As shown, n-type S / D structure 110A may be formed on fin structure 108 covered with dielectric layer 1316. Hard mask layers 1332 and 1334 may be formed on sacrificial gate structure 712. Hard mask layer 1336 may be formed on transistor 102A and patterned to expose transistor 102B for epitaxial growth of S / D structure 110B. In some embodiments, dielectric layer 1316 on transistor 102B may be removed by an etching process. A pre-cleaning process may clean any residual dielectric material on first epitaxial layer 110-1. After the etching and pre-cleaning processes, first epitaxial layer 110-1 of transistor 102B may be exposed for epitaxial growth of additional layers, such as Fig.15 , Fig.16A and Fig. 16B shown.

[0058] refer to Figure 6 In operation 630, a second epitaxial layer is formed on the sidewalls of the channel structure and the first epitaxial layer. The second epitaxial layer includes clusters of dopants extending in the direction of the channel structure. For example, Fig.17 , Fig.18A and Fig.18B As shown, the second epitaxial layer 110-2 may be formed on the sidewalls of the nanostructure 122 and the first epitaxial layer 110-1. In some embodiments, the second epitaxial layer 110-2 may include horizontal dopant clusters 113h along the direction of the nanostructure 122, such as Figure 2AIn some embodiments, the second epitaxial layer 110 - 2 may include horizontal dopant clusters 113 h along the direction of the nanostructures 122 and tilted dopant clusters 113 s along the (111) growth plane of the second epitaxial layer 110 - 2 , as shown in FIG. Figure 3 In some embodiments, the horizontal dopant clusters 113h and the tilted dopant clusters 113s in the second epitaxial layer 110-2 may include aggregations of boron.

[0059] In some embodiments, during the epitaxial growth of the second epitaxial layer 110 - 2 , the dopant-containing precursor may be controlled at a substantially constant flow rate to form a dopant-containing precursor having a thickness greater than about 5×10 20 Atom / cm 3 In some embodiments, during epitaxial growth, horizontal dopant clusters 113h and / or tilted dopant clusters 113s may be formed in the second epitaxial layer 110-2. In some embodiments, dopants in the second epitaxial layer 110-2 may be gathered on the (111) growth plane of the second epitaxial layer 110-2, and horizontal dopant clusters 113h may be formed along the intersection of the (111) growth plane. In some embodiments, dopants in the second epitaxial layer 110-2 may be gathered on the (111) growth plane of the second epitaxial layer 110-2 and form tilted dopant clusters 113s. In some embodiments, the angle between the tilted dopant clusters 113s and the horizontal dopant clusters 113h may be in the range of about 40 degrees to about 70 degrees. In some embodiments, the tilted dopant clusters 113s may extend along the (111) growth plane to the inner spacer 121 and may contact the inner spacer 121.

[0060] In some embodiments, the second epitaxial layer 110 - 2 may include silicon germanium, wherein the germanium concentration is about 0 atomic percent to about 50 atomic percent, and any remaining atomic percent is Si. In some embodiments, the horizontal dopant clusters 113 h and the tilted dopant clusters 113 s may include a concentration of boron with a concentration of about 5×10 20 About 5×10 21 Atom / cm 3 In some embodiments, the second epitaxial layer 110 - 2 may be doped during epitaxial growth to a concentration less than about 5×10 20 Atom / cm 3 of boron, for example, about 1×10 20 Atom / cm 3 About 5×10 20 Atom / cm 3In some embodiments, the concentration of the dopant in the horizontal dopant cluster 113h and / or the tilted dopant cluster 113s may be more than ten times the concentration of the dopant in the second epitaxial layer 110-2 and the dopant on other planes (e.g., (001) plane) of the second epitaxial layer 110-2. In some embodiments, the concentration of the dopant in the horizontal dopant cluster 113h may be greater than the concentration of the dopant in the tilted dopant cluster 113s.

[0061] In some embodiments, the high dopant concentration in the horizontal dopant clusters 113h and / or the tilted dopant clusters 113s can improve the etching resistance of the S / D structure 110 and / or the inner spacer 121 during the sheet formation process of the nanostructure 122. Therefore, the horizontal dopant clusters 113h and the tilted dopant clusters 113s can reduce etching damage to the S / D structure 110, reduce gate-S / D short defects, and improve the device performance and yield of the semiconductor device 100. If the dopant concentration in the horizontal dopant clusters 113h and / or the tilted dopant clusters 113s is less than about 5×10 20 Atom / cm 3 , the etching damage to the S / D structure 110 may not be reduced. If the dopant concentration in the horizontal dopant cluster 113h and / or the tilted dopant cluster 113s is greater than about 5×10 21 Atom / cm 3 , more dopants may diffuse into the nanostructure 122 and may increase the device leakage current.

[0062] refer to Figure 6 In operation 640, a third epitaxial layer is formed on the second epitaxial layer. Fig.19 , Fig. 20A and Fig. 20B As shown, the third epitaxial layer 110-3 can be formed on the second epitaxial layer 110-2. In some embodiments, the third epitaxial layer 110-3 can be epitaxially grown on the (111) growth plane of the second epitaxial layer 110-2. Therefore, the tilted dopant clusters 113s can extend along the interface between the second epitaxial layer 110-2 and the third epitaxial layer 110-3. In some embodiments, the third epitaxial layer 110-3 may include silicon germanium, wherein the germanium concentration is about 50 atomic percent to about 80 atomic percent, and any remaining atomic percent is Si. In some embodiments, the germanium concentration in the third epitaxial layer 110-3 can be greater than the germanium concentration in the second epitaxial layer 110-2. In some embodiments, the third epitaxial layer 110-3 can be doped during epitaxial growth to a concentration of about 5×10 20 Atoms / cm3 is about 5×10 21 Atom / cm 3In some embodiments, the dopant concentration in the third epitaxial layer 110-3 may be greater than the dopant concentration in the second epitaxial layer 110-2 to reduce the contact resistance between the S / D structure 110 and the subsequently formed S / D contact structure 130. In some embodiments, an annealing process may be performed after forming the third epitaxial layer 110-3. In some embodiments, the horizontal dopant clusters 113h and the tilted dopant clusters 113s in the second epitaxial layer 110-2 may remain after the annealing process.

[0063] After forming the third epitaxial layer 110 - 3 , the dielectric layer 1316 may be removed. Fig.21 , Fig.22A and Fig. 22B After removing the dielectric layer 1316, the ESL 116 may be formed, the ILD layer 118 may be formed, the sacrificial gate structure 712 may be replaced with the metal gate structure 112, and the S / D contact structure 130 may be formed to form the semiconductor device 100. Figure 1-Figure 3 For the sake of clarity, these processes are not described in detail. In some embodiments, Figure 1-Figure 3 As shown, the S / D contact structure 130 can extend into the S / D structure 110 and can contact the horizontal dopant cluster 113h and / or the tilted dopant cluster 113s. In some embodiments, the high dopant concentration in the horizontal dopant cluster 113h and the tilted dopant cluster 113s can further reduce the contact resistance between the S / D contact structure 130 and the S / D structure 110.

[0064] Various embodiments of the present disclosure provide an example method for forming an S / D structure 110 having a horizontal dopant cluster 113h in a semiconductor device 100. In some embodiments, a nanostructure 122 may be formed on a substrate 104. The S / D structure 110 may be formed on the substrate 104 and adjacent to the nanostructure 122. In some embodiments, the S / D structure 110 may include a first epitaxial layer 110-1 on the substrate 104, a sidewall of the nanostructure 122 and a second epitaxial layer 110-2 on the first epitaxial layer 110-1, and a third epitaxial layer 110-3 on the second epitaxial layer 110-2. In some embodiments, the second epitaxial layer 110-2 may include a horizontal dopant cluster 113h extending in the direction of the nanostructure 122. In some embodiments, the first concentration of the dopant in the horizontal dopant cluster 113h may be about ten times or more of the concentration of the dopant in the second epitaxial layer 110-2. In some embodiments, the horizontal dopant cluster 113h may extend along the intersection of the (111) growth plane of the second epitaxial layer. In some embodiments, the second epitaxial layer 110-2 may include tilted dopant clusters 113s along the (111) growth plane of the second epitaxial layer 110-2. The horizontal dopant clusters 113h and the tilted dopant clusters 113s may reduce etching damage to the S / D structure 110, reduce gate-S / D short defects, and improve device performance and yield.

[0065] In some embodiments, a semiconductor structure includes a channel structure on a substrate, and an epitaxial structure on the substrate and adjacent to the channel structure. The epitaxial structure includes a first epitaxial layer on a sidewall of the channel structure, and a second epitaxial layer on the first epitaxial layer. The first epitaxial layer includes a cluster of dopants extending along the direction of the channel structure.

[0066] In some embodiments, a semiconductor device includes a first channel structure and a second channel structure on a substrate, and a source / drain (S / D) structure between the first channel structure and the second channel structure. The S / D structure includes a first epitaxial layer on the sidewalls of the first channel structure and the second channel structure, and a second epitaxial layer on the first epitaxial layer. The first epitaxial layer includes a first cluster of dopants extending from the first channel structure to the second channel structure.

[0067] In some embodiments, a method includes forming a channel structure on a substrate, forming a first epitaxial layer on sidewalls of the channel structure and the substrate, and forming a second epitaxial layer on the first epitaxial layer. The first epitaxial layer includes clusters of dopants extending along a direction of the channel structure.

[0068] It should be understood that the detailed description section is intended to be used to interpret the claims, but the abstract of the disclosure section is not. The abstract of the disclosure section may set forth one or more possible embodiments of the disclosure contemplated by the inventor(s), but not all possible embodiments, and therefore, is not intended to limit the appended claims in any way.

[0069] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0070] Example 1 is a semiconductor structure, comprising: a channel structure located on a substrate; and an epitaxial structure located on the substrate and adjacent to the channel structure, wherein the epitaxial structure comprises: a first epitaxial layer located on a sidewall of the channel structure, wherein the first epitaxial layer comprises a cluster of dopants extending in the direction of the channel structure; and a second epitaxial layer located on the first epitaxial layer.

[0071] Example 2 is the semiconductor structure of Example 1, wherein a first concentration of the dopant in the cluster is greater than a second concentration of the dopant in the first epitaxial layer.

[0072] Example 3 is the semiconductor structure of Example 2, wherein the first concentration is at least ten times the second concentration.

[0073] Example 4 is the semiconductor structure of Example 2, wherein the first concentration is greater than about 5×10 20 Atom / cm 3 .

[0074] Example 5 is the semiconductor structure of Example 1, wherein the first epitaxial layer further includes additional clusters of the dopant extending along an interface between the first epitaxial layer and the second epitaxial layer.

[0075] Example 6 is the semiconductor structure of Example 5, wherein the additional cluster is along a (111) growth plane of the first epitaxial layer, and the cluster extends along an intersection line between the (111) growth plane and an additional (111) growth plane of the first epitaxial layer.

[0076] Example 7 is the semiconductor structure of Example 5, further comprising: an internal spacer located between the channel structure and the epitaxial structure, wherein the additional cluster is in contact with the internal spacer.

[0077] Example 8 is the semiconductor structure of Example 5, wherein a first concentration of the dopant in the cluster is greater than a second concentration of the dopant in the additional cluster.

[0078] Example 9 is the semiconductor structure of Example 1, further comprising: a contact structure extending into the epitaxial structure, wherein the cluster is in contact with the contact structure.

[0079] Example 10 is the semiconductor structure described in Example 1, wherein the epitaxial structure further includes an additional epitaxial layer located between the first epitaxial layer and the substrate, and wherein the germanium concentration in the first epitaxial layer is greater than the germanium concentration in the additional epitaxial layer and less than the germanium concentration in the second epitaxial layer.

[0080] Example 11 is a semiconductor device, comprising: a first channel structure and a second channel structure, located on a substrate; and a source / drain (S / D) structure, located between the first channel structure and the second channel structure, wherein the S / D structure comprises: a first epitaxial layer, located on the side walls of the first channel structure and the second channel structure, wherein the first epitaxial layer comprises a first cluster of dopants extending from the first channel structure to the second channel structure; and a second epitaxial layer, located on the first epitaxial layer.

[0081] Example 12 is the semiconductor device of Example 11, wherein a first concentration of the dopant in the first cluster is greater than a second concentration of the dopant in the first epitaxial layer.

[0082] Example 13 is the semiconductor device of Example 12, wherein the first concentration is at least ten times the second concentration.

[0083] Example 14 is a semiconductor device described in Example 11, wherein the first epitaxial layer further includes a second cluster of the dopant located at the interface of the first epitaxial layer and the second epitaxial layer, and wherein the first concentration of the dopant in the first cluster is greater than the second concentration of the dopant in the second cluster.

[0084] Example 15 is the semiconductor device of Example 14, wherein an angle between the first cluster and the second cluster of the dopant is in a range from about 40 degrees to about 70 degrees.

[0085] Example 16 is the semiconductor device of Example 14, further comprising: a contact structure extending into the S / D structure, wherein the first cluster and the second cluster are in contact with the contact structure.

[0086] Example 17 is a method for forming a semiconductor structure, comprising: forming a channel structure on a substrate; forming a first epitaxial layer on the sidewalls of the channel structure and the substrate, wherein the first epitaxial layer includes a cluster of dopants extending along the direction of the channel structure; and forming a second epitaxial layer on the first epitaxial layer.

[0087] Example 18 is the method of Example 17, wherein forming the first epitaxial layer includes controlling a precursor containing the dopant at a substantially constant flow rate.

[0088] Example 19 is the method described in Example 17, further comprising: forming an additional cluster of the dopant at the interface of the first epitaxial layer and the second epitaxial layer, wherein an angle between the cluster of the dopant and the additional cluster is in a range of about 40 degrees to about 70 degrees.

[0089] Example 20 is the method of Example 17, further comprising: forming an additional epitaxial layer on the substrate before forming the first epitaxial layer, and forming a contact structure in the second epitaxial layer, wherein the cluster is in contact with the contact structure.

Claims

1. A semiconductor structure comprising: A channel structure is located on the substrate; as well as An epitaxial structure, located on the substrate and adjacent to the channel structure, wherein the epitaxial structure comprises: a first epitaxial layer located on a sidewall of the channel structure, wherein the first epitaxial layer comprises a cluster of dopants extending in a direction of the channel structure; and The second epitaxial layer is located on the first epitaxial layer.

2. The semiconductor structure according to claim 1, wherein: A first concentration of the dopant in the clusters is greater than a second concentration of the dopant in the first epitaxial layer.

3. The semiconductor structure according to claim 2, wherein: The first concentration is at least ten times greater than the second concentration.

4. The semiconductor structure according to claim 2, wherein: The first concentration is greater than 5×10 20 Atom / cm 3 .

5. The semiconductor structure according to claim 1, wherein: The first epitaxial layer further includes additional clusters of the dopant extending along an interface between the first epitaxial layer and the second epitaxial layer.

6. The semiconductor structure according to claim 5, wherein: The additional cluster is along a (111) growth plane of the first epitaxial layer, and the cluster extends along an intersection of the (111) growth plane and an additional (111) growth plane of the first epitaxial layer.

7. The semiconductor structure according to claim 5, further comprising: An inner spacer is located between the channel structure and the epitaxial structure, wherein the additional cluster is in contact with the inner spacer.

8. The semiconductor structure according to claim 5, wherein: A first concentration of the dopant in the cluster is greater than a second concentration of the dopant in the additional cluster.

9. A semiconductor device comprising: A first channel structure and a second channel structure are located on a substrate; as well as A source / drain S / D structure is located between the first channel structure and the second channel structure, wherein the S / D structure includes: a first epitaxial layer disposed on sidewalls of the first channel structure and the second channel structure, wherein the first epitaxial layer comprises a first cluster of dopants extending from the first channel structure to the second channel structure; and The second epitaxial layer is located on the first epitaxial layer.

10. A method of forming a semiconductor structure, comprising: forming a channel structure on a substrate; forming a first epitaxial layer on the sidewalls of the channel structure and the substrate, wherein the first epitaxial layer comprises clusters of dopants extending in the direction of the channel structure; and A second epitaxial layer is formed on the first epitaxial layer.

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