Integrated circuit device and method of forming same

Abstract

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device includes a weakening transistor stack and a reference transistor stack on a substrate. The weakening transistor stack may include a first inter-gate insulator that is thicker than a second inter-gate insulator of the reference transistor stack. Due to the thicker first inter-gate insulator, the number of first upper channel regions of the weakened transistor stack may be less than the number of second upper channel regions of the reference transistor stack, and / or the number of first lower channel regions of the weakened transistor stack may be less than the number of second lower channel regions of the reference transistor stack.

Description

Technical Field

[0001] The present disclosure relates generally to the field of integrated circuit devices and, more particularly, to integrated circuit devices including stacked transistors. Background Art

[0002] Various structures of integrated circuit devices and methods of forming the same have been proposed to increase integration density and reduce leakage current and / or power consumption. For example, a transistor stack including a plurality of transistors stacked vertically has been proposed to increase integration density. Summary of the invention

[0003] According to some embodiments, an integrated circuit device may include: a wimpy transistor stack on a substrate, the wimpy transistor stack including a first upper transistor, a first lower transistor, and a first inter-gate insulator, the first upper transistor including a plurality of first upper channel regions stacked in a vertical direction, a first upper gate structure, and a first upper source / drain region contacting the plurality of first upper channel regions, the plurality of first upper channel regions being provided in the first upper gate structure, the first lower transistor being between the substrate and the first upper transistor and including a plurality of first lower channel regions stacked in a vertical direction, a first lower gate structure, and a first lower source / drain region contacting the plurality of first lower channel regions, the plurality of first lower channel regions being provided in the first lower gate structure, the first inter-gate insulator being between the first upper gate structure and the first lower gate structure; and a transistor stack adjacent to the wimpy transistor stack on the substrate, the transistor stack including a second upper transistor, a second lower transistor, and a second inter-gate insulator. insulator, the second upper transistor includes a plurality of second upper channel regions stacked in a vertical direction and a second upper gate structure, wherein the first upper source / drain region contacts the plurality of second upper channel regions, and the plurality of second upper channel regions are provided in the second upper gate structure, the second lower transistor is between the substrate and the second upper transistor and includes a plurality of second lower channel regions stacked in a vertical direction and a second lower gate structure, wherein the first lower source / drain region contacts the plurality of second lower channel regions, and the plurality of second lower channel regions are provided in the second lower gate structure, the second inter-gate insulator is between the second upper gate structure and the second lower gate structure, wherein the first inter-gate insulator is spaced apart from the second inter-gate insulator in a horizontal direction, and the first inter-gate insulator overlaps with the lowest one of the plurality of second upper channel regions and / or the highest one of the plurality of second lower channel regions in a horizontal direction.

[0004] According to some embodiments, an integrated circuit device may include: a weakened transistor stack on a substrate, the weakened transistor stack including a first upper transistor and a first lower transistor, the first upper transistor including a plurality of first upper channel regions stacked in a vertical direction, a first upper gate structure, and a first upper source / drain region contacting the plurality of first upper channel regions, the plurality of first upper channel regions being provided in the first upper gate structure, the first lower transistor being between the substrate and the first upper transistor and including a plurality of first lower channel regions stacked in a vertical direction, a first lower gate structure, and a first lower source / drain region contacting the plurality of first lower channel regions, the plurality of first lower channel regions being provided in the first lower gate structure; and a transistor stack adjacent to the weakened transistor stack on the substrate, the transistor stack including a second upper transistor and a second lower transistor, the second upper transistor The invention comprises a plurality of second upper channel regions stacked in a vertical direction and a second upper gate structure, wherein a first upper source / drain region contacts the plurality of second upper channel regions, and the plurality of second upper channel regions are provided in the second upper gate structure. The second lower transistor is between a substrate and a second upper transistor and comprises a plurality of second lower channel regions stacked in a vertical direction and a second lower gate structure, wherein the first lower source / drain region contacts the plurality of second lower channel regions, and the plurality of second lower channel regions are provided in the second lower gate structure, wherein the lowermost one of the plurality of first upper channel regions and the uppermost one of the plurality of first lower channel regions are spaced apart from each other by a first distance in the vertical direction, and the lowermost one of the plurality of second upper channel regions and the uppermost one of the plurality of second lower channel regions are spaced apart from each other by a second distance in the vertical direction, and the first distance is longer than the second distance.

[0005] According to some embodiments, an integrated circuit device may include: a weakened transistor stack on a substrate, the weakened transistor stack including a first upper transistor and a first lower transistor, the first upper transistor including a plurality of first upper channel regions stacked in a vertical direction, a first upper gate structure, and a first upper source / drain region contacting the plurality of first upper channel regions, the plurality of first upper channel regions being provided in the first upper gate structure, the first lower transistor being between the substrate and the first upper transistor and including a plurality of first lower channel regions stacked in a vertical direction, a first lower gate structure, and a first lower source / drain region contacting the plurality of first lower channel regions, the plurality of first lower channel regions being provided in the first lower gate structure; and a transistor stack adjacent to the weakened transistor stack on the substrate, the ... The body transistor stack includes a second upper transistor and a second lower transistor, the second upper transistor including a plurality of second upper channel regions stacked in a vertical direction and a second upper gate structure, wherein a first upper source / drain region contacts the plurality of second upper channel regions, and the plurality of second upper channel regions are provided in the second upper gate structure, the second lower transistor is between the substrate and the second upper transistor and includes a plurality of second lower channel regions stacked in a vertical direction and a second lower gate structure, wherein the first lower source / drain region contacts the plurality of second lower channel regions, and the plurality of second lower channel regions are provided in the second lower gate structure, wherein the number of the plurality of first upper channel regions is less than the number of the plurality of second upper channel regions, and / or the number of the plurality of first lower channel regions is less than the number of the plurality of second lower channel regions.

[0006] According to some embodiments, a method for forming an integrated circuit device may include: forming a stack structure on an upper surface of a substrate, the stack structure including alternately stacked lower channel layers and lower sacrificial layers, inter-gate insulator layers on the lower channel layers and the lower sacrificial layers, and alternately stacked upper channel layers and upper sacrificial layers; etching the stack structure to form a recess therein; forming a weakened inter-gate insulator layer in the recess, the weakened inter-gate insulator layer having a greater thickness than the inter-gate insulator layer; etching the stack structure to form a weakened transistor stack and a reference transistor stack, the weakened gate ... gate insulator layer; etching the stack structure to form a weakened gate insulator layer; etching the stack structure to form a weakened gate insulator layer; etching the weakened gate insulator layer; etching the stack structure to form a weakened gate insulator layer; etching the weakened gate insulator layer; etching the weakened gate insulator layer; etching the weakened gate insulator layer; etching the weakened gate insulator layer; etching the weakened gate insulator layer; etching the weakened gate insulator layer; etching the weakened gate insulator layer; etching the weaken The transistor stack includes a weakened inter-gate insulator layer, which overlaps with at least one of the upper channel layer and the lower channel layer of the reference transistor stack in a direction parallel to the upper surface of the substrate; forms a first initial gate structure for the weakened transistor stack and a second initial gate structure for the reference transistor stack; forms a lower source / drain region adjacent to the weakened transistor stack and the reference transistor stack; forms a source / drain isolation layer on the lower source / drain region; and forms an upper source / drain region on the source / drain isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view of an integrated circuit device according to some embodiments.

[0008] Figure 2 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line AA′ in FIG.

[0009] Figure 3 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line AA′ in FIG.

[0010] Figure 4 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line AA′ in FIG.

[0011] Figure 5 is a flow chart of a method of forming an integrated circuit device according to some embodiments.

[0012] Figures 6 to 12 is a cross-sectional view illustrating a method of forming an integrated circuit device according to some embodiments.

[0013] Fig.13 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line AA′ in FIG.

[0014] Fig.14 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line AA′ in FIG.

[0015] Fig.15 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along line AA′ in FIG.

[0016] Figures 16 to 22 is a cross-sectional view illustrating a method of forming an integrated circuit device according to some embodiments.

[0017] Fig.23 is a flow chart of a method of forming an integrated circuit device according to some embodiments. DETAILED DESCRIPTION

[0018] Some embodiments arise from the recognition that it may be beneficial to provide a wimpy transistor in a specific region of an integrated circuit device to reduce leakage current and / or power consumption. As used herein, a "wimpy transistor" is a transistor having one or more channels that are electrically isolated to reduce current flowing through it. In the specific region, a lower current flowing through the wimpy transistor may be acceptable, and leakage current and / or power consumption may be reduced by the wimpy transistor.

[0019] In integrated circuit devices using multi-channel transistors, the complexity of the process for reducing the number of channels (e.g., nanosheets) or reducing the width of the channels may be high. In addition, in transistor stacks, changing the channel width may be highly restricted in the process. According to some embodiments, weakened transistors can be provided by changing the characteristics of the integrated circuit device (e.g., the thickness of the source / drain isolation layer or the thickness of the gate insulator), which does not significantly increase the process complexity and does not substantially change the existing design.

[0020] In some embodiments, the weakened transistor stack can be configured by changing the thickness of the source / drain isolation layer that separates the upper source / drain region and the lower source / drain region. Specifically, the thickness of the source / drain isolation layer can be increased to electrically isolate at least one of the channels of the weakened transistor stack, so that leakage current and / or power consumption can be reduced due to the lower current flowing through the weakened transistor stack.

[0021] In some embodiments, the weakened transistor stack can be configured by changing the thickness of the inter-gate insulator (e.g., intermediate dielectric isolation (MDI)) that separates the upper gate structure and the lower gate structure. Specifically, the thickness of the inter-gate insulator can be increased to reduce the number of channels of the weakened transistor stack. The number of channels of the weakened transistor stack can be less than the number of channels of the reference transistor stack adjacent to the weakened transistor stack. Due to the reduction in the number of channels, the current flowing through the weakened transistor stack can be reduced, thereby also reducing leakage current and / or power consumption.

[0022] Example embodiments will be described in more detail with reference to the accompanying drawings. As used herein, the vertical direction Z may be perpendicular to the back side of the substrate. The X and Y horizontal directions may be parallel to the back side of the substrate, may be perpendicular to each other, and may each be perpendicular to the Z direction. The X direction, the Y direction, and the Z direction may be referred to as the first direction, the second direction, and the third direction, respectively.

[0023] Figure 1 is a schematic layout diagram of an integrated circuit device including a standard cell according to some embodiments, Figure 2 , Figure 3 and Figure 4 According to some embodiments, Figure 1A cross-sectional view of an integrated circuit device taken along line AA' in FIG. Figure 1 1 is a schematic layout diagram of a single height standard cell defined between a first power line P1 and a second power line P2 and a pair of cell boundaries CB. The first power line P1 can be electrically connected to a drain voltage V DD ) of the first power source, the second power line P2 can be electrically connected to a first power source having a second voltage (eg, a source voltage V SS ) of the second power supply. For example, the second voltage may be an electrical ground voltage. Figure 1 A single height standard cell is shown, but the inventive concept is not limited thereto.

[0024] Reference Figure 1 and Figure 2 In some embodiments, the standard cell may include three reference transistor stacks TS (also referred to as transistor stacks) and one weakened transistor stack TSw (e.g. Figure 2 TSw_1 or Fig.13 TSw_4 in ). The weakened transistor stack TSw_1 may include a first upper transistor (also referred to as an upper transistor) and a first lower transistor (also referred to as a lower transistor) between the first upper transistor and the substrate 100. The first upper transistor may include a plurality of first upper channel regions 402a (also referred to as a plurality of upper channel regions) stacked in a vertical direction Z, a first upper source / drain region 404a (also referred to as an upper source / drain region), a second upper source / drain region 404b, and a first upper gate structure 12a. The first upper source / drain region 404a may contact at least one of the plurality of first upper channel regions 402a. For example, the first upper source / drain region 404a may contact two first upper channel regions 402a of the three first upper channel regions 402a.

[0025] The first upper gate structure 12a may include a first upper gate insulator 406a, a first upper gate electrode 408a, and a first upper gate spacer 410a. The plurality of first upper channel regions 402a may be provided in the first upper gate structure 12a. The first upper source / drain region 404a and the second upper source / drain region 404b may be spaced apart from each other in a first direction X (also referred to as a first horizontal direction or a horizontal direction). The vertical direction Z may be perpendicular to the back side 100b of the substrate 100. The substrate 100 may also include a front side 100f opposite to the back side 100b and facing the weakened transistor stack TSw_1. In some embodiments, the first power line P1 and the second power line P2 may be spaced apart from each other in a second direction Y (also referred to as a second horizontal direction). Both the first direction X and the second direction Y may be parallel to the back side 100b of the substrate 100 and may be perpendicular to the vertical direction Z. In some embodiments, the first direction X may be perpendicular to the second direction Y. The vertical direction Z may also be referred to as a third direction.

[0026] The first lower transistor of the weakened transistor stack TSw_1 may include a plurality of first lower channel regions 202a (also referred to as a plurality of lower channel regions), a first lower source / drain region 204a (also referred to as a lower source / drain region), a second lower source / drain region 204b, and a first lower gate structure 14a. The first lower source / drain region 204a may contact at least one of the plurality of first lower channel regions 202a. The first lower gate structure 14a may include a first lower gate insulator 206a, a first lower gate electrode 208a, and a first lower gate spacer 210a. The plurality of first lower channel regions 202a may be provided in the first lower gate structure 14a. A first inter-gate insulator 304a (also referred to as an inter-gate insulator) may be provided between the first upper gate structure 12a and the first lower gate structure 14a.

[0027] The weakened transistor stack TSw_1 may further include a first source / drain isolation layer 302a (also referred to as a source / drain isolation layer) separating the first upper source / drain region 404a from the first lower source / drain region 204a. Figure 2 As shown, the first source / drain isolation layer 302a may include a first portion adjacent to the plurality of first upper channel regions 402a and having a first thickness t1 in the vertical direction Z. The first portion of the first source / drain isolation layer 302a may include an upper portion extending into a space between the lowest one of the plurality of first upper channel regions 402a and the first upper source / drain region 404a. Figure 2 As shown, the lowest one of the plurality of first upper channel regions 402a is electrically isolated from the first upper source / drain region 404a. In some embodiments, the upper portion of the first source / drain isolation layer 302a may contact the lowest one of the plurality of first upper channel regions 402a. The upper portion of the first source / drain isolation layer 302a may contact the entire side surface of the lowest one of the plurality of first upper channel regions 402a facing the first upper source / drain region 404a, so that the lowest one of the plurality of first upper channel regions 402a may be electrically isolated from the first upper source / drain region 404a. Therefore, the lowest one of the plurality of first upper channel regions 402a does not allow current to flow therethrough. The upper portion of the first source / drain isolation layer 302a may overlap with the lowest one of the plurality of first upper channel regions 402a in the first direction X, as shown in FIG. Figure 2As shown. The upper surface of the lowest one of the multiple first upper channel regions 402a can be spaced apart from the substrate 100 by a first distance d1 in the vertical direction Z, and the upper surface of the first source / drain isolation layer 302a (i.e., the upper surface of the first portion of the first source / drain isolation layer 302a) can be spaced apart from the substrate 100 by a second distance d2 in the vertical direction Z. The second distance d2 can be greater than or equal to the first distance d1 to electrically isolate the lowest one of the multiple first upper channel regions 402a from the first upper source / drain region 404a. By electrically isolating the lowest one of the multiple first upper channel regions 402a from the first upper source / drain region 404a, the current flowing through the first upper transistor of the weakened transistor stack TSw_1 can be reduced, thereby reducing the leakage current and / or power consumption of the integrated circuit device. Although Figure 2 The first source / drain isolation layer 302a is shown to separate only the lowest one of the multiple first upper channel regions 402a from the first upper source / drain region 404a (e.g., electrically isolate), but in some embodiments, the first source / drain isolation layer 302a may also separate additional first upper channel regions of the multiple first upper channel regions 402a from the first upper source / drain region 404a (e.g., electrically isolate).

[0028] The first portion of the first source / drain isolation layer 302a having the first thickness t1 in the vertical direction Z may also include a lower portion extending into a space between the uppermost one of the plurality of first lower channel regions 202a and the first lower source / drain region 204a. Figure 2 As shown, the uppermost one of the plurality of first lower channel regions 202a is electrically isolated from the first lower source / drain region 204a. In some embodiments, the lower portion of the first source / drain isolation layer 302a may contact the uppermost one of the plurality of first lower channel regions 202a. The lower portion of the first source / drain isolation layer 302a may contact the entire side surface of the uppermost one of the plurality of first lower channel regions 202a facing the first lower source / drain region 204a, so that the uppermost one of the plurality of first lower channel regions 202a may be electrically isolated from the first lower source / drain region 204a. Therefore, the uppermost one of the plurality of first lower channel regions 202a does not allow current to flow therethrough. The lower portion of the first source / drain isolation layer 302a may overlap with the uppermost one of the plurality of first lower channel regions 202a in the first direction X, as shown in FIG. Figure 2As shown. The lower surface of the uppermost one of the multiple lower channel regions 202a may be spaced apart from the substrate 100 by a third distance d3 in the vertical direction Z, and the lower surface of the first source / drain isolation layer 302a (i.e., the lower surface of the first portion of the first source / drain isolation layer 302a) may be spaced apart from the substrate 100 by a fourth distance d4 in the vertical direction Z. The third distance d3 may be greater than or equal to the fourth distance d4 so as to electrically isolate the uppermost one of the multiple first lower channel regions 202a from the first lower source / drain region 204a. By electrically isolating the uppermost one of the multiple first lower channel regions 202a from the first lower source / drain region 204a, the current flowing through the first lower transistor of the weakened transistor stack TSw_1 may be reduced, thereby reducing the leakage current and / or power consumption of the integrated circuit device. Although Figure 2 The first source / drain isolation layer 302a is shown to separate only the topmost one of the multiple first lower channel regions 202a from the first lower source / drain region 204a, but in some embodiments, the first source / drain isolation layer 302a may also separate (e.g., electrically isolate) additional first lower channel regions of the multiple first lower channel regions 202a from the first lower source / drain region 204a.

[0029] In addition, the weakened transistor stack TSw_1 may include a second source / drain isolation layer 302b between the second upper source / drain region 404b and the second lower source / drain region 204b. The second source / drain isolation layer 302b may separate the second upper source / drain region 404b from the second lower source / drain region 204b and may have a second thickness t2 in the vertical direction Z. In some embodiments, the first thickness t1 may be greater than the second thickness t2. Figure 2 As shown, the plurality of first upper channel regions 402a may all contact the second upper source / drain region 404b, and the plurality of first lower channel regions 202a may all contact the second lower source / drain region 204b.

[0030] The first upper transistor and the first lower transistor of the weakening transistor stack TSw_1 may have different conductivity types or may have the same conductivity type. In some embodiments, the first upper transistor may be a P-type transistor and the first lower transistor may be an N-type transistor. In some other embodiments, the first upper transistor may be an N-type transistor and the first lower transistor may be a P-type transistor.

[0031] The reference transistor stack TS may include a second upper transistor including a plurality of second upper channel regions 402b stacked in the vertical direction Z and a third upper source / drain region 404c. The first upper source / drain region 404a may be shared by the first upper transistor of the weakened transistor stack TSw_1 and the second upper transistor of the reference transistor stack TS. The plurality of second upper channel regions 402b may all contact both the first upper source / drain region 404a and the third upper source / drain region 404c, so that current flows therethrough. The first upper transistor of the weakened transistor stack TSw_1 and the second upper transistor of the reference transistor stack TS may have the same conductivity type.

[0032] The reference transistor stack TS may further include a second lower transistor, which is between the substrate 100 and the second upper transistor and includes a plurality of second lower channel regions 202b stacked in the vertical direction Z and a third lower source / drain region 204c. The first lower source / drain region 204a may be shared by the first lower transistor of the weakened transistor stack TSw_1 and the second lower transistor of the reference transistor stack TS. The plurality of second lower channel regions 202b may all contact both the second lower source / drain region 204a and the third lower source / drain region 204c, so that current flows therethrough. The first lower transistor of the weakened transistor stack TSw_1 and the second lower transistor of the reference transistor stack TS may have the same conductivity type.

[0033] The second upper transistor of the reference transistor stack TS may further include a second upper gate structure 12b. The second upper gate structure 12b may include a second upper gate insulator 406b, a second upper gate electrode 408b, and a second upper gate spacer 410b. The plurality of second upper channel regions 402b may be provided in the second upper gate structure 12b. The second lower transistor of the reference transistor stack TS may further include a second lower gate structure 14b. The second lower gate structure 14b may include a second lower gate insulator 206b, a second lower gate electrode 208b, and a second lower gate spacer 210b. The plurality of second lower channel regions 202b may be provided in the second lower gate structure 14b. A second inter-gate insulator 304b may be provided between the second upper gate structure 12b and the second lower gate structure 14b.

[0034] Still refer to Figure 2, the first source / drain isolation layer 302a may also include a second portion adjacent to the plurality of second upper channel regions 402b and having a third thickness t3 in the vertical direction Z. The first thickness t1 of the first portion of the first source / drain isolation layer 302a may be thicker than the third thickness t3 of the second portion of the first source / drain isolation layer 302a. In some embodiments, the third thickness t3 may be equal to the second thickness t2 of the second source / drain isolation layer 302b. In some embodiments, the third thickness t3 may be greater than or equal to the first thickness t1. In such an embodiment, the reference transistor stack TS will also be a weakened transistor stack, resulting in two weakened transistor stacks adjacent to each other. The reference transistor stack TS may also include a third source / drain isolation layer 302c between the third upper source / drain region 404c and the third lower source / drain region 204c. The third source / drain isolation layer 302c may separate the third upper source / drain region 404c from the third lower source / drain region 204c and may have a fourth thickness t4 in the vertical direction Z. The first thickness t1 of the first portion of the first source / drain isolation layer 302a may be thicker than the fourth thickness t4 of the third source / drain isolation layer 302c. In some embodiments, the fourth thickness t4 may be equal to the second thickness t2 of the second source / drain isolation layer 302b. In some embodiments, the third source / drain isolation layer 302c may not overlap with the lowermost one of the plurality of first upper channel regions 402a and the uppermost one of the plurality of first lower channel regions 202a in the first direction X, such as Figure 2 As shown. The fifth thickness t5 of the first upper source / drain region 404a in the portion adjacent to the plurality of first upper channel regions 402a in the vertical direction Z may be thinner than the sixth thickness t6 of the first upper source / drain region 404a in the portion adjacent to the plurality of second upper channel regions 402b in the vertical direction Z. The seventh thickness t7 of the first lower source / drain region 204a in the portion adjacent to the plurality of first lower channel regions 202a in the vertical direction Z may be thinner than the eighth thickness t8 of the first lower source / drain region 204a in the portion adjacent to the plurality of second lower channel regions 202b in the vertical direction Z.

[0035] although Figure 2It is shown that each transistor (e.g., the first upper transistor, the second upper transistor, the first lower transistor, or the second lower transistor) includes three channel regions stacked in the vertical direction Z, but in some embodiments, each transistor may include one, two, or more than three channel regions stacked in the vertical direction Z. In some embodiments, the first upper transistor of the weakened transistor stack TSw_1 and the second upper transistor of the reference transistor stack TS may include an equal number of channel regions, and the first lower transistor of the weakened transistor stack TSw_1 and the second lower transistor of the reference transistor stack TS may include an equal number of channel regions, such as Figure 2 As shown. Therefore, the channel region of the weakened transistor stack TSw_1 and the channel region of the reference transistor stack TS can be formed using the same process, and the current flowing through the weakened transistor stack TSw_1 can be reduced by adjusting the thickness of the first source / drain isolation layer 302a. In some embodiments, the lower surface of the lowest one of the multiple first upper channel regions 402a and the lower surface of the lowest one of the multiple second upper channel regions 402b can be spaced apart from the substrate 100 by an equal distance in the vertical direction Z, and the upper surface of the uppermost one of the multiple first lower channel regions 202a and the upper surface of the uppermost one of the multiple second lower channel regions 202b can be spaced apart from the substrate 100 by an equal distance in the vertical direction Z, as shown. Figure 2 shown.

[0036] In some embodiments, a bottom insulator 102 may be provided on the substrate 100 and may separate the substrate 100 from the first, second, and third lower source / drain regions 204a, 204b, and 204c. In addition, an insulating layer 104 may be provided on the weakened transistor stack TSw_1 and the reference transistor stack TS.

[0037] Reference Figure 3 , integrated circuit devices similar to Figure 2 The main difference of the integrated circuit device is that the weakened transistor stack TSw_2 is configured as follows: due to the configuration of the first source / drain isolation layer 302a', none of the plurality of first lower channel regions 202a are electrically isolated. In other words, current can flow through all of the plurality of first lower channel regions 202a. Figure 3 As shown, the first source / drain isolation layer 302a′ includes an upper portion extending into a space between the lowest one of the plurality of first upper channel regions 402a and the first upper source / drain region 404a, but does not include the upper portion of the first upper channel region 402a. Figure 24. The embodiment shown in FIG. 4 extends to the lower portion in the space between the uppermost one of the plurality of first lower channel regions 202a and the first lower source / drain region 204a. Therefore, the first thickness t1′ of the first source / drain isolation layer 302a′ in the portion adjacent to the plurality of first upper channel regions 402a in the vertical direction Z may be greater than the third thickness t3 of the first source / drain isolation layer 302a′ in the portion adjacent to the plurality of second upper channel regions 402b in the vertical direction Z. The fifth thickness t5 of the first upper source / drain region 404a in the portion adjacent to the plurality of first upper channel regions 402a in the vertical direction Z may be thinner than the sixth thickness t6 of the first upper source / drain region 404a in the vertical direction Z in the portion adjacent to the plurality of second upper channel regions 402b.

[0038] Reference Figure 4 , integrated circuit devices similar to Figure 2 The main difference is that the weakened transistor stack TSw_3 is configured as follows: due to the configuration of the first source / drain isolation layer 302a", none of the multiple first upper channel regions 402a are electrically isolated. In other words, current can flow through all of the multiple first upper channel regions 402a. Figure 4 As shown, the first source / drain isolation layer 302a" does not include Figure 2 The upper portion extending to the space between the lowest one of the plurality of first upper channel regions 402a and the first upper source / drain region 404a shown in the embodiment, but includes a lower portion extending to the space between the highest one of the plurality of first lower channel regions 202a and the first lower source / drain region 204a. Therefore, the first thickness t1″ of the first source / drain isolation layer 302a″ in the vertical direction Z in the portion adjacent to the plurality of first lower channel regions 202a may be greater than the third thickness t3 of the first source / drain isolation layer 302a″ in the vertical direction Z in the portion adjacent to the plurality of second lower channel regions 202b. The seventh thickness t7 of the first lower source / drain region 204a in the vertical direction Z in the portion adjacent to the plurality of first lower channel regions 202a may be thinner than the eighth thickness t8 of the first lower source / drain region 204a in the vertical direction Z in the portion adjacent to the plurality of second lower channel regions 202b.

[0039] exist Figures 1 to 4In some embodiments, the substrate 100 may include one or more semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP) and / or may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, and / or low-k materials). In some embodiments, the substrate 100 may be a bulk substrate (e.g., a silicon wafer), a semiconductor-on-insulator (SOI) substrate, or an insulating layer (e.g., a monolithic insulating layer). The low-k material may include, for example, fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymer dielectrics, and / or spin-on silicon-based polymer dielectrics.

[0040] Each of the first upper channel region 402a and the second upper channel region 402b and the first lower channel region 202a and the second lower channel region 202b may independently include, for example, one or more semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, each of the first upper channel region 402a and the second upper channel region 402b and the first lower channel region 202a and the second lower channel region 202b may be a nanosheet (which may have a thickness in the vertical direction Z in the range from 1nm to 100nm), or may be a nanowire (which may have a circular cross-section with a diameter in the range from 1nm to 100nm).

[0041] Each of the first upper gate insulator 406a and the second upper gate insulator 406b and the first lower gate insulator 206a and the second lower gate insulator 206b may include an interface layer and / or a high-k material layer sequentially stacked on a channel region (e.g., a corresponding one of the first upper channel region 402a and the second upper channel region 402b and the first lower channel region 202a and the second lower channel region 202b). For example, the interface layer may be a silicon oxide layer, and the high-k material layer may include, for example, hafnium silicate, zirconium silicate, hafnium dioxide, and / or zirconium dioxide.

[0042] Each of the first upper gate electrode 408a and the second upper gate electrode 408b and the first lower gate electrode 208a and the second lower gate electrode 208b may include a work function layer and / or a metal gate layer. The work function layer may include, for example, one or more work function materials (e.g., a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer). The metal gate layer may include, for example, tungsten (W), aluminum (Al), and / or copper (Cu).

[0043] Each of the first upper source / drain region 404a, the second upper source / drain region 404b and the third upper source / drain region 404c and the first lower source / drain region 204a, the second lower source / drain region 204b and the third lower source / drain region 204c may independently include, for example, one or more semiconductor layers (e.g., a silicon layer and / or a silicon germanium layer) and may further include dopants in the one or more semiconductor layers.

[0044] Each of the first upper gate spacer 410a and the second upper gate spacer 410b and the first lower gate spacer 210a and the second lower gate spacer 210b may independently include, for example, silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbon nitride. Each of the first source / drain isolation layer 302a, the second source / drain isolation layer 302b and the third source / drain isolation layer 302c, the first inter-gate insulator 304a and the second inter-gate insulator 304b, the bottom insulator 102 and the insulating layer 104 may independently include, for example, one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride and / or low-k material).

[0045] Figure 5 is a flow chart of a method of forming an integrated circuit device according to some embodiments. Figures 6 to 12 FIG. 1 is a diagram showing a method of forming an integrated circuit device (such as Figure 2 A cross-sectional view of a method of an integrated circuit device). Figure 5 and Figure 6 , the method may include forming a stack structure on a substrate 100 (block 502). The stack structure may include lower channel layers 202 alternately stacked with lower sacrificial layers 602, inter-gate insulator layers 304 formed on the lower sacrificial layers 602, and upper channel layers 402 alternately stacked with upper sacrificial layers 802. An etching mask 902 may be formed on the upper sacrificial layer 802. The lower sacrificial layer 602 may include a material having an etching selectivity relative to the lower channel layer 202, and the upper sacrificial layer 802 may include a material having an etching selectivity relative to the upper channel layer 402. Each of the lower sacrificial layer 602 and the upper sacrificial layer 802 may independently include, for example, one or more semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). For example, each of the lower sacrificial layer 602 and the upper sacrificial layer 802 may be a SiGe layer (e.g., a SiGe layer having a germanium atomic concentration of approximately 20%).

[0046] Reference Figure 5 and Figure 7, the stack structure may be etched using, for example, a wet etching process and / or a dry etching process to form a structure for weakening the transistor stack TSw_1 (left stack) and the reference transistor stack TS (right stack). Figure 8 An initial gate structure is formed as shown (block 504). Figure 8 As shown, after the recess etching, the first upper gate spacer 410a and the second upper gate spacer 410b may be formed on the side surface of the first upper sacrificial layer 802a and the side surface of the second upper sacrificial layer 802b, respectively, and the first lower gate spacer 210a and the second lower gate spacer 210b may be formed on the side surface of the first lower sacrificial layer 602a and the side surface of the second lower sacrificial layer 602b, respectively. The initial gate structure for the weakened transistor stack TSw_1 may include the first upper channel region 402a and the first lower channel region 202a, and the initial gate structure for the reference transistor stack TS may include the second upper channel region 402b and the second lower channel region 202b.

[0047] Reference Figure 5 and Fig. 9 , a first lower source / drain region 204a, a second lower source / drain region 204b, and a third lower source / drain region 204c may be formed (block 506). The first lower source / drain region 204a, the second lower source / drain region 204b, and the third lower source / drain region 204c may be formed, for example, by an epitaxial growth process. The first lower source / drain region 204a may be formed using both the first lower channel region 202a and the second lower channel region 202b as seed layers, the second lower source / drain region 204b may be formed using the first lower channel region 202a as a seed layer, and the third lower source / drain region 204c may be formed using the second lower channel region 202b as a seed layer. The first lower source / drain region 204a may include a first recess R1 adjacent to the first lower channel region 202a. In some embodiments, the first lower source / drain region 204a may be first formed to have a uniform thickness in the vertical direction Z, and then a portion of the first lower source / drain region 204a may be etched to form a first recess R1. The first recess R1 may expose a side surface of an uppermost one of the first lower channel regions 202a. Before forming the first lower source / drain region 204a, the second lower source / drain region 204b, and the third lower source / drain region 204c, a bottom insulator 102 may be formed on the substrate 100.

[0048] Reference Figure 5 and Fig.10, a first source / drain isolation layer 302a, a second source / drain isolation layer 302b, and a third source / drain isolation layer 302c may be formed (block 508). The first source / drain isolation layer 302a may include a second recess R2. In some embodiments, a first source / drain isolation layer 302a having a flat upper surface may be first formed, and then a portion of the first source / drain isolation layer 302a adjacent to the second upper channel region 402b may be etched to form a second recess R2. The second recess R2 may expose a side surface of the lowermost one of the second upper channel regions 402b. In some embodiments, the first source / drain isolation layer 302a, the second source / drain isolation layer 302b, and the third source / drain isolation layer 302c may first be deposited or grown to approximately the same thickness, a mask may be formed on a portion of the first source / drain isolation layer 302a adjacent to the upper sacrificial layer 802a, and then the first source / drain isolation layer 302a, the second source / drain isolation layer 302a, and the third source / drain isolation layer 302c may be etched so that a second recess R2 is formed in the first source / drain isolation layer 302a.

[0049] Reference Figure 5 and Fig.11 , a first upper source / drain region 404a, a second upper source / drain region 404b, and a third upper source / drain region 404c may be formed (block 510). The first upper source / drain region 404a, the second upper source / drain region 404b, and the third upper source / drain region 404c may be formed, for example, by an epitaxial growth process. The first upper source / drain region 404a may be formed using both the first upper channel region 402a and the second upper channel region 402b as seed layers, the second upper source / drain region 404b may be formed using the first upper channel region 402a as a seed layer, and the third upper source / drain region 404c may be formed using the second upper channel region 402b as a seed layer.

[0050] Reference Figure 5 and Fig.12 , the etching mask 902 may be removed, and an insulating layer 104 may be formed on the first upper source / drain region 404a, the second upper source / drain region 404b, and the third upper source / drain region 404c. By removing the etching mask 902, the uppermost layer in the first upper sacrificial layer 802a and the uppermost layer in the second upper sacrificial layer 802b may be exposed. Return to reference Figure 2, gate insulators (e.g., first and second upper gate insulators 406a and 406b and first and second lower gate insulators 206a and 206b) and gate electrodes (e.g., first and second upper gate electrodes 408a and 408b and first and second lower gate electrodes 208a and 208b) may be formed (block 512). The gate insulators and gate electrodes may be formed in the space from which the sacrificial layers (e.g., first and second upper sacrificial layers 802a and 802b and first and second lower sacrificial layers 602a and 602b) are removed.

[0051] Fig.13 , Fig.14 and Fig.15 According to some embodiments, Figure 1 A cross-sectional view of the integrated circuit device taken along the line AA' in FIG. Fig.13 , integrated circuit devices similar to Figure 2 The integrated circuit device has a main difference in that: instead of using the first source / drain isolation layer 302a to electrically isolate the bottommost one of the multiple first upper channel regions 402a and the topmost one of the multiple first lower channel regions 202a to reduce the current flowing through the weakened transistor stack TSw_1, the thickness of the first inter-gate insulator 305a can be adjusted to change the number of the multiple first upper channel regions 402a and the number of the multiple first lower channel regions 202a.

[0052] like Fig.13 As shown, the ninth thickness t9 of the first inter-gate insulator 305a of the weakened transistor stack TSw_4 in the vertical direction Z may be greater than the tenth thickness t10 of the second inter-gate insulator 304b in the vertical direction Z. As a result, the first inter-gate insulator 305a may overlap with the lowermost one of the plurality of second upper channel regions 402b and the uppermost one of the plurality of second lower channel regions 202b in the first direction X. The second inter-gate insulator 304b may not overlap with the lowermost one of the plurality of first upper channel regions 402a and the uppermost one of the plurality of first lower channel regions 202a in the first direction X.

[0053] Due to the ninth thickness t9 of the first inter-gate insulator 305a, the number of the plurality of first upper channel regions 402a in the weakened transistor stack TSw_4 may be smaller than the number of the plurality of second upper channel regions 402b in the reference transistor stack TS, and the number of the plurality of first lower channel regions 202a in the weakened transistor stack TSw_4 may be smaller than the number of the plurality of second lower channel regions 202b in the reference transistor stack TS. In addition, the upper surface of the first inter-gate insulator 305a and the upper surface of the bottommost one of the plurality of second upper channel regions 402b may be equidistant from the substrate 100, that is, the seventh distance d7 may be equal to the eighth distance d8. The lower surface of the first inter-gate insulator 305a and the lower surface of the topmost one of the plurality of second lower channel regions 202b may also be equidistant from the substrate 100, that is, the ninth distance d9 may be equal to the tenth distance d10. In addition, the fifth distance d5 from the lower surface of the lowest one of the multiple first upper channel regions 402a to the upper surface of the highest one of the multiple first lower channel regions 202a may be greater than the sixth distance d6 from the lower surface of the lowest one of the multiple second upper channel regions 402b to the upper surface of the highest one of the multiple second lower channel regions 202b.

[0054] and Figures 2 to 4 Unlike the weakened transistor stacks TSw_1, TSw_2, and TSw_3 shown in FIG, the first source / drain isolation layer 303a of the weakened transistor stack TSw_4 may have a thickness in the vertical direction Z that is the same as or similar to the thickness of the second source / drain isolation layer 302b and the third source / drain isolation layer 302c, such as Fig.13 shown.

[0055] Reference Fig.14 , integrated circuit devices similar to Fig.13The integrated circuit device of the present invention mainly differs in that the first inter-gate insulator 305a' of the weakened transistor stack TSw_5 overlaps only with the bottommost one of the plurality of second upper channel regions 402b in the first direction X and does not overlap with the topmost one of the plurality of second lower channel regions 202b. Therefore, the number of the plurality of first upper channel regions 402a in the weakened transistor stack TSw_5 may be less than the number of the plurality of second upper channel regions 402b in the reference transistor stack TS, but the number of the plurality of first lower channel regions 202a in the weakened transistor stack TSw_5 may be equal to the number of the plurality of second lower channel regions 202b in the reference transistor stack TS. The ninth thickness t9' of the first inter-gate insulator 305a' may be greater than the tenth thickness t10 of the second inter-gate insulator layer 304b. A fifth distance d5′ from a lower surface of a lowermost one of the plurality of first upper channel regions 402a to an upper surface of an uppermost one of the plurality of first lower channel regions 202a may be greater than a sixth distance d6 from a lower surface of a lowermost one of the plurality of second upper channel regions 402b to an upper surface of an uppermost one of the plurality of second lower channel regions 202b.

[0056] like Fig.14 As shown, in some embodiments, the upper surface of the first inter-gate insulator 305a' may be farther from the substrate 100 than the upper surface of the second inter-gate insulator 304b in the vertical direction Z. In addition, the upper surface of the uppermost one of the plurality of first upper channel regions 402a and the upper surface of the uppermost one of the plurality of second upper channel regions 402b may be equidistant from the substrate 100 in the vertical direction Z, and the lower surface of the lowermost one of the plurality of first upper channel regions 402a may be farther from the substrate 100 in the vertical direction Z than the lower surface of the lowermost one of the plurality of second upper channel regions 402b.

[0057] Reference Fig.15 , integrated circuit devices similar to Fig.13The integrated circuit device of the present invention mainly differs in that the first inter-gate insulator 305a" of the weakened transistor stack TSw_6 overlaps only with the uppermost one of the plurality of second lower channel regions 202b in the first direction X and does not overlap with the lowermost one of the plurality of second upper channel regions 402b. Therefore, the number of the plurality of first lower channel regions 202a in the weakened transistor stack TSw_6 may be less than the number of the plurality of second lower channel regions 202b in the reference transistor stack TS, but the number of the plurality of first upper channel regions 402a in the weakened transistor stack TSw_6 may be equal to the number of the plurality of second lower channel regions 202b in the reference transistor stack TS. The number of the multiple second upper channel regions 402b in the body tube stack TS. The ninth thickness t9" of the first inter-gate insulator 305a" may be greater than the tenth thickness t10 of the second inter-gate insulator 304b. In the vertical direction Z, the fifth distance d5" from the lower surface of the lowest one of the multiple first upper channel regions 402a to the upper surface of the highest one of the multiple first lower channel regions 202a may be greater than the sixth distance d6 from the lower surface of the lowest one of the multiple second upper channel regions 402b to the upper surface of the highest one of the multiple second lower channel regions 202b.

[0058] like Fig.15 As shown, in some embodiments, a lower surface of the first inter-gate insulator 305a" may be closer to the substrate 100 in the vertical direction Z than a lower surface of the second inter-gate insulator 304b. In addition, a lower surface of a lowermost one of the plurality of first lower channel regions 202a and a lower surface of a lowermost one of the plurality of second lower channel regions 202b may be equidistant from the substrate 100 in the vertical direction Z, and an upper surface of an uppermost one of the plurality of first lower channel regions 202a may be closer to the substrate 100 in the vertical direction Z than an upper surface of an uppermost one of the plurality of second lower channel regions 202b.

[0059] Fig.23 is a flow chart of a method of forming an integrated circuit device according to some embodiments. Figures 16 to 22 FIG. 1 is a diagram showing a method of forming an integrated circuit device (such as Fig.13 A cross-sectional view of a method for an integrated circuit device). Figures 16 to 22 The method shown in is similar to that shown in Figures 5 to 12 The methods described mainly differ in the stacking structure (e.g. Fig.19 The structure shown in FIG. 1 includes a thick first inter-gate insulator layer 305 to form a first inter-gate insulator 305a that weakens the transistor stack TSw_4.

[0060] Reference Fig.16 and Fig.23, a lower portion of the stacked structure may be formed (block 2302). The lower portion of the stacked structure may include lower channel layers 202 alternately stacked with lower sacrificial layers 602, inter-gate insulator layers 304 formed on the lower sacrificial layers 602, upper sacrificial layers 802 (e.g., the lowermost one of the upper sacrificial layers 802), and upper channel layers 402 (e.g., the lowermost one of the upper channel layers 402).

[0061] Reference Fig.17 and Fig.23 By removing a portion of the upper channel layer 402, a portion of the upper sacrificial layer 802, a portion of the inter-gate insulator layer 304, a portion of the uppermost one of the lower sacrificial layers 602, and a portion of the uppermost one of the lower channel layers 202, it is possible to Fig.16 A third recess R3 is formed in the lower portion of the stacked structure as shown (block 2304). The third recess R3 may be formed by, for example, a wet etching process and / or a dry etching process.

[0062] Reference Fig.18 and Fig.23 , a first inter-gate insulator layer 305 may be formed in the third recess R3 using, for example, deposition (block 2306). The first inter-gate insulator layer 305 may include, for example, one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, and / or low-k material). In some embodiments, the first inter-gate insulator layer 305 and the inter-gate insulator layer 304 may include the same material. Fig.19 and Fig.23 , additional upper sacrificial layers 802 and upper channel layers 402 may be formed in an alternating manner, and then an etch mask 902 may be formed on the resulting stacked structure (block 2308 ).

[0063] Reference Fig. 20 and Fig.23 , can be executed and referenced Figure 7 and Figure 8 The initial gate structure for the weakened transistor stack TSw_4 (the structure on the left) and the initial gate structure for the reference transistor stack TS (the structure on the right) are formed by a process similar to the process described above (block 2310). The initial gate structure for the weakened transistor stack TSw_4 may include a first inter-gate insulator 305a, which is thicker than the second inter-gate insulator 304b of the initial gate structure for the reference transistor stack TS. Since a portion of the upper channel layer 402 and a portion of the uppermost one of the lower channel layers 202 (reference transistor stack TS) are removed when forming the third recess R3, the initial gate structure for the weakened transistor stack TSw_4 may include a first inter-gate insulator 305a, which is thicker than the second inter-gate insulator 304b of the initial gate structure for the reference transistor stack TS. Fig.17), the number of the multiple first upper channel regions 402a in the initial gate structure for weakening the transistor stack TSw_4 can be smaller than the number of the multiple second upper channel regions 402b in the initial gate structure for the reference transistor stack TS, and the number of the multiple first lower channel regions 202a in the initial gate structure for weakening the transistor stack TSw_4 can be smaller than the number of the multiple second lower channel regions 202b in the initial gate structure for the reference transistor stack TS.

[0064] Reference Fig.21 and Fig.23 , the first lower source / drain region 204a, the second lower source / drain region 204b, and the third lower source / drain region 204c may be formed by, for example, an epitaxial growth process (block 2312). The first lower source / drain region 204a may be formed using both the first lower channel region 202a and the second lower channel region 202b as seed layers, the second lower source / drain region 204b may be formed using the first lower channel region 202a as a seed layer, and the third lower source / drain region 204c may be formed using the second lower channel region 202b as a seed layer. Then, a first source / drain isolation layer 303a, a second source / drain isolation layer 302b, and a third source / drain isolation layer 302c may be formed. The first upper source / drain region 404a, the second upper source / drain region 404b, and the third upper source / drain region 404c may be formed on the first source / drain isolation layer 303a, the second source / drain isolation layer 302b, and the third source / drain isolation layer 302c, respectively. The first upper source / drain region 404a, the second upper source / drain region 404b, and the third upper source / drain region 404c may be formed, for example, by an epitaxial growth process. The first upper source / drain region 404a may be formed using both the first upper channel region 402a and the second upper channel region 402b as seed layers, the second upper source / drain region 404b may be formed using the first upper channel region 402a as a seed layer, and the third upper source / drain region 404c may be formed using the second upper channel region 402b as a seed layer.

[0065] Reference Fig. 22 and Fig.23 , the etching mask 902 may be removed, and an insulating layer 104 may be formed on the first upper source / drain region 404a, the second upper source / drain region 404b, and the third upper source / drain region 404c (block 2314). By removing the etching mask 902, the uppermost layer in the first upper sacrificial layer 802a and the uppermost layer in the second upper sacrificial layer 802b may be exposed. Return to reference Fig.13, gate insulators (e.g., first upper gate insulators 406a and second upper gate insulators 406b and first lower gate insulators 206a and second lower gate insulators 206b) and gate electrodes (e.g., first upper gate electrodes 408a and second upper gate electrodes 408b and first lower gate electrodes 208a and second lower gate electrodes 208b) may be formed. The gate insulator and the gate electrode may be formed in a space from which the sacrificial layers (e.g., first upper sacrificial layers 802a and second upper sacrificial layers 802b and first lower sacrificial layers 602a and second lower sacrificial layers 602b) are removed.

[0066] Example embodiments are described herein with reference to the accompanying drawings. Without departing from the teachings of the present disclosure, many different forms and embodiments are possible, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be conveyed to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Throughout the specification, the same reference numerals refer to the same elements. Note that aspects described with respect to one embodiment may be incorporated into different embodiments, although not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0067] Example embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of intermediate structures of idealized embodiments and example embodiments. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments herein should not be construed as limited to the specific shapes shown herein, but may include deviations in shapes caused, for example, by manufacturing.

[0068] It should also be noted that in some alternative implementations, the function / action pointed out in the flow chart square frame here may not occur in the order pointed out in the flow chart. For example, two square frames shown continuously can actually be performed substantially simultaneously, or square frame can sometimes be performed in reverse order, depending on the function / action involved. In addition, the function of the given square frame of flow chart and / or block diagram can be divided into a plurality of square frames and / or the function of two or more square frames of flow chart and / or block diagram can be integrated at least in part. Finally, without departing from the scope of the present invention, other square frames can be added / inserted between the square frames shown, and / or square frame / operation can be omitted.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0070] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups thereof.

[0071] It will be understood that when an element is referred to as being "connected to" or "on" another element, it may be directly connected to or directly on another element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected to" or "directly on" another element, there are no intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (e.g., when used in the term "source / drain") will be understood to be equivalent to the term "and / or".

[0072] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this embodiment, the first element may be referred to as the second element.

[0073] As used herein, "lower surface" refers to the surface facing the substrate (e.g. Figure 2 In the embodiment of the present invention, the term "upper surface" refers to a surface opposite to the lower surface. In addition, as used herein, "lower portion" refers to a portion closer to the substrate than the "upper portion". In addition, as used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one line that extends in direction X and intersects both element A and element B.

[0074] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein and the manner and process of making and using them, and will support claims to any such combination or subcombination.

[0075] The subject matter disclosed above is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent permitted by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0076] This application claims the benefit of priority to U.S. Provisional Patent Application Serial No. 63 / 519338, filed on August 14, 2023, entitled “Method for Implementing Stacked Field Effect Transistor Weakening Device,” U.S. Patent Application No. 18 / 593051, filed on March 1, 2024, and Korean Patent Application No. 10-2024-0087800, filed on July 3, 2024, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. An integrated circuit device, comprising: A weakened transistor stack on a substrate, the weakened transistor stack comprising: A first upper transistor comprises: A plurality of first upper channel regions are stacked in a vertical direction; a first upper gate structure, the plurality of first upper channel regions being provided in the first upper gate structure; and a first upper source / drain region contacting the plurality of first upper channel regions; A first lower transistor is between the substrate and the first upper transistor and comprises: A plurality of first lower channel regions, stacked in the vertical direction; a first lower gate structure, the plurality of first lower channel regions being provided in the first lower gate structure; and a first lower source / drain region contacting the plurality of first lower channel regions; and a first inter-gate insulator between the first upper gate structure and the first lower gate structure; and a transistor stack adjacent to the weakened transistor stack on the substrate, the transistor stack comprising: The second upper transistor comprises: a plurality of second upper channel regions stacked in the vertical direction, wherein the first upper source / drain region contacts the plurality of second upper channel regions; and a second upper gate structure, the plurality of second upper channel regions being provided in the second upper gate structure; A second lower transistor is between the substrate and the second upper transistor and comprises: a plurality of second lower channel regions stacked in the vertical direction, wherein the first lower source / drain region contacts the plurality of second lower channel regions; and a second lower gate structure, the plurality of second lower channel regions being provided in the second lower gate structure; and a second inter-gate insulator, between the second upper gate structure and the second lower gate structure, wherein the first inter-gate insulator is spaced apart from the second inter-gate insulator in a horizontal direction, and The first inter-gate insulator overlaps a lowermost one of the plurality of second upper channel regions and / or an uppermost one of the plurality of second lower channel regions in the horizontal direction. 2 . The integrated circuit device according to claim 1 , wherein the second inter-gate insulator does not overlap with a lowermost one of the plurality of first upper channel regions and an uppermost one of the plurality of first lower channel regions in the horizontal direction. 3 . The integrated circuit device according to claim 1 , wherein the first inter-gate insulator has a first thickness in the vertical direction, the second inter-gate insulator has a second thickness in the vertical direction, and the first thickness is thicker than the second thickness.

4. An integrated circuit device according to claim 1, wherein the first inter-gate insulator overlaps with the lowest one of the plurality of second upper channel regions in the horizontal direction, and an upper surface of the first inter-gate insulator is farther away from the substrate than an upper surface of the second inter-gate insulator in the vertical direction. 5 . The integrated circuit device according to claim 4 , wherein the upper surface of the first inter-gate insulator and the upper surface of the lowermost one of the plurality of second upper channel regions are equidistant from the substrate in the vertical direction.

6. An integrated circuit device according to claim 1, wherein the first inter-gate insulator overlaps with the uppermost one of the plurality of second lower channel regions in the horizontal direction, and a lower surface of the first inter-gate insulator is closer to the substrate than a lower surface of the second inter-gate insulator in the vertical direction. 7 . The integrated circuit device of claim 6 , wherein the lower surface of the first inter-gate insulator and the lower surface of the uppermost one of the plurality of second lower channel regions are equidistant from the substrate in the vertical direction.

8. The integrated circuit device according to claim 1, wherein the first inter-gate insulator overlaps the lowermost one of the plurality of second upper channel regions in the horizontal direction, and The number of the plurality of first upper channel regions is smaller than the number of the plurality of second upper channel regions. 9 . The integrated circuit device according to claim 8 , wherein an upper surface of an uppermost one of the plurality of first upper channel regions and an upper surface of an uppermost one of the plurality of second upper channel regions are equidistant from the substrate in the vertical direction.

10. The integrated circuit device of claim 1, wherein the first inter-gate insulator overlaps the uppermost one of the plurality of second lower channel regions in the horizontal direction, the number of the plurality of first lower channel regions being smaller than the number of the plurality of second lower channel regions. 11 . The integrated circuit device of claim 10 , wherein a lower surface of a lowermost one of the plurality of first lower channel regions and a lower surface of a lowermost one of the plurality of second lower channel regions are equidistant from the substrate in the vertical direction.

12. An integrated circuit device comprising: A weakened transistor stack on a substrate, the weakened transistor stack comprising: A first upper transistor comprises: A plurality of first upper channel regions are stacked in a vertical direction; a first upper gate structure, the plurality of first upper channel regions being provided in the first upper gate structure; and a first upper source / drain region contacting the plurality of first upper channel regions; and A first lower transistor is between the substrate and the first upper transistor and comprises: A plurality of first lower channel regions, stacked in the vertical direction; a first lower gate structure, the plurality of first lower channel regions being provided in the first lower gate structure; and a first lower source / drain region contacting the plurality of first lower channel regions; and a transistor stack adjacent to the weakened transistor stack on the substrate, the transistor stack comprising: The second upper transistor comprises: a plurality of second upper channel regions stacked in the vertical direction, wherein the first upper source / drain region contacts the plurality of second upper channel regions; and a second upper gate structure, the plurality of second upper channel regions being provided in the second upper gate structure; and A second lower transistor is between the substrate and the second upper transistor and comprises: a plurality of second lower channel regions stacked in the vertical direction, wherein the first lower source / drain region contacts the plurality of second lower channel regions; and a second lower gate structure, the plurality of second lower channel regions being provided in the second lower gate structure, wherein the lowest one of the plurality of first upper channel regions and the highest one of the plurality of first lower channel regions are spaced apart from each other by a first distance in the vertical direction, and the lowest one of the plurality of second upper channel regions and the highest one of the plurality of second lower channel regions are spaced apart from each other by a second distance in the vertical direction, and the first distance is longer than the second distance.

13. The integrated circuit device of claim 12, wherein the weakened transistor stack further comprises a first inter-gate insulator between the first upper gate structure and the first lower gate structure, The transistor stack further includes a second inter-gate insulator between the second upper gate structure and the second lower gate structure, The first inter-gate insulator has a first thickness in the vertical direction, and the second inter-gate insulator has a second thickness in the vertical direction, and the first thickness is thicker than the second thickness. 14 . The integrated circuit device according to claim 12 , wherein the number of the plurality of first upper channel regions is smaller than the number of the plurality of second upper channel regions. 15 . The integrated circuit device of claim 14 , wherein a lower surface of the lowermost one of the plurality of first upper channel regions is farther from the substrate in the vertical direction than a lower surface of the lowermost one of the plurality of second upper channel regions. 16 . The integrated circuit device of claim 12 , wherein the number of the plurality of first lower channel regions is smaller than the number of the plurality of second lower channel regions. 17 . The integrated circuit device of claim 16 , wherein an upper surface of the uppermost one of the plurality of first lower channel regions is closer to the substrate in the vertical direction than an upper surface of the uppermost one of the plurality of second lower channel regions.

18. An integrated circuit device comprising: A weakened transistor stack on a substrate, the weakened transistor stack comprising: A first upper transistor comprises: A plurality of first upper channel regions are stacked in a vertical direction; a first upper gate structure, the plurality of first upper channel regions being provided in the first upper gate structure; and a first upper source / drain region contacting the plurality of first upper channel regions; and A first lower transistor is between the substrate and the first upper transistor and comprises: A plurality of first lower channel regions, stacked in the vertical direction; a first lower gate structure, the plurality of first lower channel regions being provided in the first lower gate structure; and a first lower source / drain region contacting the plurality of first lower channel regions; and a transistor stack adjacent to the weakened transistor stack on the substrate, the transistor stack comprising: The second upper transistor comprises: a plurality of second upper channel regions stacked in the vertical direction, wherein the first upper source / drain region contacts the plurality of second upper channel regions; and a second upper gate structure, the plurality of second upper channel regions being provided in the second upper gate structure; A second lower transistor is between the substrate and the second upper transistor and comprises: a plurality of second lower channel regions stacked in the vertical direction, wherein the first lower source / drain region contacts the plurality of second lower channel regions; and a second lower gate structure, the plurality of second lower channel regions being provided in the second lower gate structure, wherein the number of the plurality of first upper channel regions is less than the number of the plurality of second upper channel regions, and / or The number of the plurality of first lower channel regions is smaller than the number of the plurality of second lower channel regions.

19. The integrated circuit device according to claim 18, wherein the number of the plurality of first upper channel regions is smaller than the number of the plurality of second upper channel regions, and A lower surface of a lowermost one of the plurality of first upper channel regions is farther from the substrate in the vertical direction than a lower surface of a lowermost one of the plurality of second upper channel regions.

20. The integrated circuit device according to claim 18, wherein the number of the plurality of first lower channel regions is smaller than the number of the plurality of second lower channel regions, and An upper surface of an uppermost one of the plurality of first lower channel regions is closer to the substrate in the vertical direction than an upper surface of an uppermost one of the plurality of second lower channel regions.

21. A method of forming an integrated circuit device, comprising: forming a stacked structure on an upper surface of the substrate, the stacked structure comprising alternately stacked lower channel layers and lower sacrificial layers, an inter-gate insulator layer on the lower channel layers and the lower sacrificial layers, and alternately stacked upper channel layers and upper sacrificial layers; etching the stack structure to form a recess therein; forming a weakened inter-gate insulator layer in the recess, the weakened inter-gate insulator layer having a greater thickness than the inter-gate insulator layer; etching the stack structure to form a weakened transistor stack and a reference transistor stack, the weakened transistor stack comprising the weakened inter-gate insulator layer, the weakened inter-gate insulator layer overlapping at least one of the upper channel layer and the lower channel layer of the reference transistor stack in a direction parallel to the upper surface of the substrate; forming a first initial gate structure for the weakened transistor stack and a second initial gate structure for the reference transistor stack; forming a lower source / drain region adjacent to the weakened transistor stack and the reference transistor stack; forming a source / drain isolation layer on the lower source / drain region; as well as An upper source / drain region is formed on the source / drain isolation layer.

22. The method of claim 21, wherein each of the lower sacrificial layer and the upper sacrificial layer comprises Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP.

23. The method of claim 21 , wherein etching the stack structure to form the weakened transistor stack and the reference transistor stack comprises: The stack structure is dry-etched or wet-etched to form the weakened transistor stack and the reference transistor stack.

24. The method of claim 21, wherein forming the first initial gate structure comprises: forming a first upper gate spacer on a side surface of the upper sacrificial layer of the weakened transistor stack and forming a first lower gate spacer on a side surface of the lower sacrificial layer of the weakened transistor stack; as well as A first upper gate spacer is formed on a side surface of the upper sacrificial layer of the reference transistor stack and a first lower gate spacer is formed on a side surface of the lower sacrificial layer of the reference transistor stack.

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