Integrated circuit device including diode

Abstract

An integrated circuit device includes: a substrate including a first surface and a second surface opposite the first surface; and a diode structure including: an upper semiconductor layer disposed on the first surface of the substrate and including a first dopant of a first conductivity type; a lower semiconductor layer disposed on the second surface of the substrate and including a second dopant of a second conductivity type different from the first conductivity type; and a first well region disposed in a portion of the substrate between the upper semiconductor layer and the lower semiconductor layer, where the first well region is in contact with the upper semiconductor layer or the lower semiconductor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0103698 filed on August 8, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept relate to an integrated circuit device, and more particularly, to an integrated circuit device including a diode. Background Art

[0004] Due to the continuous development of electronic technology, the demand for high integration of integrated circuit devices is increasing, and miniaturization is advancing. As the size of integrated circuit devices decreases, the demand for electrostatic discharge (ESD) protection in integrated circuit devices is increasing. Traditional ESD protection elements include diodes connected between power / ground connection units and integrated circuit pin connection units. However, in three-dimensional integrated circuit devices such as finFETs or nanosheet FETs, the thickness and / or volume of the silicon substrate is reduced, which may make it difficult to form an effective pn junction. Summary of the invention

[0005] According to an embodiment conceived in the present invention, an integrated circuit device includes: a substrate including a first surface and a second surface opposite to the first surface; and a diode structure including: an upper semiconductor layer, disposed on the first surface of the substrate and including a first dopant of a first conductivity type; a lower semiconductor layer, disposed on the second surface of the substrate and including a second dopant of a second conductivity type different from the first conductivity type; a first well region, disposed in a portion of the substrate located between the upper semiconductor layer and the lower semiconductor layer, wherein the first well region is in contact with the upper semiconductor layer or the lower semiconductor layer.

[0006] According to an embodiment conceived in the present invention, an integrated circuit device includes: a diode structure, wherein the diode structure includes: an upper semiconductor layer, disposed on a first surface of a substrate and including a first dopant of a first conductivity type; a lower semiconductor layer, disposed on a second surface of the substrate opposite to the first surface of the substrate and including a second dopant of a second conductivity type different from the first conductivity type; a first well region, arranged in a first portion of the substrate and including a third dopant of the first conductivity type, wherein the first portion is adjacent to the first surface of the substrate; and a second well region, arranged in a second portion of the substrate and including a fourth dopant of the second conductivity type, wherein the second portion is adjacent to the second surface of the substrate.

[0007] According to an embodiment conceived in the present invention, an integrated circuit device includes: a diode structure, wherein the diode structure includes: an upper semiconductor layer, which is arranged on a first surface of a substrate and includes a first dopant of a first conductivity type; a lower semiconductor layer, which is arranged on a second surface of the substrate opposite to the first surface of the substrate and includes a second dopant of a second conductivity type different from the first conductivity type; a first well region, which is arranged in a first portion of the substrate and includes a third dopant of the first conductivity type, wherein the first portion of the substrate is adjacent to the first surface of the substrate; and a second well region, which is arranged in a second portion of the substrate and includes a fourth dopant of the second conductivity type, wherein the second portion of the substrate is adjacent to the second surface of the substrate; a nanosheet structure, which is arranged on the first surface of the substrate and is arranged to be adjacent to a side wall of the upper semiconductor layer; a first contact portion, which is arranged on the first surface of the upper semiconductor layer; a front surface wiring structure, which is electrically connected to the first contact portion; a molded insulating layer, which is arranged on the second surface of the substrate and the lower semiconductor layer; a second contact portion, which is arranged on the first surface of the lower semiconductor layer; and a rear surface wiring structure, which is electrically connected to the second contact portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects of the present inventive concept will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:

[0009] Figure 1 is a schematic layout of an integrated circuit device according to an embodiment of the inventive concept;

[0010] Figure 2 yes Figure 1 The integrated circuit device is along Figure 1 A cross-sectional view taken along line A1-A1';

[0011] Figure 3 yes Figure 1 The integrated circuit device is along Figure 1 A cross-sectional view taken along line A2-A2';

[0012] Figure 4 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0013] Figure 5 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0014] Figure 6 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0015] Figure 7 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0016] Figure 8is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0017] Fig. 9 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0018] Fig.10 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0019] Fig.11 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0020] Fig.12 is a layout of an integrated circuit device according to an embodiment of the inventive concept;

[0021] Fig.13 yes Fig.12 The integrated circuit device is along Fig.12 A cross-sectional view taken along line A1-A1';

[0022] Fig.14 yes Fig.12 The integrated circuit device is along Fig.12 A cross-sectional view taken along line A2-A2';

[0023] Fig.15 and Fig.16 is a cross-sectional view of an integrated circuit device according to an embodiment; and

[0024] Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 and Fig.32 is a cross-sectional view of a method of fabricating an integrated circuit device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] Embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a schematic layout of an integrated circuit device 100 according to an embodiment of the inventive concept. Figure 2 yes Figure 1 The integrated circuit device 100 is along Figure 1A cross-sectional view taken along line A1-A1'. Figure 3 yes Figure 1 The integrated circuit device 100 is along Figure 1 A cross-sectional view taken along line A2-A2'.

[0027] Reference Figures 1 to 3 , the integrated circuit device 100 may include a diode structure DS formed on the substrate 110. The integrated circuit device 100 may also include a field effect transistor formed on the substrate 110, and at least a portion of the diode structure DS may be formed simultaneously in a process of manufacturing the field effect transistor. In an embodiment of the inventive concept, the field effect transistor may include a logic unit including a multi-bridge channel FET (MBCFET) element. The diode structure DS may be part of an electrostatic discharge (ESD) protection circuit electrically connected to the logic unit.

[0028] In an embodiment of the present inventive concept, the substrate 110 may include a Group IV semiconductor such as Si or Ge, a Group IV-IV compound semiconductor such as SiGe or SiC, or a Group III-V compound semiconductor such as GaAs, InAs or InP. The substrate 110 may include a first surface 110F1 and a second surface 110F2 opposite to the first surface 110F1.

[0029] The diode structure DS may include an upper semiconductor layer 122, a lower semiconductor layer 124, a first well region WE1, and a second well region WE2. The upper semiconductor layer 122, the lower semiconductor layer 124, the first well region WE1, and the second well region WE2 may be arranged to overlap each other in a vertical direction Z, and the diode structure DS may include a vertical diode having a current path formed along the vertical direction Z.

[0030] The upper semiconductor layer 122 may be disposed on the first surface 110F1 of the substrate 110. The bottom of the upper semiconductor layer 122 may be arranged in a first recessed region RS1 formed in the first surface 110F1 of the substrate 110, and may extend upward from the first surface 110F1 of the substrate 110 (or, for example, in a direction away from the first surface 110F1 of the substrate 110). For example, the first recessed region RS1 may refer to a portion of the substrate 110 that is recessed in a direction from the first surface 110F1 of the substrate 110 toward the second surface 110F2 of the substrate 110, and the upper semiconductor layer 122 may extend from above the first recessed region RS1 in a direction away from the second surface 110F2 of the substrate 110 (or in a direction away from the substrate 110) along the vertical direction Z.

[0031] In an embodiment of the present inventive concept, the upper semiconductor layer 122 may include at least one semiconductor material such as Si, SiGe, SiP, SiGeB, and SiGeC. In an embodiment of the present inventive concept, the upper semiconductor layer 122 may be formed on the first surface 110F1 of the substrate 110 through an epitaxial growth process by using an exposed surface of the first recessed region RS1 as a seed layer.

[0032] In an embodiment of the present inventive concept, the upper semiconductor layer 122 may include a first dopant of a first conductivity type, and, for example, the first conductivity type may be an n-type. For example, the first dopant may include phosphorus or arsenic. The upper semiconductor layer 122 may be a region including a relatively high concentration of the first dopant, and, for example, may be referred to as an N+ region.

[0033] The lower semiconductor layer 124 may be disposed on the second surface 110F2 of the substrate 110. The lower semiconductor layer 124 may be arranged in a second recessed region RS2 formed in the second surface 110F2 of the substrate 110, and may extend downward from the second surface 110F2 of the substrate 110. For example, the lower semiconductor layer 124 may extend away from the substrate 110. For example, the second recessed region RS2 may refer to a portion of the substrate 110 that is recessed in a direction from the second surface 110F2 of the substrate 110 toward the first surface 110F1 of the substrate 110. For example, the upper surface of the lower semiconductor layer 124 may contact the second recessed region RS2, and the lower semiconductor layer 124 may extend in a vertical direction Z in a direction away from the first surface 110F1 of the substrate 110 (or in a direction away from the substrate 110). For example, as Figure 2 As shown, the upper semiconductor layer 122 and the lower semiconductor layer 124 may vertically overlap each other, and the substrate 110 may be disposed between the upper semiconductor layer 122 and the lower semiconductor layer 124. However, the inventive concept is not limited thereto. For example, the upper semiconductor layer 122 may not overlap the lower semiconductor layer 124.

[0034] In an embodiment of the present inventive concept, the lower semiconductor layer 124 may include at least one of Si, SiGe, SiP, SiGeB, and SiGeC. In an embodiment of the present inventive concept, the lower semiconductor layer 124 may be formed on the second surface 110F2 of the substrate 110 through an epitaxial growth process using an exposed surface of the second recessed region RS2 as a seed layer.

[0035] In an embodiment of the present inventive concept, the lower semiconductor layer 124 may include a second dopant of a second conductivity type, and the second conductivity type may be different from the first conductivity type. For example, the second conductivity type may be a p-type. For example, the second dopant may include boron. The lower semiconductor layer 124 may be a region including a relatively high concentration of the second dopant, and may be referred to as a P+ region, for example.

[0036] The first well region WE1 may be disposed at an upper side of the substrate 110 (the upper side being adjacent to the first surface 110F1 of the substrate 110), or may be arranged in a first portion of the substrate 110. In addition, the first well region WE1 may be arranged between the upper semiconductor layer 122 and the lower semiconductor layer 124 along the vertical direction Z. The first well region WE1 may contact the upper semiconductor layer 122.

[0037] In an embodiment of the present inventive concept, the first well region WE1 may include a third dopant of the first conductivity type. For example, the first well region WE1 may be an impurity region formed by ion-implanting the third dopant into a first portion of the substrate 110, the first portion being adjacent to the first surface 110F1 of the substrate 110. For example, the third dopant may include phosphorus or arsenic.

[0038] The second well region WE2 may be disposed in a lower side of the substrate 110 adjacent to the second surface 110F2 of the substrate 110, or may be disposed in a second portion of the substrate 110. The second well region WE2 may be disposed between the upper semiconductor layer 122 and the lower semiconductor layer 124 along the vertical direction Z. The second well region WE2 may contact the lower semiconductor layer 124.

[0039] In an embodiment of the present inventive concept, the second well region WE2 may include a fourth dopant of the second conductivity type. For example, the second well region WE2 may be an impurity region formed by ion-implanting the fourth dopant into a second portion of the substrate 110, the second portion being adjacent to the second surface 110F2 of the substrate 110. For example, the fourth dopant may include boron.

[0040] like Figure 2 As shown, the first well region WE1 may be disposed on the upper side of the substrate 110, and the second well region WE2 may be disposed on the lower side of the substrate 110 to vertically overlap with the first well region WE1. The first well region WE1 and the second well region WE2 may form a pn junction. Since the first well region WE1 and the second well region WE2 are arranged adjacent to each other in the vertical direction Z in the substrate 110, a pn junction having a relatively large area may be obtained.

[0041] exist Figure 2 , a junction boundary JB between the first well region WE1 and the second well region WE2 is schematically illustrated as a dotted line. Figure 2 FIG. 2 shows that the junction boundary JB between the first well region WE1 and the second well region WE2 has a flat profile over the entire width of the first well region WE1 and the second well region WE2. However, due to the conditions of the ion implantation process for forming the first well region WE1 and the second well region WE2, or tolerances occurring in the ion implantation process, the junction boundary JB may have a flat profile over the entire width of the first well region WE1 and the second well region WE2. Figure 2The profiles shown have different profiles, for example having a curved profile or a wavy profile.

[0042] The nanosheet structure 130 may be disposed on the first surface 110F1 of the substrate 110. The nanosheet structure 130 may include at least two nanosheets overlapping each other along the vertical direction Z on the first surface 110F1 of the substrate 110. For example, Figure 2 It is shown that the nanosheet structure 130 includes a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3, but the number of nanosheets is not limited thereto and may vary.

[0043] In an embodiment of the inventive concept, the nanosheet structure 130 may include a group IV semiconductor such as Si or Ge, a group IV-IV compound semiconductor such as SiGe or SiC, or a group III-V compound semiconductor such as GaAs, InAs, InP. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may each have a relatively large width in the first horizontal direction X and the second horizontal direction Y, and a relatively small width in the vertical direction Z, and may each have a nanosheet shape, for example.

[0044] In an embodiment of the present inventive concept, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may each have a width of about 5 nm to about 100 nm in the second horizontal direction Y, and the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may each have a thickness of about 1 nm to about 10 nm in the vertical direction Z, but the present inventive concept is not limited thereto.

[0045] The capping insulating wire 132 may be arranged to surround the nanosheet structure 130. For example, the capping insulating wire 132 may be arranged between the first nanosheet N1 and the first surface 110F1 of the substrate 110, between the first nanosheet N1 and the second nanosheet N2, and between the second nanosheet N2 and the third nanosheet N3, and may be disposed on the upper surface of the third nanosheet N3. The capping insulating wire 132 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Carbonitride (SiC x N y ), silicon oxide carbonitride (SiO x C y N z ) or a combination thereof.

[0046] The nanosheet structure 130 and the capping insulating line 132 may be disposed adjacent to the sidewall of the upper semiconductor layer 122. For example, the upper semiconductor layer 122 may have an upper surface disposed at a height higher than an upper surface of the third nanosheet N3, and, for example, the sidewall of the upper semiconductor layer 122 may be at least partially surrounded by the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the capping insulating line 132.

[0047] A pair of spacers 134 may be disposed on the nanosheet structure 130. The pair of spacers 134 may be disposed on the sidewalls of the capping insulating line 132, and may extend along the second horizontal direction Y, wherein the capping insulating line 132 is disposed on the upper surface of the third nanosheet N3. The pair of spacers 134 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Carbonitride (SiC x N y ), silicon oxide carbonitride (SiO x C y N z ) or a combination thereof.

[0048] In an embodiment of the inventive concept, in a manufacturing process for forming a nanosheet structure included in an MBCFET element, the nanosheet structure 130 may be simultaneously formed, wherein the MBCFET element may be formed on another portion of the substrate 110. In addition, in a manufacturing process for forming a spacer disposed on both sides of a gate line included in the MBCFET element, a pair of spacers 134 may be simultaneously formed. In addition, in a manufacturing process for forming a source / drain region disposed on both sides of a gate line included in the MBCFET element, the upper semiconductor layer 122 may be simultaneously formed.

[0049] In an embodiment of the present invention, Figure 1 As shown, a plurality of pairs of spacers 134 may be arranged apart from each other at a reference interval CPP, or a plurality of capping insulating lines 132 may be arranged apart from each other at a reference interval CPP. In this regard, the reference interval CPP may be the same as a gate interval of a gate line included in an MBCFET element.

[0050] The etch stop film 136 may be disposed on a wall of each of the pair of spacers 134 to conformally cover the upper surface of the upper semiconductor layer 122. For example, the etch stop film 136 may be disposed on an outer wall of each of the pair of spacers 134. The first buried insulating layer 138 may be disposed on the etch stop film 136.

[0051] like Figure 1As shown, the first buried insulating layer 138 may have a layout of a line pattern that fills a space between two upper semiconductor layers 122 that are arranged adjacent to each other along the second horizontal direction Y and extends along the second horizontal direction Y. For example, the first buried insulating layer 138 may be arranged between two capping insulating lines 132 that extend along the second horizontal direction Y and are arranged adjacent to each other along the first horizontal direction X.

[0052] In an embodiment of the present inventive concept, the etch stop film 136 may include silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The first buried insulating layer 138 may include, for example, a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but the present inventive concept is not limited thereto.

[0053] The first contact portion 140 may be connected to the upper semiconductor layer 122 through the first buried insulating layer 138 and the etch stop film 136. For example, the first contact portion 140 may be disposed on an upper surface or a first surface of the upper semiconductor layer 122. The metal silicide film 142 may be disposed between the first contact portion 140 and the upper semiconductor layer 122. In an embodiment of the inventive concept, the metal silicide film 142 may be omitted, and the first contact portion 140 and the upper semiconductor layer 122 may directly contact each other.

[0054] In an embodiment of the present invention, the first contact 140 may include a conductive barrier pattern and a contact plug, and the conductive barrier pattern may at least partially surround the bottom surface and sidewall of the contact plug and may contact the bottom surface and sidewall of the contact plug. In an embodiment of the present invention, the conductive barrier pattern may include a metal or a metal nitride. For example, the conductive barrier pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but the present invention is not limited thereto. The contact plug may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the present invention is not limited thereto. The metal silicide film 142 may include tungsten silicide, nickel silicide, or cobalt silicide.

[0055] The front surface wiring structure 150 may be disposed on the first buried insulating layer 138. The front surface wiring structure 150 may include a front surface via 152, a front surface wiring layer 154, and a front surface interlayer insulating film 156. For example, the front surface wiring layer 154 may be disposed at multiple heights along the vertical direction Z, and the front surface via 152 may be connected between the front surface wiring layers 154 arranged at different vertical heights. The front surface via 152 may be disposed on the first contact portion 140, and the first contact portion 140 may be connected to the front surface wiring layer 154 via the front surface via 152. A portion of the front surface wiring layer 154 may have a pad shape to apply a power supply voltage or a ground voltage to the diode structure DS. Therefore, the power supply voltage or the ground voltage may be applied to the diode structure DS via the portion of the front surface wiring layer 154, and a current path may be formed in the diode structure DS along the vertical direction Z.

[0056] The molded insulating layer 160 may be disposed on the second surface 110F2 of the substrate 110. The molded insulating layer 160 may be disposed on the second surface 110F2 of the substrate 110, and may at least partially surround the sidewall of the lower semiconductor layer 124. For example, the molded insulating layer 160 may include an opening 160H, and the lower semiconductor layer 124 may be disposed in the opening 160H. The lower semiconductor layer 124 may protrude downward from the bottom surface of the molded insulating layer 160 (in this regard, the surface of the molded insulating layer 160 that contacts the second surface 110F2 of the substrate 110 is referred to as the upper surface of the molded insulating layer 160, and the surface opposite to the upper surface of the molded insulating layer 160 is referred to as the bottom surface of the molded insulating layer 160). The height of the lower semiconductor layer 124 in the vertical direction Z may be greater than the height of the molded insulating layer 160 in the vertical direction Z, and therefore, the bottom surface or first surface of the lower semiconductor layer 124 may protrude downward relative to the bottom surface of the molded insulating layer 160. For example, a bottom surface of the lower semiconductor layer 124 may be lower than a bottom surface of the mold insulation layer 160 .

[0057] In an embodiment of the inventive concept, the mold insulation layer 160 may include a TEOS film, a HDP oxide film, a BPSG film, a FCVD oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but the inventive concept is not limited thereto.

[0058] The second buried insulating layer 162 may be disposed on the bottom surface of the mold insulating layer 160. The second buried insulating layer 162 may be disposed on the bottom surface of the mold insulating layer 160 to cover the bottom surface or the first surface of the lower semiconductor layer 124. For example, the mold insulating layer 160 and the second buried insulating layer 162 may be sequentially disposed on the second surface 110F2 of the substrate 110, and may be disposed at a vertical height lower than the second surface 110F2 of the substrate 110.

[0059] In an embodiment of the inventive concept, the second buried insulating layer 162 may include a TEOS film, a HDP oxide film, a BPSG film, a FCVD oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but the inventive concept is not limited thereto.

[0060] The second contact 170 may be connected to the lower semiconductor layer 124 through the second buried insulating layer 162. The metal silicide film 172 may be disposed between the second contact 170 and the lower semiconductor layer 124. In an embodiment of the inventive concept, the metal silicide film 172 may be omitted, and the second contact 170 and the lower semiconductor layer 124 may directly contact each other.

[0061] In an embodiment of the present invention, the second contact 170 may include a conductive barrier pattern and a contact plug, and the conductive barrier pattern may at least partially surround the bottom surface and sidewall of the contact plug and may contact the bottom surface and sidewall of the contact plug. In an embodiment of the present invention, the conductive barrier pattern may include a metal or a metal nitride. For example, the conductive barrier pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but the present invention is not limited thereto. The contact plug may include, for example, molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the present invention is not limited thereto. The metal silicide film 172 may include, for example, tungsten silicide, nickel silicide, or cobalt silicide.

[0062] The rear surface wiring structure 180 may be disposed on the bottom surface of the second buried insulating layer 162. The rear surface wiring structure 180 may include a rear surface via 182, a rear surface wiring layer 184, and a rear surface interlayer insulating film 186. For example, the rear surface wiring layer 184 may be disposed at a plurality of heights in the vertical direction Z, and the rear surface via 182 may be connected between the rear surface wiring layers 184 arranged at different vertical heights. The rear surface via 182 may be disposed on the second contact portion 170, and the second contact portion 170 may be connected to the rear surface wiring layer 184 via the rear surface via 182. A portion of the rear surface wiring layer 184 may have a pad shape to apply a power supply voltage or a ground voltage to the diode structure DS. Therefore, the power supply voltage or the ground voltage may be applied to the diode structure DS via this portion of the rear surface wiring layer 184, and a current path may be formed in the diode structure DS along the vertical direction Z.

[0063] The ESD protection element usually included in the integrated circuit device includes a diode connected between the power supply / ground connection unit and the integrated circuit pin connection unit. The diode is designed to be turned on when static electricity is generated and quickly release static electricity to protect the integrated circuit device. However, as the thickness and / or volume of the silicon substrate decreases, when the diode is turned on, the resistance of the diode increases, making effective ESD protection difficult. In order to solve this problem, a "gate boundary diode" has been proposed, which forms a diode in the silicon region of the integrated circuit device (for example, in a semiconductor layer used as a source / drain region). However, in the gate boundary diode, the N+ region and P+ region arranged laterally and the substrate arranged below the N+ region and the P+ region form the current path of the diode, so in order to achieve effective ESD protection, a substrate with a relatively large thickness is required.

[0064] According to the above-described embodiments of the inventive concept, the upper semiconductor layer 122 disposed on the first surface 110F1 of the substrate 110 and the lower semiconductor layer 124 disposed on the second surface 110F2 of the substrate 110 can be used as an N+ region and a P+ region, respectively, and the first well region WE1 and the second well region WE2 can be formed in the substrate 110, thereby forming a vertical diode. Therefore, even when the substrate 110 is thin (or regardless of the thickness of the substrate 110), a pn junction with a relatively large area can be ensured, and effective ESD protection can be achieved.

[0065] Figure 4 is a cross-sectional view of an integrated circuit device 100A according to an embodiment of the inventive concept. Figure 4 In, with Figures 1 to 3 The same reference numerals as those in the drawings may denote similar elements, and thus redundant descriptions may be omitted.

[0066] Reference Figure 4 , the diode structure DSA may include an upper semiconductor layer 122A, a lower semiconductor layer 124A, a first well region WE1A, and a second well region WE2A.

[0067] The upper semiconductor layer 122A may include a first dopant of a first conductivity type, and, for example, the first conductivity type may be a p-type. The upper semiconductor layer 122A may be a region including a relatively high concentration of the first dopant, and, for example, may be referred to as a P+ region. The lower semiconductor layer 124A may include a second dopant of a second conductivity type, and the second conductivity type may be different from the first conductivity type. For example, the second conductivity type may be an n-type. The lower semiconductor layer 124A may be a region including a relatively high concentration of the second dopant, and, for example, may be referred to as an N+ region.

[0068] The first well region WE1A may be in contact with the upper semiconductor layer 122A and may include a third dopant of the first conductivity type. For example, the first well region WE1A may be an impurity region formed by ion-implanting the third dopant into a first portion of the substrate 110, the first portion being adjacent to the first surface 110F1 of the substrate 110. The second well region WE2A may be in contact with the lower semiconductor layer 124 and may include a fourth dopant of the second conductivity type. For example, the second well region WE2A may be an impurity region formed by ion-implanting the fourth dopant into a second portion of the substrate 110, the second portion being adjacent to the second surface 110F2 of the substrate 110.

[0069] Figure 5 is a cross-sectional view of an integrated circuit device 100B according to an embodiment of the inventive concept.

[0070] Reference Figure 5 , the diode structure DSB may include an upper semiconductor layer 122B, a lower semiconductor layer 124B, and a first well region WE1A.

[0071] The upper semiconductor layer 122B may be disposed on the first surface 110F1 of the substrate 110. The upper semiconductor layer 122B may include a first dopant of a first conductivity type, and, for example, the first conductivity type may be an n-type. The upper semiconductor layer 122B may be a region including a relatively high concentration of the first dopant, and, for example, may be referred to as an N+ region.

[0072] The lower semiconductor layer 124B may be disposed on the second surface 110F2 of the substrate 110. The lower semiconductor layer 124B may include a second dopant of a second conductivity type, and the second conductivity type may be different from the first conductivity type. For example, the second conductivity type may be a p-type. The lower semiconductor layer 124B may be a region including a relatively high concentration of the second dopant, and, for example, may be referred to as a P+ region.

[0073] The first well region WE1B may be disposed in the substrate 110 between the upper semiconductor layer 122B and the lower semiconductor layer 124B, and may contact both the upper semiconductor layer 122B and the lower semiconductor layer 124B. Figure 5 As shown, the first well region WE1B may be disposed over the entire thickness of the substrate 110 .

[0074] In an embodiment of the present inventive concept, the first well region WE1B may include a third dopant of the first conductivity type. For example, the first well region WE1B may be an impurity region formed by ion-implanting the third dopant into a first portion of the substrate 110 adjacent to the first surface 110F1 of the substrate 110 .

[0075] In an embodiment of the present inventive concept, the substrate 110 may be formed relatively thin, and, for example, a bodyless transistor element may be disposed on another portion of the substrate 110. In an embodiment of the present inventive concept, the substrate 110 may have a thickness of about 30 nm to about 300 nm, but the thickness of the substrate 110 is not limited thereto.

[0076] In the embodiments of the present invention, referring to Figure 5 Because the first well region WE1B has the first conductivity type (eg, n-type), a pn junction may be formed at a boundary between the first well region WE1B and the lower semiconductor layer 124B.

[0077] Figure 6 is a cross-sectional view of an integrated circuit device 100C according to an embodiment of the inventive concept.

[0078] Reference Figure 6 , the diode structure DSC may include an upper semiconductor layer 122C, a lower semiconductor layer 124C and a first well region WE1C.

[0079] The upper semiconductor layer 122C may be disposed on the first surface 110F1 of the substrate 110. The upper semiconductor layer 122C may include a first dopant of a first conductivity type, and, for example, the first conductivity type may be a p-type. The upper semiconductor layer 122C may be a region including a relatively high concentration of the first dopant, and, for example, may be referred to as a P+ region.

[0080] The lower semiconductor layer 124C may be disposed on the second surface 110F2 of the substrate 110. The lower semiconductor layer 124C may include a second dopant of a second conductivity type, and the second conductivity type may be different from the first conductivity type. For example, the second conductivity type may be an n-type. The lower semiconductor layer 124C may be a region including a relatively high concentration of the second dopant, and, for example, may be referred to as an N+ region.

[0081] The first well region WE1C may be disposed in the substrate 110 between the upper semiconductor layer 122C and the lower semiconductor layer 124C, and may contact both the upper semiconductor layer 122C and the lower semiconductor layer 124C. Figure 6 As shown, the first well region WE1C may be disposed over the entire thickness of the substrate 110 .

[0082] In an embodiment of the present inventive concept, the first well region WE1C may include a third dopant of a first conductivity type (e.g., p-type). For example, the first well region WE1C may be an impurity region formed by ion-implanting the third dopant into a first portion of the substrate 110, and the first portion may be adjacent to the first surface 110F1 of the substrate 110.

[0083] In an embodiment of the present inventive concept, the substrate 110 may be formed relatively thin, and, for example, a bodyless transistor element may be disposed on another portion of the substrate 110. In an embodiment of the present inventive concept, the substrate 110 may have a thickness of about 30 nm to about 300 nm, but the thickness of the substrate 110 is not limited thereto.

[0084] In the embodiments of the present invention, referring to Figure 6 Because the first well region WE1C has the first conductivity type (eg, p-type), a pn junction may be formed at a boundary between the first well region WE1C and the lower semiconductor layer 124C.

[0085] Figure 7 is a cross-sectional view of an integrated circuit device 100D according to an embodiment of the inventive concept.

[0086] Reference Figure 7 , the diode structure DSD may include an upper semiconductor layer 122D, a lower semiconductor layer 124D, and a first well region WE1D.

[0087] The upper semiconductor layer 122D may include a first dopant of a first conductivity type, and for example, the first conductivity type may be an n-type, and for example, may be referred to as an N+ region. The lower semiconductor layer 124D may include a second dopant of a second conductivity type, and the second conductivity type may be different from the first conductivity type. For example, the second conductivity type may be a p-type, and for example, may be referred to as a P+ region.

[0088] The first well region WE1D may be disposed in the substrate 110 between the upper semiconductor layer 122D and the lower semiconductor layer 124D, and may contact both the upper semiconductor layer 122D and the lower semiconductor layer 124D. The first well region WE1D may include a fourth dopant of the second conductivity type.

[0089] In the embodiments of the present invention, referring to Figure 7 Since the first well region WE1D has the second conductivity type (eg, p-type), a pn junction may be formed at a boundary between the first well region WE1D and the upper semiconductor layer 122D.

[0090] Figure 8 is a cross-sectional view of an integrated circuit device 100E according to an embodiment of the inventive concept.

[0091] Reference Figure 8 , the diode structure DSE may include an upper semiconductor layer 122E, a lower semiconductor layer 124E and a first well region WE1E.

[0092] The upper semiconductor layer 122E may include a first dopant of a first conductivity type, and for example, the first conductivity type may be a p-type, and for example, may be referred to as a P+ region. The lower semiconductor layer 124E may include a second dopant of a second conductivity type, and the second conductivity type may be different from the first conductivity type. For example, the second conductivity type may be an n-type, and for example, may be referred to as an N+ region.

[0093] The first well region WE1E may be disposed in the substrate 110 between the upper semiconductor layer 122E and the lower semiconductor layer 124E and may contact both the upper semiconductor layer 122E and the lower semiconductor layer 124E. The first well region WE1E may include a fourth dopant of the second conductivity type (eg, n-type).

[0094] In the embodiments of the present invention, referring to Figure 8 Because the first well region WE1E has the second conductivity type (eg, n-type), a pn junction may be formed at a boundary between the first well region WE1E and the upper semiconductor layer 122E.

[0095] Fig. 9 is a cross-sectional view of an integrated circuit device 100F according to an embodiment of the inventive concept.

[0096] Reference Fig. 9 , the diode structure DSF may include an upper semiconductor layer 122F, a lower semiconductor layer 124 , a first well region WE1 , and a second well region WE2 .

[0097] The upper semiconductor layer 122F may have a sidewall profile different from that of the lower semiconductor layer 124. For example, a first portion of the sidewall of the upper semiconductor layer 122F may be in contact with the nanosheet structure 130, and a second portion of the sidewall of the upper semiconductor layer 122F may be in contact with the capping insulation line 132. The second portion of the sidewall of the upper semiconductor layer 122F may protrude outward relative to the first portion of the sidewall of the upper semiconductor layer 122F. The second portion of the sidewall of the upper semiconductor layer 122F may be referred to as a protrusion 122P.

[0098] For example, a portion of the capping insulation line 132 contacting the protrusion 122P of the upper semiconductor layer 122F may be recessed inwardly along the shape of the protrusion 122P of the upper semiconductor layer 122F. For example, the protrusion 122P may be formed in the recess of the capping insulation line 132 .

[0099] Unlike the protrusion 122P formed on the sidewall of the upper semiconductor layer 122F, the lower semiconductor layer 124 may have a sidewall profile surrounded by the mold insulating layer 160 and extending substantially vertically.

[0100] In an embodiment of the present inventive concept, the upper semiconductor layer 122F may be simultaneously formed in a manufacturing process for forming a source / drain region included in an MBCFET element, wherein the MBCFET may be formed on another portion of the substrate 110. In the manufacturing process for forming the source / drain region, a lateral etching process may be additionally performed before forming the upper semiconductor layer 122F in the first recessed region RS1, and in this case, the upper semiconductor layer 122F may be formed to include a protrusion 122P protruding toward the capping insulating line 132.

[0101] In an embodiment of the present invention, in reference to Figures 3 to 8 In the described diode structures DSA, DSB, DSC, DSD, and DSE, the upper semiconductor layers 122A to 122E may be modified to include the protrusion 122P.

[0102] Fig.10 is a cross-sectional view of an integrated circuit device 100G according to an embodiment of the inventive concept.

[0103] Reference Fig.10 , the diode structure DSG may include an upper semiconductor layer 122G, a lower semiconductor layer 124G, a first well region WE1 and a second well region WE2.

[0104] The upper semiconductor layer 122G may have a first width w1 in the first horizontal direction X, and the lower semiconductor layer 124G may have a second width w2 in the first horizontal direction X. The second width w2 may be different from the first width w1. Fig.10 As shown, the second width w2 of the lower semiconductor layer 124G may be greater than the first width w1 of the upper semiconductor layer 122G. However, in an embodiment of the inventive concept, the second width w2 of the lower semiconductor layer 124G may be less than the first width w1 of the upper semiconductor layer 122G.

[0105] For example, the first width wl of the upper semiconductor layer 122G may be formed to be the same as the width of a source / drain region included in an MBCFET element that may be formed on another portion of the substrate 110. The second width w2 of the lower semiconductor layer 124G may be selected independently of the first width w1 of the upper semiconductor layer 122G.

[0106] Fig.11 is a cross-sectional view of an integrated circuit device 100H according to an embodiment of the inventive concept.

[0107] Reference Fig.11 , the diode structure DSH may include an upper semiconductor layer 122H, a lower semiconductor layer 124H, a first well region WE1 and a second well region WE2.

[0108] The upper semiconductor layer 122H may have a first height h1 in the vertical direction Z, and the lower semiconductor layer 124H may have a second height h2 in the vertical direction Z. The second height h2 may be different from the first height h1. Fig.11 As shown, the second height h2 of the lower semiconductor layer 124H may be less than the first height h1 of the upper semiconductor layer 122H. However, in an embodiment of the inventive concept, the second height h2 of the lower semiconductor layer 124H may be greater than the first height h1 of the upper semiconductor layer 122H.

[0109] For example, the first height h1 of the upper semiconductor layer 122H may be formed to be substantially the same as the height of source / drain regions included in an MBCFET element that may be formed on another portion of the substrate 110. The second height h2 of the lower semiconductor layer 124H may be selected independently of the first height h1 of the upper semiconductor layer 122H.

[0110] Fig.12 is a layout of an integrated circuit device 100I according to an embodiment of the inventive concept, and Fig.13 is along Fig.12 1 is a cross-sectional view of the integrated circuit device 100I taken along line A1 - A1 ′.

[0111] Fig.14 is along Fig.12 The line A2-A2' intercepts Fig.12 1 is a cross-sectional view of an integrated circuit device 100I.

[0112] Reference Figure 12 to Figure 14 , the nanosheet structure 130 may be at least partially surrounded by the dummy gate line 190 instead of the capping insulating line 132. The dummy gate line 190 may extend along the second horizontal direction Y to at least partially surround the nanosheet structure 130 (e.g., the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3), and a plurality of dummy gate lines 190 may be arranged spaced apart from each other along the first horizontal direction X at a reference interval CPP.

[0113] In an embodiment of the inventive concept, the dummy gate line 190 may include a main gate portion 190M and a sub-gate portion 190S. The main gate portion 190M may cover the upper surface of the third nanosheet N3 and extend along the second horizontal direction Y, and a pair of spacers 134 may be arranged at both sides of the main gate portion 190M. The sub-gate portion 190S may be arranged between the first surface 110F1 of the substrate 110 and the first nanosheet N1, between the first nanosheet N1 and the second nanosheet N2, and between the second nanosheet N2 and the third nanosheet N3.

[0114] In an embodiment of the present inventive concept, a fin-shaped active region extending in a first horizontal direction X and protruding in a vertical direction Z may be defined in the first surface 110F1 of the substrate 110, and an element isolation film may be disposed on both sides of the fin-shaped active region. In this case, the nanosheet structure 130 is disposed on the fin-shaped active region, and the dummy gate line 190 may at least partially surround the nanosheet structure 130 and extend in a second horizontal direction Y on the upper surface of the element isolation film and the upper surface of the fin-shaped active region.

[0115] In an embodiment of the present invention, the dummy gate line 190 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the dummy gate line 190 may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof, but the present invention is not limited thereto. In an embodiment of the present invention, the dummy gate line 190 may include a work function metal layer and a gap filling metal film. The work function metal layer may include, for example, at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd. The gap filling metal film may include a W film or an Al film. In an embodiment of the inventive concept, the dummy gate line 190 may include a stack structure of TiAlC / TiN / W, a stack structure of TiN / TaN / TiAlC / TiN / W, or a stack structure of TiN / TaN / TiN / TiAlC / TiN / W, but the inventive concept is not limited thereto.

[0116] The gate insulating layer 192 may be disposed between the dummy gate line 190 and the nanosheet structure 130. For example, the gate insulating layer 192 may be disposed between the main gate portion 190M of the dummy gate line 190 and the third nanosheet N3, between the sub-gate portion 190S and the nanosheet structure 130, and between the sub-gate portion 190S and the upper surface of the first surface 110F1 of the substrate 110.

[0117] In an embodiment of the present inventive concept, the gate insulating layer 192 may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxynitride film, or a combination thereof. The high-k dielectric film may include a metal oxide or a metal oxynitride. For example, the high-k dielectric film that may be used as the gate insulating layer 192 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 or a combination thereof, but the inventive concept is not limited thereto.

[0118] The gate capping layer 194 may be disposed on the dummy gate line 190. In an embodiment of the present inventive concept, the gate capping layer 194 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Carbonitride (SiC x N y ), silicon oxide carbonitride (SiO x C y N z ) or a combination thereof.

[0119] In an embodiment of the inventive concept, the dummy gate line 190 may be simultaneously formed in a manufacturing process for forming a gate line included in an MBCFET element, wherein the MBCFET element may be formed on another portion of the substrate 110. In addition, a separate contact portion may not be connected to the dummy gate line 190, and the dummy gate line 190 may be configured to float because no signal or voltage is applied to the dummy gate line 190.

[0120] In the embodiments of the present invention, referring to Figures 3 to 11 The described integrated circuit devices 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 100H may be modified to include a dummy gate line 190 instead of the capping insulation line 132 .

[0121] Fig.15 and Fig.16 is a cross-sectional view of an integrated circuit device 200 according to an embodiment of the inventive concept.

[0122] Reference Fig.15 and Fig.16 The fin-shaped active area FA may be arranged on the first surface 110F1 of the substrate 110. The fin-shaped active area FA may be arranged to protrude from the first surface 110F1 of the substrate 110 in the vertical direction Z and may extend in the first horizontal direction X.

[0123] A dummy gate line 190 extending along the second horizontal direction Y may be disposed on the fin-shaped active area FA. A gate insulating layer 192 may be disposed between the fin-shaped active area FA and the dummy gate line 190 and may extend along the second horizontal direction Y. The gate insulating layer 192 may be disposed between the sidewall of the fin-shaped active area FA and the dummy gate line 190 and between the upper surface of the fin-shaped active area FA and the dummy gate line 190. The gate insulating layer 192 may extend on the sidewall and the lower surface of the dummy gate line 190. A portion of the gate insulating layer 192 may be disposed between the dummy gate line 190 and a pair of spacers 134.

[0124] In an embodiment of the inventive concept, in a manufacturing process for forming a fin-shaped active region included in a fin-shaped FET element, the fin-shaped active region FA may be simultaneously formed, wherein the fin-shaped FET element may be formed on another portion of the substrate 110. In addition, a separate contact portion may not be connected to the dummy gate line 190, and the dummy gate line 190 may be configured to float because no signal or voltage is applied.

[0125] In the embodiments of the present invention, referring to Figures 3 to 14 The described integrated circuit devices 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, and 100I may be modified to include a fin-shaped active area FA instead of the nanosheet structure 130 .

[0126] Figures 17 to 32 is a cross-sectional view of a method of manufacturing an integrated circuit device 100 according to an embodiment of the inventive concept. Figures 17 to 32 is along Figure 1 The cross-sectional view corresponds to the cross-sectional view taken along the line A1-A1'.

[0127] Reference Fig.17 , a first well region WE1 may be formed in the substrate 110 adjacent to the first surface 110F1 by ion implanting a third dopant of the first conductivity type through the first surface 110F1 of the substrate 110. Then, a second well region WE2 may be formed in the substrate 110 and below the first well region WE1 by ion implanting a fourth dopant of the second conductivity type through the first surface 110F1 of the substrate 110.

[0128] In an embodiment of the present inventive concept, the first conductivity type may be an n-type and the second conductivity type may be a p-type. For example, the third dopant may include phosphorus or arsenic, and the fourth dopant may include boron. The first well region WE1 and the second well region WE2 may be arranged to vertically overlap each other in the substrate 110, and a junction boundary JB may be formed between the first well region WE1 and the second well region WE2.

[0129] In an embodiment of the inventive concept, the ion implantation process for forming the second well region WE2 may be performed before the ion implantation process for forming the first well region WE1 .

[0130] Reference Fig.18 , sacrificial layers 310P and channel semiconductor layers 130P may be alternately formed with each other on the first surface 110F1 of the substrate 110 to form a channel stack 310S.

[0131] In an embodiment of the present inventive concept, the sacrificial layer 310P and the channel semiconductor layer 130P may be formed by an epitaxial process. In an embodiment of the present inventive concept, the sacrificial layer 310P and the channel semiconductor layer 130P may include materials having an etching selectivity relative to each other. For example, each of the sacrificial layer 310P and the channel semiconductor layer 130P may include a single crystal layer of a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor, and the sacrificial layer 310P and the channel semiconductor layer 130P may include materials different from each other. In an embodiment of the present inventive concept, the sacrificial layer 310P may include SiGe, and the nanosheet structure 130 may include single crystal silicon.

[0132] In an embodiment of the present inventive concept, the epitaxial process may be vapor phase epitaxy (VPE), or a chemical vapor deposition (CVD) process such as ultra-high vacuum CVD, molecular beam epitaxy, or a combination thereof. In the epitaxial process, a liquid or gaseous precursor may be used as a precursor for forming the sacrificial layer 310P and the channel semiconductor layer 130P.

[0133] Reference Fig.19 After forming a hard mask pattern extending in the first direction (X direction) to have a predetermined length on the uppermost channel semiconductor layer 130P, the sacrificial layer 310P and the channel semiconductor layer 130P are patterned using the hard mask pattern as an etching mask to form a sacrificial layer pattern 310 and a nanosheet structure 130.

[0134] For example, the nanosheet structure 130 may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 spaced apart from each other along the vertical direction Z on the first surface 110F1 of the substrate 110. The sacrificial layer pattern 310 may be disposed between the first surface 110F1 of the substrate 110 and the first nanosheet N1, between the first nanosheet N1 and the second nanosheet N2, and between the second nanosheet N2 and the third nanosheet N3.

[0135] Then, a sacrificial gate structure 320 may be formed on the sacrificial layer pattern 310 and the nanosheet structure 130. The sacrificial gate structure 320 may include a sacrificial insulating layer pattern 322, a sacrificial gate line 324, and a sacrificial gate capping layer 326.

[0136] The sacrificial insulating layer pattern 322 may extend in the second horizontal direction Y, and may be conformally formed on the upper surface and sidewall of the sacrificial layer pattern 310 and the nanosheet structure 130, and the first surface 110F1 of the substrate 110. In an embodiment of the inventive concept, the sacrificial insulating layer pattern 322 may include a material having an etch selectivity with respect to the sacrificial gate line 324, and may include, for example, at least one film such as thermal oxide, silicon oxide, and silicon nitride.

[0137] The sacrificial gate line 324 may be formed to have a relatively large height to cover the sacrificial layer pattern 310 and the nanosheet structure 130 on the sacrificial insulating layer pattern 322. The upper surface of the sacrificial gate line 324 may have a flat horizontal plane. In an embodiment of the inventive concept, the sacrificial gate line 324 may include polysilicon, but the inventive concept is not limited thereto.

[0138] The sacrificial gate capping layer 326 may be disposed on an upper surface of the sacrificial gate line 324. In an embodiment of the inventive concept, the sacrificial gate capping layer 326 may include a silicon nitride film.

[0139] A pair of spacers 134 may be disposed on the sidewalls of the sacrificial insulating layer pattern 322, the sacrificial gate line 324, and the sacrificial gate capping layer 326. In an embodiment of the inventive concept, the pair of spacers 134 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Carbonitride (SiC x N y ), silicon oxide carbonitride (SiO x C y N z ) or a combination thereof.

[0140] Reference Fig. 20 , portions of the sacrificial layer pattern 310, portions of the nanosheet structure 130, and portions of the substrate 110 disposed on both sides of the sacrificial gate structure 320 may be etched to form first recessed regions RS1 on both sides of the sacrificial gate structure 320. When the first recessed regions RS1 are formed, the nanosheet structure 130 may be divided into a plurality of nanosheet structures 130 in the first horizontal direction X.

[0141] In an embodiment of the present invention, Fig. 20 As shown, the first recessed region RS1 includes sidewalls aligned with sidewalls of the sacrificial gate structure 320 (eg, sidewalls of a spacer in the pair of spacers 134 ), and extends continuously.

[0142] Reference Fig.21 , an upper semiconductor layer 122 may be formed in the first recess region RS1. For example, the upper semiconductor layer 122 may be formed by epitaxially growing a semiconductor material from surfaces of the nanosheet structure 130, the sacrificial layer pattern 310, and the substrate 110, which are exposed to the inner wall of the first recess region RS1.

[0143] In an embodiment of the present inventive concept, the upper semiconductor layer 122 may be formed by using at least one semiconductor material such as Si, SiGe, SiP, SiGeB, and / or SiGeC. In an embodiment of the present inventive concept, during an epitaxial process for forming the upper semiconductor layer 122, a first dopant of a first conductivity type may be co-doped. In addition, after the epitaxial process for forming the upper semiconductor layer 122, the first dopant may be ion-implanted. The upper semiconductor layer 122 may be a region including a relatively high concentration of the first dopant, and may be referred to as an N+ region, for example.

[0144] The first surface 122F1 of the upper semiconductor layer 122 may be disposed at a height higher than the upper surface of the nanosheet structure 130 , and may protrude above the upper surface of the nanosheet structure 130 .

[0145] Reference Fig. 22 An etch stop film 136 is formed to cover the first surface 122F1 of the upper semiconductor layer 122 , and a first buried insulating layer 138 may be formed on the etch stop film 136 to fill the space between the sacrificial gate structures 320 .

[0146] In an embodiment of the present invention, a planarization process is performed on the upper side of the first buried insulating layer 138 so that the upper surface of the sacrificial gate structure 320 is not covered by the first buried insulating layer 138, and the upper surface of the sacrificial gate structure 320 can be arranged at a vertical height substantially the same as the upper surface of the first buried insulating layer 138.

[0147] Reference Fig.23 , the sacrificial gate structure 320 may be removed.

[0148] In an embodiment of the present inventive concept, the sacrificial gate capping layer 326, the sacrificial gate line 324, and the sacrificial insulating layer pattern 322 may be sequentially removed. The space from which the sacrificial gate structure 320 is removed may be referred to as a gate space GS. In an embodiment of the present inventive concept, the gate space GS may be disposed between a pair of spacers 134, and the sidewalls of the sacrificial layer pattern 310 and the upper surface and sidewalls of the nanosheet structure 130 may be exposed in the gate space GS.

[0149] Then, the sacrificial layer pattern 310 remaining in the gate space GS may be removed. The process of removing the sacrificial layer pattern 310 may be a wet etching process using an etching selectivity between the sacrificial layer pattern 310 and the nanosheet structure 130 .

[0150] Reference Fig.24 , a capping insulating line 132 may be formed in the gate space GS. The capping insulating line 132 may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x), silicon oxynitride (SiO x N y ), Silicon Carbonitride (SiC x N y ) and / or silicon oxycarbonitride (SiO x C y N z ).

[0151] The capping insulating line 132 may fill the inside of the gate space GS disposed between the pair of spacers 134 , and may fill the spaces between the first to third nanosheets N1 , N2 , and N3 of the nanosheet structure 130 .

[0152] Reference Fig.25 A mask pattern may be formed on the first buried insulating layer 138, and by using the mask pattern as an etching mask, a portion of the first buried insulating layer 138 and a portion of the etching stopper film 136 may be removed to form a first contact hole 140H.

[0153] In an embodiment of the inventive concept, the first contact hole 140H may be formed to expose the first surface 122F1 of the upper semiconductor layer 122. For example, in an etching process for forming the first contact hole 140H, an upper portion of the upper semiconductor layer 122 may be removed.

[0154] Reference Fig.26 , a metal silicide film 142 may be formed in the first contact hole 140H, the metal silicide film 142 may be formed on the first surface 122F1 of the upper semiconductor layer 122, and the first surface 122F1 may be exposed through the first contact hole 140H. In an embodiment of the inventive concept, the metal silicide film 142 may include tungsten silicide, nickel silicide, and / or cobalt silicide.

[0155] Then, the first contact part 140 may be formed in the first contact hole 140H.

[0156] In an embodiment of the present invention, the first contact 140 may include a conductive barrier pattern and a contact plug, and the conductive barrier pattern may at least partially surround the bottom surface and sidewall of the contact plug and may contact the bottom surface and sidewall of the contact plug. In an embodiment of the present invention, the conductive barrier pattern may include a metal or a metal nitride. For example, the conductive barrier pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but the present invention is not limited thereto. The contact plug may include, for example, molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the present invention is not limited thereto.

[0157] Reference Fig. 27 , a front surface wiring structure 150 may be formed on the first buried insulating layer 138. The front surface wiring structure 150 may include a front surface via 152, a front surface wiring layer 154, and a front surface interlayer insulating film 156. The front surface wiring structure 150 may be arranged to be electrically connected to the first contact portion 140. In addition, a portion of the front surface wiring layer 154 may have a pad shape to apply a power supply voltage or a ground voltage to the upper semiconductor layer 122 via the first contact portion 140.

[0158] Reference Fig.28 , the thickness of the substrate 110 may be reduced by performing a grinding process on the second surface 110F2 of the substrate 110 .

[0159] In an embodiment of the present inventive concept, the substrate 110 may be ground to a predetermined thickness so that the first well region WE1 is disposed on an upper side of the substrate 110 and the second well region WE2 is disposed on a lower side of the substrate 110, and thus the first well region WE1 and the second well region WE2 are arranged to vertically overlap each other in the substrate 110. Therefore, the second well region WE2 may be exposed at the second surface 110F2 of the substrate 110.

[0160] For ease of description, Fig.28 It is shown that the second surface 110F2 of the substrate 110 faces downward, but the process for grinding the substrate 110 may be performed in a state where the second surface 110F2 of the substrate 110 is turned over to face upward.

[0161] Reference Fig.29 , a mold insulating layer 160 may be formed on the second surface 110F2 of the substrate 110. The mold insulating layer 160 may include a TEOS film, a HDP oxide film, a BPSG film, a FCVD oxide film, a SiON film, a SiN film, a SiOC film, or a SiCOH film.

[0162] Then, a portion of the mold insulation layer 160 may be removed to form an opening 160H. The opening 160H may expose a portion of the second surface 110F2 of the substrate 110 vertically overlapping the upper semiconductor layer 122. In the process of forming the opening 160H, a portion of the second surface 110F2 of the substrate 110 may be further removed to form a second recessed region RS2, and the portion is exposed inside the opening 160H.

[0163] Reference Fig.30 , a lower semiconductor layer 124 may be formed in the second recess region RS2. For example, the lower semiconductor layer 124 may be formed by epitaxially growing a semiconductor material from the second surface 110F2 of the substrate 110, and the second surface 110F2 is exposed to the inner wall of the second recess region RS2.

[0164] In an embodiment of the present inventive concept, the lower semiconductor layer 124 may be formed by using at least one semiconductor material such as Si, SiGe, SiP, SiGeB and / or SiGeC. In an embodiment of the present inventive concept, during the epitaxial process for forming the lower semiconductor layer 124, a second dopant of a second conductivity type may be co-doped. In addition, after the epitaxial process for forming the lower semiconductor layer 124, the second dopant may be ion-implanted. The lower semiconductor layer 124 may be a region including a relatively high concentration of the second dopant, and may be referred to as a P+ region, for example.

[0165] The first surface 124F1 of the lower semiconductor layer 124 may be arranged to protrude outside the mold insulating layer 160. For example, the first surface 124F1 of the lower semiconductor layer 124 may refer to a surface of the lower semiconductor layer 124, and the surface may be arranged to be away from the second surface 110F2 of the substrate 110. In addition, the first surface 124F1 of the lower semiconductor layer 124 may refer to a bottom surface of the lower semiconductor layer 124, such as Fig.30 shown.

[0166] The upper semiconductor layer 122, the first well region WE1, the second well region WE2, and the lower semiconductor layer 124 are collectively referred to as a diode structure DS. The diode structure DS may be a vertical diode extending from the first surface 110F1 of the substrate 110 to the second surface 110F2 of the substrate 110, and may have a current path formed therein along a vertical direction Z via the diode structure DS.

[0167] Reference Fig.31 , a second buried insulating layer 162 may be formed on the mold insulating layer 160 to cover the first surface 124F1 of the lower semiconductor layer 124 .

[0168] Then, a portion of the second buried insulating layer 162 may be removed to form a second contact hole 170H. The second contact hole 170H may expose the first surface 124F1 of the lower semiconductor layer 124.

[0169] Reference Fig.32 , a metal silicide film 172 may be formed in the second contact hole 170H, and the metal silicide film 172 may be formed on the first surface 124F1 of the lower semiconductor layer 124, and the first surface 124F1 may be exposed through the second contact hole 170H. In an embodiment of the inventive concept, the metal silicide film 172 may include tungsten silicide, nickel silicide, or cobalt silicide.

[0170] Then, the second contact portion 170 may be formed in the second contact hole 170H.

[0171] In an embodiment of the inventive concept, the second contact 170 may include a conductive barrier pattern and a contact plug, and the conductive barrier pattern may at least partially surround and may be in contact with a bottom surface and a sidewall of the contact plug.

[0172] Then, a rear surface wiring structure 180 may be formed on the second buried insulating layer 162 and the second contact portion 170. The rear surface wiring structure 180 may include a rear surface via 182, a rear surface wiring layer 184, and a rear surface interlayer insulating film 186. The rear surface wiring structure 180 may be arranged to be electrically connected to the second contact portion 170. In addition, a portion of the rear surface wiring layer 184 may have a pad shape to apply a power supply voltage or a ground voltage to the lower semiconductor layer 124 via the second contact portion 170.

[0173] The integrated circuit device 100 may be formed by performing the above-described processes.

[0174] Although the inventive concepts have been described with reference to example embodiments thereof, persons skilled in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concepts.

Claims

1. An integrated circuit device, comprising: a substrate comprising a first surface and a second surface opposite to the first surface; as well as Diode structure, including: an upper semiconductor layer disposed on the first surface of the substrate and comprising a first dopant of a first conductivity type; a lower semiconductor layer disposed on the second surface of the substrate and including a second dopant of a second conductivity type different from the first conductivity type; and A first well region is disposed in a portion of the substrate between the upper semiconductor layer and the lower semiconductor layer, wherein the first well region is in contact with the upper semiconductor layer or the lower semiconductor layer.

2. The integrated circuit device according to claim 1, wherein: The first well region contacts the upper semiconductor layer and includes a third dopant of the first conductivity type, and The diode structure further includes a second well region disposed in a portion of the substrate between the upper semiconductor layer and the lower semiconductor layer, wherein the second well region contacts the lower semiconductor layer and includes a fourth dopant of the second conductivity type.

3. The integrated circuit device according to claim 2, wherein: The first well region is arranged in a first portion of the substrate adjacent to the first surface of the substrate, The second well region is arranged in a second portion of the substrate adjacent to the second surface of the substrate, and The first well region and the second well region overlap each other in a vertical direction perpendicular to the first surface of the substrate.

4. The integrated circuit device according to claim 2, wherein: The upper semiconductor layer, the first well region, the second well region, and the lower semiconductor layer form a vertical diode.

5. The integrated circuit device according to claim 4, wherein: The upper semiconductor layer has a first width in a second horizontal direction parallel to the first surface of the substrate, and the first width of the upper semiconductor layer is greater than or equal to 0.5 nm.

6. The integrated circuit device according to claim 1, further comprising: A first contact portion, disposed on the upper semiconductor layer; a front surface wiring structure electrically connected to the first contact portion; A second contact portion, disposed on the lower semiconductor layer; as well as A rear surface wiring structure is electrically connected to the second contact portion.

7. The integrated circuit device according to claim 1, further comprising: a nanosheet structure disposed on the first surface of the substrate and arranged adjacent to a sidewall of the upper semiconductor layer; as well as a molded insulating layer disposed on the second surface of the substrate and at least partially surrounding a sidewall of the lower semiconductor layer, The nanosheet structure includes at least two nanosheets, and the at least two nanosheets are spaced apart from each other in a vertical direction perpendicular to the first surface of the substrate.

8. The integrated circuit device according to claim 7, further comprising: A capping insulating line at least partially surrounds the at least two nanosheets and contacts a portion of the sidewall of the upper semiconductor layer.

9. The integrated circuit device according to claim 7, wherein: The sidewall profile of the upper semiconductor layer is different from the sidewall profile of the lower semiconductor layer.

10. The integrated circuit device according to claim 8, wherein: The sidewall of the upper semiconductor layer includes a first portion in contact with the nanosheet structure and a second portion in contact with the capping insulating line, and The second portion of the sidewall of the upper semiconductor layer protrudes outward relative to the first portion of the sidewall of the upper semiconductor layer.

11. The integrated circuit device according to claim 7, further comprising: a gate electrode at least partially surrounding the at least two nanosheets and extending in a first horizontal direction parallel to the first surface of the substrate; as well as A gate insulating layer is arranged between the gate electrode and the at least two nanosheets.

12. The integrated circuit device according to claim 1, wherein: The upper semiconductor layer has a first width in a second horizontal direction parallel to the first surface of the substrate, and The lower semiconductor layer has a second width in the second horizontal direction that is the same as the first width.

13. The integrated circuit device according to claim 1, wherein: The upper semiconductor layer has a first height in a vertical direction perpendicular to the first surface of the substrate, and The lower semiconductor layer has a second height in the vertical direction that is different from the first height.

14. The integrated circuit device according to claim 1, wherein: The first well region includes an upper surface and a bottom surface, The upper surface of the first well region is in contact with the upper semiconductor layer, The bottom surface of the first well region contacts the lower semiconductor layer, and The first well region includes a fourth dopant of the second conductivity type.

15. An integrated circuit device comprising: A diode structure, wherein the diode structure comprises: an upper semiconductor layer disposed on the first surface of the substrate and including a first dopant of a first conductivity type; a lower semiconductor layer disposed on a second surface of the substrate opposite to the first surface of the substrate and including a second dopant of a second conductivity type different from the first conductivity type; a first well region disposed in a first portion of the substrate and comprising a third dopant of the first conductivity type, wherein the first portion is adjacent to the first surface of the substrate; and A second well region is arranged in a second portion of the substrate and includes a fourth dopant of the second conductivity type, wherein the second portion is adjacent to the second surface of the substrate.

16. The integrated circuit device according to claim 15, wherein: The first well region and the second well region overlap each other, and The upper semiconductor layer and the lower semiconductor layer overlap each other.

17. The integrated circuit device of claim 15, further comprising: A first contact portion, disposed on the upper semiconductor layer; a front surface wiring structure electrically connected to the first contact portion; A second contact portion, disposed on the lower semiconductor layer; as well as A rear surface wiring structure is electrically connected to the second contact portion.

18. The integrated circuit device of claim 15, further comprising: a nanosheet structure disposed on the first surface of the substrate and arranged adjacent to a sidewall of the upper semiconductor layer, wherein the nanosheet structure includes at least two nanosheets spaced apart from each other in a vertical direction; a molded insulating layer disposed on the second surface of the substrate and at least partially surrounding a sidewall of the lower semiconductor layer; and A capping insulating line at least partially surrounds the at least two nanosheets and contacts a portion of the sidewall of the upper semiconductor layer.

19. The integrated circuit device according to claim 15, wherein: The first well region and the second well region form a pn junction.

20. An integrated circuit device comprising: A diode structure, wherein the diode structure comprises: an upper semiconductor layer disposed on the first surface of the substrate and including a first dopant of a first conductivity type; a lower semiconductor layer disposed on a second surface of the substrate opposite to the first surface of the substrate and including a second dopant of a second conductivity type different from the first conductivity type; a first well region disposed in a first portion of the substrate and comprising a third dopant of the first conductivity type, wherein the first portion of the substrate is adjacent to the first surface of the substrate; and a second well region disposed in a second portion of the substrate and comprising a fourth dopant of the second conductivity type, wherein the second portion of the substrate is adjacent to the second surface of the substrate; a nanosheet structure disposed on the first surface of the substrate and arranged adjacent to a sidewall of the upper semiconductor layer; A first contact portion, disposed on a first surface of the upper semiconductor layer; a front surface wiring structure electrically connected to the first contact portion; a molded insulating layer disposed on the second surface of the substrate and the lower semiconductor layer; A second contact portion disposed on the first surface of the lower semiconductor layer; and A rear surface wiring structure is electrically connected to the second contact portion.

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