Decoder, decoding method, memory controller, memory system

Abstract

A decoder, based on a message updating manner of adopting inter-block serial decoding for a plurality of circulant permutation matrices in a layer of a check matrix corresponding to a frame code word, comprises a posterior probability storage module (701) configured to store a posterior probability message corresponding to each circulant permutation matrix respectively, a node message storage module (702) configured to store a message transmitted by a check node to a variable node corresponding to each circulant permutation matrix respectively, and a message updating module (703) configured to receive the posterior probability message corresponding to each circulant permutation matrix respectively and the message transmitted by the check node to the variable node in a first order respectively, and output an updated message transmitted by the check node to the variable node corresponding to each circulant permutation matrix respectively and an updated posterior probability message in a second order respectively; the first order is the same as or different from the second order.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a decoder, a decoding method, a memory controller, a memory system, and an electronic device. Background Technology

[0002] With the rapid development of data storage technology, more and more data storage systems are appearing in electronic devices, such as solid-state drives (SSDs). SSDs, due to their fast read / write speeds, shock resistance, low power consumption, noiselessness, low heat generation, and light weight, have been widely used in military, automotive, industrial, medical, and aerospace fields. However, many problems still need to be solved in these storage systems. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a decoder is provided, which updates messages based on inter-block serial decoding of multiple cyclic permutation matrices in a layer of a parity-check matrix corresponding to a frame of codewords. The decoder includes:

[0004] The posterior probability storage module is configured to store posterior probability messages corresponding to each of the cyclic permutation matrices.

[0005] The node message storage module is configured to: store messages passed from the verification node to the variable node corresponding to each of the cyclic permutation matrices; and

[0006] The message update module is configured to: receive the posterior probability message corresponding to each of the cyclic permutation matrices and the message passed from the verification node to the variable node in a first order, and output the updated message passed from the verification node to the variable node and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order; the first order and the second order may be the same or different.

[0007] In some implementations, the message update module includes: a first storage unit and a second storage unit;

[0008] The first storage unit is configured to: store the symbol values ​​of messages passed from the variable nodes corresponding to the multiple cyclic permutation matrices to the verification nodes; the first storage unit is provided with a first read address and a first write address, the first write address causes the first storage unit to sequentially input the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification nodes in the first order, and the first read address causes the first storage unit to sequentially output the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification nodes in the second order;

[0009] The second storage unit is configured to: store the latest messages from the check nodes to the variable nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module; the second storage unit is provided with a second read address and a second write address, wherein the second write address enables the second storage unit to sequentially input the latest messages from the check nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module in the first order, and the second read address enables the second storage unit to sequentially output the latest messages from the check nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module in the second order.

[0010] In some embodiments, the first storage unit and the second storage unit each include random access memory.

[0011] In some implementations, the depth of the first storage cell is the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is the product of the size of a cyclic permutation matrix and the message width passed from the check node to the variable node.

[0012] The depth of the second storage cell is the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is the size of a cyclic permutation matrix.

[0013] In some implementations, the message update module further includes: a first calculation unit and a message update unit that verifies the message from the node to the variable node;

[0014] The first calculation unit is configured to: calculate the minimum value, the second minimum value, and the sign XOR value corresponding to the first layer of the parity check matrix;

[0015] The message update unit that the verification node passes to the variable node is configured to: sequentially receive the sign values ​​of the messages passed to the verification node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit in a second order, and receive the minimum value, second minimum value, and sign XOR value of the first layer of the verification matrix calculated by the first calculation unit, and sequentially output the updated messages passed to the variable node by the verification node corresponding to each of the cyclic permutation matrices in a second order.

[0016] In some implementations, the message update module further includes: an inverse permutation unit;

[0017] The inverse permutation unit is configured such that the sequence of messages updated by the message update unit that transmits the verification node to the variable node, corresponding to each of the cyclic permutation matrices, is permuted from the order of the verification nodes to the order of the corresponding variable nodes.

[0018] In some implementations, the message update module further includes: a second computing unit;

[0019] The second calculation unit is configured to: based on the messages corresponding to each of the cyclic permutation matrices obtained by the inverse permutation unit, the messages corresponding to each of the cyclic permutation matrices stored in the second storage unit, and the messages corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module, output the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order.

[0020] In some implementations, the posterior probability storage module includes two real dual-port random access memories.

[0021] In some implementations, the message update module further includes: a third computing unit;

[0022] The third computing unit is configured to: receive the latest posterior probability messages corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module in a first order, and receive the latest messages from the verification nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module in a first order, and output the messages from the variable nodes corresponding to each of the cyclic permutation matrices to the verification nodes in a first order.

[0023] In some implementations, the message update module further includes: a replacement unit;

[0024] The permutation unit is configured to: change the sequence of messages from the variable nodes corresponding to each cyclic permutation matrix output by the third calculation unit to the verification nodes from the order of the variable nodes to the order of the corresponding verification nodes.

[0025] According to a second aspect of the present disclosure, a memory controller is provided, including a decoder as described in any of the embodiments above.

[0026] According to a third aspect of the present disclosure, a memory system is provided, including a memory controller as described in the above embodiments and a memory device coupled to the memory controller.

[0027] According to a fourth aspect of the present disclosure, an electronic device is provided, including a decoder as described in any of the above embodiments, and a memory device coupled to the decoder.

[0028] According to a fifth aspect of the present disclosure, a decoding method is provided. During message updates using inter-block serial decoding of multiple cyclic permutation matrices in a layer of a parity-check matrix corresponding to a frame of codewords, the method includes:

[0029] The posterior probability storage module stores the posterior probability messages corresponding to each of the cyclic permutation matrices.

[0030] The node message storage module stores the messages passed from the verification node to the variable node for each of the cyclic permutation matrices.

[0031] The message update module receives the posterior probability message corresponding to each of the cyclic permutation matrices and the message passed from the verification node to the variable node in a first order, and outputs the updated message passed from the verification node to the variable node and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order; the first order and the second order may be the same or different.

[0032] In some implementations, the step of sequentially outputting the updated verification node's message and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order includes:

[0033] The first storage unit stores the symbol values ​​of messages passed from the variable nodes corresponding to the multiple cyclic permutation matrices to the verification node; the first storage unit is provided with a first read address and a first write address. The first write address enables the first storage unit to sequentially input the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification node in the first order, and the first read address enables the first storage unit to sequentially output the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification node in the second order.

[0034] The second storage unit stores the latest messages from the check nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module, which are then passed to the variable nodes. The second storage unit is provided with a second read address and a second write address. The second write address enables the second storage unit to sequentially input the latest messages from the check nodes corresponding to each cyclic permutation matrix stored in the negative node message storage module, which are then passed to the variable nodes, in the first order. The second read address enables the second storage unit to sequentially output the latest messages from the check nodes corresponding to each cyclic permutation matrix stored in the negative node message storage module, which are then passed to the variable nodes, in the second order.

[0035] In some implementations, the step of sequentially outputting the updated verification nodes corresponding to each of the cyclic permutation matrices to the variable nodes in a second order includes:

[0036] The first calculation unit is used to calculate the minimum, second minimum, and sign XOR values ​​of the first layer of the parity check matrix;

[0037] The message update unit, which uses the verification node to pass the message to the variable node, receives the sign value of the message passed to the verification node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit in a second order, and receives the minimum value, second minimum value, and sign XOR value of the first layer of the verification matrix calculated by the first calculation unit. Then, it outputs the updated message passed to the variable node by the verification node corresponding to each of the cyclic permutation matrices in a second order.

[0038] In some implementations, the step of sequentially outputting the updated verification node's message and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order includes:

[0039] The message update unit, which uses the inverse permutation unit to pass the verification node to the variable node, outputs the updated sequence of messages passed from the verification node to the variable node in the second order, corresponding to each of the cyclic permutation matrices. The sequence is changed from being arranged according to the order of the verification nodes to being arranged according to the order of the corresponding variable nodes.

[0040] In some implementations, the step of sequentially outputting the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order includes:

[0041] The message corresponding to each cyclic permutation matrix obtained by the second calculation unit based on the inverse permutation unit, the message corresponding to each cyclic permutation matrix stored in the second storage unit, and the message corresponding to each cyclic permutation matrix stored in the posterior probability storage module are sequentially output in a second order, and the updated posterior probability message corresponding to each cyclic permutation matrix is ​​output in order.

[0042] In some implementations, the step of sequentially outputting the updated verification node's message and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order includes:

[0043] The third computing unit sequentially receives the latest posterior probability messages corresponding to each cyclic permutation matrix stored in the posterior probability storage module in the first order, and sequentially receives the latest messages from the verification node to the variable node stored in the negative node message storage module corresponding to each cyclic permutation matrix in the first order, and sequentially outputs the messages from the variable node to the verification node corresponding to each cyclic permutation matrix in the first order.

[0044] In some implementations, the step of sequentially outputting the updated verification node's message and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order includes:

[0045] The permutation unit transforms the sequence of messages from the variable nodes corresponding to each cyclic permutation matrix output by the third calculation unit to the verification nodes from the order of the variable nodes to the order of the corresponding verification nodes.

[0046] In some embodiments, the method further includes: receiving updated posterior probability messages corresponding to each of the cyclic permutation matrices, and substituting the received updated posterior probability messages corresponding to each of the cyclic permutation matrices into the verification equations for verification; if all verification equations are satisfied, the decoding is determined to be successful; if all verification equations are not satisfied, the decoding is determined to be unsuccessful, and the next iteration is required to update the posterior probability messages and the messages passed from the verification node to the variable node, until the decoding is successful or the maximum number of iterations is reached. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0048] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0049] Figure 2bThis is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0050] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0051] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0052] Figure 4 This is a schematic cross-sectional view of a memory array including memory strings according to an embodiment of the present disclosure;

[0053] Figure 5 This is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of the present disclosure;

[0054] Figure 6 This is a schematic diagram of the framework structure of a decoder according to an embodiment of the present disclosure;

[0055] Figure 7 This is a schematic diagram of the structure of a decoder according to an embodiment of the present disclosure;

[0056] Figure 8 This is a schematic diagram of the structure of a posterior probability storage module according to an embodiment of the present disclosure;

[0057] Figure 9 This is a schematic diagram of a memory system according to an embodiment of the present disclosure;

[0058] Figure 10 This is a schematic diagram illustrating the implementation flow of a decoding method according to an embodiment of the present disclosure;

[0059] Figure 11 This is a schematic diagram of the framework flow of a decoding method according to an embodiment of the present disclosure. Detailed Implementation

[0060] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0061] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0062] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0063] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0064] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0066] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0067] Figure 1 A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit) of an electronic device or a system-on-a-chip (e.g., an application processor). The host 108 may be configured to send data to or receive data from the memory device 104.

[0068] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as secure digital cards, compact flash memory cards, universal serial bus flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0069] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable function, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with an external device via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect High Speed ​​(PCHIHS), Advanced Technology Attached Protocol (ATIP), Serial Advanced Technology Attached Protocol (STP), Parallel Advanced Technology Attached Protocol (PATP), Minicomputer Small Interface Protocol (MSIP), Enhanced Small Disk Interface (MSDI), Integrated Drive Electronic Devices Protocol (IDEMP), firmware protocols, etc.

[0070] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a compact flash memory card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0071] Figure 3a An exemplary schematic diagram of a three-dimensional NAND flash memory array is provided, such as... Figure 3aAs shown, the memory array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Every four rows of memory cells are separated by a gate isolation structure and an up-select gate isolation structure. Each row of memory cells includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The storage block shown contains 6 memory chips. In practical applications, the number of memory chips in a storage block is not limited to this. A memory cell in a memory chip coupled to a word line can be called a memory page (English expression: Page), where a memory page is a physical page.

[0072] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0073] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, where memory cells 306 are NAND memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0074] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0075] like Figure 3b As shown, each memory string 308 may include a bottom-selected transistor (BST) 310 at its source end and a top-selected transistor (TST) 312 at its drain end. BST 310 and TST 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TST312) or a deselection voltage (e.g., 0V) to the corresponding TST312 via one or more TSL (Top selected line) 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BST310) or a deselection voltage (e.g., 0V) to the corresponding BST310 via one or more BSL (Bottom Selected line) 315.

[0076] like Figure 3bAs shown, memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line 314 of the selected memory block and unselected memory blocks on the same plane as the selected memory block can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a memory page 320 of memory cell 306. The size of a memory page 320, in bits, can be related to the number of memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A memory page 320 contains multiple memory cells 306, which are separated by an upselect gate isolation structure and a gate isolation structure. The multiple memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the upselect gate isolation structure. The memory cells in the memory chip sharing the same word line form a programmable (read / write) page.

[0077] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including a memory string 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array 301 is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0078] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0079] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0080] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0081] Return to reference Figure 3bPeripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, BSL 315, and TSL 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSL 315, and TSL 313, and sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic circuitry 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0082] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic circuitry 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic circuitry 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0083] The row decoder / word line driver 508 can be configured to be controlled by control logic circuitry 512 and to select / deselect memory blocks 304 of memory array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSL 315 and TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic circuitry 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0084] Control logic circuitry 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic circuitry 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic circuitry 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic circuitry 512, as well as to buffer status information received from control logic circuitry 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0085] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0086] 3D NAND flash memory, a more stable and faster storage device than traditional hard disk drives, has permeated every corner of daily life. To meet ever-increasing storage demands, the manufacturing process of 3D NAND flash memory is continuously shrinking, increasing the number of bits per flash cell. The cell types are evolving from SLC to MLC, TLC, and QLC. However, this has led to a continuous increase in the error probability of flash memory, making BCH (Bose-Chaudhuri Hocquenghem) error correction codes insufficient to guarantee data security. Low-Density Parity Check (LDPC), an error correction method approaching the Shannon limit, is gradually replacing BCH as the error correction coding method in next-generation flash memory controllers.

[0087] In some embodiments of this disclosure, the decoder includes a posterior probability storage module, a node message storage module, and a message update module. During message updates of multiple cyclic permutation matrices (CPMs) in one layer of the parity-check matrix corresponding to a frame of codewords using inter-block serial decoding, the message update module uses a FIFO to temporarily store the relevant values ​​of the messages passed from variable nodes to the parity nodes, and also uses a FIFO to temporarily store the intermediate calculated values ​​of the messages passed from variable nodes to the parity nodes corresponding to one layer of the parity-check matrix. Since the FIFO is a first-in-first-out memory, the data that enters the FIFO first will be output first, and the input order of the data is consistent with the output order. Although this eliminates the waiting period for the update results corresponding to each layer of the parity-check matrix, it still needs to be output sequentially according to the input order of the messages passed from variable nodes to the parity nodes in the message update module, resulting in low degrees of freedom and hindering subsequent optimization. Furthermore, the flag signal added to the decoder indicates the age of the posterior probability message used by the variable nodes to pass messages to the parity nodes, increasing control complexity. How to improve throughput, degrees of freedom, and simplify system implementation has become an urgent problem to be solved at this stage.

[0088] To address one or more of the aforementioned problems, embodiments of this disclosure provide a decoder, such as... Figure 6 As shown, the decoder, based on inter-block serial decoding of multiple cyclic permutation matrices in one layer of the parity-check matrix corresponding to a frame of codewords, performs message updates. The decoder includes:

[0089] The posterior probability storage module 701 is configured to store posterior probability messages corresponding to each of the cyclic permutation matrices.

[0090] The node message storage module 702 is configured to: store messages passed from the verification node to the variable node corresponding to each of the cyclic permutation matrices; and

[0091] The message update module 703 is configured to: receive the posterior probability message corresponding to each of the cyclic permutation matrices and the message passed from the verification node to the variable node in a first order, and output the updated message passed from the verification node to the variable node and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order; the first order and the second order may be the same or different.

[0092] Here, the posterior probability storage module 701 is connected to the message update module 703, and the message update module 703 is connected to the node message storage module 702.

[0093] The decoder provided in this disclosure includes a quasi-cyclic low-density parity-check code layered decoder.

[0094]

[0095] Table 1

[0096] Table 1 above provides an example of a parity check matrix. The parity check matrix in Table 1 has mb = 3 layers, nb = 4 columns, a cyclic permutation matrix size cmp_size = 5, and a total weight of 8 for the base matrices. The eight non-zero sub-matrices are numbered 1-8 sequentially from top to bottom and left to right. Here, non-zero sub-matrices 1-3 and the first all-zero sub-matrix from top to bottom constitute the first layer; non-zero sub-matrices 4-6 and the second all-zero sub-matrix from top to bottom constitute the second layer; and non-zero sub-matrices 7-8, the third and fourth all-zero sub-matrices from top to bottom constitute the third layer. Non-zero sub-matrices 1 and 4, along with the first all-zero sub-matrix from left to right, constitute the first column; non-zero sub-matrices 2, 5, and 7 constitute the second column; and so on for the other columns. Here, v0-v19 represent the variable node messages corresponding to each column, and c0-c14 represent the parity check node messages corresponding to each row.

[0097] Figure 7 This is a schematic diagram of the architecture of a decoder provided in an embodiment of the present disclosure; Figure 8 This is a schematic diagram of a posterior probability storage module 701 provided in an embodiment of this disclosure. The following will be combined with... Figure 6 , Figure 7 , Figure 8 Table 1 provides further information on the decoder.

[0098] In some embodiments, the posterior probability storage module 701 includes two real dual-port random access memories (RAM).

[0099] Figure 7RD1 and RD2 shown are two read ports of the posterior probability storage module 701, and WR1 and WR2 are two write ports of the posterior probability storage module 701.

[0100] During the first iteration, the posterior probability message stored in the posterior probability storage module is the log-likelihood ratio (LLR) message.

[0101] In this embodiment, the depth of each real dual-port RAM in the posterior probability storage module 701 is nb, and the width is the width of one posterior probability message * cmp_size. For example, if the posterior probability message width of a node is quantized to 8 bits, then the width is 8 * 5 = 40 bits. The depth of the posterior probability storage module 701 is 4. Address 0 stores the posterior probability messages LLR(y0, y1, y2, y3, y4) for v0 to v4, totaling 40 bits; address 1 stores the posterior probability messages LLR(y5, y6, y7, y8, y9) for nodes v5 to v9; address 2 stores v... 10 ~v 14 The node posterior probability message LLR(y) 10 y 11 y 12 y 13 y 14 Address 3 stores v 15 ~v 19 The node posterior probability message LLR(y) 15 y 16 y 17 y 18 y 19 ).

[0102] At the very beginning of decoding, the ping_pong signal is set to 0, and LLR... in The initial channel messages are input into `llr_ram_0`. When `nb` initial channel messages have been buffered, the `ping_pong` signal is inverted. During decoding, the updated posterior probability message, i.e., `LLR`, is used. updated Store the initial channel message of the second frame codeword in llr_ram_0, and store it in llr_ram_1.

[0103] It is understood that the posterior probability storage module 701 in this embodiment includes two real dual-port RAMs, one for decoding the current codeword and the other for storing the initial channel message of the next frame codeword. Reading and writing can be performed independently. The next layer of the parity check matrix can directly read the current posterior probability message during the decoding process. The posterior probability message no longer needs to be judged as old or new, thus eliminating the calculation of the old and new flag signals and simplifying the decoding architecture.

[0104] In some specific examples, the node message storage module 702 includes a simple dual-port RAM with a depth equal to the total weight of the base matrix and a width equal to the width of a check node's message (C2V message) passed to the variable node * cmp_size. For example, if the width of a check node's C2V message is quantized to 6 bits, then the depth of the node message storage module 702 is 8. Address 0 can access the C2V messages of non-zero submatrix 1, with a width of 6 * 5 = 30 bits, including the five check node messages: c4 to v0, c0 to v1, c1 to v2, c2 to v3, and c3 to v4. Address 1 can access the C2V messages of non-zero submatrix 2, with a width of 30 bits, including the check node messages: c3 to v5, c4 to v6, c0 to v7, c1 to v8, and c2 to v9. Addresses 2 to 7 store the C2V messages of non-zero submatrixes 3 to 8, respectively. Messages output from the node message storage module 702 to the message update module 703 are as follows... Figure 7 The image shown is

[0105] In some specific examples, the message update module 703 includes a fourth calculation unit 707, configured to invert the message passed from the check node to the variable node in the node message storage module 702, obtaining the negative of the latest message passed from the check node to the variable node corresponding to each cyclic permutation matrix. The input and output data from the fourth calculation unit 707 are in the same order, both being first order. In some specific examples, the fourth calculation unit 707 may be a multiplier.

[0106] Taking the first layer of the verification matrix in Table 1 as an example, when the order of the cyclic permutation matrix corresponding to the input data in the fourth calculation unit 707 is: non-zero submatrix 2 → non-zero submatrix 1 → non-zero submatrix 3, then the order of the cyclic permutation matrix corresponding to the output data from the fourth calculation unit 707 is: non-zero submatrix 2 → non-zero submatrix 1 → non-zero submatrix 3.

[0107] In some embodiments, the message update module 703 further includes: a third computing unit 706;

[0108] The third calculation unit 706 is configured to: receive the latest posterior probability messages stored in the posterior probability storage module 701 corresponding to each of the cyclic permutation matrices in a first order; receive the latest messages from the verification node to the variable node stored in the negative node message storage module 702 corresponding to each of the cyclic permutation matrices in a first order; and output the messages from the variable node to the verification node corresponding to each of the cyclic permutation matrices in a first order.

[0109] Here, the message calculated from the third computing unit 706 is as follows: Figure 7 The image shown is It is a message passed from the variable nodes corresponding to multiple cyclic permutation matrices in one layer of the verification matrix to the verification node.

[0110] In some embodiments, the message update module 703 includes a permutation unit 711; the permutation unit 711 is configured to: permutate the sequence of messages passed from the variable node corresponding to each cyclic permutation matrix output by the third calculation unit 706 to the verification node from the order of the variable nodes to the order of the corresponding verification nodes.

[0111] In some specific examples, the permutation unit 711 includes a barrel shifter that can cyclically shift the input message vector, facilitating the first calculation unit 705 to calculate the minimum and second smallest non-zero elements in a row. For example, the message (V2C message) passed from the variable node corresponding to non-zero submatrix 1 to the check node is LLR(v02c4, v12c0, v22c1, v32c2, v42c3), the V2C message corresponding to non-zero submatrix 2 is LLR(v52c3, v62c4, v72c0, v82c1, v92c2), and the V2C message corresponding to non-zero submatrix 3 is LLR(v... 15 2c0, v 16 2c1, v 17 2c2, v 18 2c3, v 19 2c4). The shift factor of the non-zero submatrix may not be 0, so the V2C messages need to be cyclically shifted to align the V2C message vectors corresponding to the non-zero elements of the check matrix.

[0112] That is, the V2C message corresponding to non-zero submatrix 1 is LLR(v02c4, v12c0, v22c1, v32c2, v42c3), which needs to be circularly shifted left by 1 to become LLR(v12c0, v22c1, v32c2, v42c3, v02c4) for output; the V2C message corresponding to non-zero submatrix 2 is LLR(v52c3, v62c4, v72c0, v 8v sdv The submatrix 2c1, v92c2) needs to be circularly shifted left by 2 to become LLR(v72c0, v82c1, v92c2, v52c3, v62c4) output; the V2C message corresponding to the non-zero submatrix 3 is LLR(v 15 2c0, v 16 2c1, v 17 2c2, v 18 2c3, v 19 2c4) Circular left shift to 0 becomes LLR(v 15 2c0, v 16 2c1, v17 2c2, v 18 2c3, v 19 2c4) Output.

[0113] In some embodiments, the message update module 703 includes: a first storage unit 708 and a second storage unit 709;

[0114] The first storage unit 708 is configured to: store the symbol values ​​of messages passed from the variable nodes corresponding to the multiple cyclic permutation matrices to the verification nodes; the first storage unit 708 is provided with a first read address and a first write address, the first write address causes the first storage unit 708 to sequentially input the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification nodes in the first order, and the first read address causes the first storage unit 708 to sequentially output the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification nodes in the second order;

[0115] The second storage unit 709 is configured to: store the latest messages from the check nodes to the variable nodes corresponding to the plurality of cyclic permutation matrices stored in the negative node message storage module 702; the second storage unit 709 is provided with a second read address and a second write address, wherein the second write address enables the second storage unit 709 to sequentially input the latest messages from the check nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module 702 in the first order, and the second read address enables the second storage unit 709 to sequentially output the latest messages from the check nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module 702 in the second order.

[0116] In some embodiments, both the first storage unit 708 and the second storage unit 709 include random access memory.

[0117] In some specific examples, the first storage unit 708 and the second storage unit 709 include a simple dual-port RAM.

[0118] It should be noted that the first storage unit 708 and the second storage unit 709 are not limited to the random access memory proposed in the above embodiments, but can also be other memories that include read addresses and write addresses.

[0119] Here, the first storage unit 708 stores the sign values ​​of the messages passed from the variable nodes corresponding to the multiple cyclic permutation matrices after permutation by the permutation unit 711 to the check node. The second storage unit 709 stores the negative C2V messages, i.e. Figure 7 As shown The output value is used in the second calculation unit 704 for calculation. Since the updated C2V message has not yet been rewritten to the node message storage module 702, the node message update module 703 stores the old C2V message from the previous iteration of a frame of codewords. Therefore, the second storage unit 709 stores the negative C2V message from the previous iteration.

[0120] It is understandable that, since RAM has read and write addresses, data can be written to and read from any location in RAM. The first storage unit 708 provided in this embodiment, having a first read address and a first write address, allows it to write V2C messages corresponding to any cyclic permutation matrix in a layer, and freely outputs the sign value of the V2C message corresponding to any cyclic permutation matrix in a layer. Therefore, when updating C2V messages, the output order of the updated C2V messages for any cyclic permutation matrix can be determined, providing optimized degrees of freedom. The second storage unit 709, having a second read address and a second write address, allows it to write negative C2V messages corresponding to any cyclic permutation matrix in a layer, and freely outputs negative C2V messages corresponding to any cyclic permutation matrix in a layer. Therefore, when updating posterior probability messages, the output order of posterior probability messages corresponding to any cyclic permutation matrix in a layer can be determined.

[0121] In some embodiments, the depth of the first storage unit 708 is: the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is: the product of the size of a cyclic permutation matrix and the message width passed from the check node to the variable node.

[0122] The depth of the second storage unit 709 is the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is the size of a cyclic permutation matrix.

[0123] In some embodiments, the message update module 703 further includes: a first calculation unit 705 and a message update unit 713 that verifies the node and transmits the message to the variable node;

[0124] The first calculation unit 705 is configured to: calculate the minimum value, the second smallest value, and the sign XOR value corresponding to the first layer of the parity check matrix;

[0125] The message update unit 713, which transmits the verification node to the variable node, is configured to: sequentially receive the sign values ​​of the messages transmitted by the variable nodes to the verification nodes corresponding to each of the cyclic permutation matrices stored in the first storage unit 708 in a second order; receive the minimum value, the second smallest value, and the sign XOR value of the first layer of the verification matrix calculated by the first calculation unit 705; and sequentially output the updated messages transmitted by the verification nodes to the variable nodes corresponding to each of the cyclic permutation matrices in a second order.

[0126] In some specific examples, the message update module 703 further includes a third storage unit 710, which is configured to cache the minimum value, the second smallest value, and the sign XOR value of the first layer of the parity matrix calculated by the first calculation unit 705.

[0127] In some specific examples, the third storage unit 710 includes a FIFO.

[0128] In some specific examples, the first calculation unit 705 can calculate the minimum and second smallest values ​​of the V2C messages corresponding to the first layer of the parity matrix based on the V2C messages output by the permutation unit 711, and output the column position of the minimum value. After the permuted V2C messages corresponding to the first layer of the cyclic permutation matrix are output, the minimum value, column position, second smallest value, and sign XOR value of the V2C messages corresponding to the first layer can be obtained and output to the third storage unit 710. In some specific examples, the message update unit 713, which transmits the parity node to the variable node, can read the minimum value, column position, second smallest value, and sign XOR value of the variable node corresponding to the first layer of the parity matrix cached in the third storage unit 710, and at the same time read the sign value of the V2C messages in the first storage unit 708. Based on the data read from the first storage unit 708 and the data read from the third storage unit 710, it determines whether the current node is the minimum value. If it is the minimum value, the parity node message is assigned the second smallest value; otherwise, the parity node message is assigned the minimum value. The C2V messages corresponding to the first layer of the updated parity-check matrix are LLR(c02v1, c12v2, c22v3, c32v4, c42v0), LLR(c02v7, c12v8, c22v9, c32v5, c42v_6), and LLR(c02v_7, c12v8, c22v9, c32v5, c42v_6), respectively. 15 c12v 16 c22v 17 c32v 18 c42v 19 ).

[0129] In some embodiments, the message update module 703 further includes: an inverse permutation unit 712;

[0130] The inverse permutation unit 712 is configured such that the sequence of messages updated by the message update unit 713, which transmits the verification node to the variable node in a second order, corresponding to each of the cyclic permutation matrices, is changed from being arranged according to the order of the verification nodes to being arranged according to the order of the corresponding variable nodes.

[0131] It is understandable that the inverse permutation unit 712 here performs a cyclic shift on the message output by the message update unit 713, which is passed from the verification node to the variable node. The sum of the shift values ​​of the inverse permutation unit 712 and the permutation unit 711 equals the size of a cyclic permutation matrix.

[0132] In some specific examples, the inverse permutation unit 712 circularly shifts the message from the check node to the variable node output by the message update unit 713: the LLR(c02v1, c12v2, c22v3, c32v4, c42v0) corresponding to the non-zero submatrix 1 is circularly shifted left by 4 to become LLR(c42v0, c02v1, c12v2, c22v3, c32v4); the LLR(c02v7, c12v8, c22v9, c32v5, c42v6) corresponding to the non-zero submatrix 2 is circularly shifted left by 3 to become LLR(c32v5, c42v6, c02v7, c12v8, c22v9); the LLR(c02v7, c12v8, c22v9) corresponding to the non-zero submatrix 3 is circularly shifted left by 3 to become LLR(c02v7, c12v8, c22v9); the LLR(c02v7, c12v8, c22v9) corresponding to the non-zero submatrix 3 is circularly shifted left by 4 to become LLR(c02v7, c12v8, c22v9); the LLR(c02v7, c12v8, c22v9) corresponding to the non-zero submatrix 2 is circularly shifted left by 4 to become LLR(c02v7, c12v8, c22v9); the LLR(c02v7, c12v8, c22v9) corresponding to the non-zero submatrix 3 is circularly shifted left by 4 to become LLR(c02v7, c12v8, c22v9); the LLR(c02v7, c12v8, c22v9) corresponding to the non 15 c12v 16 c22v 17 c32v 18 c42v 19 ) Circular left shift to 0 becomes LLR(c02v) 15 c12v 16 c22v 17 c32v 18 c42v 19 ).

[0133] The message output by the inverse permutation unit 712 here is the updated C2V message corresponding to the first layer of the parity check matrix, that is... Figure 7 As shown The message output from the inverse permutation unit 712 enters the node message storage module 702 through one path and enters the second calculation unit 704 through the other path to participate in the calculation.

[0134] In some embodiments, the message update module 703 further includes: a second computing unit 704;

[0135] The second calculation unit 704 is configured to: based on the messages corresponding to each of the cyclic permutation matrices obtained by the inverse permutation unit 712, the messages corresponding to each of the cyclic permutation matrices stored in the second storage unit 709, and the messages corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module 701, output the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order.

[0136] Here, the second computing unit 704 includes a first sub-computing unit 7041 and a second sub-computing unit 7042, wherein the first sub-computing unit 7041 is configured to: Add After obtaining ΔC2V, the second sub-computation unit is configured to add ΔC2V to the posterior probability message stored in the posterior probability storage module 701 to obtain the updated posterior probability message LLR. updated .

[0137] In some specific examples, the first sub-computation unit 7041 and the second sub-computation unit 7042 include adders.

[0138] In this embodiment of the present disclosure, the message update module 703 receives messages corresponding to each of the cyclic permutation matrices in a first order, and outputs messages corresponding to each of the cyclic permutation matrices in a second order. The first order and the second order can be the same or different. This allows for the free selection of the output order of messages corresponding to any cyclic permutation matrix in one layer of the parity matrix, increasing the degree of freedom, which is beneficial for optimizing the convergence time and improving the throughput.

[0139] Based on the decoder described above, this disclosure also provides a memory controller, including the decoder described in any of the above embodiments.

[0140] Based on the memory controller described above, this disclosure also provides a memory system, including the memory controller described in the above embodiments and a memory device coupled to the memory controller.

[0141] Figure 9A block diagram of a memory system 601 is shown. The memory system 601 includes a memory controller 602 and a memory device 603. The memory controller 602 controls the memory device 603 to perform read and write operations. Here, the memory controller 602 and the memory device 603 can be coupled in any suitable manner. The memory controller 602 includes a control unit (CPU) 608, a data buffer 609, an error correction module 606, a host I / F 605, and a memory I / F 607. In this embodiment, the memory device 603 can be a non-volatile semiconductor memory for storing data, such as a NAND flash memory. The memory system 601 is connected to a host 604. The host I / F 605 outputs commands and valid data (write data) received from the host 604 to the internal bus 610, and sends valid data read from the memory device 603 (read data) and responses from the control unit 608 to the host 604.

[0142] The control unit 608 can instruct the memory I / F 607 to write valid data, parity data, and parity matrix to the memory device 603 according to the command from the host 604. In addition, the control unit can instruct the memory I / F 607 to read valid data, parity data, and parity matrix from the memory device according to the command from the host 604.

[0143] The error correction module 606 here includes an encoding unit and a decoding unit. The encoding unit encodes the written valid data of a predetermined size to generate parity check data (e.g., low-density parity check code LDPC) and the corresponding parity check matrix. The parity check data and the corresponding parity check matrix generated by the encoding unit can be stored in a memory device. The decoding unit uses the parity check data and the corresponding parity check matrix to decode. The decoding unit here includes a decoder. The parity check code and the corresponding parity check matrix during decoding can be obtained from the memory device.

[0144] Based on the memory system described above, this disclosure also provides an electronic device, including a decoder as described in any of the above embodiments, and a memory device coupled to the decoder.

[0145] Here, the decoder can be built into the memory controller, or it can be placed outside the memory controller.

[0146] Here, the specific structure and composition of the memory controller, memory system, and electronic devices can be referred to the aforementioned section. Figure 1 , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4 , Figure 5For the sake of brevity, a detailed introduction will not be repeated here.

[0147] Based on the above decoder, this disclosure also provides a decoding method for layered decoding of quasi-cyclic low-density parity-check codes. During message updates using inter-block serial decoding of multiple cyclic permutation matrices in one layer of the parity-check matrix corresponding to a frame of codewords, such as... Figure 10 As shown, the method includes:

[0148] The posterior probability message is stored using a posterior probability storage module.

[0149] The node message storage module stores the messages passed from the verification node to the variable node.

[0150] The message update module sequentially receives the latest posterior probability messages corresponding to each cyclic permutation matrix stored in the posterior probability storage module in a first order, and sequentially receives the latest messages from the verification nodes to the variable nodes corresponding to each cyclic permutation matrix stored in the node message storage module in the first order. Then, the updated messages from the verification nodes to the variable nodes corresponding to each cyclic permutation matrix are sequentially output in a second order, and the updated posterior probability messages corresponding to each cyclic permutation matrix are sequentially output in a second order. The first order and the second order may be the same or different.

[0151] In some embodiments, the step of sequentially outputting the updated verification node messages corresponding to each of the cyclic permutation matrices to the variable nodes in a second order, and sequentially outputting the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order, includes:

[0152] The third computing unit sequentially receives the latest posterior probability messages corresponding to each cyclic permutation matrix stored in the posterior probability storage module in the first order, and sequentially receives the latest messages from the verification node to the variable node stored in the negative node message storage module corresponding to each cyclic permutation matrix in the first order, and sequentially outputs the messages from the variable node to the verification node corresponding to each cyclic permutation matrix in the first order.

[0153] The above embodiment mainly reads the posterior probability message in the posterior probability message and the verification node message in the node message storage module and passes them to the variable node, and uses the third calculation unit to calculate the message passed from the variable node to the verification node.

[0154] In some embodiments, the step of sequentially outputting the updated verification node messages corresponding to each of the cyclic permutation matrices to the variable nodes in a second order, and sequentially outputting the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order, includes:

[0155] The permutation unit transforms the sequence of messages from the variable nodes corresponding to each cyclic permutation matrix output by the third calculation unit to the verification nodes from the order of the variable nodes to the order of the corresponding verification nodes.

[0156] The above embodiments mainly utilize the substitution unit to cyclically shift the messages from the variable node to the verification node so that they can be transmitted to the first calculation unit for corresponding calculations.

[0157] In some embodiments, the step of sequentially outputting the updated verification node messages corresponding to each of the cyclic permutation matrices to the variable nodes in a second order, and sequentially outputting the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order, includes:

[0158] The first storage unit stores the symbol values ​​of messages passed from the variable nodes corresponding to the multiple cyclic permutation matrices to the verification node; the first storage unit is provided with a first read address and a first write address. The first write address enables the first storage unit to sequentially input the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification node in the first order, and the first read address enables the first storage unit to sequentially output the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification node in the second order.

[0159] The second storage unit stores the latest messages from the check nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module, which are then passed to the variable nodes. The second storage unit is provided with a second read address and a second write address. The second write address enables the second storage unit to sequentially input the latest messages from the check nodes corresponding to each cyclic permutation matrix stored in the negative node message storage module, which are then passed to the variable nodes, in the first order. The second read address enables the second storage unit to sequentially output the latest messages from the check nodes corresponding to each cyclic permutation matrix stored in the negative node message storage module, which are then passed to the variable nodes, in the second order.

[0160] In some embodiments, the step of sequentially outputting the updated verification nodes corresponding to each of the cyclic permutation matrices to the variable nodes in a second order includes:

[0161] The first calculation unit is used to calculate the minimum, second minimum, and sign XOR values ​​of the first layer of the parity check matrix;

[0162] The message update unit, which uses the verification node to pass the message to the variable node, receives the sign value of the message passed to the verification node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit in a second order, and receives the minimum value, second minimum value, and sign XOR value of the first layer of the verification matrix calculated by the first calculation unit. Then, it outputs the updated message passed to the variable node by the verification node corresponding to each of the cyclic permutation matrices in a second order.

[0163] The above embodiments mainly involve calculating the message passed from the variable node to the check node after cyclic shifting in the replacement unit to obtain the updated message passed from the check node to the variable node.

[0164] In some embodiments, the step of sequentially outputting the updated verification node messages corresponding to each of the cyclic permutation matrices to the variable nodes in a second order, and sequentially outputting the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order, includes:

[0165] The message update unit, which uses the inverse permutation unit to pass the verification node to the variable node, outputs the updated sequence of messages passed from the verification node to the variable node in the second order, corresponding to each of the cyclic permutation matrices. The sequence is changed from being arranged according to the order of the verification nodes to being arranged according to the order of the corresponding variable nodes.

[0166] The above embodiments mainly involve using an inverse permutation unit to cyclically shift the message from the updated verification node to the variable node so that it can participate in the calculation in the second calculation unit.

[0167] In some embodiments, the step of sequentially outputting the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order includes:

[0168] The message corresponding to each cyclic permutation matrix obtained by the second calculation unit based on the inverse permutation unit, the message corresponding to each cyclic permutation matrix stored in the second storage unit, and the message corresponding to each cyclic permutation matrix stored in the posterior probability storage module are sequentially output in a second order, and the updated posterior probability message corresponding to each cyclic permutation matrix is ​​output in order.

[0169] The above embodiment mainly involves adding the message from the negative check node output from the second storage unit to the variable node and the updated and shifted check node output from the inverse permutation unit to the variable node using the second calculation unit to obtain the updated posterior probability message.

[0170] In some embodiments, the method further includes: receiving updated posterior probability messages corresponding to each of the cyclic permutation matrices, and substituting the received updated posterior probability messages corresponding to each of the cyclic permutation matrices into the verification equations for verification; if all verification equations are satisfied, the decoding is determined to be successful; if all verification equations are not satisfied, the decoding is determined to be unsuccessful, and the posterior probability messages and the messages passed from the verification node to the variable node need to be updated in the next iteration until the decoding is successful or the maximum number of iterations is reached.

[0171] The above embodiments are mainly for determining whether the number of iterations has been reached.

[0172] Figure 11 A decoding flowchart is provided for an embodiment of this disclosure, which is described below in conjunction with... Figure 7 as well as Figure 11 The decoding method provided in the above embodiments will be further described.

[0173] After the initial channel message of a codeword frame is stored, decoding begins by reading the posterior probability message from the posterior probability storage module, such as... Figure 7 In As shown, the posterior probability message of a cyclic permutation matrix is ​​read one at a time. The C2V message read from the node message storage module is inverted and summed. The V2C message obtained by addition is entered into the substitution unit, and the inverted C2V message is stored in the second storage unit.

[0174] The V2C message is passed through the permutation unit and cyclically shifted. The permuted V2C message takes the sign value and stores it in the first storage unit, and enters the first calculation unit for calculation. The first calculation unit outputs the minimum value, column position, second smallest value, and sign XOR value of the V2C message corresponding to the first layer of the parity check matrix, and caches it in the third storage unit. The message update unit of the check node passes the data in the third storage unit and the V2C message sign value cached in the first storage unit to perform C2V message update.

[0175] The updated C2V message is cyclically shifted by the inverse permutation unit and stored in the node message storage module. At the same time, the second storage unit reads the negative C2V message stored in the node message storage module, and the second calculation unit adds the negative C2V message to the updated C2V message to obtain ΔC2V.

[0176] Retrieve the posterior probability message stored in the posterior probability storage module, such as... Figure 7 In As shown, The updated posterior probability message LLR is obtained by adding ΔC2V to it through the second computation unit. updatedThe updated posterior probability message is stored in the posterior probability storage module and participates in subsequent message updates.

[0177] The above process is a message update process in an iterative process. After one iteration is completed, it is determined whether the maximum number of iterations has been reached. If the maximum number of iterations has not been reached, the next iteration of decoding is performed; otherwise, decoding ends and the decoded codeword is output.

[0178] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0179] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A decoder, characterized in that, The decoder is based on a message update method that uses inter-block serial decoding to perform message updates on multiple cyclic permutation matrices in one layer of the parity-check matrix corresponding to a frame of codewords. The decoder includes: The posterior probability storage module is configured to store posterior probability messages corresponding to each of the cyclic permutation matrices. The node message storage module is configured to: store messages passed from the verification node to the variable node corresponding to each of the cyclic permutation matrices; and The message update module is configured to: receive the posterior probability message corresponding to each of the cyclic permutation matrices and the message passed from the verification node to the variable node in a first order, and output the updated message passed from the verification node to the variable node and the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order; the first order and the second order are different. The message update module includes: a first storage unit and a second storage unit; The first storage unit is configured to: store the symbol values ​​of messages passed from the variable nodes corresponding to the multiple cyclic permutation matrices to the verification nodes; the first storage unit is provided with a first read address and a first write address, the first write address causes the first storage unit to sequentially input the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification nodes in the first order, and the first read address causes the first storage unit to sequentially output the symbol values ​​of messages passed from the variable nodes corresponding to each cyclic permutation matrix to the verification nodes in the second order; The second storage unit is configured to: store the latest messages from the check nodes to the variable nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module; the second storage unit is provided with a second read address and a second write address, wherein the second write address enables the second storage unit to sequentially input the latest messages from the check nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module in the first order, and the second read address enables the second storage unit to sequentially output the latest messages from the check nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module in the second order.

2. The decoder according to claim 1, characterized in that, The first storage unit and the second storage unit each include random access memory.

3. The decoder according to claim 1, characterized in that, The depth of the first storage unit is: the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is: the product of the size of a cyclic permutation matrix and the message width passed from the check node to the variable node. The depth of the second storage cell is the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is the size of a cyclic permutation matrix.

4. The decoder according to claim 1, characterized in that, The message update module further includes: a first calculation unit and a message update unit that verifies the node and transmits the message to the variable node; The first calculation unit is configured to: calculate the minimum value, the second minimum value, and the sign XOR value corresponding to the first layer of the parity check matrix; The message update unit that the verification node passes to the variable node is configured to: sequentially receive the sign values ​​of the messages passed to the verification node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit in a second order, and receive the minimum value, second minimum value, and sign XOR value of the first layer of the verification matrix calculated by the first calculation unit, and sequentially output the updated messages passed to the variable node by the verification node corresponding to each of the cyclic permutation matrices in a second order.

5. The decoder according to claim 4, characterized in that, The message update module further includes: an inverse permutation unit; The inverse permutation unit is configured such that the sequence of messages updated by the message update unit that transmits the verification node to the variable node, corresponding to each of the cyclic permutation matrices, is permuted from the order of the verification nodes to the order of the corresponding variable nodes.

6. The decoder according to claim 5, characterized in that, The message update module further includes: a second calculation unit; The second calculation unit is configured to: based on the messages corresponding to each of the cyclic permutation matrices obtained by the inverse permutation unit, the messages corresponding to each of the cyclic permutation matrices stored in the second storage unit, and the messages corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module, output the updated posterior probability messages corresponding to each of the cyclic permutation matrices in a second order.

7. The decoder according to claim 1, characterized in that, The posterior probability storage module includes two real dual-port random access memories.

8. The decoder according to claim 1, characterized in that, The message update module further includes: a third calculation unit; The third computing unit is configured to: receive the latest posterior probability messages corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module in a first order, and receive the latest messages from the verification nodes to the variable nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module in a first order, and output the messages from the variable nodes corresponding to each of the cyclic permutation matrices to the verification nodes in a first order.

9. The decoder according to claim 8, characterized in that, The message update module further includes: a replacement unit; The permutation unit is configured to: change the sequence of messages from the variable nodes corresponding to each cyclic permutation matrix output by the third calculation unit to the verification nodes from the order of the variable nodes to the order of the corresponding verification nodes.

10. A memory controller, characterized in that, Includes the decoder as described in any one of claims 1-9.

11. A memory system, characterized in that, Includes the memory controller as described in claim 10 and the memory device coupled to the memory controller.

12. An electronic device, characterized in that, It includes a decoder as described in any one of claims 1-9, and a memory device coupled to the decoder.

13. A decoding method, characterized in that, In the process of updating messages by using inter-block serial decoding on multiple cyclic permutation matrices in one layer of the parity-check matrix corresponding to a frame of codewords, the method includes: The posterior probability storage module stores the posterior probability messages corresponding to each of the cyclic permutation matrices. The node message storage module stores the messages passed from the verification node to the variable node for each of the cyclic permutation matrices. The message update module receives the posterior probability message corresponding to each cyclic permutation matrix and the message passed from the verification node to the variable node in a first order, and outputs the updated message passed from the verification node to the variable node and the updated posterior probability message corresponding to each cyclic permutation matrix in a second order; the first order and the second order are different. The step of sequentially outputting the updated messages and updated posterior probability messages corresponding to each of the cyclic permutation matrices from the verification nodes in the second order includes: storing the sign values ​​of the messages from the variable nodes corresponding to the multiple cyclic permutation matrices to the verification nodes using a first storage unit; the first storage unit is provided with a first read address and a first write address, wherein the first write address enables the first storage unit to sequentially input the sign values ​​of the messages from the variable nodes corresponding to each of the cyclic permutation matrices to the verification nodes in the first order, and the first read address enables the first storage unit to sequentially output the sign values ​​of the messages from the variable nodes corresponding to each of the cyclic permutation matrices to the verification nodes in the second order; The second storage unit stores the latest messages from the check nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module, which are then passed to the variable nodes. The second storage unit is provided with a second read address and a second write address. The second write address enables the second storage unit to sequentially input the latest messages from the check nodes corresponding to each cyclic permutation matrix stored in the negative node message storage module, which are then passed to the variable nodes, in the first order. The second read address enables the second storage unit to sequentially output the latest messages from the check nodes corresponding to each cyclic permutation matrix stored in the negative node message storage module, which are then passed to the variable nodes, in the second order.

14. The decoding method according to claim 13, characterized in that, The step of sequentially outputting the updated verification nodes corresponding to each of the cyclic permutation matrices and passing them to the variable nodes in the second order includes: The first calculation unit is used to calculate the minimum, second minimum, and sign XOR values ​​of the first layer of the parity check matrix; The message update unit, which uses the verification node to pass the message to the variable node, receives the sign value of the message passed to the verification node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit in a second order, and receives the minimum value, second minimum value, and sign XOR value of the first layer of the verification matrix calculated by the first calculation unit. Then, it outputs the updated message passed to the variable node by the verification node corresponding to each of the cyclic permutation matrices in a second order.

15. The decoding method according to claim 14, characterized in that, The step of sequentially outputting the updated verification node's message and the updated posterior probability message corresponding to each of the cyclic permutation matrices in the second order includes: The message update unit, which uses the inverse permutation unit to pass the verification node to the variable node, outputs the updated sequence of messages passed from the verification node to the variable node in the second order, corresponding to each of the cyclic permutation matrices. The sequence is changed from being arranged according to the order of the verification nodes to being arranged according to the order of the corresponding variable nodes.

16. The decoding method according to claim 15, characterized in that, The step of sequentially outputting the updated posterior probability messages corresponding to each of the cyclic permutation matrices in the second order includes: The message corresponding to each cyclic permutation matrix obtained by the second calculation unit based on the inverse permutation unit, the message corresponding to each cyclic permutation matrix stored in the second storage unit, and the message corresponding to each cyclic permutation matrix stored in the posterior probability storage module are sequentially output in a second order, and the updated posterior probability message corresponding to each cyclic permutation matrix is ​​output in order.

17. The decoding method according to claim 13, characterized in that, The step of sequentially outputting the updated verification node's message and the updated posterior probability message corresponding to each of the cyclic permutation matrices in the second order includes: The third computing unit sequentially receives the latest posterior probability messages corresponding to each cyclic permutation matrix stored in the posterior probability storage module in the first order, and sequentially receives the latest messages from the verification node to the variable node stored in the negative node message storage module corresponding to each cyclic permutation matrix in the first order, and sequentially outputs the messages from the variable node to the verification node corresponding to each cyclic permutation matrix in the first order.

18. The decoding method according to claim 17, characterized in that, The step of sequentially outputting the updated verification node's message and the updated posterior probability message corresponding to each of the cyclic permutation matrices in the second order includes: The permutation unit transforms the sequence of messages from the variable nodes corresponding to each cyclic permutation matrix output by the third calculation unit to the verification nodes from the order of the variable nodes to the order of the corresponding verification nodes.

19. The decoding method according to claim 13, characterized in that, The method further includes: receiving updated posterior probability messages corresponding to each of the cyclic permutation matrices, and substituting the received updated posterior probability messages corresponding to each of the cyclic permutation matrices into the verification equations for verification. If all verification equations are satisfied, the decoding is determined to be successful; if all verification equations are not satisfied, the decoding is determined to be unsuccessful, and the next iteration is required to update the posterior probability messages and the messages passed from the verification node to the variable node, until the decoding is successful or the maximum number of iterations is reached.

Images