Self-Testing Device for an Ultrasonic Transducer Array

Abstract

The present invention discloses a self-testing device for an ultrasonic transducer array, which relates to the technical field of transducer array testing. It solves the technical problem of the slow development speed of the transducer array integration process due to the lack of accuracy and efficiency in transducer array testing. The key technical solution is to calculate the size of the capacitance under test by calculating the rise time and fall time of the charge and discharge of the capacitance under test, so as to realize the measurement of the elements in the transducer array; at the same time, a reference capacitance is introduced to reduce the error of the current and the inaccuracy caused by the parasitic capacitance of the circuit. Through this self-testing device, the measurement of the electrical parameters of all mainstream transducers can be realized, and the development speed of the transducer array integration process is greatly improved.

Description

Technical Field

[0001] This application relates to the technical field of transducer array testing, and particularly to a self-testing device for an ultrasonic transducer array. Background Art

[0002] Large-scale one-dimensional or two-dimensional ultrasonic transducer arrays usually contain thousands or even tens of thousands of array elements. These array elements are connected to an ultrasonic imaging host through a flexible PCB or ASIC as a substrate. How to efficiently evaluate the electrical connection performance of each transducer array element and the substrate has always been a very difficult problem. The most direct approach is to connect each transducer array element to the host individually for testing. However, this method is time-consuming and inefficient, and the test accuracy will be limited by the parasitic capacitance and impedance mismatch brought by the wires. Therefore, there is an urgent need for an efficient testing method that can ensure measurement accuracy while achieving rapid measurement.

[0003] Generally, the capacitance of the transducer is measured to evaluate whether an effective electrical connection is established between the transducer array element and the substrate. The electrical characteristics of the transducer can be modeled by the BVD (Butterworth-van-Dyke) model, as Figure 1 shown. There are many different types of transducers, such as PZT, CMUT, PMUT, PVDF, etc. These transducers can be divided into two categories, single-ended and double-ended. In a single-ended transducer, the bottom electrode is usually grounded or connected to a fixed level, and the top electrode is connected to the circuit for signal amplification. A double-ended transducer has three ports, and its outer electrode and inner electrode are both connected to the circuit. By measuring the capacitance Cp of each transducer array element, the electrical connection characteristics between the transducer array element and the substrate and the physical characteristics of the transducer itself can be effectively evaluated.

[0004] An on-chip self-test circuit (BIST) can be used to measure the capacitance of each transducer array element. Figure 2a And Figure 2b The BIST circuit shown in is for single-ended ultrasonic transducers or other sensors. Its current source charges and discharges the capacitance to be measured. During the process of charging from to or discharging from the output of the comparator will flip when the input is higher or lower than the reference voltage . Given the size of, the size of the capacitance to be measured can be measured by a counter at the chip end or system end to measure the rise time of the charge and discharge of the capacitance to be measured. and fall time Calculated and expressed as:

[0005] (1)

[0006] Wherein, represents the error of the current source and represents the magnitude of the circuit parasitic capacitance.

[0007] However, the above BIST circuit cannot eliminate the error of the reference current and the inaccuracy caused by the circuit parasitic capacitance, and there are deficiencies in the efficiency and accuracy of the transducer array test. Summary of the Invention

[0008] The present application provides a self-testing device for an ultrasonic transducer array, and its technical purpose is to improve the test accuracy and efficiency of the transducer array, so as to greatly improve the development speed of the transducer array integration process.

[0009] The above technical purpose of the present application is achieved through the following technical solutions:

[0010] A self-testing device for an ultrasonic transducer array, comprising:

[0011] A charge and discharge module for charging and discharging the reference capacitor, the capacitor module to be measured, and the circuit parasitic capacitance;

[0012] A comparison / amplification module for obtaining the charge and discharge times of the reference capacitor, the capacitor module to be measured, and the circuit parasitic capacitance;

[0013] Obtaining the magnitude of the capacitor module to be measured according to the charge and discharge times of the reference capacitor, the capacitor module to be measured, and the circuit parasitic capacitance;

[0014] Wherein, the comparison / amplification module includes at least one comparator or at least one amplifier, and each comparator or amplifier includes two input terminals and one output terminal. One input terminal is connected to the charge and discharge module, and the other input terminal is connected to a reference voltage.

[0015] Further, the charge and discharge module includes at least one charge and discharge unit, and each charge and discharge unit includes a charging unit and a discharging unit;

[0016] Or each charge and discharge unit includes a charging unit and a reset switch;

[0017] Or each charge and discharge unit includes a discharging unit and a set switch.

[0018] Further, the capacitor module to be measured includes a capacitor to be measured, the comparison / amplification module includes a comparator / amplifier, and the charge and discharge module includes a charge and discharge unit;

[0019] One end of the circuit parasitic capacitance is grounded; the other end is connected to the charge and discharge unit and is connected to the reference capacitor through the reference switch.

[0020] One end of the reference capacitor is grounded, and the other end is connected to the charge and discharge unit and the circuit parasitic capacitance through the reference switch.

[0021] One end of the capacitor under test is grounded; the other end is connected to the charge and discharge unit through the switch under test and is connected to the reference capacitor through the switch under test and the reference switch.

[0022] When the charge and discharge unit includes a charging unit and a discharging unit, both the charging unit and the discharging unit are connected to the reference capacitor through the reference switch, connected to the capacitor under test through the switch under test, connected to the circuit parasitic capacitance, and connected to one input end of the comparator / amplifier.

[0023] When the charge and discharge unit includes a charging unit and a reset switch, both the charging unit and the reset switch are connected to the reference capacitor through the reference switch, connected to the capacitor under test through the switch under test, connected to the circuit parasitic capacitance, and connected to one input end of the comparator / amplifier.

[0024] When the charge and discharge unit includes a discharging unit and a set switch, both the discharging unit and the set switch are connected to the reference capacitor through the reference switch, connected to the capacitor under test through the switch under test, connected to the circuit parasitic capacitance, and connected to one input end of the comparator / amplifier.

[0025] Further, the charge and discharge module includes a first charge and discharge unit and a second charge and discharge unit, the comparison / amplification module includes a first comparator / amplifier and a second comparator / amplifier, the capacitor under test module includes a first capacitor under test, a second capacitor under test, a first switch and a second switch, and the switch under test includes a first switch under test and a second switch under test;

[0026] One input end of both the first comparator / amplifier and the second comparator / amplifier is connected to the reference voltage, the other input end of the first comparator / amplifier is connected to the output of the first charge and discharge unit, the other input end of the second comparator / amplifier is connected to the output of the second charge and discharge unit, and the output ends of both the first comparator / amplifier and the second comparator / amplifier are connected to the logic gate module.

[0027] When both the first charge and discharge unit and the second charge and discharge unit include a charging unit and a discharging unit, the charging unit and the discharging unit of the first charge and discharge unit are both connected to the reference capacitor through the reference switch and are connected to the first capacitor under test and the circuit parasitic capacitance through the first switch under test; the charging unit and the discharging unit of the second charge and discharge unit are connected to the second capacitor under test through the second switch under test.

[0028] When both the first charge-discharge unit and the second charge-discharge unit include a charging unit and a reset switch, both the charging unit and the reset switch of the first charge-discharge unit are connected to a reference capacitor through a reference switch, and are connected to a first capacitor under test and circuit parasitic capacitance through a first switch under test; the charging unit and the reset switch of the second charge-discharge unit are connected to a second capacitor under test through a second switch under test.

[0029] When both the first charge-discharge unit and the second charge-discharge unit include a discharging unit and a setting switch, both the discharging unit and the setting switch of the first charge-discharge unit are connected to a reference capacitor through a reference switch, and are connected to a first capacitor under test and circuit parasitic capacitance through a first switch under test; the discharging unit and the setting switch of the second charge-discharge unit are connected to a second capacitor under test through a second switch under test.

[0030] Further, one end of the first capacitor under test is grounded; the other end is grounded through a first switch, connected to the first charge-discharge unit through a first switch under test, and connected to the reference capacitor through the first switch under test and the reference switch.

[0031] One end of the second capacitor under test is grounded; the other end is grounded through a second switch and connected to the second charge-discharge unit through a second switch under test.

[0032] One end of the circuit parasitic capacitance is grounded through a first switch, connected to the first charge-discharge unit through a first switch under test, and connected to the reference capacitor through the first switch under test and the reference switch; the other end is grounded through a second switch and connected to the second charge-discharge unit through a second switch under test.

[0033] One end of the first switch is grounded, and the other end is connected to the first charge-discharge unit through a first switch under test, and connected to the reference capacitor through the first switch under test and the reference switch; one end of the second switch is grounded, and the other end is connected to the second charge-discharge unit through a second switch under test.

[0034] Further, the capacitor module under test further includes a third switch; one end of the third switch is connected to the first charge-discharge unit, connected to one end of the first switch, the first capacitor under test and the circuit parasitic capacitance through a first switch under test, and connected to the reference capacitor through the reference switch; the other end of the third switch is connected to the second charge-discharge unit, connected to the other end of the second switch, the second capacitor under test and the circuit parasitic capacitance through a second switch under test.

[0035] Further, the first switch, the second switch, the first switch under test and the second switch under test are all MOS switches.

[0036] Further, the self-test device further includes a self-test selection module and an amplification selection module; the self-test selection module includes a first capacitor and a self-test selection switch connected in parallel; the amplification selection module includes a second capacitor, a resistor, and an amplification selection switch, the second capacitor and the resistor are connected in parallel, one end of the second capacitor and one end of the resistor are both connected to the amplification selection switch, and the other ends are both connected to the output end of the comparison / amplification module, and the amplification selection switch, the first capacitor, the self-test selection switch, and one input end of the comparison / amplification module are all connected;

[0037] The first capacitor and the self-test selection switch are both connected to the charge and discharge unit, and are both connected to the reference capacitor through the reference switch.

[0038] Further, when the comparison / amplification module includes a first comparator / amplifier and a second comparator / amplifier: the amplification selection switch, the first capacitor, the self-test selection switch, and one input end of the first comparator / amplifier and the second comparator / amplifier are all connected; the other end of the second capacitor and the other end of the resistor are both connected to the output ends of the first comparator / amplifier and the second comparator / amplifier.

[0039] Further, the ultrasonic transducer array includes a linear array ultrasonic transducer and a planar array ultrasonic transducer.

[0040] The beneficial effect of the present application lies in: the self-test device for the ultrasonic transducer array described in the present application calculates the size of the capacitance to be measured through the rise time and fall time of charging and discharging the capacitance to be measured, and realizes the measurement of the elements in the transducer array; at the same time, a reference capacitor is introduced to reduce the error of the current and the inaccuracy caused by the parasitic capacitance of the circuit. Through this self-test device, the electrical parameters of all mainstream transducers can be measured, and the development speed of the transducer array integration process is greatly improved. Description of the Drawings

[0041] Figure 1 It is a schematic diagram of the electrical model of the transducer;

[0042] Figure 2a It is a schematic diagram of the existing self-test circuit;

[0043] Figure 2b For Figure 2a It is the timing diagram of the charge and discharge process corresponding to the self-test circuit in

[0044] Figure 2c For Figure 2a One embodiment of , its discharge unit is replaced with a reset switch, and only one measurement is required;

[0045] Figure 2d For Figure 2a Another embodiment of , its charging unit is replaced with a set switch, and only one measurement is required;

[0046] Figure 3 Structural schematic diagram of the capacitance self - test device according to the first embodiment of the present application;

[0047] Figure 4 Structural schematic diagram of the differential capacitance self - test device according to the second embodiment of the present application;

[0048] Figure 5 Structural schematic diagram of the differential capacitance self - test device according to the third embodiment of the present application;

[0049] Figure 6 Structural schematic diagram of the differential capacitance self - test device according to the fourth embodiment of the present application. Detailed implementation manners

[0050] The technical solution of the present application will be described in detail below in conjunction with the accompanying drawings.

[0051] The self - test device for an ultrasonic transducer array described in the present application includes a charge - discharge module and a comparison / amplification module. The charge - discharge module is used to charge and discharge a reference capacitor, a capacitor module to be measured, and a circuit parasitic capacitance; the comparison / amplification module is used to obtain the charge - discharge times of the reference capacitor, the capacitor module to be measured, and the circuit parasitic capacitance; and finally, the size of the capacitor module to be measured is obtained based on the charge - discharge times of the reference capacitor, the capacitor module to be measured, and the circuit parasitic capacitance.

[0052] Among them, the comparison / amplification module includes at least one comparator or at least one amplifier. Each comparator or amplifier includes two input terminals and one output terminal. One input terminal is connected to the charge - discharge module, and the other input terminal is connected to a reference voltage.

[0053] As a specific embodiment, the charge - discharge module includes at least one charge - discharge unit. In the embodiment of the present application, the specific implementation manner of the charge - discharge unit is as Figure 2a , Figure 2c and Figure 2d shown. Figure 2a In, each charge - discharge unit includes a charging unit and a discharging unit; Figure 2c In, each charge - discharge unit includes a charging unit and a reset switch; Figure 2d In, each charge - discharge unit includes a discharging unit and a set switch.

[0054] Figure 3 This is an embodiment of the self - test device described in the present application. In order to eliminate Figure 2a the error of the reference current and the inaccuracy caused by the circuit parasitic capacitance in the self - test circuit shown, a reference capacitor is introduced in the present application.

[0055] In addition, Figure 2aAfter the discharge unit in the charge and discharge unit is replaced with a reset switch, only one measurement needs to be performed. The schematic diagram and the corresponding timing diagram of the charge and discharge process are as Figure 2c shown.

[0056] Figure 2a After the charge unit in the charge and discharge unit is replaced with a set switch, only one measurement needs to be performed. The schematic diagram and the corresponding timing diagram of the charge and discharge process are as Figure 2d shown.

[0057] Embodiment 1:

[0058] Figure 3 The corresponding capacitance measurement is for a single-port transducer or sensor, and the measurement process includes:

[0059] 1) Close the switch cal-en, close the switch in-en, and the current source charges and discharges the reference capacitor According to the Figure 2b shown timing diagram, the charge and discharge time required to measure the reference capacitor is:

[0060] (2)

[0061] 2) Open the switch cal-en, close the switch in-en, and the current source charges and discharges the capacitor under test , and measures the charge and discharge time required for the capacitor under test is:

[0062] (3)

[0063] Open the switch cal-en and the switch in-en, and the current source charges and discharges the circuit parasitic capacitance , and measures the charge and discharge time required for the circuit parasitic capacitance is:

[0064] (4)

[0065] 4) By subtracting the formulas (2), (3), and (4) from each other in pairs, a ratio independent of the error from the reference current and the magnitude of the circuit parasitic capacitance can be obtained, and finally the magnitude of the capacitor under test is calculated through the ratio. This ratio is expressed as:

[0066] (5)

[0067] For a two-port transducer or sensor, the present application proposes a differential BIST circuit, asFigure 4 and Figure 5 as shown

[0068] Embodiment 2:

[0069] Figure 5 in is the circuit parasitic capacitance, and are the parasitic capacitances of the transducer. In order to measure and and this application uses two - path BIST to measure the three capacitors respectively through switches S0, S1 and S2, including:

[0070] 1) When S1 is closed, is short - circuited to ground, and BIST measures + , and the result is:

[0071] (6)

[0072] 2) When S2 is closed, is short - circuited to ground, and BIST measures + , and the result is:

[0073] (7)

[0074] 3) When S0 is closed, is short - circuited to ground, and BIST measures + , and the result is:

[0075] (8)

[0076] 4) By solving equations (6), (7) and (8), and and can be measured respectively.

[0077] Embodiment 3:

[0078] Figure 4 The corresponding differential BIST circuit has no switch S0 in Figure 5 , and its measurement process includes:

[0079] 1) Disconnect switch S1 and switch S2, measure the capacitance of node (1), and the result is:

[0080] (9)

[0081] 2) Close switch S2 and open switch S1, measure the capacitance of node (1), and obtain:

[0082] (10)

[0083] 3) Open switch S1 and switch S2, measure the capacitance of node (2), and obtain:

[0084] (11)

[0085] 4) Close switch S1 and open switch S2, measure the capacitance of node (2), and obtain:

[0086] (12)

[0087] 5) According to formulas (9), (10), (11) and (12), obtain:

[0088] (13)

[0089] According to and formula (10), obtain , according to and formula (12), obtain .

[0090] Example 4:

[0091] As Figure 6 shown, the self-measurement device further includes a self-test selection module and an amplification selection module.

[0092] The self-test selection module includes a parallel-connected capacitance Cin and a self-test selection switch BIST_EN. The amplification selection module includes a capacitance CF, a resistance RF and an amplification selection switch AMP_EN. When the self-test selection switch BIST_EN is closed and the amplification selection switch AMP_EN is open, the self-measurement device is in the BIST self-test mode. When the self-test selection switch BIST_EN is open and the amplification selection switch AMP_EN is closed, the self-measurement device is in the amplifier mode for amplifying the received signal of the ultrasonic transducer array.

[0093] Through the above self-measurement device of the present application, the measurement of the electrical parameters of all mainstream transducers can be realized, and the development speed of the transducer array integration process can be greatly improved.

[0094] The above are exemplary embodiments of the present application, and the protection scope of the present application is defined by the claims and their equivalents.

Claims

1. A self-testing device for an ultrasonic transducer array, characterized in that: include: A charge-discharge module for charging and discharging a reference capacitor, a capacitor module to be measured, and a circuit parasitic capacitor; A comparison / amplification module for obtaining the charge and discharge time of the reference capacitor, the capacitor module to be tested, and the circuit parasitic capacitor; The size of the capacitor module to be measured is obtained according to the charge and discharge time of the reference capacitor, the capacitor module to be measured and the circuit parasitic capacitance; Wherein, the capacitance module to be measured includes a capacitance to be measured, the comparison / amplification module includes a comparator, and the charge-discharge module includes a charge-discharge unit; the comparator includes two input terminals and an output terminal, one input terminal is connected to the charge-discharge module, and the other input terminal is connected to a reference voltage; When the charge-discharge unit includes a charge unit and a discharge unit, the charge unit and the discharge unit are both connected to a reference capacitor through a reference switch, connected to a capacitor to be tested through a switch to be tested, connected to a circuit parasitic capacitor, and connected to an input terminal of a comparator; Or when the charge-discharge unit includes a charging unit and a reset switch, the charging unit and the reset switch are both connected to the reference capacitor through the reference switch, connected to the capacitor to be tested through the switch to be tested, connected to the circuit parasitic capacitance, and connected to one input terminal of the comparator; Or when the charge-discharge unit includes a discharge unit and a set switch, the discharge unit and the set switch are connected to the reference capacitor through the reference switch, connected to the capacitor to be tested through the switch to be tested, connected to the circuit parasitic capacitance, and connected to an input terminal of the comparator; The charging and discharging module charges and discharges the reference capacitor, the capacitor to be measured and the circuit parasitic capacitor through a current source.

2. The self-test device according to claim 1, characterized in that: One end of the circuit parasitic capacitor is grounded; the other end is connected to the charge and discharge unit, and is connected to the reference capacitor through a reference switch; One end of the reference capacitor is grounded, and the other end is connected to the charge and discharge unit and the circuit parasitic capacitance through a reference switch; One end of the capacitor to be tested is grounded; the other end is connected to the charge and discharge unit through the switch to be tested, and is connected to the reference capacitor through the switch to be tested and the reference switch.

3. The self-test device according to claim 2, characterized in that: The self-test device further comprises a self-test selection module and an amplification selection module; the self-test selection module comprises a first capacitor and a self-test selection switch connected in parallel; the amplification selection module comprises a second capacitor, a resistor and an amplification selection switch, the second capacitor and the resistor are connected in parallel, one end of the second capacitor and one end of the resistor are both connected to the amplification selection switch, and the other ends are both connected to the output end of the comparator, and the amplification selection switch, the first capacitor, the self-test selection switch and an input end of the comparator are all connected; The first capacitor and the self-test selection switch are both connected to the charge and discharge unit, and are both connected to the reference capacitor through the reference switch.

4. A self-testing device for an ultrasonic transducer array, characterized in that: include: A charge-discharge module for charging and discharging the reference capacitor and the capacitor module to be tested; A comparison / amplification module for obtaining the charge and discharge time of the reference capacitor and the capacitor module to be tested; The size of the capacitor module to be tested is obtained according to the charge and discharge time of the reference capacitor and the capacitor module to be tested; Wherein, the charge and discharge module includes a first charge and discharge unit and a second charge and discharge unit, the comparison / amplification module includes a first comparator and a second comparator, the capacitance module to be measured includes a first parasitic capacitance, a second parasitic capacitance, a third capacitance to be measured, a first switch and a second switch, and the switch to be measured includes a first switch to be measured and a second switch to be measured; the first comparator and the second comparator each include two input terminals and one output terminal; One input end of the first comparator and the second comparator are both connected to a reference voltage, another input end of the first comparator is connected to the output of the first charge and discharge unit, another input end of the second comparator is connected to the output of the second charge and discharge unit, and the output ends of the first comparator and the second comparator are both connected to a logic gate module; When the first charge-discharge unit and the second charge-discharge unit both include a charge unit and a discharge unit, the charge unit and the discharge unit of the first charge-discharge unit are both connected to the reference capacitor through a reference switch, and connected to the first parasitic capacitor and the third capacitor to be tested through a first switch to be tested; the charge unit and the discharge unit of the second charge-discharge unit are connected to the second parasitic capacitor through a second switch to be tested; When the first charge-discharge unit and the second charge-discharge unit both include a charging unit and a reset switch, the charging unit and the reset switch of the first charge-discharge unit are connected to the reference capacitor through the reference switch, and connected to the first parasitic capacitor and the third capacitor to be tested through the first switch to be tested; the charging unit and the reset switch of the second charge-discharge unit are connected to the second parasitic capacitor through the second switch to be tested; When the first charge-discharge unit and the second charge-discharge unit both include a discharge unit and a set switch, the discharge unit and the set switch of the first charge-discharge unit are connected to the reference capacitor through the reference switch, and are connected to the first parasitic capacitor and the third capacitor to be measured through the first switch to be measured; the discharge unit and the set switch of the second charge-discharge unit are connected to the second parasitic capacitor through the second switch to be measured; The charging and discharging module charges and discharges the reference capacitor and the capacitor module to be measured through a current source.

5. The self-test device according to claim 4, characterized in that: One end of the first parasitic capacitor is grounded; the other end is grounded through a first switch, connected to the first charge and discharge unit through a first switch to be tested, and connected to a reference capacitor through the first switch to be tested and a reference switch; One end of the second parasitic capacitor is grounded; the other end is grounded through a second switch and connected to the second charge and discharge unit through a second switch to be tested; One end of the third capacitor to be tested is grounded through the first switch, connected to the first charge and discharge unit through the first switch to be tested, and connected to the reference capacitor through the first switch to be tested and the reference switch; the other end is grounded through the second switch, and connected to the second charge and discharge unit through the second switch to be tested; One end of the first switch is grounded, and the other end is connected to the first charge and discharge unit through the first switch to be tested, and is connected to the reference capacitor through the first switch to be tested and the reference switch; One end of the second switch is grounded, and the other end is connected to the second charge and discharge unit through the second switch to be tested.

6. The self-test device according to claim 5, characterized in that: The capacitor module to be tested also includes a third switch; one end of the third switch is connected to the first charge and discharge unit, connected to the first switch, the first parasitic capacitor and one end of the third capacitor to be tested through the first switch to be tested, and connected to the reference capacitor through the reference switch; the other end of the third switch is connected to the second charge and discharge unit, and connected to the second switch, the second parasitic capacitor and the other end of the third capacitor to be tested through the second switch to be tested.

7. The self-test device according to any one of claims 4 to 6, characterized in that: The first switch, the second switch, the first switch to be tested, and the second switch to be tested are all MOS switches.

8. The self-test device according to any one of claims 4 to 6, characterized in that: The self-test device further comprises a self-test selection module and an amplification selection module; the self-test selection module comprises a first capacitor and a self-test selection switch connected in parallel; the amplification selection module comprises a second capacitor, a resistor and an amplification selection switch, the second capacitor and the resistor are connected in parallel, one end of the second capacitor and one end of the resistor are both connected to the amplification selection switch, the other end of the second capacitor and the other end of the resistor are both connected to the output ends of the first comparator and the second comparator, and the amplification selection switch, the first capacitor, the self-test selection switch and one input end of the first comparator and the second comparator are all connected; The first capacitor and the self-test selection switch are both connected to the charge and discharge unit, and are both connected to the reference capacitor through the reference switch.

9. The self-test device according to claim 1 or 4, characterized in that: The ultrasonic transducer array includes a linear array ultrasonic transducer and a planar array ultrasonic transducer.

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