Low power consumption maximum voltage selection circuit with fast switching function

Abstract

The application provides a low-power maximum voltage selection circuit with a quick switching function, comprising a detection circuit for comparing a first voltage signal and a second voltage signal and outputting a comparison signal to an input end of an acceleration comparison circuit and a first logic gate circuit through a first node; the acceleration comparison circuit comprises a third control tube, a second logic gate circuit and a discharge circuit, a gate of the third control tube is connected with the comparison signal, and an output end of the third control tube is connected with an input end of the second logic gate circuit through a second node; the second logic gate circuit outputs a first level signal to the discharge circuit to turn on a discharge loop of the first node according to a voltage rising / falling state of the second node. The application can quickly respond to the change of an input source voltage and quickly select the highest voltage output through the acceleration comparison circuit and a quick response control circuit, so that the reliability of an anti-backflow power tube substrate switching chip is improved, and the effect of not increasing additional static current power consumption is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a low-power maximum voltage selection circuit with fast switching function. BACKGROUND

[0002] In the field of chip design, the power chip needs to switch the substrate voltage of the power tube to the highest voltage of the circuit for the application of preventing backflow, and fast and low-power switching to the highest voltage helps to improve the performance and application reliability of the chip. Referring to Figure 1 , Figure 1 The existing commonly used maximum voltage selection circuit includes a detection circuit, a driving circuit and a selection circuit. The detection circuit includes resistors R1 and R2, a common-gate differential pair MP1 and MP2, current mirror tubes MN1-MN4, switch tubes MNS1 and MNS2, and logic gates in the V_MAX domain; the driving circuit is composed of logic gates in the V_MAX domain and has a dead zone control processing function; the selection circuit is composed of M1 and M2 tubes connected in a back-to-back manner, and the maximum selection voltage V_MAX is output by the M1 and M2 tubes, and the maximum selection voltage V_MAX is the maximum value of the input voltage signals V1 and V2. Among them, resistors R1 and R2 can be used to set the threshold value of input voltage signals V1 and V2, and can also prevent electrostatic discharge (ESD); the common-gate differential pair MP1 and MP2 and the current mirror MN2 and MN3 constitute a common-gate comparator; the switch tube MNS2 and MN4 control the comparison threshold voltage of the input voltage signals V1 and V2; the switch tube MNS1 controls the static current of the input source V1; the control signal SEL_V1 output by the detection circuit generates the maximum selection voltage V_MAX through the circuit driving and the selector devices M1 and M2 tubes.

[0003] Among them, when the input voltage signal V2 has no voltage, only the input bias current (IBIAS) of the MN1 tube generates static power consumption, and the static power consumption of the detection circuit can be controlled by controlling the bias current of the current mirror MN2 and MN3, so that the maximum voltage selection circuit has low static power consumption when the input voltage signal V2 has no voltage. However, when the change amplitude of the input voltage signals V1 and V2 is small, the delay time from the input voltage signal to the control signal SEL_V1 is inconsistent on the rising and falling edges. Referring to Figure 2 , Figure 2The waveform diagram of the node voltage with small amplitude change is input to the low quiescent current detection circuit, and it can be seen that the rising edge of the control signal SEL_V1 has large delay, and the falling edge has small delay, thus causing the relatively long time required for switching the maximum selection voltage V_MAX from V2 to V1. The rising delay time of the control signal SEL_V1 is controlled by the discharging speed of the voltage at the OUT_CMP node (i.e. controlled by the bias current of the MN3 transistor). However, the bias current of the MN3 transistor is small due to the low power consumption design of the circuit, and the falling threshold of the Schmitt inverter is lower than V_MAX / 2, thus the rising delay time of the control signal SEL_V1 is long, and the time required for switching the maximum selection voltage V_MAX from V2 to V1 is long. However, if the delay time is reduced by increasing the current of the MN3 transistor, the quiescent current power consumption of the circuit will increase, which will be contrary to the original intention of the low quiescent power consumption design.

[0004] In addition, in some special low quiescent power consumption designs of multiple voltage domains, Figure 1 The bias current IBIAS in the detection circuit may be equal to zero in some special cases, for example, the bias current IBIAS is generated by other voltage domains other than the V1 / V2 / V_MAX domain, and the voltage domain has no power supply at this time. At this time, the common gate comparator composed of MP1 / MP2 and MN2 / MN3 will fail, and may generate an incorrect control signal SEL_V1, thus causing the output voltage V_MAX to be not the maximum value. At this time, for the power device in the chip that needs to switch the substrate, the substrate voltage V_MAX is not the maximum value, which will cause the anti-inrush function to fail. At the same time, there may be a situation that the power transistor leaks through the parasitic diode, and the conduction of the parasitic PN junction may induce latch-up and other problems affecting the reliability of the circuit.

[0005] Therefore, it is necessary to design a maximum voltage selection circuit capable of reducing switching delay time, achieving fast switching, improving circuit reliability and having low quiescent power consumption. SUMMARY

[0006] The low power consumption maximum voltage selection circuit with fast switching function provided by the application mainly solves the problems of the maximum voltage selection circuit in the existing low power consumption design scene, such as inconsistent switching speed when the input source amplitude changes little, long unidirectional switching delay time, and reduced circuit reliability in the absence of bias current, thereby achieving the effects of reducing switching delay time, achieving fast switching, improving circuit reliability and having low quiescent power consumption.

[0007] The application achieves the above-mentioned purpose by the following technical solutions:

[0008] The application discloses a low-power maximum voltage selection circuit with a quick switching function, which comprises a detection circuit, a driving circuit and a selection circuit, wherein the detection circuit is respectively connected with a first voltage signal and a second voltage signal and is provided with a first logic gate circuit; the selection circuit comprises a first switch connected with the first voltage signal, a second switch connected with the second voltage signal, and further comprises:

[0009] The detection circuit is used for comparing the first voltage signal and the second voltage signal and outputting a comparison signal to an input end of an accelerated comparison circuit and a first logic gate circuit through a first node; the accelerated comparison circuit comprises a third control tube, a second logic gate circuit and a discharge circuit, the gate of the third control tube is connected with the comparison signal, and the output end of the third control tube is connected with the input end of the second logic gate circuit through a second node; the second logic gate circuit outputs a first level signal to the discharge circuit according to the voltage rise / fall state of the second node to turn on a discharge loop of the first node; the first logic gate circuit is used for outputting a second level signal to the driving circuit according to the voltage amplitude of the first node; the quick response control circuit comprises a first driving control circuit and a second driving control circuit, the driving circuit outputs a first driving signal and a second driving signal with opposite level logic to the first driving control circuit and the second driving control circuit according to the second level signal; the first driving control circuit outputs a first control signal to the control end of the first switch to control the first switch to be turned on so as to output the first voltage signal as a maximum voltage; the second driving control circuit outputs a second control signal to the control end of the second switch to control the second switch to be turned on so as to output the second voltage signal as a maximum voltage.

[0010] The first driving control circuit is provided with a first threshold voltage, the first threshold voltage is the absolute value of the second voltage signal, and is used for controlling the first switch to be turned off when the amplitude of the first voltage signal is lower than the first threshold voltage; the second driving control circuit is provided with a second threshold voltage, the second threshold voltage is the absolute value of the first voltage signal, and is used for controlling the second switch to be turned off when the amplitude of the second voltage signal is lower than the second threshold voltage.

[0011] Further, the detection circuit further comprises a comparison circuit and a first bias circuit, the comparison circuit comprises a first control tube and a second control tube which constitute a common-gate differential pair, the sources of the first control tube and the second control tube are respectively connected with the first voltage signal and the second voltage signal, and the drains of the first control tube and the second control tube are connected with the first bias circuit.

[0012] Further, the acceleration comparison circuit further comprises a third switch tube, a second bias circuit, a gate of the third switch tube is connected with a drain of the second control tube through the first node, a drain of the third switch tube is connected with the second bias circuit through the third switch tube, a gate of the third switch tube is connected with the second voltage signal, and the third switch tube is used to cut off the static current of the circuit when the second voltage signal has no input.

[0013] Further, the second logic gate circuit comprises a first Schmitt inverter and a first NOR gate, an input end of the first Schmitt inverter is connected with the drain of the third control tube, an output end of the first Schmitt inverter is connected with a first input end of the first NOR gate, a second input end of the first NOR gate is connected with the second voltage signal, and an output end of the first NOR gate outputs the first voltage signal.

[0014] Further, the discharge circuit comprises a fifth switch tube and a seventh control tube, a gate of the fifth switch tube is connected with an output end of the first NOR gate, a drain of the fifth switch tube is connected with an input end of the first logic gate circuit, and a source of the fifth switch tube is connected with a drain of the seventh control tube; a gate of the seventh control tube is connected with a bias current, and a source of the seventh control tube is grounded.

[0015] Further, the rising time of the second voltage signal is shortened by increasing the bias current input to the seventh control tube to increase the voltage drop speed of the first node during the discharge.

[0016] Further, the first drive control circuit comprises a first push-pull circuit, a first fast response control tube and a third logic gate circuit, the first drive signal is output to an input end of the third logic gate circuit after being processed by the first push-pull circuit, a gate of the first fast response control tube is connected with the first voltage signal, a source of the first fast response control tube is connected with the second voltage signal, and a drain of the first fast response control tube is connected with the input end of the third logic gate circuit, and the third logic gate circuit outputs the first control signal.

[0017] The second drive control circuit comprises a second push-pull circuit, a second fast response control tube and a fourth logic gate circuit, the second drive signal is output to an input end of the fourth logic gate circuit after being processed by the second push-pull circuit, a gate of the second fast response control tube is connected with the second voltage signal, a source of the second fast response control tube is connected with the first voltage signal, and a drain of the second fast response control tube is connected with the input end of the fourth logic gate circuit, and the fourth logic gate circuit outputs the second control signal.

[0018] Further, the fast response control circuit further comprises two hysteresis inverting level shift circuits, the inverting level shift circuits are connected with the drive circuit, and are used to control the dead time of the drive circuit.

[0019] Further, the driving circuit further comprises a zero bias control circuit, the zero bias control circuit sets a control judgment mechanism for the bias current through a logic gate circuit, and is used for outputting a third level signal to the driving circuit when the bias current is zero, and switching the first control signal and the second control signal to high level output through the fast response control circuit.

[0020] Further, the zero bias control circuit comprises a fourth control tube, a third Schmitt inverter, a first NOR gate, a first NOT gate and a first AND gate, the third Schmitt inverter is connected to the first voltage signal through the fourth control tube, the output end of the third Schmitt inverter is connected with the first input end of the first NOR gate, the second input end of the first NOR gate is connected to the second level signal, the output end of the first NOR gate is connected with the first input end of the AND gate, the second input end of the AND gate is connected to the bias current state signal through the NOT gate, and the output end of the AND gate outputs the third level signal.

[0021] Therefore, the present application has the following beneficial effects:

[0022] 1. The present application accelerates the comparison circuit, when the first voltage signal V1 and the second voltage signal V2 of the input source change slightly, the first node voltage is discharged quickly through the conduction of the discharge circuit, compared with the traditional maximum voltage selection circuit, the delay time of the input source to the rising edge of the second level signal SEL_V1 output by the second Schmitt inverter is reduced, and then the maximum voltage V_MAX can be quickly switched from the second voltage signal V2 to the first voltage signal V1 output through the driving circuit.

[0023] 2. The acceleration comparison circuit of the present application can quickly turn off the third switch tube MNS3 when the input source is powered off, so that static power consumption is not generated, and only intermittent work is generated in the middle of the second Schmitt inverter inversion process; at the same time, the bias current of the MN7 tube is set to make the circuit have low static power consumption, so that the switching speed of the output maximum voltage is accelerated, and the static power consumption of the circuit is also low, and the contradiction between the low static power consumption and the switching speed in the traditional scheme is solved.

[0024] 3. The present application introduces the output source first voltage signal V1 and the second voltage signal V2 directly powered by the driving module output stage through the fast response control circuit, so as to further accelerate the switching speed of the maximum voltage V_MAX of the first voltage signal V1 and the second voltage signal V2 when they change greatly, and then improve the reliability of the anti-backflow power tube substrate switching chip, and will not increase the additional static current power consumption.

[0025] 4、The application is aimed at the special low-power application scenario where the bias current can be zero, and the zero-bias current control circuit identifies the error state of the second Schmitt inverter output level SEL_V1 when the bias current is zero, and superimposes the logic control of the fast response control module to ensure the correct output of the maximum voltage V_MAX.

[0026] The application will be further described in detail below in combination with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is the schematic diagram of the maximum voltage selection circuit of the prior art.

[0028] Figure 2 is the voltage waveform diagram of the key nodes in the circuit of the maximum voltage selection circuit of the prior art when the input signal changes slightly.

[0029] Figure 3 is the schematic diagram of the maximum voltage selection circuit for low-power fast switching in the embodiment of the application.

[0030] Figure 4 is the schematic diagram of the maximum voltage selection circuit for low-power fast switching in the embodiment of the application.

[0031] Figure 5 is the voltage waveform diagram of the key nodes in the circuit when the input signal changes slightly in the embodiment of the application.

[0032] Figure 6 is the schematic diagram of the first driving control circuit / second driving control circuit in the embodiment of the application.

[0033] Figure 7 is the flowchart of the zero-bias current control judgment mechanism in the embodiment of the application.

[0034] Figure 8 is the equivalent circuit of the maximum voltage selection circuit when the zero bias is identified as an error state in the embodiment of the application. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions and advantages of the embodiments of the application clearer, the technical solutions of the embodiments of the application will be described clearly and completely below in combination with the drawings of the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments of the application. Based on the described embodiments of the application, all other embodiments obtained by those of ordinary skill in the art without any creative effort belong to the protection scope of the application.

[0036] A low-power maximum voltage selection circuit with fast switching function

[0037] See Figures 3-4 The application relates to a low-power maximum voltage selection circuit with a quick switching function, which comprises a detection circuit 10, a driving circuit 20 and a selection circuit 30, the detection circuit 10 is respectively connected with a first voltage signal V1 and a second voltage signal V2, and is provided with a first logic gate circuit, the selection circuit 30 comprises a first switch M1 connected with the first voltage signal V1 and a second switch M2 connected with the second voltage signal V2, and further comprises:

[0038] an acceleration comparison circuit 40 and a quick response control circuit 50, the detection circuit 10 is used for comparing the first voltage signal V1 and the second voltage signal V2 and outputting a comparison signal to the acceleration comparison circuit 40 and the input end of the first logic gate circuit through a first node OUT_CMP; the acceleration comparison circuit 40 comprises a third control tube MP3, a second logic gate circuit and a discharge circuit, the gate of the third control tube MP3 is connected with the comparison signal, and the output end of the third control tube MP3 is connected with the input end of the second logic gate circuit through a second node OUT_FAST; the second logic gate circuit outputs a first level signal SPD to the discharge circuit according to the voltage rise / fall state of the second node OUT_FAST to turn on the discharge loop of the first node OUT_CMP; the first logic gate circuit is used for outputting a second level signal SEL_V1 to the driving circuit 20 according to the voltage amplitude of the first node OUT_CMP; the quick response control circuit 50 comprises a first driving control circuit 51 and a second driving control circuit 52, the driving circuit 20 outputs a first driving signal and a second driving signal with opposite level logic to the first driving control circuit 51 and the second driving control circuit 52 according to the second level signal SEL_V1; the first driving control circuit 51 outputs a first control signal DRV_M1 to the control end of the first switch M1, and is used for controlling the first switch M1 to be turned on so as to output the first voltage signal V1 as a maximum voltage V_MAX; the second driving control circuit 52 outputs a second control signal DRV_M2 to the control end of the second switch M2, and is used for controlling the second switch M2 to be turned on so as to output the second voltage signal V2 as the maximum voltage V_MAX.

[0039] The first driving control circuit 51 is provided with a first threshold voltage, the first threshold voltage is the absolute value of the second voltage signal V2, and is used for controlling the first switch M1 to be turned off when the amplitude of the first voltage signal V1 is lower than the first threshold voltage; the second driving control circuit 52 is provided with a second threshold voltage, the second threshold voltage is the absolute value of the first voltage signal V1, and is used for controlling the second switch M2 to be turned off when the amplitude of the second voltage signal V2 is lower than the second threshold voltage.

[0040] In the embodiment, the detection circuit 10 further comprises a comparison circuit and a first bias circuit, the comparison circuit comprises a first control tube MP1 and a second control tube MP2 constituting a common gate differential pair, the sources of the first control tube MP1 and the second control tube MP2 are connected to a first voltage signal V1 and a second voltage signal V2 respectively, and the drains thereof are connected to the first bias circuit.

[0041] Specifically, the first control tube MP1, the second control tube MP2 and the third control tube MP3 in the embodiment are all PMOS tubes.

[0042] Specifically, the comparison circuit in the embodiment further comprises a first resistor R1, a second resistor R2 and a first switch tube MNS1, the first resistor R1 is connected to the source of the first control tube MP1, and the comparison threshold of the input first voltage signal V1 is changed by adjusting the resistance value of the first resistor R1; the second resistor R2 is connected to the source of the first control tube, and the comparison threshold of the input second voltage signal V2 is changed by adjusting the resistance value of the second resistor R2; the gate of the first switch tube MNS1 is connected to the second voltage signal V2, and is used to turn off the static current of the circuit when there is no input of the second voltage signal V2.

[0043] Specifically, the first bias circuit in the embodiment comprises MN1-MN4 tubes constituting a current mirror, the MN1-MN4 tubes are all NMOS tubes, the gates thereof are all connected to a bias current IBIAS, and the sources thereof are all grounded. The drain of the MN2 tube is connected to the source of the first switch tube MNS1, and the drain of the MN3 tube is connected to the drain of the second control tube MP2 through a first node OUT_CMP.

[0044] Specifically, the first logic gate circuit in the embodiment comprises a second Smitter inverter U2 and a second switch tube MNS2, the input end of the second Smitter inverter U2 is connected to the first node OUT_CMP and the drain of a fifth switch tube MNS5, the drain and the gate of the second switch tube MNS2 are connected in parallel to the input end and the output end of the second Smitter inverter U2, and the source thereof is connected to the drain of the MN4 tube.

[0045] In the embodiment, the acceleration comparison circuit 40 further comprises a third switch tube MNS3 and a second bias circuit, the gate of the third control tube MP3 is connected to the drain of the second control tube MP2 through the first node OUT_CMP, the drain thereof is connected to the second bias circuit through the third switch tube MNS3, the gate of the third switch tube MNS3 is connected to the second voltage signal V2, and is used to turn off the static current of the circuit when there is no input of the second voltage signal V2.

[0046] In the embodiment, the second logic gate circuit comprises a first Schmitt inverter U1 and a first NOR gate NOR1, an input terminal of the first Schmitt inverter U1 is connected with the drain of the third control transistor MP3, an output terminal of the first Schmitt inverter U1 is connected with a first input terminal of the first NOR gate NOR1, a second input terminal of the first NOR gate NOR1 is connected with a second level signal SEL_V1, and an output terminal of the first NOR gate NOR1 outputs a first level signal SPD.

[0047] Specifically, the acceleration comparison circuit 40 in the embodiment further comprises a fourth switch transistor MNS4, which is a hysteresis control switch transistor, a gate of the fourth switch transistor MNS4 is connected with the first input terminal of the first NOR gate NOR1, a drain of the fourth switch transistor MNS4 is connected with a source of the third switch transistor MNS3, and a source of the fourth switch transistor MNS4 is connected with the second bias circuit, for introducing a hysteresis characteristic to maintain the stability of the circuit output state and avoid frequent switching of the first level signal SPD output state caused by small amplitude signal fluctuation.

[0048] Specifically, the second bias circuit in the embodiment comprises MN5 and MN6 transistors which constitute a current mirror, both the MN5 and MN6 transistors are NMOS transistors, both the gate of the MN5 and MN6 transistors are connected with a bias current IBIAS, and both the source of the MN5 and MN6 transistors are connected with the ground. The drain of the MN5 is connected with the source of the third switch transistor MNS3, and the drain of the MN6 is connected with the source of the fourth switch transistor MNS4, for setting the working point thereof.

[0049] In the embodiment, the discharge circuit comprises a fifth switch transistor MNS5 and a seventh control transistor MN7, a gate of the fifth switch transistor MNS5 is connected with an output terminal of the first NOR gate NOR1, a drain of the fifth switch transistor MNS5 is connected with an input terminal of the first logic gate circuit, and a source of the fifth switch transistor MNS5 is connected with a drain of the seventh control transistor MN7; a gate of the seventh control transistor MN7 is connected with the bias current IBIAS, and a source of the seventh control transistor MN7 is connected with the ground.

[0050] In the embodiment, the bias current input to the seventh control transistor MN7 is increased, so as to increase the voltage drop speed of the first node OUT_CMP during discharging, thereby shortening the rising time of the second level signal SEL_V1.

[0051] Specifically, the working process of the acceleration comparison circuit 40 in the embodiment is as follows:

[0052] When the voltage of the first node OUT_CMP drops below the V_MAX voltage minus the absolute threshold voltage of the third control transistor MP3, the third control transistor MP3 is turned on, at this time, the voltage of the second node OUT_FAST is rapidly increased, the first level signal SPD output by the second logic gate circuit is rapidly flipped high, so that the fifth switch transistor MNS5 is turned on, at this time, the voltage of the first node OUT_CMP is discharged through the current mirror discharge path.

[0053] Referring to Figure 5, the first node OUT_CMP voltage falling speed is controlled by MN3 and MN7 current, for low power consumption design, without increasing MN3 current, the first node OUT_CMP is made to fall below the falling threshold of the second stage second Smith inverter U2 by increasing the bias current IBIAS of MN7, thereby reducing the delay time from input source voltage change to second level signal SEL_V1 high; at the same time, when the second voltage signal V2 has no input, the third switch tube MNS3 is turned off to reduce the static power consumption of the circuit in the discharge state.

[0054] Referring to Figure 6 In the embodiment, the first drive control circuit 51 comprises a first push-pull circuit, a first fast response control tube, and a third logic gate circuit. The first drive signal is output to the input end of the third logic gate circuit after signal processing by the first push-pull circuit. The gate of the first fast response control tube is connected to the first voltage signal V1, the source is connected to the second voltage signal V2, and the drain is connected to the input end of the third logic gate circuit. The third logic gate circuit outputs the first control signal DRV_M1.

[0055] The second drive control circuit 52 comprises a second push-pull circuit, a second fast response control tube, and a fourth logic gate circuit. The second drive signal is output to the input end of the fourth logic gate circuit after signal processing by the second push-pull circuit. The gate of the second fast response control tube is connected to the second voltage signal V2, the source is connected to the first voltage signal V1, and the drain is connected to the input end of the fourth logic gate circuit. The fourth logic gate circuit outputs the second control signal DRV_M2.

[0056] Specifically, the circuit structures of the first push-pull circuit and the second push-pull circuit in the embodiment are consistent, Figure 6 The upper P and lower N type push-pull circuit is used to amplify the first drive signal or the second drive signal and output the amplified signal to the input end of the fourth logic gate circuit through the third node INB.

[0057] Specifically, in the first push-pull circuit and the second push-pull circuit of the embodiment, the common drain lines of the upper and lower tubes are connected in series with a current-limiting resistor .

[0058] Specifically, the third logic gate circuit and the fourth logic gate circuit in the embodiment each comprise two first-stage inverters and second-stage inverters connected in series.

[0059] Specifically, the control tube in the embodiment includes but is not limited to MOS tube / BJT.

[0060] Specifically, this embodiment uses the initial value of V_MAX = V2 as an example to illustrate the operation of the fast response control circuit 50 as follows:

[0061] See Figure 6 At this point, the MPS transistor in the diagram is the second fast response control transistor, Vx=V2, the power supply input is the first voltage signal V1, the first control signal DRV_M1 output by the first drive control circuit 51 is at a high level, i.e., DRV_M1=V2, and the second control signal DRV_M2 output by the second drive control circuit 52 is at a low level. When the second voltage signal V2 rapidly decreases to the threshold voltage of the second fast response control transistor (i.e., the absolute value of the first voltage signal V1), the second fast response control transistor is turned on. At this time, the voltage of the third node INB is forcibly pulled high, the second control signal DRV_M2 switches to a high level, i.e., DRV_M2=V1, and the second switch M2 is turned off. At the same time, the first control signal DRV_M1 output by the first drive control signal switches to a low level, the first switch M1 is turned on, and the maximum voltage switches to the output of the first voltage signal V1, i.e., V_MAX=V1.

[0062] When the first-level comparison result does not respond in time, the input second drive signal remains high. At this time, the signal is transmitted through the second fast response control transistor and the current-limiting resistor. The conduction path to the NMOS transistor in the second push-pull circuit is limited by setting a current-limiting resistor. The resistance value makes:

[0063]

[0064] in, For current limiting resistor value, The on-resistance of the NMOS transistor in the second push-pull circuit is... This is the on-resistance of the second fast-response control transistor.

[0065] This allows the voltage of the third node INB to be pulled to a valid high level, preventing leakage in the second-stage inverter and reducing the power consumption of the first-stage inverter.

[0066] In this process, after the first-level detection circuit 10 outputs the second-level signal SEL_V1 high, the first control signal DRV_M1 output after passing through the drive circuit 20 and the fast response control circuit 50 is low, and the second control signal DRV_M2 is also high and equal to the first voltage signal V1. Therefore, the second drive control circuit 52 has no static current power consumption.

[0067] The above working process is also reversible. When initially V_MAX = V1, when the first voltage signal V1 rapidly decreases to below the threshold voltage of the first fast response control tube (i.e. the absolute value of the second voltage signal V2), the first control signal DRV_M1 switches to high level, i.e. DRV_M1 = V2, the first switch M1 is turned off; at the same time, the second control signal DRV_M2 switches to low level, the second switch M2 is turned on, so that the maximum voltage is switched to the second voltage signal V2 output, i.e. V_MAX = V2.

[0068] In the embodiment, the fast response control circuit 50 further comprises two hysteresis reverse level shift circuits connected with the driving circuit 20 for dead time control of the driving circuit 20.

[0069] Specifically, the driving circuit 20 of the embodiment comprises a second NOT gate NOT2, a first driving circuit and a second driving circuit with the same circuit structure, the second level signal SEL_V1 is connected to the second driving circuit and connected to the first driving circuit through the second NOT gate NOT2.

[0070] The first driving circuit comprises a second NOR gate NOR2, a third NOT gate NOT3 and a fourth NOR gate NOR4, the first input end of the second NOR gate NOR2 is connected with the output end of the first NOT gate NOT1, the second input end thereof is connected to the output end of the second driving control circuit 52 through a reverse level shift circuit, the output end thereof is connected to the first input end of the fourth NOR gate NOR4 through the third NOT gate NOT3, and the second input end of the fourth NOR gate NOR4 is connected to the third level signal ERROR output from the zero bias control circuit 60.

[0071] The second driving circuit comprises a third NOR gate NOR3, a fourth NOT gate NOT4 and a fifth NOR gate NOR5, the first input end of the third NOR gate NOR3 is connected to the second level signal SEL_V1, the second input end thereof is connected to the output end of the first driving control circuit 51 through another reverse level shift circuit, the output end thereof is connected to the first input end of the fifth NOR gate NOR5 through the fourth NOT gate NOT4, and the second input end of the fifth NOR gate NOR5 is connected to the third level signal ERROR output from the zero bias control circuit 60.

[0072] In the embodiment, the driving circuit 20 further comprises a zero bias control circuit 60, the zero bias control circuit 60 sets a control judgment mechanism for the bias current IBIAS through a logic gate circuit, for outputting the third level signal ERROR to the driving circuit 20 when the bias current IBIAS is zero, and switching the first control signal DRV_M1 and the second control signal DRV_M2 to high level output through the fast response control circuit 50.

[0073] In the embodiment, the zero-bias control circuit 60 comprises a fourth control transistor MP4, a third Schmitt inverter U3, a first NOR gate X1, a first NOT gate NOT1 and a first AND gate A1, the third Schmitt inverter U3 is connected to the first voltage signal V1 through the fourth control transistor MP4, the output terminal of the third Schmitt inverter U3 is connected to the first input terminal of the first NOR gate X1, the second input terminal of the first NOR gate X1 is connected to the second voltage signal SEL_V1, the output terminal of the first NOR gate X1 is connected to the first input terminal of the AND gate, the second input terminal of the AND gate is connected to the bias current IBIAS state signal through the NOT gate, and the output terminal of the AND gate outputs the third voltage signal ERROR.

[0074] Specifically, the MN8 transistor is connected to the drain of the fourth control transistor MP4, and the gate and the source of the MN8 transistor are grounded.

[0075] Specifically, when the bias current IBIAS=0 in the detection circuit 10, the voltage of the first node OUT_CMP has no current mirror discharge path, and only when the input second voltage signal V2 is low, the voltage of the first node OUT_CMP will be discharged to the outside through the parasitic PN junction diode of the second control transistor MP2. Accordingly, the bias current IBIAS judgment signal IBIAS_OK is introduced in the embodiment, and the zero-bias current judgment logic is as follows: when IBIAS_OK=0, SEL_V1=1, and the output error judgment result signal IBIAS_OKB=1; at the same time, the state of the input source first voltage signal V2 is detected and the detection signal SEL_V2 is output, the second voltage signal SEL_V1 and the detection signal SEL_V2 are input into the first NOR gate X1, and the control signal ERR_ZB is output; the control signal ERR_ZB and the error judgment result signal IBIAS_OKB are input into the first AND gate A1, and the third voltage signal ERROR is output, and the zero-bias current judgment logic is shown in Table 1.

[0076] Table 1 Zero-bias current judgment logic table

[0077]

[0078] When the third voltage signal ERROR signal is high, the first driving signal output by the fourth NOR gate NOR4 in the driving circuit 20 is high, i.e. DRV_M1=V2, and the second driving signal output by the fifth NOR gate NOR5 is also high, i.e. DRV_M2=V1, at this time, the equivalent circuit of the driving stage and the selection circuit 30 is as follows Figure 8As shown in the figure, the selection circuit 30 is equivalent to the simplest comparator circuit architecture without bias current IBIAS, and the maximum voltage can still be normally selected as the output when the voltage difference between the first voltage signal V1 and the second voltage signal V2 is large, to ensure that the output voltage is the maximum value of the first voltage signal V1 and the second voltage signal V2.

[0079] The above embodiments are only preferred embodiments of the present application, and cannot be used to limit the scope of protection of the present application. Any non-essential changes and substitutions made by those skilled in the art on the basis of the present application shall fall within the scope of protection of the present application.

Claims

1. A low-power maximum voltage selection circuit with fast switching function, comprising a detection circuit, a driving circuit, and a selection circuit, wherein the detection circuit receives a first voltage signal and a second voltage signal respectively, and is provided with a first logic gate circuit, and the selection circuit includes a first switch connected to the first voltage signal and a second switch connected to the second voltage signal, characterized in that, Also include: The detection circuit is used for comparing the first voltage signal, second voltage signal, and outputting the comparison signal to the input end of the acceleration comparison circuit and the first logic gate circuit through the first node respectively; the acceleration comparison circuit includes a third control tube, a second logic gate circuit and a discharge circuit, the gate of the third control tube is connected to the comparison signal, and the output end is connected to the input end of the second logic gate circuit through the second node; the second logic gate circuit outputs a first level signal to the discharge circuit according to the voltage rise / fall state of the second node to turn on the discharge loop of the first node; the first logic gate circuit is used for outputting a second level signal to the driving circuit according to the voltage amplitude of the first node; The fast response control circuit includes a first drive control circuit and a second drive control circuit, and the driving circuit outputs a first drive signal and a second drive signal with opposite logic levels to the first drive control circuit and the second drive control circuit according to the second level signal; The first drive control circuit outputs a first control signal to the control end of the first switch, which is used to control the first switch to turn on so as to output the first voltage signal as the maximum voltage; The second drive control circuit outputs a second control signal to the control end of the second switch, which is used to control the second switch to turn on so as to output the second voltage signal as the maximum voltage; Wherein, the first drive control circuit is provided with a first threshold voltage, the first threshold voltage is the absolute value of the second voltage signal, which is used to control the first switch to turn off when the amplitude of the first voltage signal is lower than the first threshold voltage; the second drive control circuit is provided with a second threshold voltage, the second threshold voltage is the absolute value of the first voltage signal, which is used to control the second switch to turn off when the amplitude of the second voltage signal is lower than the second threshold voltage.

2. The low-power maximum voltage selection circuit with fast switching function according to claim 1, characterized in that: The detection circuit further includes a comparison circuit and a first bias circuit, the comparison circuit includes a first control tube and a second control tube constituting a common-gate differential pair, the sources of the first control tube and the second control tube are connected to the first voltage signal and the second voltage signal respectively, and the drains thereof are connected to the first bias circuit.

3. The low-power maximum voltage selection circuit with fast switching function according to claim 2, characterized in that: The acceleration comparison circuit further includes a third switch tube and a second bias circuit, the gate of the third control tube is connected to the drain of the second control tube through the first node, the drain of the third control tube is connected to the second bias circuit through the third switch tube, and the gate of the third switch tube is connected to the second voltage signal, which is used to turn off the static current of the circuit when there is no input of the second voltage signal.

4. The low-power maximum voltage selection circuit with fast switching function according to claim 1, characterized in that: The second logic gate circuit comprises a first Schmitt inverter and a first NAND gate, an input end of the first Schmitt inverter is connected with the drain of the third control tube, an output end of the first Schmitt inverter is connected with a first input end of the first NAND gate, a second input end of the first NAND gate is connected with the second voltage signal, and an output end of the first NAND gate outputs the first voltage signal.

5. The low-power maximum voltage selection circuit with fast switching function according to claim 4, wherein: The discharge circuit comprises a fifth switch tube and a seventh control tube, a gate of the fifth switch tube is connected with an output end of the first NAND gate, a drain of the fifth switch tube is connected with an input end of the first logic gate circuit, and a source of the fifth switch tube is connected with a drain of the seventh control tube; a gate of the seventh control tube is connected with a bias current, and a source of the seventh control tube is grounded.

6. The low-power maximum voltage selection circuit with fast switching function according to claim 5, wherein: The voltage drop speed of the first node during the discharging is increased by increasing the bias current input to the seventh control tube, so as to shorten the rising time of the second voltage signal.

7. The low-power maximum voltage selection circuit with fast switching function according to claim 1, wherein: The first drive control circuit comprises a first push-pull circuit, a first fast response control tube and a third logic gate circuit, the first drive signal is processed by the first push-pull circuit and then output to an input end of the third logic gate circuit, a gate of the first fast response control tube is connected with the first voltage signal, a source of the first fast response control tube is connected with the second voltage signal, and a drain of the first fast response control tube is connected with the input end of the third logic gate circuit, and the third logic gate circuit outputs the first control signal; The second drive control circuit comprises a second push-pull circuit, a second fast response control tube and a fourth logic gate circuit, the second drive signal is processed by the second push-pull circuit and then output to an input end of the fourth logic gate circuit, a gate of the second fast response control tube is connected with the second voltage signal, a source of the second fast response control tube is connected with the first voltage signal, and a drain of the second fast response control tube is connected with the input end of the fourth logic gate circuit, and the fourth logic gate circuit outputs the second control signal.

8. The low-power maximum voltage selection circuit with fast switching function according to claim 7, wherein: The fast response control circuit further comprises two inverse level shift circuits with hysteresis, the inverse level shift circuits are connected with the drive circuit, and are used for dead time control of the drive circuit.

9. The low-power maximum voltage selection circuit with fast switching function according to any one of claims 1-8, wherein: The drive circuit further comprises a zero bias control circuit, the zero bias control circuit sets a control judgment mechanism for the bias current through a logic gate circuit, is used for outputting a third voltage signal to the drive circuit when the bias current is zero, and switching the first control signal and the second control signal to high level output through the fast response control circuit.

10. The low-power maximum voltage selection circuit with fast switching function according to claim 9, characterized in that: the zero-bias control circuit comprises a fourth control tube, a third Schmitt inverter, a first EXCLUSIVE-OR gate, a first NOT gate and a first AND gate, the third Schmitt inverter is connected to the first voltage signal through the fourth control tube, the output terminal of the third Schmitt inverter is connected to the first input terminal of the first EXCLUSIVE-OR gate, the second input terminal of the first EXCLUSIVE-OR gate is connected to the second voltage signal, the output terminal of the first EXCLUSIVE-OR gate is connected to the first input terminal of the AND gate, the second input terminal of the AND gate is connected to the bias current state signal through the NOT gate, and the output terminal of the AND gate outputs the third voltage signal.

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