Testers and their service boards

Abstract

This application relates to a test machine and its service board. The service board includes: a waveform generation module connected to a waveform synthesis module, which outputs waveform data to the waveform synthesis module; a waveform synthesis module connected to a parallel-to-serial conversion module, which splits the waveform data output by the waveform generation module into parallel data and sends it to the parallel-to-serial conversion module; a parallel-to-serial conversion module connected to the device under test (DUT) and a comparison module, which performs parallel-to-serial conversion and delay processing on the received parallel data, sends the delayed serial data to the DUT, and performs delay and serial-to-parallel conversion on the feedback data from the DUT, outputting sampled data to the comparison module; and a comparison module receiving the sampled data sent by the parallel-to-serial conversion module and outputting the comparison result. By centralizing the data conversion and delay processing within the parallel-to-serial conversion module, other modules outside the parallel-to-serial conversion module can use a low-speed clock to process data, reducing data processing power consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a testing machine and its business board. Background Technology

[0002] Waveform generation and sampling are crucial components of a test suite, used to generate precise waveforms required for testing a specific chip or to sample and compare signals output by the chip under test. The period and drive / sampling edges are two key parameters in this process, directly affecting the timing accuracy, frequency resolution, and sampling accuracy of the waveform.

[0003] Traditional waveform generation and sampling methods for test machines use a high-speed clock to encode and delay serial data before outputting it to the device under test (DUT), and also perform delayed sampling of the serial data fed back by the DUT. The entire waveform generation and sampling architecture is based on a high-speed clock, which has the disadvantage of high power consumption during data processing. Utility Model Content

[0004] Therefore, it is necessary to provide a test machine and its service boards that can reduce data processing power consumption to address the above problems.

[0005] The first aspect of this application provides a service board for a test machine, comprising:

[0006] The waveform generation module is connected to the waveform synthesis module, and waveform data is output to the waveform synthesis module.

[0007] The waveform synthesis module is connected to the parallel-to-serial conversion module, and splits the waveform data output by the waveform generation module into parallel data and sends it to the parallel-to-serial conversion module.

[0008] The parallel-to-serial conversion module connects the device under test (DUT) and the comparison module. It performs parallel-to-serial conversion and delay processing on the received parallel data, and sends the delayed serial data to the DUT. It also performs delay and serial-to-parallel conversion on the feedback data from the DUT, and outputs sampled data to the comparison module.

[0009] The comparison module receives the sampled data sent by the parallel-to-serial conversion module and outputs the comparison result.

[0010] In one embodiment, the parallel-to-serial conversion module includes:

[0011] The output data processing channel connects the waveform synthesis module and the device under test, receives the parallel data output by the waveform synthesis module, and sends the delayed serial data to the device under test.

[0012] The input data processing channel connects the comparison module and the device under test, receives feedback data output by the device under test, and outputs sampled data to the comparison module.

[0013] In one embodiment, the output data processing channel includes a parallel-to-serial conversion unit, an output register, and an output delay unit connected in sequence. The parallel-to-serial conversion unit is connected to the waveform synthesis module, and the output delay unit is connected to the device under test via an I / O interface.

[0014] In one embodiment, the input data processing channel includes an input delay unit, an input register, a serial-to-parallel conversion unit, and a buffer unit connected in sequence. The input delay unit is connected to the device under test via an I / O interface, and the buffer unit is connected to the comparison module.

[0015] In one embodiment, the service board further includes:

[0016] The waveform control module is connected to the parallel-to-serial conversion module, and the delay parameters of the parallel-to-serial conversion module are adjusted according to the configured time information.

[0017] In one embodiment, the waveform control module includes a timing setting unit and a timing control unit, wherein the timing control unit is connected to the timing setting unit and the parallel-to-serial conversion unit, output delay unit, input delay unit and buffer unit in the parallel-to-serial conversion module.

[0018] In one embodiment, the service board further includes:

[0019] The phase-locked loop module connects the waveform generation device, the waveform generation module, the waveform synthesis module, the parallel-to-serial conversion module, and the waveform control module. It receives the base clock from the waveform generation device and outputs the operating clock to the waveform generation module, the waveform synthesis module, the parallel-to-serial conversion module, and the waveform control module.

[0020] In one embodiment, the phase-locked loop module includes a high-frequency clock output interface and a low-frequency clock output interface. The high-frequency clock output interface is connected to the parallel-to-serial conversion unit, output register, input register, serial-to-parallel conversion unit, and buffer unit in the parallel-to-serial conversion module. The low-frequency clock output interface is connected to the waveform generation module, the waveform synthesis module, the waveform control module, and the output delay unit and input delay unit in the parallel-to-serial conversion module.

[0021] In one embodiment, the service board further includes an interface module that connects the waveform generation module, the waveform control module, the phase-locked loop module, the waveform generation device, and the communication board.

[0022] A second aspect of this application provides a test machine, including a waveform generation device, a communication board, and the aforementioned service board.

[0023] The aforementioned test machine and its service boards, in their waveform synthesis module, split the waveform data output by the waveform generation module into parallel data and send it to the parallel-to-serial conversion module. The parallel-to-serial conversion module performs parallel-to-serial conversion and delay processing on the received parallel data, sending the delayed serial data to the device under test (DUT). It also delays and performs serial-to-parallel conversion on the feedback data from the DUT, outputting sampled data to the comparison module, which then outputs the comparison result. By centralizing data conversion and delay processing within the parallel-to-serial conversion module, other modules outside the module can use a low-speed clock to process data, reducing data processing power consumption. Attached Figure Description

[0024] Figure 1 This is a structural block diagram of the service board of the test machine in one embodiment;

[0025] Figure 2 This is a schematic diagram of the service board of a test machine in one embodiment. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0028] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0029] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof.

[0030] In one embodiment, such as Figure 1As shown, a service board for a test machine is provided, including a waveform generation module 110, a waveform synthesis module FC, a parallel-to-serial conversion module 120, and a comparison module CP. The waveform generation module 110 is connected to the waveform synthesis module FC and outputs waveform data to the waveform synthesis module FC. The waveform synthesis module FC is connected to the parallel-to-serial conversion module 120 and splits the waveform data output by the waveform generation module 110 into parallel data and sends it to the parallel-to-serial conversion module 120. The parallel-to-serial conversion module 120 is connected to the device under test and the comparison module CP. It performs parallel-to-serial conversion and delay processing on the received parallel data and sends the delayed serial data to the device under test. It also performs delay and serial-to-parallel conversion on the feedback data from the device under test and outputs sampled data to the comparison module CP. The comparison module CP receives the sampled data sent by the parallel-to-serial conversion module 120 and outputs the comparison result.

[0031] The device under test (DUT) can be a chip under test or other electronic devices. The waveform generation module 110 can be an Algorithmic Pattern Generator (ALPG) module or a Pattern Generator (PG) module. In this embodiment, the waveform generation module 110 uses an ALPG module to generate relevant waveform data according to configuration information. The waveform synthesis module FC encodes and parses the waveform data output by the ALPG module, splitting the serial data into parallel data and sending it to the parallel-to-serial conversion module 120. Depending on actual needs, the waveform synthesis module FC can split the waveform data into 8, 16, or other numbers of parallel data. The parallel-to-serial conversion module 120 can specifically use the FPGA's BITSLICE hardware resources to implement parallel-to-serial / serial-to-parallel data conversion and data delay processing. The service board also includes a waveform control module 130, which is connected to the parallel-to-serial conversion module 120 and adjusts the delay parameters of the parallel-to-serial conversion module 120 according to configured time information.

[0032] Furthermore, the service board also includes an interface module 140, which connects to the waveform generation module 110, the waveform control module 130, the comparison module CP, and a communication board. The communication board communicates with the host computer. The interface module 140 receives relevant configuration data from the host computer and distributes it to the waveform generation module 110 and the waveform control module 130 for waveform output and timing control. The comparison module CP uploads the comparison results to the host computer through the interface module 140. The specific type of the interface module 140 is not unique; in this embodiment, the interface module 140 uses an Aurora interface.

[0033] In one embodiment, such as Figure 2As shown, the parallel-to-serial conversion module 120 includes an output data processing channel 122 and an input data processing channel 124. The output data processing channel 122 is connected to the waveform synthesis module FC and the device under test, receives the parallel data output by the waveform synthesis module FC, and sends the delayed serial data to the device under test. The input data processing channel 124 is connected to the comparison module CP and the device under test, receives the feedback data output by the device under test, and outputs the sampled data to the comparison module CP.

[0034] The output data processing channel 122 specifically includes a parallel-to-serial conversion unit 1222, an output register DFF1, and an output delay unit 1224 connected in sequence. The parallel-to-serial conversion unit 1222 is connected to the waveform synthesis module FC, and the output delay unit 1224 is connected to the device under test (DUT) via an I / O interface. The parallel-to-serial conversion unit 1222 and the output delay unit 1224 are also connected to the edge waveform control module 130. Further, the input data processing channel 124 specifically includes an input delay unit 1242, an input register DFF2, a serial-to-parallel conversion unit 1244, and a buffer unit 1246 connected in sequence. The input delay unit 1242 is connected to the DUT via an I / O interface, and the buffer unit 1246 is connected to the comparison module CP. The input delay unit 1242 and the buffer unit 1246 are also connected to the edge waveform control module 130. The output delay unit 1224 / input delay unit 1242 can use dedicated resources inside the FPGA, such as IDELAY, ODELAY, CARRY, to implement signal delay, and the buffer unit 1246 can use FIFO (First Input First Output) to buffer data.

[0035] Depending on the actual amount of parallel data required for the input and output of the parallel-to-serial conversion module 120, the data conversion methods of the parallel-to-serial conversion unit 1222 and the serial-to-parallel conversion unit 1244 will also differ. For example, the parallel-to-serial conversion unit 1222 can be an 8:1 / 4:1 serial structure, and the serial-to-parallel conversion unit 1244 can be an 8:1 / 4:1 deserialization structure. In this embodiment, the waveform synthesis module FC splits the serial data into 16 parallel data channels A1-A16. It performs a bitwise OR operation on the 16 channels of data (two 8-channel data channels) and outputs 8 channels of data to the parallel-to-serial conversion unit 1222. The parallel-to-serial conversion unit 1222 adopts an 8:1 serial structure. Based on the signal sent along the waveform control module 130, it converts the 8 channels of data into one serial data channel and sends it to the output register DFF1. The output delay unit 1224, based on the signal sent along the waveform control module 130, delays the serial data in register DFF1 and outputs it to the device under test. The input delay unit 1242, based on the signal sent by the waveform control module 130, delays the serial data returned by the device under test and sends it to the input register DFF2. The serial-to-parallel conversion unit 1244, employing an 8:1 deserialization structure, converts the serial data in the input register DFF2 into a parallel output value based on the signal sent by the waveform control module 130 and sends it to the buffer unit 1246. The waveform control module 130 also controls the buffer unit 1246 to output sampled data to the comparison module CP. The comparison module CP receives the sampled data, analyzes it to determine the actual sampled value, and then compares the actual sampled value with the preset expected value to determine whether the actual sampled value is consistent with the expectation. After obtaining the comparison result, it outputs it.

[0036] It is understood that in other embodiments, the waveform synthesis module FC may also split the serial data into 8 parallel data streams, perform an OR operation on two sets of 4-stream data streams, and output 4-stream data streams to the parallel-to-serial conversion unit 1222. The parallel-to-serial conversion unit 1222 adopts a 4:1 serial structure, converting the 4-stream data streams into a single serial data stream and sending it to the output register DFF1. The serial-to-parallel conversion unit 1244 adopts a 4:1 deserialization structure, converting the serial data in the input register DFF2 into a parallel output value and sending it to the buffer unit 1246.

[0037] In one embodiment, such as Figure 2 As shown, the waveform control module 130 includes a timing setting unit 132 and a timing control unit TC. The timing control unit TC is connected to the timing setting unit 132 and the parallel-to-serial conversion unit 1222, the output delay unit 1224, the input delay unit 1242, and the buffer unit 1246 in the parallel-to-serial conversion module 120.

[0038] The timing setting unit 132 generates delay information based on the configured time information and sends it to the timing control unit TC. The timing control unit TC, based on the delay information, controls the parallel-to-serial conversion unit 1222 to perform data conversion, adjusts the delay times of the output delay unit 1224 and the input delay unit 1242, and selects sampled data from the parallel output value in the buffer unit 1244 to send to the comparison module CP. By issuing signals through the timing control unit TC, the data adjustment position of the parallel-to-serial conversion unit 1222 during serial conversion and the delay time of the output delay unit 1224 are adjusted, achieving coarse and fine adjustments on the output side, respectively. Similarly, by issuing signals through the timing control unit TC, the delay time of the input delay unit 1242 is controlled, and the reading of sampled data from the buffer unit 1244 is controlled, achieving fine and coarse adjustments on the input side, respectively.

[0039] In one embodiment, the service board further includes a phase-locked loop (PLL) module. The PLL module is connected to the waveform generation device 210, the edge waveform generation module 110, the waveform synthesis module FC, the parallel-to-serial conversion module 120, and the edge waveform control module 130. The PLL module receives the base clock from the waveform generation device 210 and outputs the operating clock to the edge waveform generation module 110, the waveform synthesis module FC, the parallel-to-serial conversion module 120, and the edge waveform control module 130. The interface module 140 is also connected to the PLL module and the waveform generation device 210, sending the configuration command (CMD) issued by the host computer (PC) to the PLL module and the waveform generation device 210. The waveform generation device 210 generates a lower frequency clock source based on the received configuration command (CMD) and outputs it as the base clock to the PLL module. The PLL module multiplies the base clock according to the received configuration command (CMD) to obtain a higher frequency clock.

[0040] Specifically, the operating clock output of the phase-locked loop (PLL) module includes a low-frequency base clock and a multiplied high-frequency clock. The PLL module includes a high-frequency clock output interface and a low-frequency clock output interface. The high-frequency clock output interface connects to the parallel-to-serial conversion unit 1222, output register DFF1, input register DFF2, serial-to-parallel conversion unit 1244, and buffer unit 1246 in the parallel-to-serial conversion module 120, outputting a high-frequency clock as the clock signal for the corresponding device. The low-frequency clock output interface connects to the edge waveform generation module 110, waveform synthesis module FC, edge waveform control module 130, and the output delay unit 1224 and input delay unit 1242 in the parallel-to-serial conversion module 120, outputting a low-frequency base clock as the clock signal for the corresponding device. The high-frequency clock is used by the parallel-to-serial conversion module 120 to output data, ensuring that all data uses the same type of edge to prevent the influence of clock duty cycle on data accuracy. In addition, other modules besides the parallel-to-serial conversion module 120 use a low-frequency base clock. By using a high-speed clock only in local areas, high data rates are guaranteed without introducing excessive power consumption that could degrade signal accuracy.

[0041] In one embodiment, such as Figure 2 As shown, a test machine is also provided, including a waveform generation device 210, a communication board 220, and the aforementioned service board. The waveform generation device 210 can specifically be an arbitrary waveform generator (DDS). The test machine may also include a host computer (PC), which communicates with the service board through the communication board 220.

[0042] To address the issues of insufficient period and edge control accuracy and frequency bottlenecks in test equipment when generating excitation and sampling chip outputs, the test equipment and its service board provided in this application have the following workflow:

[0043] Waveform generation:

[0044] 1. Generation of excitation source: By setting the relevant pattern file on the host computer PC, the host computer PC parses the file to obtain the excitation file that needs to be output.

[0045] 2. The generation of time edges is also achieved by setting relevant timing configuration data, including the data period and edge position information, which are then parsed by the host computer (PC).

[0046] 3. Data distribution: The host PC, after parsing the relevant information, transmits the data to the communication board 220 via the network port. The communication board 220 then distributes the data to the service board via the Aurora interface.

[0047] 4. Data Processing: The service board assigns data to the waveform generation module 110 and the timing setting unit 132 according to data type. The waveform generation module 110 generates relevant waveform data based on configuration information. The next-level waveform synthesis module FC then encodes and parses the waveform data output by the waveform generation module 110, splitting the serial data into 16 data streams. This low-speed parallel data is adapted to the high-frequency serial data structure of BITSLICE. Another portion of the data is processed by the timing setting unit 132, which splits the time edge information into different delay levels, including coarse and fine delay adjustments, adapting to the BITSLICE structure. The fine delay adjustment accuracy reaches 5ps.

[0048] 5. High-speed clock architecture: The host PC sends configuration commands (CMD) to an external DDS to generate a low-frequency clock source. The host PC then uses the CMD to control the phase-locked loop (PLL) module to multiply the frequency and output a high-frequency clock for the bitskipper structure to output data. This ensures that all data uses the same edge type, preventing the clock duty cycle from affecting data accuracy. Meanwhile, other modules outside the bitskipper structure use the low-frequency clock output from the PLL module. By using a high-speed clock only in localized areas, high data rates are guaranteed without introducing excessive power consumption that could degrade signal accuracy.

[0049] Waveform sampling:

[0050] 1. The data distribution and processing, as well as the clock architecture planning, are the same as steps 1, 2, 3, and 5 of the waveform generation section.

[0051] 2. Data processing: The timing information calculated in real time by the timing control unit TC is used to extract the data of the BITSLICE structure as needed to obtain relevant sampling data. The data is then compared by the comparison module CP, and the comparison results are reported to the host computer PC.

[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A service board card of a test machine, characterized by, include: The waveform generation module is connected to the waveform synthesis module, and waveform data is output to the waveform synthesis module. The waveform synthesis module is connected to the parallel-to-serial conversion module, and splits the waveform data output by the waveform generation module into parallel data and sends it to the parallel-to-serial conversion module. The parallel-to-serial conversion module connects the device under test (DUT) and the comparison module. It performs parallel-to-serial conversion and delay processing on the received parallel data, and sends the delayed serial data to the DUT. It also performs delay and serial-to-parallel conversion on the feedback data from the DUT, and outputs sampled data to the comparison module. The comparison module receives the sampled data sent by the parallel-to-serial conversion module and outputs the comparison result.

2. The service board card of claim 1, wherein, The parallel-to-serial conversion module includes: The output data processing channel connects the waveform synthesis module and the device under test, receives the parallel data output by the waveform synthesis module, and sends the delayed serial data to the device under test. The input data processing channel connects the comparison module and the device under test, receives feedback data output by the device under test, and outputs sampled data to the comparison module.

3. The service board card of claim 2, wherein, The output data processing channel includes a parallel-to-serial conversion unit, an output register, and an output delay unit connected in sequence. The parallel-to-serial conversion unit is connected to the waveform synthesis module, and the output delay unit is connected to the device under test through an I / O interface.

4. The service board card of claim 2, wherein, The input data processing channel includes an input delay unit, an input register, a serial-to-parallel conversion unit, and a buffer unit connected in sequence. The input delay unit is connected to the device under test through an I / O interface, and the buffer unit is connected to the comparison module.

5. The service board card according to any one of claims 1 to 4, characterized by Also includes: The waveform control module is connected to the parallel-to-serial conversion module, and the delay parameters of the parallel-to-serial conversion module are adjusted according to the configured time information.

6. The service board card of claim 5, wherein, The waveform control module includes a timing setting unit and a timing control unit. The timing control unit is connected to the timing setting unit and the parallel-to-serial conversion unit, output delay unit, input delay unit, and buffer unit in the parallel-to-serial conversion module.

7. The service board card of claim 5, wherein, Also includes: The phase-locked loop module connects the waveform generation device, the waveform generation module, the waveform synthesis module, the parallel-to-serial conversion module, and the waveform control module. It receives the base clock from the waveform generation device and outputs the operating clock to the waveform generation module, the waveform synthesis module, the parallel-to-serial conversion module, and the waveform control module.

8. The service board card of claim 7, wherein, The phase-locked loop module includes a high-frequency clock output interface and a low-frequency clock output interface. The high-frequency clock output interface is connected to the parallel-to-serial conversion unit, output register, input register, serial-to-parallel conversion unit, and buffer unit in the parallel-to-serial conversion module. The low-frequency clock output interface is connected to the waveform generation module, the waveform synthesis module, the waveform control module, and the output delay unit and input delay unit in the parallel-to-serial conversion module.

9. The service board card of claim 7, wherein, It also includes an interface module, which connects the waveform generation module, the waveform control module, the phase-locked loop module, the waveform generation device, and the communication board.

10. A testing machine characterized by, It includes a waveform generation device, a communication board, and a service board as described in any one of claims 1 to 9.

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