A self-oscillating comparator and method for a successive approximation analog-to-digital converter
By using a self-excited comparator structure and multi-phase clock control, the problems of device mismatch and kickback noise in SAR ADC comparators under low power conditions are solved, achieving robust voltage comparison decision and making it suitable for low voltage and small signal environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NORTHWEST UNIV
- Filing Date
- 2026-03-23
- Publication Date
- 2026-06-23
AI Technical Summary
Existing successive approximation analog-to-digital converter (SAR ADC) comparators are susceptible to device mismatch and kickback noise under low power conditions, leading to unstable decisions, especially performance degradation in low voltage and small signal environments.
A self-excited oscillation comparator structure is adopted. By constructing a dual-node cross-coupled self-excited oscillation core, the input differential voltage is converted into the difference in the number of flips of the oscillation node within a fixed time window. The digital result is output through edge detection and counting decision. Combined with multi-phase clock control and isolation mechanism, noise interference is reduced.
It improves the comparator's decision robustness in low-voltage and small-signal environments, reduces the impact of kickback noise, and achieves a flexible trade-off between speed and accuracy to adapt to different resolution requirements.
Smart Images
Figure CN122268331A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog and mixed-signal integrated circuit design, and more specifically to a self-oscillating comparator and method for successive approximation analog-to-digital converters. Background Technology
[0002] Successive approximation analog-to-digital converters (SAR ADCs) are widely used in medium sampling rate and medium-to-high resolution scenarios due to their simple structure, low power consumption, small area, and good trade-off between resolution and speed. The comparator is the core decision unit in a SAR ADC. During each successive approximation process, it needs to compare the input voltage with the reference voltage of the digital-to-analog converter (DAC). Therefore, the comparator's offset, noise, speed, and power consumption directly affect key performance indicators of the ADC, such as differential nonlinearity (DNL), integral nonlinearity (INL), signal-to-noise and distortion ratio (SNDR), and effective number of bits (ENOB).
[0003] Existing SAR ADCs commonly employ StrongARM comparators, dual-tailed dynamic comparators, or regenerative latch comparators. These comparators utilize cross-coupled positive feedback to rapidly amplify small signals, offering advantages such as zero quiescent power consumption and high speed. However, as process dimensions shrink and supply voltage decreases, several shortcomings have gradually emerged. First, input mismatch caused by device misalignment directly leads to deviations in comparison results. Second, when the regeneration node flips, it feeds back charge to the input and the capacitive digital-to-analog converter (CDAC), generating significant kickback noise. Third, when the input differential is small or the supply voltage is low, the regeneration time increases significantly. Fourth, pursuing speed often requires increasing device size or improving equivalent drive capability, resulting in increased area and dynamic power consumption.
[0004] To address the aforementioned issues, if a single regeneration flip is still used as the sole decision criterion, the comparison results will be more sensitive to instantaneous noise and random device mismatches. Therefore, it is necessary to propose a novel comparator structure that differs from the traditional single-regeneration latch decision mechanism, enabling it to achieve more robust magnitude comparisons through multiple oscillations under low power consumption conditions. Summary of the Invention
[0005] The purpose of this invention is to provide a self-oscillating comparator for successive approximation ADCs. By constructing a cross-coupled self-oscillating core with two oscillating nodes, the input differential voltage is converted into the difference in the number of flips of the two oscillating nodes within a fixed time window. The digital comparison result is then output by edge detection, counting, and decision logic to reduce random noise, mitigate input kickback interference, and improve comparison robustness under low voltage conditions.
[0006] To overcome the shortcomings of the prior art, in a first aspect, this application proposes a self-oscillating comparator for a successive approximation analog-to-digital converter, comprising: a differential input stage, a self-oscillating core, an isolation and clock control unit, an oscillation detection module, a counting and decision module, and an output interface module; the differential input stage is used to receive the input signal to be compared and a reference signal; the self-oscillating core, connected to the differential input stage, is composed of cross-coupled MOS transistor pairs forming a dual-node positive feedback loop, used to convert the input differential voltage into the difference in the number of flips of the dual nodes within a preset time window during the comparison phase; the isolation and clock control unit... The system comprises: a component, a differential input stage, and a self-excited oscillation core, used to control the orderly switching of the sampling phase, isolation phase, comparison phase, and reset phase; an oscillation detection module, connected to two oscillation nodes of the self-excited oscillation core, used to detect and output the edge flipping signals of the two oscillation nodes; a counting and decision module, connected to the oscillation detection module, used to count the number of flips of the two oscillation nodes within a preset comparison window, and output a digital comparison result based on the comparison result of the number of flips; and an output interface module, connected to the counting and decision module, used to latch the digital comparison result and output it to the SAR logic circuit.
[0007] Preferably, the self-oscillation core includes: a first oscillation node, a second oscillation node, a first NMOS transistor, a second NMOS transistor, a first PMOS load transistor, and a second PMOS load transistor; the drain of the first NMOS transistor is connected to the first oscillation node, and the source is connected to the first intermediate node of the differential input stage; the drain of the second NMOS transistor is connected to the second oscillation node, and the source is connected to the second intermediate node of the differential input stage; the drain of the first PMOS load transistor is connected to the first oscillation node, and the source is connected to the power supply voltage; the drain of the second PMOS load transistor is connected to the second oscillation node, and the source is connected to the power supply voltage; the first oscillation node and the second intermediate node are cross-coupled, and the second oscillation node and the first intermediate node are cross-coupled to form a positive feedback self-oscillation loop.
[0008] Preferably, the isolation and clock control unit includes: a sampling control unit, an isolation control unit, a comparison control unit, and a reset control unit; the sampling control unit is used to turn on the sampling switch during the valid sampling phase, so that the input signal and the reference signal are loaded to the comparator input terminal; the isolation control unit is used to disconnect the coupling path between the input signal and the internal node of the comparator during the valid isolation phase, so as to suppress kickback noise; the comparison control unit is used to turn on the tail current branch during the valid comparison phase, start the self-excited oscillation core, and limit the time length of the preset comparison window through the self-oscillation window control module; the reset control unit is used to turn off the tail current branch and turn on the pre-charge path during the valid reset phase, so as to restore the internal node of the comparator to the initial level.
[0009] Preferably, the counting decision module is specifically used for: accumulating the number of flips of the first oscillation node within the preset comparison window to obtain a first count value; accumulating the number of flips of the second oscillation node within the preset comparison window to obtain a second count value; comparing the first count value with the second count value; if the first count value is greater than the second count value, outputting a logic level indicating that the input signal is greater than the reference signal; otherwise, outputting a logic level indicating that the input signal is not greater than the reference signal.
[0010] Preferably, the comparator further includes: an adjustable comparison window control signal terminal, used to dynamically adjust the statistical duration of the preset comparison window according to the number of bits of successive approximation, the range of the input signal, or the system speed requirements.
[0011] Preferably, the comparator further includes an input isolation switch or a precharge switch, disposed at the input terminal of the differential input stage, for isolating the comparison phase and the sampling phase to reduce kickback noise to the input terminal and the CDAC.
[0012] Preferably, the differential input stage includes: a first input transistor, a second input transistor, and a tail current transistor; the gate of the first input transistor receives a positive input signal, and the gate of the second input transistor receives an inverted input signal; the sources of the first input transistor and the second input transistor are connected to the drain of the tail current transistor, the source of the tail current transistor is grounded, and its gate receives a comparison control signal from the isolation and clock control unit.
[0013] Preferably, the differential input stage includes: a first input transistor and a second input transistor; the gate of the first input transistor receives a positive input signal, and its drain is connected to the first intermediate node; the gate of the second input transistor receives an inverted input signal, and its drain is connected to the second intermediate node; the first intermediate node and the second intermediate node are precharged to the same potential during the reset phase.
[0014] Secondly, this invention application also proposes a voltage comparison method based on statistical decision-making of self-excited oscillation, comprising: in the sampling phase, loading the input signal to be compared and the reference signal onto the differential input stage; in the isolation phase, disconnecting the direct coupling path between the input signal and the internal nodes; in the comparison phase, activating the self-excited oscillation core, and detecting and statistically analyzing the self-excited oscillation within a preset time window.
[0015] The number of flips of the two oscillation nodes in the oscillation core is used to obtain the first count value and the second count value;
[0016] The first count value is compared with the second count value, and the digital comparison result is output; in the reset phase, the internal nodes of the comparator are initialized and reset.
[0017] Preferably, the step of activating the self-excited oscillation core and detecting and counting the number of flips of the two oscillation nodes in the self-excited oscillation core within a preset time window includes: when the input signal is greater than the reference signal, the flip speed of the first oscillation node is faster than that of the second oscillation node, so that the first count value is greater than the second count value; when the input signal is less than the reference signal, the flip speed of the second oscillation node is faster than that of the first oscillation node, so that the first count value is less than the second count value.
[0018] Preferably, the step of activating the self-excited oscillation core and detecting and counting the number of flips of the two oscillation nodes in the self-excited oscillation core within a preset time window includes:
[0019] When the input signal is greater than the reference signal, the first oscillation node flips faster than the second oscillation node, causing the first count value to be greater than the second count value.
[0020] When the input signal is less than the reference signal, the second oscillation node flips faster than the first oscillation node, causing the first count value to be less than the second count value.
[0021] Compared with the closest prior art, the present invention application has the following beneficial effects:
[0022] (1) By constructing a dual-node cross-coupled self-excited oscillation structure, the present invention converts the input voltage difference into the difference of the number of oscillation flips, realizes voltage comparison decision based on time domain statistics, and significantly improves the robustness of the comparator in low voltage, small signal and high noise environments;
[0023] (2) The present invention adopts a multi-phase clock control mechanism to realize the orderly switching of sampling, isolation, comparison and reset stages, effectively reducing the interference of input kickback noise in the comparison process on the sampling network and CDAC, and improving the stability and reliability of the overall system.
[0024] (3) By setting an adjustable comparison window control signal, the present invention can dynamically adjust the oscillation statistical duration according to the resolution position, input signal range or system speed requirements, and achieve a flexible balance between comparison speed and decision accuracy.
[0025] (4) The present invention can introduce isolation switches or pre-charge switches at nodes DP and DN to further reduce kickback noise during the comparison process; it can also improve the comparison accuracy by introducing an offset calibration circuit to compensate for device mismatch. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the overall structure of the present invention applied to a SAR ADC;
[0027] Figure 2 This is a schematic diagram of the core circuit structure of the dual-oscillation node self-excited oscillation comparator described in this invention;
[0028] Figure 3 This is a schematic diagram of the multi-phase clock drive and oscillation start / reset control described in this invention;
[0029] Figure 4 This is a schematic diagram of the oscillation detection, counting, and decision logic structure described in this invention;
[0030] Figure 5 This is a schematic diagram showing the timing relationship of the comparator described in this invention during the sampling, isolation, comparison, and reset phases;
[0031] Figure 6 This is a schematic diagram of the comparison process based on oscillation statistical decision-making as described in this invention. Detailed Implementation
[0032] The specific embodiments of this invention will be further described in detail below with reference to the accompanying drawings.
[0033] Example 1:
[0034] like Figure 1 As shown, this invention provides a self-oscillating comparator for a successive approximation analog-to-digital converter (SAR ADC). This comparator, as the core decision unit of the SAR ADC, compares the input voltage with the CDAC output reference voltage during each successive approximation process and sends the comparison result to the SAR logic circuit for bit-by-bit approximation control. In the successive approximation SAR ADC, Vin is the voltage input and Dout is the output data.
[0035] like Figure 2As shown, the self-excited oscillation comparator of this invention includes a differential input stage, a cross-coupled self-excited oscillation core, and a tail current control branch. The differential input stage consists of input transistors MN1 and MN2, the cross-coupled self-excited oscillation core consists of transistors MN3 and MN4 and load transistors MP1 and MP2, and the tail current is provided by the tail transistor Mtail. Mtail is the tail current transistor, VDD is the power supply voltage, VSS is the ground potential, DP is the positive terminal midpoint, and DN is the negative terminal midpoint.
[0036] Input signals Vin+ and Vin− are connected to the gates of transistors MN1 and MN2, respectively. The sources of MN1 and MN2 are connected to the drains of the tail transistor Mtail. The source of the tail transistor Mtail is grounded to VSS, and its gate receives a comparison control signal to control the on and off of the comparison phase. The drains of MN1 and MN2 are connected to intermediate nodes DP and DN, respectively. The DP and DN nodes are intermediate dynamic nodes between the input differential stage and the self-excited oscillation core.
[0037] Furthermore, transistors MN3 and MN4 are connected to nodes A and B, respectively. The drain of MN3 is connected to node A, and its source to node DP; the drain of MN4 is connected to node B, and its source to node DN. Load transistors MP1 and MP2 are connected between the power supply VDD and nodes A and B, respectively, to provide pull-up current paths for the oscillation core. Positive feedback structures are formed through cross-connections between nodes A and DN, and between node B and node DP, thus constituting a two-node cross-coupled self-excited oscillation loop.
[0038] During the reset phase, nodes A, B, DP, and DN are precharged to the same potential, typically close to the power supply voltage VDD, by external clock control, in order to eliminate the residual state from the previous comparison cycle.
[0039] During the comparison phase, the tail diode Mtail is turned on, and the differential input stage begins to operate. The voltage difference between the input signals Vin+ and Vin− is converted into a current difference through MN1 and MN2, resulting in a small voltage difference between the intermediate nodes DP and DN. When Vin+ is greater than Vin−, the conduction capability of MN1 is enhanced, and the discharge speed of the DP node is faster than that of the DN node; when Vin+ is less than Vin−, the discharge speed of the DN node is faster than that of the DP node.
[0040] Under the cross-coupling structure, a positive feedback relationship is formed between node A and node B. When there is a small voltage difference between DP and DN, this difference is amplified by MN3 and MN4 and continuously enhanced by the cross-feedback between node A and node B. Under certain conditions, the system will not immediately enter a stable latching state, but will instead form a self-excited oscillation with alternating flips between node A and node B.
[0041] Specifically, a rise in the voltage of node A will suppress the voltage of node B through the cross-coupling structure, while a change in the voltage of node B will in turn affect node A, thus forming a closed-loop positive feedback oscillation process. In this process, the input differential signal will modulate the switching speed of nodes A and B, causing a difference in the number of switching times of the two nodes per unit time.
[0042] In this invention, instead of directly using a single regeneration flip as the comparison result, the flipping behavior of node A and node B is statistically analyzed within a preset comparison time window. The level flipping edges of node A and node B are detected by an edge detection circuit, and the number of flips is accumulated by a counter to obtain count values CountA and CountB.
[0043] Subsequently, CountA and CountB are compared using a size comparator. When CountA is greater than CountB, a logic "1" is output, indicating that Vin+ is greater than Vin−; when CountA is less than or equal to CountB, a logic "0" is output, indicating that Vin+ is not greater than Vin−. The comparison result is latched in the output register and then sent to the SAR logic circuit to control the successive approximation process.
[0044] like Figure 3 As shown, the present invention also provides a multiphase clock control and signal scheduling structure for driving the self-excited oscillation comparator. The structure includes a sampling control unit, an isolation control unit, a comparison control unit, and a reset control unit, each of which is driven by corresponding clock signals ΦS, ΦI, ΦC, and ΦR.
[0045] Specifically, the sampling control unit turns on the sampling switch during the valid period of the sampling phase ΦS, so that the input signal Vin and the CDAC output reference signal are loaded to the input terminal of the comparator. At the same time, it controls the precharge / reset branch to initialize the internal nodes of the comparator, so that nodes A, nodes B and intermediate nodes DP and DN are pulled to preset levels to eliminate the residual state of the previous comparison cycle.
[0046] During the effective isolation phase ΦI, the isolation control unit disconnects the direct coupling path between the input signal and the internal nodes of the comparator, isolating the input from the subsequent oscillation nodes and thus suppressing the interference of kickback noise generated during the comparison process on the sampling network and CDAC. Simultaneously, the pre-charge path is closed during this phase to establish initial conditions for subsequent comparison stages.
[0047] During the active period of the comparison phase ΦC, the comparison control unit activates the tail current branch, turning on the tail transistor Mtail and initiating the differential input stage, simultaneously starting the self-excited oscillation core. Furthermore, this stage also includes a self-oscillation window control module to limit the length of the oscillation statistics time window. Within this time window, the cross-coupled structure drives nodes A and B to generate alternating self-excited oscillation signals, and the subsequent edge detection and counting circuit counts the number of reversals.
[0048] During the active period of the reset phase ΦR, the reset control unit closes the tail current branch and reopens the pre-charge path, restoring nodes A, B, DP, and DN to their initial levels. At the same time, the latch latches the statistical decision result of the previous comparison cycle and outputs it to the SAR logic unit to control the successive approximation process of the next bit.
[0049] like Figure 4 The diagram shows the oscillation detection, counting, and decision logic structure of this invention. The structure includes an edge detection circuit, counter A, counter B, a digital comparator, and an output register. The edge detection circuit is connected to nodes A and B respectively, detecting the level transition edge and outputting a counting pulse to the corresponding counter. Counters A and B accumulate the number of transitions of nodes A and B respectively within a comparison window. The digital comparator compares the output values of the two counters and generates a comparison result. The output register latches the comparison result during the reset phase and outputs it.
[0050] like Figure 5 The diagram illustrates the timing relationship of the comparator in the sampling, isolation, comparison, and reset stages of this invention. The diagram clearly shows the phase relationships of clock signals ΦS, ΦI, ΦC, and ΦR, as well as the voltage changes of nodes A, B, DP, and DN at each stage, illustrating the working mechanism of this invention that achieves orderly switching through multi-phase clock control.
[0051] like Figure 6 The diagram shown illustrates the comparison process of this invention based on oscillation statistical decision-making, specifically including the following steps:
[0052] Step S601: Sampling phase, load the input signal and reference signal, and reset the internal node at the same time; Step S602: Isolation phase, disconnect the coupling path between the input and the internal node; Step S603: Comparison phase, turn on the tail current, and start self-excited oscillation;
[0053] Step S604: Within a preset time window, detect and count the number of flips CountA and CountB of node A and node B; Step S605: Compare the magnitudes of CountA and CountB; Step S606: Output digital logic level based on the comparison result; Step S607: Reset phase, latch the output result and reset internal nodes.
[0054] In a further implementation, a trade-off between comparison speed and decision accuracy can be struck by adjusting the comparison time window length. For high-order comparisons, a shorter window can be used to increase speed, while for low-order comparisons, the window can be appropriately extended to enhance noise immunity. Furthermore, isolating switches can be introduced at nodes DP and DN to reduce the impact of kickback noise during the comparison process on the input and CDAC. Additionally, offset calibration circuitry can be introduced to compensate for device mismatch, further improving comparison accuracy.
[0055] In summary, this implementation method constructs a dual-node cross-coupled self-excited oscillation structure, converting the input voltage difference into a difference in the number of oscillation flips, thereby realizing a comparison decision based on time-domain statistics, which significantly improves the robustness of the comparator in low-voltage, small-signal, and high-noise environments.
[0056] Example 2:
[0057] Based on the same inventive concept, this embodiment provides a voltage comparison method based on self-excited oscillation statistical decision, applied to the comparator as described in Embodiment 1, including the following steps:
[0058] Step 1: In the sampling phase, the input signal to be compared and the reference signal are loaded into the differential input stage, and the internal nodes of the comparator are initialized and reset at the same time;
[0059] Step 2: In the isolation phase, disconnect the direct coupling path between the input signal and the internal nodes of the comparator to suppress kickback noise;
[0060] Step 3: In the comparison phase, start the self-excited oscillation core, and within the preset time window, detect and count the number of flips of the two oscillation nodes in the self-excited oscillation core to obtain the first count value and the second count value;
[0061] When the input signal is greater than the reference signal, the first oscillation node flips faster than the second oscillation node, causing the first count value to be greater than the second count value; when the input signal is less than the reference signal, the second oscillation node flips faster than the first oscillation node, causing the first count value to be less than the second count value.
[0062] Step 4: Compare the first count value with the second count value, and output the numerical comparison result;
[0063] Step 5: In the reset phase, latch the digital comparison result and output it to the SAR logic circuit, while resetting the internal nodes of the comparator.
[0064] The solution of the present invention also has the following advantages:
[0065] 1. The self-excited oscillation comparator proposed in this invention adopts the comparison mechanism of "oscillation establishment-edge counting-statistical decision", which is different from the "single regeneration-latch output" mechanism of traditional comparators. By counting the number of flips in multiple oscillation cycles, it effectively suppresses the influence of random noise and instantaneous glitches on the comparison results.
[0066] 2. This invention achieves orderly switching of the sampling, isolation, comparison and reset phases through multi-phase clock control. In the isolation phase, the coupling path between the input and the internal node is disconnected, which significantly reduces the interference of kickback noise on the front-end sampling network and CDAC.
[0067] 3. By setting an adjustable comparison window control signal, the present invention can dynamically adjust the statistical duration according to application requirements, thereby achieving a flexible balance between comparison speed and decision accuracy and adapting to successive approximation requirements of different number of digits.
[0068] 4. Under low power supply voltage and small input differential conditions, the present invention can still achieve stable decision-making through oscillation statistics, and has good low voltage operating characteristics.
[0069] Secondly, the main innovative points of this application, based on the technical solution, are summarized as follows:
[0070] 1. A novel comparator structure based on statistical decision-making for self-excited oscillation is proposed. A dual-node self-excited oscillation core is constructed at the sending end using cross-coupled positive feedback, which converts the input voltage difference into the difference in the number of oscillation node flips, thereby realizing time-domain statistical comparison.
[0071] 2. A multi-phase clock control method is proposed, which achieves orderly switching of the comparison process through timing control of four stages: sampling, isolation, comparison, and reset, effectively suppressing kickback noise;
[0072] 3. An adjustable comparison window control mechanism is proposed, which can dynamically adjust the statistical duration according to the successive approximation position, thus optimizing the trade-off between speed and accuracy.
[0073] Those skilled in the art should know that:
[0074] Traditional dynamic comparators use single-regenerative latching as the decision criterion, which is sensitive to small signals and noise, and suffers from significant kickback noise. Under deep submicron processes and low supply voltage conditions, the performance limitations of traditional comparators are even more pronounced.
[0075] The self-excited oscillation comparator proposed in this invention converts the input voltage difference into a difference in the number of oscillation flips by constructing a dual-node cross-coupled self-excited oscillation structure, thereby achieving voltage comparison decision based on time-domain statistics. This structure not only effectively reduces the influence of random noise and kickback noise, but also improves the comparator's decision robustness under low voltage and small signal conditions, and can be widely used in low-power medium-speed SAR ADCs, sensor interfaces, and mixed-signal system chips.
[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that after reading the present invention, they can still make various changes, modifications or equivalent substitutions to the specific implementation of the application, but these changes, modifications or equivalent substitutions are all within the protection scope of the claims pending approval.
Claims
1. A self-oscillating comparator for a successive approximation analog-to-digital converter, characterized in that, include: Differential input stage, self-excited oscillation core, isolation and clock control unit, oscillation detection module, counting and decision module, and output interface module; The differential input stage is used to receive the input signal to be compared and the reference signal; the self-excited oscillation core is connected to the differential input stage and is composed of cross-coupled MOS transistor pairs forming a dual-node positive feedback loop, used to convert the input differential voltage into the difference in the number of flips of the dual nodes within a preset time window during the comparison phase; the isolation and clock control unit is connected to the differential input stage and the self-excited oscillation core, used to control the orderly switching of the sampling phase, isolation phase, comparison phase and reset phase; The oscillation detection module is connected to the two oscillation nodes of the self-excited oscillation core, and is used to detect and output the edge flipping signals of the two oscillation nodes; the counting and decision module is connected to the oscillation detection module, and is used to count the number of flips of the two oscillation nodes within the preset comparison window, and output a digital comparison result based on the comparison result of the number of flips; the output interface module is connected to the counting and decision module, and is used to latch the digital comparison result and output it to the SAR logic circuit.
2. The comparator according to claim 1, characterized in that, The self-excited oscillation core includes: a first oscillation node, a second oscillation node, a first NMOS transistor, a second NMOS transistor, a first PMOS load transistor, and a second PMOS load transistor; the drain of the first NMOS transistor is connected to the first oscillation node, and the source is connected to the first intermediate node of the differential input stage; the drain of the second NMOS transistor is connected to the second oscillation node, and the source is connected to the second intermediate node of the differential input stage; the drain of the first PMOS load transistor is connected to the first oscillation node, and the source is connected to the power supply voltage; the drain of the second PMOS load transistor is connected to the second oscillation node, and the source is connected to the power supply voltage; the first oscillation node and the second intermediate node are cross-coupled, and the second oscillation node and the first intermediate node are cross-coupled to form a positive feedback self-excited oscillation loop.
3. The comparator according to claim 1, characterized in that, The isolation and clock control unit includes: a sampling control unit, an isolation control unit, a comparison control unit, and a reset control unit; the sampling control unit is used to turn on the sampling switch during the valid sampling phase, so that the input signal and the reference signal are loaded to the comparator input terminal; the isolation control unit is used to disconnect the coupling path between the input signal and the internal node of the comparator during the valid isolation phase, so as to suppress kickback noise; the comparison control unit is used to turn on the tail current branch during the valid comparison phase, start the self-excited oscillation core, and limit the time length of the preset comparison window through the self-oscillation window control module; the reset control unit is used to turn off the tail current branch and turn on the pre-charge path during the valid reset phase, so as to restore the internal node of the comparator to the initial level.
4. The comparator according to claim 1, characterized in that, The counting decision module is specifically used for: accumulating the number of flips of the first oscillation node within the preset comparison window to obtain a first count value; accumulating the number of flips of the second oscillation node within the preset comparison window to obtain a second count value; comparing the first count value with the second count value, and if the first count value is greater than the second count value, outputting a logic level indicating that the input signal is greater than the reference signal; Otherwise, the output indicates that the input signal is not greater than the logic level of the reference signal.
5. The comparator according to claim 1, characterized in that, Also includes: The adjustable comparison window control signal terminal is used to dynamically adjust the statistical duration of the preset comparison window according to the number of bits of successive approximation, the range of input signals, or the system speed requirements.
6. The comparator according to claim 1, characterized in that, It also includes an input isolation switch or precharge switch, which is set at the input of the differential input stage to achieve isolation between the comparison phase and the sampling phase, so as to reduce kickback noise to the input and CDAC.
7. The comparator according to claim 1, characterized in that, The differential input stage includes a first input transistor, a second input transistor, and a tail current transistor; the gate of the first input transistor receives a positive input signal, and the gate of the second input transistor receives an inverted input signal; the sources of the first input transistor and the second input transistor are connected to the drain of the tail current transistor, the source of the tail current transistor is grounded, and its gate receives a comparison control signal from the isolation and clock control unit.
8. The comparator according to claim 2, characterized in that, The differential input stage includes: a first input transistor and a second input transistor; the gate of the first input transistor receives a positive input signal, and its drain is connected to the first intermediate node; the gate of the second input transistor receives an inverted input signal, and its drain is connected to the second intermediate node; the first intermediate node and the second intermediate node are precharged to the same potential during the reset phase.
9. A voltage comparison method based on self-excited oscillation statistical decision, applied to the comparator as described in any one of claims 1-8, characterized in that, include: In the sampling phase, the input signal to be compared and the reference signal are loaded into the differential input stage; In the isolation phase, the direct coupling path between the input signal and the internal nodes is broken; In the comparison phase, the self-excited oscillation core is activated, and within a preset time window, the number of flips of the two oscillation nodes in the self-excited oscillation core is detected and counted to obtain the first count value and the second count value. The first count value is compared with the second count value, and the digital comparison result is output; in the reset phase, the internal nodes of the comparator are initialized and reset.
10. The method according to claim 9, characterized in that, The process of activating the self-excited oscillation core and detecting and counting the number of flips of the two oscillation nodes in the self-excited oscillation core within a preset time window includes: when the input signal is greater than the reference signal, the flip speed of the first oscillation node is faster than that of the second oscillation node, so that the first count value is greater than the second count value; when the input signal is less than the reference signal, the flip speed of the second oscillation node is faster than that of the first oscillation node, so that the first count value is less than the second count value.