Antifuse memory readout circuit, antifuse memory readout method, and antifuse memory

Abstract

The read circuit of the antifuse memory of the present invention is used for logic to read a specific antifuse cell in the antifuse memory. It includes: a pre-charged PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific antifuse cell, and a read enable signal input to its gate; the pre-charged PMOS pre-charges the bit line to a predetermined level of the internal power supply of the memory; a comparator, the level of the bit line is input to the negative input of the comparator, a reference level is input to the positive input of the comparator, the comparator compares the level of the bit line with the reference level, and outputs the comparison result from its output; a feedback circuit, which is composed of a PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific antifuse cell, and the gate of which is connected to the output of the comparator; and a latch, which receives the comparison result output from the output of the comparator, latches the comparison result, and outputs it. The feedback circuit is configured to slow down the rate of voltage drop of the bit line when the bit line of the selected specific antifuse cell is discharged due to a decrease in the resistance value of the specific antifuse cell.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to an antifuse memory readout circuit, an antifuse memory readout method, and an antifuse memory. Background Technology

[0002] Semiconductor memory devices are electronic devices used to store data and are widely used in computers, mobile phones, embedded systems, and other devices. Depending on the method and purpose of data storage, semiconductor memory chips can be divided into several types. One-time programmable (OTP) memory is a non-volatile memory technology that allows data to be permanently stored and cannot be changed after programming. This characteristic makes OTP memory ideal for applications requiring high security and data integrity.

[0003] Antifuse memory, a non-volatile memory technology, is primarily used in one-time programmable (OTP) applications. Widely used in semiconductor memories, antifuse memory stores the address of a damaged main memory cell. Its working principle involves permanently altering the resistance state of the memory cell during programming to store data. Specifically, a very high voltage is applied to the gate oxide dielectric of the antifuse cell to break it down. After breakdown, the impedance of the path decreases. The logic 1 and logic 0 are determined by detecting the impedance of the antifuse cell. In the unprogrammed state, a high impedance typically represents logic "0," while in the programmed state, a low impedance typically represents logic "1." In short, an unprogrammed antifuse cell stores "0," and a programmed antifuse cell stores "1."

[0004] Due to the non-volatility of antifuse memory, data is retained even after power loss, and once programmed, the data cannot be altered. This makes it suitable for applications requiring permanent storage. Because the data is immutable, antifuse memory is extremely useful in applications with high security requirements, and it also exhibits good stability in high-radiation environments. Therefore, antifuse memory is commonly used to store encryption keys, configuration data, and firmware, making it suitable for operation in extreme environments. Furthermore, it is used in ASICs (Application-Specific Integrated Circuits) to store configuration data and calibration parameters, in FPGAs (Field-Programmable Gate Arrays) for secure storage of configuration data, and in industrial control systems to store firmware and configuration data, ensuring rapid system recovery after power failure. Due to these characteristics, antifuse memory is extremely useful in applications requiring high security, durability, and reliability. Summary of the Invention

[0005] The technical problem to be solved by the present invention

[0006] The working principle of an antifuse memory is to apply a very high voltage to the gate oxide dielectric of the antifuse memory cell, causing it to break down. After breakdown, the impedance of the path decreases, and the stored logic "1" and logic "0" are determined by detecting the impedance of the antifuse cell. A programmed antifuse memory cell has reduced impedance and stores logic "1," while an unprogrammed antifuse memory cell has very high impedance and stores logic "0." Ideally, an unprogrammed antifuse memory cell should read 0. However, due to leakage in the programming path and the very high voltage used during programming, some non-target fuses may also be affected, causing their impedance to decrease as well. Therefore, the logic "0" stored in the cell may be incorrectly read as "1," leading to reduced read accuracy of the antifuse memory. Furthermore, due to differences in process voltage and temperature, the impedance of programmed fuses can vary greatly, sometimes also leading to reduced read accuracy of the antifuse memory.

[0007] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a readout circuit for an antifuse memory, a readout method based on the readout circuit, and an antifuse memory having the readout circuit, which can improve the readout accuracy of the antifuse memory and adjust the readout impedance margin.

[0008] Technical solutions adopted to solve technical problems

[0009] In one aspect of the present invention, a readout circuit for an antifuse memory is provided for reading logic of a specific antifuse cell in the antifuse memory. The readout circuit includes: a pre-charged PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific antifuse cell, and a read enable signal input to its gate; the pre-charged PMOS pre-charges the bit line to a predetermined level of the internal power supply of the memory; and a comparator, the level of the bit line being input to the negative input of the comparator, and a reference level being input to the positive input of the comparator; the comparator compares the level of the bit line with the specified level of the internal power supply. The system includes a reference level and outputs a comparison result from the output terminal; a feedback circuit consisting of a PMOS transistor, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific antifuse cell, and the gate of which is connected to the output terminal of the comparator; and a latch that receives the comparison result output from the output terminal of the comparator, latches the comparison result, and outputs it. The feedback circuit is configured to slow down the rate of voltage drop of the bit line when the bit line of the selected specific antifuse cell is discharged due to a decrease in the resistance value of the specific antifuse cell.

[0010] In one aspect of the present invention, a readout circuit for an antifuse memory is provided for reading logic of a specific antifuse cell in the antifuse memory. The readout circuit includes: a pre-charged PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific antifuse cell, and a read enable signal input to its gate; the pre-charged PMOS pre-charges the bit line to a predetermined level of the internal power supply of the memory; a comparator, the level of the bit line is input to the negative input of the comparator, a reference level is input to the positive input of the comparator, the comparator compares the level of the bit line with the reference level, and outputs a comparison result from its output; and a feedback circuit, the feedback circuit consisting of a main inverter... The circuit comprises a feedback PMOS, a first margin adjustment PMOS, a second margin adjustment PMOS, and a third margin adjustment PMOS; and a latch that receives the comparison result output from the output of the comparator, latches the comparison result, and outputs it. The feedback circuit is configured to slow down the rate of voltage drop of the bit line when the bit line of the selected specific antifuse cell is discharged due to a decrease in the resistance value of the specific antifuse cell, and is configured to adjust the maximum resistance value of the programmable specific antifuse cell that can be read by adjusting the number of the first margin adjustment PMOS, the second margin adjustment PMOS, and the third margin adjustment PMOS that are turned on or off.

[0011] In one aspect of the present invention, a readout method for an antifuse memory is provided. The readout circuit of the antifuse memory utilizes logic to read a specific antifuse cell from the antifuse memory. The readout method includes: pre-charging the bit line to a predetermined level of the internal power supply using a pre-charged PMOS whose source is connected to the memory's internal power supply, whose drain is connected to the bit line of the selected specific antifuse cell, and whose gate is input with a read enable signal; using a feedback circuit to slow down the rate of voltage drop of the bit line when the bit line of the selected specific antifuse cell is discharged due to a decrease in the resistance value of the specific antifuse cell; using a comparator to compare the level of the bit line input to the negative input terminal of the comparator with a reference level input to the positive input terminal of the comparator, and outputting the comparison result from the output terminal of the comparator; and using a latch to receive the comparison result output from the output terminal of the comparator, latching the comparison result, and outputting it.

[0012] In one aspect of the present invention, an antifuse memory is provided, comprising: a plurality of antifuse subarrays, each of the plurality of antifuse subarrays being composed of a plurality of antifuse cells; a subarray selection unit for selecting an antifuse subarray; a bit line selection unit for selecting a bit line of a specific antifuse cell in the antifuse subarray; and a readout circuit for the aforementioned antifuse memory for reading logic of the specific antifuse cell in the antifuse memory.

[0013] The effects of the invention

[0014] The readout circuit of the antifuse memory, the readout method based on the readout circuit, and the antifuse memory equipped with the readout circuit disclosed in this invention can improve the readout accuracy of the antifuse memory and adjust the readout impedance margin. Attached Figure Description

[0015] This disclosure can be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a schematic diagram showing the structure of an antifuse memory.

[0017] Figure 2 This is a diagram showing the specific structure of the read circuit of the antifuse memory.

[0018] Figure 3 This is a diagram showing the specific structure of the readout circuit of the antifuse memory according to Embodiment 1 of the present invention.

[0019] Figure 4 This is a circuit diagram of the feedback circuit involved in Embodiment 2 of the present invention.

[0020] Figure 5 This is the readout timing diagram of the antifuse unit when using existing readout circuits for reading.

[0021] Figure 6 The left figure shows the timing diagram when reading is performed after the resistance of the antifuse unit decreases, and the right figure shows the timing diagram when reading is performed after the resistance of the antifuse unit decreases in this invention.

[0022] Figure 7 This is a readout resistance margin adjustment table for the antifuse unit based on the feedback circuit involved in Embodiment 2 of the present invention.

[0023] Labeling Explanation: 100 Antifuse Memory, 101a, 101n Antifuse Subarrays, FASel Subarray Select Unit, BLSW Bit Line Select Unit, WL0, WL1, WLx Word Lines, BL0, BLn, DBL0 Bit Lines, 102, 102A Readout Circuits, A Antifuse Unit, 1021 Precharge PMOS, 1022 Comparator, 1023 Latch, 1024, 1024A Feedback Circuits, PM Main Feedback PMOS, P0, P1, P2 Margin Adjustment PMOS. Detailed Implementation

[0024] The following describes specific embodiments of this disclosure. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. It should be understood that, in the actual implementation of any embodiment, just as in any engineering or design project, various specific decisions are often made to achieve the developer's specific goals and to meet system-related or business-related constraints, and this can change from one embodiment to another. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this disclosure, changes in design, manufacturing, or production based on the technical content disclosed in this disclosure are merely conventional technical means and should not be construed as insufficient content of this disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in the claims and description shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this patent application description and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0026] Unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined to form new technical solutions. Similarly, unless otherwise specified, all technical features and preferred features mentioned herein can be combined to form new technical solutions.

[0027] Hereinafter, with reference to the accompanying drawings, a readout circuit of an antifuse memory according to an embodiment of the present invention and an antifuse memory having the readout circuit will be described in detail.

[0028] Figure 1 This is a schematic diagram showing the structure of the antifuse memory 100.

[0029] like Figure 1 As shown, the antifuse memory 100 includes multiple antifuse subarrays 101a to 101n, a subarray selection unit FASel, a bit line selection unit BLSW, and a readout circuit 102, wherein n is a natural number greater than or equal to 1.

[0030] Each antifuse subarray 101a to 101n is composed of multiple antifuse cells. An antifuse cell is the basic building block of the antifuse memory, used to store one bit of binary information. Each antifuse cell represents the stored data through its physical state (high impedance or low impedance). Each antifuse subarray includes x×n antifuse cells (x and n are natural numbers greater than or equal to 1). Their rows form word lines WL0 to WLx, and their columns form bit lines BL0 to BLn. Each subarray 101a to 101n can be selected using the subarray selection unit FASel, and specific antifuse cells can be selected based on word lines WL0 to WLx and bit lines BL0 to BLn.

[0031] The readout circuit 102 is used to read the state of the antifuse cell. By reading "0" or "1", it determines whether the antifuse cell has been programmed. Typically, the readout circuit 102 can read antifuse arrays of 16 bits or more, thereby achieving efficient confirmation of the antifuse cell state. However, for ease of understanding, it is assumed here that only the state of one antifuse cell is read.

[0032] Figure 1 In the diagram, the solid line on the left represents the write path, or programming path. This is achieved by applying a very high voltage to the selected antifuse cell to burn it out. During programming, vbi_sw is a voltage much higher than the internal normal voltages VPP and VBB (neither shown in the diagram). The dashed line on the right represents the read path. The logic value stored inside the antifuse cell can be read through this path. During the read process, vbi_sw is the internal normal voltages VPP and VBB (neither shown in the diagram).

[0033] Figure 2 This is a diagram showing the specific structure of the read circuit 102 of the antifuse memory. Here, as an example, the read circuit 102 is used to read the antifuse cell A (i.e., bit line BL0, word line WL0) of the bit line BL0 and word line WL0. Figure 2 The state of the leftmost antifuse unit A).

[0034] like Figure 2 As shown, the readout circuit 102 is a general antifuse readout circuit, which is connected to the output of the bit line select unit BLSW of the antifuse memory 100, and includes a precharged PMOS 1021, a comparator 1022 and a latch 1023.

[0035] Precharged PMOS is commonly used in dynamic logic circuits, especially in dynamic random access memory (DRAM) and dynamic logic circuits (such as dynamic CMOS circuits). The main function of the precharge circuit is to precharge the node to a high level so that the corresponding logic operation can be performed during the evaluation phase.

[0036] In this example, the source of the precharge PMOS 1021 is connected to the internal memory power supply vti, the drain is connected to the selected bit line DBL0, and the read enable signal RdEn is input to the gate of the precharge PMOS 1021. The voltage of this power supply vti is the internal memory voltage and is set to a specified level.

[0037] Comparator 1022 is an electronic comparator used to compare the magnitudes of two voltage (or current) signals and output the comparison result. Comparator 1022 has two input terminals: a positive input (+) and a negative input (-). The voltage of bit line DBL0 is input to the "-" terminal, and the reference voltage VREF is input to the "+" terminal. Comparator 1022 compares the output voltage of bit line DBL0 with the reference voltage VREF and outputs the comparison result. Specifically, it outputs a low level when the voltage (level) of bit line DBL0 is greater than the voltage (level) of VREF, and outputs a high level when the voltage (level) of bit line DBL0 is less than the voltage (level) of VREF.

[0038] A latch is a basic storage element used to store one bit of binary information. It is a bistable circuit, meaning it has two stable states and can maintain its state until the input signal changes. Latches are commonly used in digital circuits as basic storage units. In this example, latch 1023 is connected to the output of comparator 1022, receiving and latching its output, ultimately outputting DLAT, the logic of antifuse unit A. The specific reading process of antifuse unit A will be explained below.

[0039] First, the reading process when the antifuse unit A is in an unprogrammed state will be explained.

[0040] During the read process, the precharge (PRE) stage is entered first. The read word line RWL0, the bit line select signal BLSW0, and the subarray select signal FA0 are enabled. The read enable signal RdEn is kept at a low potential. The bit lines DBL0 and BL0 are precharged to vti (the internal voltage of the memory, i.e., the level specified above).

[0041] Next, the sensing phase begins. RdEn goes high, the pre-charge circuit is turned off, and the latch is enabled. Since the selected antifuse unit A is in an unprogrammed state, its impedance is relatively high (for ease of understanding, it can be considered a capacitor). Therefore, it cannot discharge through antifuse unit A to bit lines DBL0 and BL0. Without internal leakage, the potential of bit lines DBL0 and BL0 is approximately equal to the voltage vti (a specified level). That is, the voltage input to the negative input (-) of comparator 1022 is vti. Additionally, the voltage VREF is the reference for comparison and is generally set to a fixed value; here, it is set to vti / 2. In other words, the voltage input to the positive input (+) of comparator 1022 is VREF = vti / 2. Since the voltage of bit line DBL0 (i.e., vti) > VREF (vti / 2), comparator 1022 outputs a low voltage, i.e., output logic "0". This output is input to input D of latch 1023, and the reading process ends.

[0042] Finally, during the local latching phase, the latch output DLAT will output logic "0".

[0043] Next, to make the explanation clearer, we will combine the above explanation with reference to... Figure 5 The reading process for antifuse unit A when it is in a programmed state is explained.

[0044] Figure 5 This is the readout timing diagram of the antifuse unit A when using the existing readout circuit 102 for reading.

[0045] During the read process, the precharge (PRE) stage is entered first. The read word line RWL0, the bit line select signal BLSW0, and the subarray select signal FA0 are enabled, the read enable signal RdEn is kept at a low potential, and the bit lines DBL0 and BL0 are precharged to vti (internal memory voltage).

[0046] Next, the sensing phase begins. RdEn goes high, the pre-charge circuit is turned off, and the latch is enabled. Since the selected antifuse unit A is in a programmed state, its impedance is low (for ease of understanding, it can be considered a resistor here). Figure 5(The resistance Rfuse is 500Ω), so at this time the antifuse unit A can discharge the bit lines DBL0 and BL0.

[0047] like Figure 5 As shown, RdEn is the read enable signal, UDTEN is the internal signal, DBL and BL represent the voltages of bit lines DBL0 and BL0 respectively (since the antifuse unit A for reading bit line BL0 is selected, DBL and BL are actually the same and change synchronously), VREF represents the reference voltage, and DLAT represents the output of latch 1023.

[0048] Since antifuse unit A has been programmed, its resistance is relatively small (e.g., Figure 5 As shown in the example (500Ω), the antifuse unit A can discharge the bit lines DBL0 and BL0, thus causing the voltages on bit lines DBL0 and BL0 to drop rapidly. Figure 5 As shown, during the sensing phase, the potentials of bit lines DBL0 and BL0 rapidly drop below VREF (=vti / 2).

[0049] Similar to the case where the antifuse unit is not programmed, the voltages of bit lines DBL0 and BL0 are input to the negative input (-) of comparator 1022, and the reference voltage VREF (=vti / 2) is input to the positive input (+) of comparator 1022. Since the voltage of bit line DBL0 is less than VREF (=vti / 2), comparator 1022 outputs a high voltage, i.e., outputs logic "1", which is input to input D of latch 1023.

[0050] Finally, during the local latching phase, the latch output DLAT will output a logic "1", and the reading process will end.

[0051] As mentioned above, antifuse memory arrays are generally used in semiconductor memories to store the addresses of damaged memory cells. As the capacity of semiconductor memories increases, the number of required antifuse (memory) cells also increases, meaning the capacity of antifuse memories is becoming increasingly larger. To save area, more antifuse cells share more common nodes. When applying high voltage to some antifuse cells for programming, it inevitably affects some nearby non-target antifuse cells, causing their impedance (resistance) to decrease. At this time, when reading these antifuse cells, the voltage on their bit lines will also decrease. On the other hand, although the programming path is closed during the reading process, the transistors (MOSFETs, IGBTs, etc.) used in programming are usually high-power, and their leakage current will also reduce the voltage on the bit lines.

[0052] Furthermore, due to the influence of process voltage and temperature, the resistance values ​​of different antifuse units will vary after they are programmed, and the range can be quite large. Figure 5 The antifuse unit shown is in a relatively ideal state with a resistance value of 500Ω after programming, indicating that the programming result is good. At this time, the bit line discharges quickly and is less likely to cause misreading problems.

[0053] Therefore, as mentioned above, when a high voltage is applied to some antifuse cells for programming, it may affect nearby non-target antifuse cells and cause their impedance (resistance) to decrease, potentially leading to misreading problems.

[0054] Figure 6 The left figure shows the timing diagram when reading is performed after the resistance of antifuse unit A decreases, and the right figure shows the timing diagram when reading is performed after the resistance of antifuse unit A decreases in this invention.

[0055] like Figure 6 As shown, suppose the resistance of antifuse unit A is reduced due to the influence of high voltage, for example, to 1000KΩ (=1MΩ). At this time, antifuse unit A has not actually been programmed (in this case, it is equivalent to antifuse unit A being misprogrammed or burned out), so it should be read as "not programmed", that is, logic "0".

[0056] However, as Figure 6 As shown in the left figure, when reading using the existing readout circuit 102, the bit lines DBL0 and BL0 can be discharged through the antifuse unit A due to the reduced resistance. Although the voltage drop rate of bit lines DBL0 and BL0 is relatively slow, during the sensing phase, the voltage of bit line DBL0 still drops to a level lower than the reference voltage VREF (=vti / 2). Therefore, comparator 1022 outputs a high voltage, which is logic "1", causing the read result to be "programmed", i.e., logic "1", which is the opposite of the original logic, i.e., a false read occurs.

[0057] In embodiments of the present invention, a method for solving the above-mentioned problems is disclosed.

[0058] (Implementation Method 1)

[0059] Figure 3 This is a diagram showing the specific structure of the readout circuit 102A of the antifuse memory according to Embodiment 1 of the present invention.

[0060] like Figure 3As shown, the readout circuit 102A involved in Embodiment 1 of the present invention is connected to the output of the bit line selection unit BLSW of the antifuse memory 100, and includes a precharge PMOS 1021, a feedback circuit 1024, a comparator 1022 and a latch 1023.

[0061] The structures of the precharge PMOS 1021, comparator 1022 and latch 1023 are the same as those in the readout circuit 102. Therefore, the following description focuses on the feedback circuit 1024 to illustrate Embodiment 1 of the present invention.

[0062] In embodiment 1, the feedback circuit 1024 is composed of a PMOS transistor. The source of the PMOS transistor is connected to the internal power supply vti (with a predetermined input level vti), the drain is connected to the selected bit line DBL0, and the gate of the PMOS transistor is connected to the output of comparator 1022, thereby feeding back the voltage of the internal power supply vti (i.e., the predetermined input level). The feedback circuit 1024 is configured to slow down the rate of voltage drop of the selected bit line DBL0 when the selected bit line DBL0 is discharged due to the decrease in the resistance value of the antifuse unit A.

[0063] Below, refer to Figure 6 To illustrate the effect of the readout circuit 102A involved in Embodiment 1 of the present invention. Figure 6 The right figure in the middle is a timing diagram showing the reading when the resistance of the antifuse unit A decreases in this invention.

[0064] like Figure 6 As shown, suppose the resistance of antifuse unit A is reduced due to the influence of high voltage, for example, to 1000KΩ (=1MΩ). At this time, antifuse unit A has not been programmed (i.e., it has been misprogrammed or burned out), so it should be read as "not programmed", that is, logic "0".

[0065] like Figure 6As shown in the right figure, when reading using the readout circuit 102A according to Embodiment 1 of the present invention, the antifuse unit A is affected by the high voltage during programming of a nearby antifuse unit, causing its resistance to decrease. At this time, the bit lines DBL0 and BL0 can be discharged through the antifuse unit A. Since the feedback circuit 104 is provided, the power supply voltage vti (internal voltage of the memory) can be fed back through the feedback circuit 104. Therefore, the voltage drop rate of the bit lines DBL0 and BL0 is slowed down. During the sensing phase, the voltage of the bit line DBL0 (DBL) does not drop lower than the reference voltage VREF (=vti / 2). Therefore, DBL>VREF, and the comparator 1022 outputs a low voltage, that is, outputs logic "0". The result of reading at this time is "not programmed", that is, logic "0", which is consistent with the actual situation. Thus, the false reading of the unprogrammed antifuse unit A is avoided.

[0066] According to this embodiment 1, the read accuracy of the antifuse memory can be improved, and the situation where an unprogrammed antifuse unit is mistakenly read as programmed can be avoided.

[0067] (Implementation Method Two)

[0068] In Embodiment 1 described above, even if the resistance of antifuse unit A is reduced to 1000KΩ (=1MΩ), misreading of unprogrammed antifuse units can be avoided. In other words, in Embodiment 1, the maximum resistance value Rmax of the programmable antifuse unit that can be read is 1000KΩ (=1MΩ). To achieve this resistance value, the structure of the feedback circuit 1024 can be changed; specifically, the channel length of the PMOS constituting the feedback circuit 1024 can be changed.

[0069] However, due to differences in process voltage and temperature, the resistances of the programmed antifuse units are not uniform, and their resistance values ​​are distributed within a range (Rmin to Rmax). If only a single PMOS is used as the feedback circuit 1024, it can only handle one type of situation. When dealing with antifuse memories of different specifications, the PMOS constituting the feedback circuit 1024 needs to be manually replaced each time, resulting in poor applicability and an inability to handle multiple situations. In Embodiment 2 of the present invention, a method for solving this problem is disclosed.

[0070] To more flexibly cover the aforementioned resistance range and thus improve the accuracy and margin of reading programmed antifuse wires, use Figure 4 To implement the circuit Figure 3 The feedback circuit 1024 in the middle.

[0071] Figure 4 This is a circuit diagram of the feedback circuit 1024A involved in Embodiment 2 of the present invention.

[0072] like Figure 4 As shown, the feedback circuit 1024A consists of a main feedback PMOS PM, a margin adjustment PMOS P0 (first margin adjustment PMOS), a margin adjustment PMOS P1 (second margin adjustment PMOS), and a margin adjustment PMOS P2 (third margin adjustment PMOS).

[0073] In this circuit, the source of the main feedback PMOS PM is connected to the power supply voltage vti (internal memory voltage), the drain is connected to the selected bit line DBL0, and the gate is connected to the output of comparator 1022. The margin adjustment PMOS P0, margin adjustment PMOS P1, and margin adjustment PMOS P2 are PMOS transistors with different specifications (e.g., different channel lengths). Their sources are connected to the internal memory power supply vti (with a specified input level vti), their drains are connected to the selected bit line DBL0, and their gates are connected to a control circuit (not shown). The feedback circuit 1024A is configured to slow down the rate of voltage drop in the selected bit line DBL0 when the resistance of the antifuse cell A decreases, and is configured to adjust the maximum readable resistance value Rmax of the programmed antifuse cell A by adjusting the number of on / off states of the margin adjustment PMOS P0, margin adjustment PMOS P1, and margin adjustment PMOS P2.

[0074] Figure 7 This is a readout resistance margin adjustment table for the antifuse unit based on the feedback circuit 1024A involved in Embodiment 2 of the present invention.

[0075] like Figure 7 As shown, four different margin adjustment scenarios are illustrated. ST_RDM<1:0> represents the various read margin scenarios, specifically including 'b00', 'b01', 'b02', and 'b03. PSel<2:0> represents the setting parameters of each margin adjustment PMOS when implementing various margin adjustments. The read margin represents the maximum resistance value Rmax of the programmed antifuse cell that can be read.

[0076] In case 'b00, the setting parameters of each margin adjustment PMOS are set to 'b011, at which time the maximum resistance value Rmax of the programmed antifuse unit that can be read is 380KΩ (this setting is the default value).

[0077] In case 'b01, the setting parameters of each margin adjustment PMOS are set to 'b101, at which time the maximum resistance value Rmax of the programmed antifuse unit that can be read is 450KΩ.

[0078] In case 'b10, the setting parameters of each margin adjustment PMOS are set to 'b001, and the maximum resistance value Rmax of the programmed antifuse unit that can be read is 330KΩ.

[0079] In case 'b11, the setting parameters of each margin adjustment PMOS are set to 'b000, and the maximum resistance value Rmax of the programmed antifuse unit that can be read is 250KΩ.

[0080] The feedback circuit 1024A involved in Embodiment 2 of the present invention, similar to Embodiment 1 above, can improve the read accuracy of the antifuse memory, avoid the situation where an unprogrammed antifuse unit is mistakenly read as programmed, and also adjust the read impedance (resistance value) margin of the antifuse unit.

[0081] The adjustment of each margin adjustment PMOS can be performed automatically by the program. Therefore, when dealing with antifuse memories of different specifications, the feedback circuit 1024A can be automatically set according to the maximum resistance value Rmax of the programmed antifuse cell that can be read, which has good applicability and can cope with various situations. According to the readout circuit of the present invention, the accuracy of reading logic "1" and logic "0" is improved, and the readout resistance margin of the antifuse cell can be adjusted. According to the resistance distribution diagram of the programmed antifuse, the margin of reading logic "1" and logic "0" can be more balanced.

[0082] Furthermore, this invention proposes a readout method for an antifuse memory, utilizing the readout circuit of the antifuse memory described in Embodiment 1 or 2 of this invention to read the logic of a specific antifuse cell in the antifuse memory. The readout method includes: using a precharged PMOS whose source is connected to the internal power supply of the memory, whose drain is connected to the bit line of the selected specific antifuse cell, and whose gate is input with a read enable signal, to precharge the bit line to a predetermined level of the internal power supply of the memory; using a feedback circuit to slow down the voltage drop rate of the bit line when the bit line of the selected specific antifuse cell is discharged due to the decrease in the resistance value of the specific antifuse cell; using a comparator to compare the level of the bit line input to the negative input terminal of the comparator with the reference level input to the positive input terminal of the comparator, and outputting the comparison result from the output terminal of the comparator; using a latch to receive the comparison result output from the output terminal of the comparator, latching the comparison result and outputting it.

[0083] Furthermore, the present invention proposes an antifuse memory, comprising: a plurality of antifuse subarrays, each of which is composed of a plurality of antifuse cells; a subarray selection unit for selecting an antifuse subarray; a bit line selection unit for selecting a bit line of a specific antifuse cell in the antifuse subarray; and a readout circuit for the antifuse memory described in embodiment 1 or 2 of the present invention, the readout circuit being used to read the logic of a specific antifuse cell in the antifuse memory.

[0084] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular conditions or materials to the teachings of the various embodiments of the invention without departing from the scope of the invention. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of the invention, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A readout circuit of an antifuse memory for reading out logic of a specific antifuse cell in an antifuse memory, the readout circuit comprising: a precharge PMOS having a source connected to an internal power supply of the memory, a drain connected to a bit line of the specific antifuse cell selected, and a gate inputted with a read enable signal, the precharge PMOS precharging the bit line to a prescribed level of the internal power supply of the memory; a comparator having a negative input inputted with a level of the bit line and a positive input inputted with a reference level, the comparator comparing the level of the bit line with the reference level and outputting a comparison result from an output; a feedback circuit composed of a PMOS having a source connected to the internal power supply of the memory, a drain connected to the bit line of the specific antifuse cell selected, and a gate connected to the output of the comparator; and a latch receiving the comparison result outputted from the output of the comparator, latching the comparison result, and outputting the comparison result, the feedback circuit configured to slow down a voltage drop speed of the bit line when the bit line of the specific antifuse cell selected is discharged due to a decrease in a resistance value of the specific antifuse cell.

2. The readout circuit of an antifuse memory according to claim 1, wherein the reference level is set to one-half of the prescribed level of the internal power supply of the memory, and a specific antifuse cell is selected based on a subarray, a bit line, and a word line of an antifuse cell in the antifuse memory.

3. A readout circuit of an antifuse memory for reading out logic of a specific antifuse cell in an antifuse memory, the readout circuit comprising: a precharge PMOS having a source connected to an internal power supply of the memory, a drain connected to a bit line of the specific antifuse cell selected, and a gate inputted with a read enable signal, the precharge PMOS precharging the bit line to a prescribed level of the internal power supply of the memory; a comparator having a negative input inputted with a level of the bit line and a positive input inputted with a reference level, the comparator comparing the level of the bit line with the reference level and outputting a comparison result from an output; a feedback circuit composed of a circuit of a main feedback PMOS, a first margin adjustment PMOS, a second margin adjustment PMOS, and a third margin adjustment PMOS; and a latch receiving the comparison result outputted from the output of the comparator, latching the comparison result, and outputting the comparison result. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The feedback circuit is configured to slow down the voltage drop speed of the bit line when discharging the selected bit line of the specific antifuse cell due to the decrease of the resistance value of the specific antifuse cell, and is configured to adjust the maximum resistance value of the programmed specific antifuse cell that can be read out by adjusting the number of on / off of the first margin adjustment PMOS, the second margin adjustment PMOS and the third margin adjustment PMOS.

4. The readout circuit of the antifuse memory as claimed in claim 3, wherein: the source of the main feedback PMOS is connected to the internal power supply of the memory, the drain is connected to the bit line of the selected specific antifuse cell, and the gate is connected to the output of the comparator, the sources of the first, second and third margin adjustment PMOS are connected to the internal power supply of the memory, the drains are connected to the bit line of the selected specific antifuse cell, and the gates are connected to a control circuit, the number of on / off of the first, second and third margin adjustment PMOS is adjusted by the control circuit.

5. The readout circuit of the antifuse memory as claimed in claim 4, wherein: the first, second and third margin adjustment PMOS have different channel lengths.

6. The readout circuit of the antifuse memory as claimed in claim 4, wherein: the adjustment of the first, second and third margin adjustment PMOS is automatically performed by the control circuit through programming.

7. The readout circuit of the antifuse memory as claimed in claim 3, wherein: the feedback circuit adjusts the maximum resistance value of the programmed specific antifuse cell that can be read out to 250KΩ, 330KΩ, 450KΩ or 380KΩ.

8. The readout circuit of the antifuse memory as claimed in claim 3, wherein: the reference level is set to half of the specified level of the internal power supply of the memory, a specific antifuse cell is selected based on a subarray, a bit line and a word line of the antifuse cell in the antifuse memory.

9. A readout method of an antifuse memory, which reads out the logic of a specific antifuse cell in the antifuse memory by using the readout circuit of the antifuse memory as claimed in any one of claims 1 to 8, the readout method comprising: precharging the bit line of the selected specific antifuse cell to a specified level of the internal power supply of the memory by using a precharge PMOS whose source is connected to the internal power supply of the memory, whose drain is connected to the bit line of the selected specific antifuse cell, and whose gate is input with a read enable signal; slowing down the voltage drop speed of the bit line when discharging the selected bit line of the specific antifuse cell due to the decrease of the resistance value of the specific antifuse cell by using a feedback circuit. comparing, with a comparator, a level of the bit line input to a negative input of the comparator with a reference level input to a positive input of the comparator, and outputting a comparison result from an output of the comparator; and latching, with a latch, the comparison result output from the output of the comparator, latching the comparison result, and outputting.

10. An antifuse memory, comprising: comprising: a plurality of antifuse sub-arrays, each of the plurality of antifuse sub-arrays being composed of a plurality of antifuse cells; a sub-array selection unit for selecting an antifuse sub-array; a bit line selection unit for selecting a bit line of a specific antifuse cell in the antifuse sub-array; and the readout circuit of any one of claims 1 to 8 for reading out a logic of the specific antifuse cell in the antifuse memory.

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