Chip operating voltage adjustment method, system and electronic device

Abstract

The application discloses a chip working voltage adjusting method and system and electronic equipment. The method comprises the following steps: in response to receiving a working voltage adjusting instruction of a chip, collecting a plurality of detection values of the chip, wherein different detection values are obtained by detecting the chip through different types of sensors; predicting the plurality of detection values by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used for describing the corresponding minimum working voltage of the chip under different working frequencies, and the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips in different working frequencies; and adjusting the current working voltage of the chip based on the frequency-voltage mapping relationship and a target working frequency of the chip. The application solves the technical problems of low chip working voltage adjusting efficiency and high chip power consumption in the related art.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processors, in particular to a chip working voltage adjustment method and system, and an electronic device chip working voltage adjustment method and system. BACKGROUND

[0002] With the development of semiconductor process technology and the continuous improvement of system design complexity, power consumption is increasingly important in integrated circuit design. High power consumption brings many serious challenges, such as increasing the operating temperature of the chip, reducing the reliability of the chip, and increasing the cost of the chip.

[0003] Due to the differences in the manufacturing and working process of the chip, the performance of the same design chip in different production batches and different working environments will be different, so it is difficult to detect the specific relationship between the chip performance and various influencing factors, which leads to the difficulty in effectively adjusting the working voltage of the chip, and thus the high power consumption of the chip.

[0004] In view of the above problems, no effective solution has been proposed so far. SUMMARY

[0005] The embodiments of the present application provide a chip working voltage adjustment method and system, and an electronic device chip working voltage adjustment method and system, to at least solve the technical problem of low chip working voltage adjustment efficiency in related technologies and high chip power consumption in related technologies.

[0006] According to an aspect of an embodiment of the present application, a chip working voltage adjustment method is provided, including: in response to receiving a working voltage adjustment instruction of a chip, collecting a plurality of detection values of the chip, wherein different detection values are obtained by detecting the chip through different types of sensors; predicting the plurality of detection values by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the corresponding minimum working voltage of the chip at different working frequencies, and the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages corresponding to sample chips in different working frequencies; and adjusting the current working voltage of the chip based on the frequency-voltage mapping relationship and a target working frequency of the chip, wherein the target working frequency is the working frequency to be reached by the chip.

[0007] According to an aspect of an embodiment of the present application, a chip working voltage adjustment system is provided, comprising: a plurality of sensors connected to a chip, configured to detect the chip to obtain a plurality of detection values; and a voltage adjustment device connected to the plurality of sensors, configured to, after receiving a working voltage adjustment instruction of the chip, collect the plurality of detection values, and use a voltage model to predict the plurality of detection values to obtain a frequency-voltage mapping relationship of the chip, and based on the frequency-voltage mapping relationship and a target working frequency of the chip, a current working voltage of the chip, wherein the frequency-voltage mapping relationship is used to describe a lowest working voltage of the chip corresponding to different working frequencies, the voltage model is trained according to a plurality of sample detection values and sample lowest working voltages of sample chips in different working frequencies, and the target working frequency is a working frequency to be reached by the chip.

[0008] According to another aspect of an embodiment of the present application, an electronic device is also provided, comprising: a memory storing an executable program; and a processor configured to run the program, wherein the program, when running, performs the method in each embodiment of the present application.

[0009] According to another aspect of an embodiment of the present application, a computer readable storage medium is also provided, comprising a stored executable program, wherein the executable program, when running, controls a device where the computer readable storage medium is located to perform the method in each embodiment of the present application.

[0010] According to another aspect of an embodiment of the present application, a computer program product is also provided, comprising a computer program, which, when executed by a processor, implements the method in each embodiment of the present application.

[0011] According to another aspect of an embodiment of the present application, a computer program product is also provided, comprising a non-volatile computer readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the method in each embodiment of the present application.

[0012] According to another aspect of an embodiment of the present application, a computer program is also provided, which, when executed by a processor, implements the method in each embodiment of the present application.

[0013] In the embodiment of the present application, in response to receiving the working voltage adjustment instruction of the chip, a plurality of detection values of the chip are collected, wherein different detection values are used to detect the chip by different types of sensors; the plurality of detection values are predicted by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the corresponding minimum working voltage of the chip at different working frequencies, and the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips in different working frequencies; and the current working voltage of the chip is adjusted based on the frequency-voltage mapping relationship and the target working frequency of the chip, wherein the target working frequency is the working frequency to be reached by the chip, thereby achieving the purpose of improving the working voltage adjustment efficiency of the chip. It is easy to note that, in the present application, the voltage model is trained in advance according to the plurality of sample detection values and sample minimum working voltages of the sample chips in different working frequencies, so that after the plurality of detection values of the chip are collected, the voltage model is used to quickly calculate the mapping relationship of the frequency-voltage, and based on the frequency-voltage mapping relationship and the target working frequency of the chip, the current working voltage of the chip is automatically adjusted to ensure that the chip works in the minimum power consumption state at the target working frequency, thereby improving the working voltage adjustment efficiency of the chip, so as to effectively reduce the power consumption of the chip, and further solve the technical problem of low working voltage adjustment efficiency of the chip in the related art.

[0014] It is easy to note that the above general description and the following detailed description are only for illustrating and explaining the present application, and do not constitute a limitation on the present application. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings described herein are used to provide further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and the description thereof are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a hardware structure block diagram of a RISC-V system for implementing a chip working voltage adjustment method according to an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application;

[0018] Figure 3 is a flowchart of a chip working voltage adjustment method according to the present application;

[0019] Figure 4 is a structure schematic diagram of an adaptive voltage adjustment flow according to an embodiment of the present application;

[0020] Figure 5 is a schematic diagram of a chip working voltage adjustment device according to an embodiment of the present application;

[0021] Figure 6 is a schematic diagram of a chip operating voltage adjustment system according to an embodiment of the application. DETAILED DESCRIPTION

[0022] In order to make the personnel in the art better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] First, some of the nouns or terms that appear in the description of the embodiments of the present application are applicable to the following explanations:

[0025] Adaptive Voltage Scaling (AVS) is a chip operation management method that can automatically adjust the supply voltage of the chip according to the current load and operating conditions of the chip. The purpose is to meet the performance requirements while minimizing power consumption.

[0026] Dynamic Voltage and Frequency Scaling (DVFS) is an energy-efficient management method that allows the system to dynamically adjust the frequency and voltage of the processor (CPU) at runtime in response to different workloads. By reducing voltage and frequency, DVFS can significantly reduce the power consumption of the chip, while when high performance is needed, the voltage and frequency can be increased to improve the computing speed. AVS is a component of DVFS, which is responsible for voltage adjustment.

[0027] Process, Voltage, Temperature, Aging (PVTA) are the main environmental and manufacturing factors that affect the performance and power consumption of chips. Process refers to the technology node in the chip manufacturing process. Chips at different technology nodes may have different performance and power consumption. Voltage refers to the power supply voltage of the chip, which directly affects the power consumption and performance of the chip. Temperature refers to the temperature of the chip when it is running. Temperature changes can significantly affect the power consumption and performance of the chip. Aging refers to the gradual aging of the chip during use, which leads to performance degradation and increased power consumption. Aging is determined by material properties and operating conditions.

[0028] Machine learning model (ML-Model) refers to a machine learning model used to process and analyze data. The training of the machine learning model is usually based on a large amount of historical data or test data.

[0029] Automatic Test Equipment (ATE) is an automated system used to test integrated circuits (ICs). It can include hardware and software components to detect the functionality, performance, and reliability of chips. ATE is very important in the chip manufacturing process, as it can help identify and reject defective chips to ensure product quality. In this technical solution, ATE is used to collect test data of chips under different PVTA conditions for training the ML-Model.

[0030] There are currently several ways to adjust the operating voltage of the chip. The first method provides a voltage value that each chip can work normally under the most severe PVTA conditions. The second method tests each chip using ATE, records the minimum operating voltage of each chip at different operating frequencies, and saves the chip's storage device (efuse). The third method detects the leakage current of the chip and adjusts the operating voltage of the chip according to the corresponding relationship between the leakage current and the operating voltage.

[0031] However, the first method described above has a serious waste of power consumption. The second method described above increases the success rate of chip testing. The third method described above does not take into account the impact of chip aging. Chip aging can also cause an increase in current. When the chip ages, the corresponding relationship between the leakage current and the operating voltage of the chip becomes inaccurate, which may cause the chip to work abnormally or increase power consumption.

[0032] According to an embodiment of the present application, a chip operating voltage adjustment method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown herein.

[0033] The method provided in the first embodiment of the present application can be executed in a RISC-V system, a RISC-V chip or similar devices. Figure 1 is a hardware structure block diagram of a RISC-V system for implementing a chip operating voltage adjustment method according to an embodiment of the present application. As shown in Figure 1 the RISC-V system 100 can be divided into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, …, 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application program layer 106 (including multiple user programs and services 106-1, 106-2, …, 106-n) from bottom to top. The RISC-V system 100 also includes a tool chain 107 between the bottom hardware and the application program layer, which can include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7 and a version control system 107-8, etc.

[0034] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set, wherein the basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operation, compression instruction, etc.

[0035] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0036] The operating system layer 104 is located at the hardware intelligence, providing a hardware abstraction layer and management mechanism, so that the application can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0037] The middleware and library layer 105 provides a set of rich services and interfaces to help applications run more efficiently. For example, the standard library provides file operations, mathematical calculations, etc., while the middleware can provide network communication, graphical user interface, etc. complex services.

[0038] The application layer 106 utilizes the functions and services provided by the lower layers to implement specific application logic, which can be command-line tools, graphical interface applications, server-side services, etc.

[0039] The tool chain 107 is a key component that connects the underlying hardware to the upper software, and various tools in the tool chain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0040] It should be noted that the layered design of the RISC-V architecture allows decoupling between different levels, so that each layer can be developed and optimized independently.

[0041] In an optional embodiment, Figure 2 shows the use of the above Figure 1 The schematic diagram of a system on chip (SOC) of the RISC-V architecture is shown. Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application, as Figure 2 shown, the SOC internally contains at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected with peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0042] Under the above operating environment, the present application provides a chip operating voltage adjustment method as shown in Figure 3 . Figure 3 is a flowchart of the chip operating voltage adjustment method according to the present application. As shown in Figure 3 , the method comprises:

[0043] Step S302, in response to receiving the operating voltage adjustment instruction of the chip, collecting a plurality of detection values of the chip.

[0044] The different detection values are used to detect the chip by different types of sensors.

[0045] The working voltage adjustment instruction of the chip refers to an instruction issued by the control logic or upper software of the chip, which is used to adjust the working voltage of the internal power management module of the chip to adapt to different working environments and performance requirements. When the system detects that the chip load is reduced or the temperature is increased, an instruction can be issued through a DVFS (Dynamic Voltage and Frequency Scaling) algorithm to require the chip to reduce the working voltage to reduce power consumption.

[0046] The plurality of detection values refer to the values reflecting the current state of the chip collected by different types of sensors, including but not limited to the process characteristics, working voltage, temperature and aging degree of the chip. The process characteristic sensor (Process sensor) can reflect the current process characteristics of the chip, the voltage sensor (Voltage sensor) can reflect the voltage condition (including voltage drop) of the chip, the temperature sensor (Temperature sensor) can reflect the temperature of the chip, and the aging sensor (Aging sensor) can reflect the aging degree of the chip.

[0047] The different types of sensors refer to hardware components for detecting different states of the chip, which can be temperature sensors, voltage monitors, process characteristic detectors or chip aging monitors, etc. The different types of sensors are not limited here, and sensors can be added or reduced according to actual needs, and the number of the above-mentioned sensors is also not limited.

[0048] For example, the P, V, T, A four types of sensors correspond to the process characteristic sensor (such as Vth cell oscillation ring), voltage sensor, temperature sensor and aging sensor, respectively. For example, the temperature sensor can be a thermistor, the voltage sensor can be a voltage-dependent resistor, the process characteristic sensor can be a Vth cell oscillation ring circuit based on different threshold voltages, and the aging sensor can indirectly reflect the aging degree of the chip by monitoring the threshold voltage change of the transistor.

[0049] When the chip receives a working voltage adjustment instruction, it will activate the built-in multiple sensors, such as process characteristic sensor (P sensor), voltage sensor (V sensor), temperature sensor (T sensor) and aging sensor (A sensor), to collect data reflecting the current state of the chip. These data are used to evaluate the performance requirements of the chip in the current environment in real time, and then a more appropriate working voltage is calculated through a machine learning model to achieve the goal of lower power consumption and higher performance.

[0050] In response to receiving the operating voltage adjustment instruction of the chip, the chip starts its built-in PVTA sensor to collect the state information of the chip, such as the current process characteristic (P), operating voltage (V), temperature (T), and aging degree (A). These information will be used to evaluate the real-time performance requirements of the chip.

[0051] In step S304, the voltage model is used to predict the plurality of detection values to obtain the frequency-voltage mapping relationship of the chip.

[0052] The frequency-voltage mapping relationship is used to describe the corresponding minimum operating voltage of the chip at different operating frequencies, and the voltage model is trained according to the plurality of sample detection values and sample minimum operating voltage corresponding to the sample chip in different operating frequencies.

[0053] The voltage model described above is a model for evaluating and predicting the minimum operating voltage requirements of the chip under different conditions (such as different frequencies, temperatures, processes, etc.). It is usually based on machine learning algorithms, such as neural networks, to learn the relationship between chip performance and environmental conditions through training. The voltage model can be an adaptive voltage model, and by inputting a plurality of detection values into the adaptive voltage model, the frequency-voltage mapping relationship of the chip can be inferred.

[0054] In an alternative embodiment, the voltage model is a machine learning model (ML-Model) trained offline for real-time prediction of the minimum operating voltage of the chip under current process, voltage, temperature, and aging (PVTA) conditions. For example, a multi-layer perceptron (MLP) can be used as the basis for the voltage model, which is trained by collecting running data of the chip under different conditions to accurately predict the minimum operating voltage of the chip under any given condition.

[0055] During the startup phase of the chip, the software system of the chip can read the values of P-sensor (process condition), V-sensor (voltage size), T-sensor (temperature size), and A-sensor (aging condition), for example, the read P-sensor value can be 120MHz, the V-sensor value is 0.2V voltage drop, the T-sensor value is 35℃, and the A-sensor value is the chip usage time of 1000 hours. The above values are only used for example and are not limited, and can be measured according to the actual situation.

[0056] The sample chip described above is a representative chip selected during the design and manufacturing process for testing and data collection, in order to build and verify the model. During the ATE test phase, different corner chips can be selected as sample chips to train the voltage model. These chips reflect different states of process variation, aging, and temperature, thereby ensuring the wide applicability and accuracy of the model.

[0057] The frequency-voltage mapping described above is a relationship table describing the correlation between the working frequency of a chip and its minimum working voltage requirement, which can allow automatic adjustment of voltage at different frequencies to optimize power consumption and performance. The F-V mapping can be obtained in the offline model training phase, and the minimum working voltage values of the chip at different working frequencies can be stored as a table or part of the model, so as to adjust the voltage in real time when the chip is working.

[0058] During the startup or working phase of the chip, the values of the PVTA sensor are first read, which are input into the pre-trained voltage model. The voltage model predicts the minimum working voltage of the chip under the current conditions based on the input values. The predicted voltage is combined with different working frequencies to form a frequency-voltage mapping (F-V). The F-V mapping describes the minimum working voltage required by the chip at different working frequencies, thereby minimizing power consumption while ensuring normal operation of the chip.

[0059] By testing the multiple detection values of the chip (including process, voltage, temperature, and aging state) using the voltage model, the frequency-voltage mapping (F-V) obtained can adjust the working voltage of the chip in real time. A better voltage supply can be provided according to the current state of the chip, avoiding waste of power consumption, and since the model does not need to be tested for each chip, the testing cost of the chip is also greatly reduced. For example, when the chip starts, the system can automatically read the PVTA sensor values, input them into the ML-Model, and obtain the F-V mapping of the specific chip under the current conditions. Subsequently, dynamic adjustment of voltage frequency can be performed according to the F-V table to ensure that the chip works in a better state while reducing power consumption and improving energy efficiency.

[0060] Step S306, adjusting the current working voltage of the chip based on the frequency-voltage mapping and the target working frequency of the chip.

[0061] Wherein, the target working frequency is the working frequency that the chip is expected to reach.

[0062] The target working frequency described above refers to the working frequency that the chip is expected or required to reach under a specific application or task state. The higher the working frequency, the faster the processing speed of the chip, but at the same time, the power consumption and heat will also increase.

[0063] The current working voltage described above refers to the working voltage of the chip at a certain moment when it is actually running. The current working voltage can be provided by a power management unit or a voltage regulator to ensure stable operation of the chip.

[0064] During the operation of the chip, the frequency-voltage mapping relationship obtained by the offline training of the ML-Model can be referred to, and the working voltage of the chip can be automatically adjusted in combination with the environmental conditions (such as temperature, voltage drop, aging degree) and process conditions of the current chip to adapt to the target working frequency. This process aims to ensure that the chip meets the performance requirements while reducing power consumption and improving energy efficiency as much as possible.

[0065] Based on the frequency-voltage mapping relationship and the target working frequency of the chip, the current working voltage of the chip can be adjusted to achieve fine voltage management and maximize power efficiency. When the chip needs to be upgraded to a higher frequency to cope with more complex computing tasks, the adaptive voltage adjustment method can analyze the chip state and environmental conditions in real time to find the lowest working voltage that can support the frequency, avoiding unnecessary power waste. At the same time, the dependence on ATE testing is reduced, the testing cost is reduced, and the production efficiency and market competitiveness of the chip are improved.

[0066] For example, the ML-Model can be trained offline in advance, which can accurately predict the lowest working voltage of the chip at different working frequencies based on the current process, temperature, voltage drop, and aging conditions. During the use of the chip, for example, when running an AI inference task, the upper-layer software detects that the CPU frequency needs to be raised to 1.5 GHz to meet the computing requirements. At this time, the values of the PVTA sensors, including the P sensor (process condition), V sensor (voltage drop condition), T sensor (temperature condition), and A sensor (aging condition), can be read and input into the ML-Model for calculation. According to these real-time parameters, the ML-Model determines that the lowest working voltage that can ensure stable operation of the chip at a frequency of 1.5 GHz is 1.2 V. Subsequently, the software updates the frequency-voltage table of the DVFS system, and sends the target frequency-voltage pair (1.5 GHz, 1.2 V) to the hardware F-V controller to realize synchronous adjustment of the frequency and voltage. This process not only ensures that the chip can efficiently complete the computing task, but also reduces power consumption by lowering the working voltage, prolongs the service life of the chip, and avoids high-cost ATE testing, significantly reducing production costs.

[0067] Through the above steps, in response to receiving the working voltage adjustment instruction of the chip, a plurality of detection values of the chip are collected, wherein different detection values are used to detect the chip by different types of sensors; the plurality of detection values are predicted by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the corresponding minimum working voltage of the chip at different working frequencies, and the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips at different working frequencies; and the current working voltage of the chip is adjusted based on the frequency-voltage mapping relationship and a target working frequency of the chip, wherein the target working frequency is a working frequency to be reached by the chip, thereby achieving the purpose of improving the working voltage adjustment efficiency of the chip. It is easy to note that, by training the voltage model in advance according to the plurality of sample detection values and the sample minimum working voltages of the sample chips at different working frequencies, the mapping relationship of the frequency-voltage can be quickly calculated by using the voltage model after the plurality of detection values of the chip are collected, the current working voltage of the chip is automatically adjusted based on the frequency-voltage mapping relationship and the target working frequency of the chip, the chip is ensured to work in the minimum power consumption state at the target working frequency, and thereby the working voltage adjustment efficiency of the chip is improved, so as to effectively reduce the power consumption of the chip, and further solve the technical problems of low working voltage adjustment efficiency of the chip and high power consumption of the chip in the related art.

[0068] In the above embodiments of the present application, adjusting the current working voltage of the chip based on the frequency-voltage mapping relationship and the target working frequency of the chip includes: adjusting the current working frequency of the chip to the target working frequency, wherein the target working frequency is determined based on the current load of the chip; selecting the minimum working voltage corresponding to the target working frequency from the frequency-voltage mapping relationship; and adjusting the current working voltage of the chip based on the minimum working voltage.

[0069] The frequency-voltage mapping relationship mentioned above refers to the set of minimum working voltages at which the chip can stably operate at different working frequencies. This mapping relationship reflects the balance point between chip performance and power consumption and is the basis for implementing dynamic voltage and frequency adjustment strategies.

[0070] The target working frequency of the chip mentioned above refers to the better working frequency at which the chip plans to operate according to the current task load and performance requirements. The target working frequency is a key parameter that determines the performance adjustment of the chip in the dynamic adjustment strategy.

[0071] For example, when the chip is processing some light tasks such as word processing or web browsing, the target working frequency can be set lower to reduce power consumption; when processing high-load tasks such as video rendering or machine learning computation, the target working frequency should be higher to improve performance.

[0072] The minimum operating voltage refers to the minimum voltage level at which the chip can ensure stable operation at a specific operating frequency. The minimum operating voltage is closely related to the current load of the chip, environmental temperature, manufacturing process, and other conditions.

[0073] Adjusting the current operating frequency of the chip to the target operating frequency belongs to frequency control, which refers to automatically adjusting the operating frequency of the chip according to system load or performance requirements to achieve power consumption or performance optimization. For example, if the system detects that the current program being executed has a low load on the CPU, the frequency control dynamically reduces the operating frequency of the chip from 1.5 GHz to 1.2 GHz to reduce unnecessary power consumption.

[0074] Adjusting the current operating voltage of the chip based on the minimum operating voltage belongs to voltage control, which refers to automatically adjusting the operating voltage of the chip according to its operating state to reduce power consumption while ensuring the stability and performance of the chip. For example, when the frequency control reduces the operating frequency of the chip from 1.5 GHz to 1.2 GHz, the voltage control reduces the operating voltage from 1.1 V to 0.9 V to achieve a better energy efficiency ratio.

[0075] In an optional embodiment, a target operating frequency can be determined according to the current load of the chip; then, the minimum operating voltage at the target frequency is found based on the frequency-voltage mapping relationship; finally, the current operating voltage of the chip is adjusted to this minimum operating voltage through voltage control to reduce power consumption while ensuring performance. By monitoring the process, voltage, temperature, and aging (PVTA) state of the chip in real time, and based on a pre-constructed machine learning model (ML-Model), the minimum operating voltage of each chip under different conditions can be accurately predicted. This not only avoids the problem of power waste in traditional methods, but also saves the cost of ATE testing for each chip, making it an energy-saving and cost-effective solution.

[0076] For example, the chip is executing an image processing task and the system load is high. At this time, the operating frequency of the chip is 1.5 GHz, but the detected PVTA conditions show that the chip is in a favorable condition in terms of process, temperature, and aging. Based on the frequency-voltage mapping relationship and the offline trained ML-Model, the system determines that the minimum operating voltage at a frequency of 1.4 GHz is 1.0 V, and predicts that the chip can still maintain stable operation under the current PVTA conditions. Therefore, through frequency control, the operating frequency of the chip is adjusted from 1.5 GHz to 1.4 GHz; at the same time, through voltage control, the operating voltage is reduced from 1.1 V to 1.0 V, which not only reduces power consumption, but also saves operating costs, while the performance of the chip still meets the task requirements. The above numerical values are only for illustrative purposes and are not limited in specific.

[0077] In the above embodiments of the present application, the current working voltage is adjusted based on the minimum working voltage, including: obtaining a voltage margin of the chip, wherein the voltage margin is used to offset the model error caused by the voltage model; determining a target working voltage based on the sum of the minimum working voltage and the voltage margin; and adjusting the current working voltage of the chip to the target working voltage.

[0078] The voltage margin described above is an additional voltage value added on the basis of the determination of the minimum working voltage, which is used to cope with model errors, chip parameter errors or environmental errors, and ensures the stability and reliability of the chip operation. For example, assuming that the minimum working voltage predicted by the ML-Model is 0.9V, considering the possible errors of the model and other uncertain factors, a voltage margin of 0.05V can be added, so that the actual working voltage is set to 0.95V. The numerical values herein are only for illustrative purposes and are not limited.

[0079] The target working voltage described above is the actual working voltage set to the chip calculated by combining the minimum working voltage and the voltage margin. For example, the minimum working voltage is 0.8V, and the voltage margin is 0.1V, so the target working voltage is 0.9V. The numerical values herein are only for illustrative purposes and are not limited.

[0080] The current working voltage described above can be the actual voltage of the chip running, which can be higher or equal to the minimum working voltage. By adjusting the current working voltage of the chip to the target working voltage, power consumption optimization can be achieved.

[0081] In an optional embodiment, the voltage margin of the chip can be obtained, which can be used to represent the accuracy of the model, the variation range of the chip parameters and the fluctuation of the working environment. The target working voltage is determined based on the sum of the minimum working voltage and the voltage margin, so as to accurately adjust the working voltage of the chip and ensure that the chip can operate stably even in adverse conditions. The current working voltage of the chip is adjusted to the target working voltage to minimize the power consumption.

[0082] Embodiments of the present application introduce a voltage margin, which not only offsets the errors that may occur when the voltage model is predicted, but also considers the uncertainty of the chip parameters and the changes of the working environment, thereby ensuring the stability and reliability of the chip in actual operation. At the same time, by accurately adjusting the working voltage to the target value, the chip power consumption can be effectively reduced, the chip heating can be reduced, the service life of the chip can be prolonged, and the test cost of the chip can be significantly reduced, thereby providing a more efficient and economical solution for chip design and manufacturing.

[0083] For example, in the chip use stage, the values detected by the sensor are as follows: the Psensor value indicates that the current process is tt angle, the Vsensor value is 0.05V (indicating the pressure drop condition), the Tsensor value is 25℃, and the Asensor value indicates that the chip aging degree is low. Through ML-Model inference, it is obtained that the minimum working voltage of the chip at the current 1GHz working frequency is 0.8V. Considering the model error and the uncertainty of the chip parameters, 0.1V can be used as the voltage margin. Therefore, the target working voltage is set to 0.8V+0.1V=0.9V. At this time, the current working voltage of the chip can be adjusted to 0.9V to ensure that the chip operates stably under the current environment, while achieving good control of power consumption. This process significantly reduces power consumption and improves energy efficiency compared to the traditional fixed voltage power supply scheme under the premise of ensuring stable chip operation, which provides strong support for high-performance and low-power chip design. The values here are only for example and are not limited.

[0084] In the above embodiments of the present application, the voltage model is obtained by adjusting the model parameters of the initial voltage model through a loss function. The loss function is constructed based on the test working voltage and the sample minimum working voltage. The test working voltage is obtained by predicting the initial voltage model for a plurality of sample detection values.

[0085] The initial voltage model described above can be a model in the field of machine learning, which is usually defined by a series of parameters and used to predict the working voltage of a chip under certain conditions. The initial voltage model can be a multilayer perceptron model, which can be preliminarily trained based on an initial data set of chip design to predict the minimum working voltage of the chip under different PVTA (process, voltage, temperature, aging) conditions. It should be noted that the initial voltage model can be a voltage model that has not been trained or a voltage model that has not been completed.

[0086] The model parameters described above refer to mathematical variables used to adjust the prediction ability of the model in the machine learning model.

[0087] In the model training process, the model parameters to be adjusted can include but are not limited to weights and biases. The model parameters described above are updated through the training process to improve the accuracy of the model in predicting the minimum working voltage.

[0088] The loss function described above is a function used to measure the difference between the predicted output of the model and the actual target output in machine learning. The loss function can be mean squared error (MSE), which can calculate the square of the difference between the predicted minimum working voltage and the actually tested minimum working voltage, and then take the average. The lower the function value of the loss function, the more accurate the prediction of the model.

[0089] The test operating voltage is the voltage value at which the chip can stably operate under given conditions. Through ATE (Automatic Test Equipment) testing, the operating voltage of the chip under specific frequency, temperature, voltage drop, and aging conditions can be obtained, and these voltage values are the test operating voltage.

[0090] The sample minimum operating voltage is the minimum voltage at which the chip can stably operate under specific PVT (process, voltage, temperature) and aging conditions. The minimum operating voltage of different chips under different conditions is recorded as the output value of the training sample in the ATE test of the chip at different operating rates.

[0091] In an optional embodiment, the initial voltage model is first trained by a large amount of sample data, which includes the PVTA detection value of the chip and the corresponding minimum operating voltage. The model parameters are optimized by a loss function, which calculates the difference between the test operating voltage predicted by the model and the actual sample minimum operating voltage. By updating the model parameters, the initial model gradually evolves into a more accurate voltage model that can accurately predict the minimum operating voltage of the chip under different PVTA conditions.

[0092] The voltage model constructed by optimizing the model parameters and the loss function can highly adapt to the actual operating environment of the chip. This means that when the chip is in different operating frequencies, temperatures, voltage drops, and aging states, the model can dynamically predict the minimum voltage at which the chip can stably operate, thereby avoiding the power waste caused by using a fixed voltage value in the traditional method. In addition, the present application does not need to perform expensive ATE testing on each chip, saving testing costs, significantly reducing the power consumption of the chip, improving the energy efficiency ratio, and reducing the economic burden of chip testing.

[0093] In the above embodiments of the present application, in response to receiving the operating voltage adjustment instruction of the chip, the plurality of detection values of the chip are collected, including: in response to receiving the operating voltage adjustment instruction of the chip, calling the software interface of different types of sensors to read the plurality of detection values.

[0094] The above-mentioned operating voltage adjustment instruction can be issued by a software system or a hardware control unit, the purpose being to adjust the operating voltage of the chip to optimize performance or power consumption. Optionally, during the startup of the chip or during the operation of the chip, the upper-layer operating system sends an instruction to the voltage adjustment module to require adjustment of the operating voltage according to the current load and performance requirement.

[0095] The operating voltage of the above-mentioned chip refers to the power supply voltage required by the chip during normal operation, which can affect the power consumption and performance of the chip.

[0096] The software interface of the above-mentioned sensor is an interface following a specific communication protocol, which can allow a software program to interact with a hardware device (such as a sensor) for data exchange. Through calling the specific software interface, the upper-layer software system can access and read the real-time data of the P, V, T, and A sensors on the chip, such as the temperature value of the temperature sensor and the voltage drop value of the voltage drop sensor.

[0097] In the embodiments of the present application, when the chip receives an instruction to adjust the operating voltage, the upper-layer software system will activate the software interface of different types of sensors to collect key parameters reflecting the current state of the chip. These parameters include the process characteristics, voltage drop, temperature, and aging degree of the chip. The collected detection values will be used to adjust the operating voltage of the chip to ensure that the performance requirements are met while minimizing power consumption as much as possible.

[0098] In the present application, after receiving the operating voltage adjustment instruction of the chip, the parameters reflecting the current state of the chip are actively read from the PVTA sensors on the chip. In this way, the chip can adjust its operating voltage in real time and intelligently to adapt to the current process, voltage, temperature, and aging conditions. Compared with providing a fixed voltage, this method significantly reduces the power consumption of the chip; compared with ATE testing of multiple chips, it greatly reduces the testing cost; compared with adjusting the voltage only according to the leakage current value, it more accurately considers the aging factor of the circuit, improving the accuracy of the chip performance model.

[0099] The design of the above-mentioned software interface separates the hardware sensors from the upper-layer software, which means that even if new sensor types need to be added or sensors need to be replaced in the future, only the corresponding software interface needs to be updated, without the need for large-scale modification of the entire chip hardware. This greatly enhances the flexibility and scalability of the system, facilitating future technology upgrades or the introduction of new performance monitoring parameters.

[0100] The above-mentioned software interface can provide a standardized data reading method, allowing the upper-layer software to efficiently and uniformly access various sensor data. This avoids the complexity and inefficiency problems that may arise from direct hardware interaction, ensuring the speed and accuracy of data reading.

[0101] Through the software interface for data interaction, the direct coupling between the upper-layer software and the hardware sensors is simplified, reducing the complexity of system design. This allows the upper-layer software to focus more on algorithm optimization and function implementation, rather than paying too much attention to the specific hardware implementation details of the sensors.

[0102] Optionally, the general software interface can include data checksum and error handling mechanism to ensure the integrity and accuracy of the read sensor data. In addition, additional data processing logic such as data filtering, outlier detection, etc. can be added through the software interface to further ensure the reliability of the voltage regulation decision based on sensor data.

[0103] The design of the above-mentioned software interface follows certain standards and specifications, so that on different hardware platforms, as long as the corresponding interface standards are implemented, the upper-layer software can seamlessly read and process sensor data, enhancing the cross-platform compatibility of the scheme, which is conducive to the wide deployment and application of the present application. By adding a software interface, the efficiency of the data reading process can be improved, and the flexibility, security, reliability and cross-platform compatibility of data reading can be enhanced, which is an indispensable key component for realizing adaptive voltage regulation.

[0104] For example, when running a high-load task, the software system detects the task demand and sends a working voltage regulation instruction. The system then calls the software interface of the on-chip P, V, T, A sensors to read the real-time detection values reflecting the current process condition, voltage drop, temperature and aging degree. This series of detection values are input into the pre-trained ML-Model, and the model calculates the lowest working voltage suitable for the current task load and performance demand according to the current PVTA condition. The software system updates the frequency-voltage table (F-V table) and notifies the hardware voltage controller to regulate the voltage. By adjusting the working voltage in real time, it can ensure that the performance of high-load tasks is met while reducing power consumption and improving energy efficiency, while reducing the need for ATE testing and reducing production costs.

[0105] Figure 4 is a structural schematic diagram of an adaptive voltage regulation process according to an embodiment of the present application, as Figure 4As shown, in a processor system of a hardware system on chip (SOC), different types of sensors are integrated, including process sensors, voltage sensors, temperature sensors, and aging sensors. The above-mentioned sensors are connected with a machine learning model (ML-Model). After the chip is started, the values of the sensors can be read by calling the related software interface of the sensors. The read values are used as the input of the machine learning model, and the inference is performed to obtain the minimum operating voltage value of the chip at different frequencies, which is suitable for the current temperature, voltage drop, and service life. The obtained frequency-voltage mapping relationship can be used to update the table storage unit of the dynamic voltage frequency adjustment framework. During the running of the hardware system on chip and the execution of the dynamic voltage frequency adjustment framework, the target frequency-voltage corresponding relationship (F-V) suitable for the current load can be selected as the frequency-voltage point of the system. The target frequency-voltage corresponding relationship is sent to the frequency-voltage controller (F-V controller), and the frequency and voltage control of the chip is completed. The power management circuit can be controlled to obtain the target voltage, and the clock management circuit can be controlled to obtain the target frequency.

[0106] The adaptive voltage adjustment flow (AVSFLOW) described above can be executed in the chip startup phase, the normal working phase of the chip, and the different service life phases of the chip. It should be noted that the values detected by the four sensors mentioned above can be used in the adaptive voltage adjustment flow proposed in the present application, but are not limited thereto. Any factor affecting the performance of the chip can also be used as the input of the machine learning model for implementing the adaptive voltage adjustment flow.

[0107] In the chip ATE test phase, a certain number of different corner chips can be selected. The minimum operating voltage can be tested under different combinations of frequency, temperature, voltage drop, and aging, that is, a plurality of sets of {process ring oscillator value, voltage value, temperature value, aging value} are collected as input sample values, and the minimum operating voltage (Vmin) is used as the target output value. An appropriate initial machine learning model can be selected for training, and a machine learning model suitable for the current processor system can be constructed offline. The machine learning model can be a multi-layer perceptron (MLP), but is not limited thereto. The type of machine learning model can be set according to the actual situation. It should be noted that, in order to ensure the reliability of the chip, the voltage margin can be increased on the hardware or software.

[0108] The above highlights that in the process of applying machine learning models to adaptively adjust the operating voltage of a chip, in order to ensure the accuracy of the algorithm model and guarantee the reliability of the chip operation, a voltage margin can be added to achieve this. The voltage margin refers to an additional part of voltage above the minimum voltage required for normal operation of the chip, which is used to cope with model prediction errors, environmental changes or chip performance fluctuations and other uncertain factors, to ensure that the chip can operate stably under various conditions.

[0109] Specifically, even if the machine learning model is well trained, the predicted minimum operating voltage value may still have some deviation from the actual situation, especially in non-standard situations such as chip aging and environmental condition changes. In order to prevent such deviations from causing unstable operation or performance degradation of the chip, a safety margin, i.e. voltage margin, can be added to the model predicted voltage value. This margin can be adjusted according to the specific application scenario of the chip, the requirement for stability and the prediction accuracy of the model.

[0110] At the hardware level, the increase in voltage margin can be achieved by designing a voltage regulator to ensure that the actual operating voltage of the chip is always above the predicted value, even in the most unfavorable conditions, to maintain sufficient performance and stability. At the software level, a voltage margin parameter can be built into the algorithm that controls the operating voltage of the chip, and by adjusting this parameter, the operating voltage in actual application can be controlled to be higher than the minimum value predicted by the model. Increasing the voltage margin is a strategy to ensure stable operation of the chip in the process of adaptive voltage adjustment, and through this way, even if there is a prediction error or environmental uncertainty, the performance of the chip can be ensured not to be affected, while maintaining a low power consumption level.

[0111] The above-mentioned corner chips can include but are not limited to slow corner (ss), typical corner (tt) and fast corner (ff), where the slow corner chip runs slower than expected, usually due to process variation, low supply voltage or low temperature, etc. The typical corner chip is in the expected normal operating state when designed, i.e. the chip behavior when the parameters are at their average or typical values. The fast corner chip runs faster than expected, which may be due to process variation, high supply voltage or high temperature, etc.

[0112] The P sensor is used to characterize the process of the current chip circuit, which can be realized by an oscillator ring composed of different threshold voltage cells (Vth cells), interconnection types (wires), etc. The V sensor is used to characterize the voltage of the current circuit, and then characterize the voltage drop (voltage droop) from the chip supply voltage to the current circuit. The voltage value of the V sensor can directly represent the voltage drop. The T sensor can be used to characterize the temperature of the circuit. The A sensor can be used to characterize the aging of the chip.

[0113] The Vth cell and wire type oscillator ring in the P sensor means that the sensor uses a ring of cells with different threshold voltages and interconnection characteristics to monitor the process conditions of the circuit. Since different process conditions (such as uneven impurity distribution during manufacturing, temperature changes, etc.) will affect the threshold voltage of the Vth cell and the signal transmission characteristics of the wire type, by measuring the frequency of the oscillator ring, the process state of the current circuit can be indirectly reflected, and as one of the inputs of the above-mentioned machine learning model, the working voltage and frequency are adjusted to reduce power consumption and improve performance.

[0114] The threshold voltage cell mentioned above refers to a cell in integrated circuit design that characterizes the threshold voltage (Vth) of the circuit through a specific cell structure (such as a transistor). Threshold voltage is an important parameter for measuring the on and off state of a transistor, and different Vth values mean that the transistor has different conduction and cutoff characteristics, thereby affecting the power consumption and performance of the circuit. In design, according to the needs, different Vth cells can be used to adjust the power consumption and performance of the circuit. For example, low Vth cells can provide higher performance, but consume more power; while high Vth cells have lower power consumption, but the performance may be limited.

[0115] The interconnection type mentioned above refers to the physical characteristics and design methods of signal lines in integrated circuits. Signal lines (interconnections) connect different parts of the circuit, and their design has an important impact on the performance and power consumption of the circuit. Interconnection types usually include the width, length, number of layers, and resistance and capacitance characteristics of metal lines. In chip design, different interconnection strategies will affect the transmission speed and energy loss of signals. For example, thicker metal lines can reduce resistance and thus reduce power consumption, but may also increase chip area and manufacturing cost; while finer metal lines can save space, but may increase signal delay and power consumption.

[0116] The application provides a method for adaptively adjusting a chip working voltage, which comprehensively considers factors such as process, voltage, temperature and aging (Process, Voltage, Temperature, Aging, referred to as PVTA) of chip performance, constructs a relationship between the lowest working voltage at different frequencies and each influencing factor through an offline trained machine learning model (ML-Model), and applies the machine learning model to an actual chip device, automatically finds the lowest working voltage value of each chip at different frequencies and under different PVTA conditions through real-time detection of sensor values of each PVTA, and further reduces chip power consumption and saves test cost.

[0117] In the application, the lowest working voltage of different chips can be effectively determined through the adaptive voltage adjustment method, so that the power consumption of different chips is effectively reduced. The application can detect sensor detection values of each PVTA in real time, automatically find the lowest working voltage value of different chips at different frequencies and under different PVTA conditions, and reduce the power consumption of each chip. The ATE test does not need to be performed on each chip, and the test cost is greatly reduced. The influence of circuit aging on chip performance is considered, and the chip performance model is more accurate.

[0118] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose authorization or refusal.

[0119] It should be noted that, for each of the foregoing method embodiments, in order to simply describe, each is described as a combination of a series of actions, but those skilled in the art should know that the application is not limited by the order of the described actions, because according to the application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0120] From the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, and of course can also be realized by hardware.

[0121] According to the embodiments of the application, a chip working voltage adjustment device for implementing the chip working voltage adjustment method is also provided, Figure 5is a schematic diagram of a chip working voltage adjusting device according to an embodiment of the present application, as shown in the figure, the device 500 comprises: an acquisition module 502, a prediction module 504, an adjusting module 506. Figure 5

[0122] The acquisition module 502 is configured to acquire a plurality of detection values of the chip in response to receiving a working voltage adjusting instruction of the chip, wherein different detection values are obtained by detecting the chip through different types of sensors; the prediction module 504 is configured to predict the plurality of detection values by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the corresponding minimum working voltage of the chip at different working frequencies, and the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips at different working frequencies; and the adjusting module 506 is configured to adjust the current working voltage of the chip based on the frequency-voltage mapping relationship and a target working frequency of the chip, wherein the target working frequency is a working frequency to be reached by the chip.

[0123] It should be noted that the acquisition module 502, the prediction module 504, and the adjusting module 506 correspond to steps S302 to S306 in Embodiment 1, and the three modules have the same instances and application scenarios as the corresponding steps, but are not limited to the content disclosed in Embodiment 1. It should be noted that the above modules or units can be hardware components or software components stored in a memory (for example, the memory 104) and processed by one or more processors (for example, the processors 102a, 102b, …, 102n), and the above modules can also be run in the computer terminal 10 provided in Embodiment 1 as a part of the device.

[0124] In the above embodiments of the present application, the adjusting module is further configured to adjust the current working frequency of the chip to the target working frequency, wherein the target working frequency is determined based on the current load of the chip; select the minimum working voltage corresponding to the target working frequency from the frequency-voltage mapping relationship; and adjust the current working voltage of the chip based on the sum of the minimum working voltage and the voltage margin.

[0125] In the above embodiments of the present application, the adjusting module is further configured to obtain a voltage margin of the chip, wherein the voltage margin is used to offset the model error caused by the voltage model; determine the target working voltage based on the sum of the minimum working voltage and the voltage margin; and adjust the current working voltage of the chip to the target working voltage.

[0126] In the above embodiments of the present application, the voltage model is obtained by adjusting the model parameters of an initial voltage model through a loss function, and the loss function is constructed based on a test working voltage and a sample minimum working voltage, wherein the test working voltage is obtained by predicting the plurality of sample detection values by using the initial voltage model.

[0127] ​In the above embodiments of the present application, the collection module is configured to read the plurality of detection values by calling the software interface of the different types of sensors in response to receiving the working voltage adjustment instruction of the chip.

[0128] It should be noted that the preferred embodiments involved in the above embodiments of the present application have the same application scenarios and implementation processes as the scheme provided in Embodiment 1, but are not limited to the scheme provided in Embodiment 1.

[0129] The present application provides a chip working voltage adjustment system, Figure 6 is a schematic diagram of a chip working voltage adjustment system according to an embodiment of the present application, as Figure 6 shown, the system 600 includes: a plurality of sensors 602 connected with a chip 604, for detecting the chip to obtain a plurality of detection values; a voltage adjustment device 606 connected with the plurality of sensors, for collecting the plurality of detection values after receiving a working voltage adjustment instruction of the chip, and predicting the plurality of detection values by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, and based on the frequency-voltage mapping relationship and a target working frequency of the chip, a current working voltage of the chip, wherein the frequency-voltage mapping relationship is used to describe the corresponding minimum working voltage of the chip at different working frequencies, the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips in different working frequencies, and the target working frequency is a working frequency to be reached by the chip.

[0130] The plurality of sensors described above are basic components of the system, which are distributed at different key positions of the chip, and are used to monitor the PVTA (process, voltage, temperature, aging) characteristics of the chip in real time. The process sensor is used to monitor the manufacturing process variation of the chip. The voltage sensor is used to measure the actual working voltage of the chip or its local block, and the voltage drop. The temperature sensor is used to detect the real-time temperature of the chip. The aging sensor is used to monitor the degree of aging of the chip over time.

[0131] The voltage adjustment device described above is responsible for receiving the working voltage adjustment instruction from the software layer, and calculating the minimum working voltage value of the chip under the current condition by the voltage model according to the real-time detection values of the sensors. The voltage adjustment device applies the adjusted voltage to the chip to ensure its stable operation at the target working frequency.

[0132] The whole system initiates the working voltage adjustment instruction through the software layer, triggers the voltage adjustment device to adjust. The software layer determines which value the working voltage of the chip should be adjusted to based on the target working frequency and the frequency-voltage mapping relationship. The prediction result of the voltage model is used to update the frequency-voltage table (F-V table) to guide the DVFS (Dynamic Voltage and Frequency Scaling) system to dynamically adjust the voltage and frequency to achieve the purpose of power consumption optimization and performance maximization. The adaptive adjustment process is dynamic, which can be executed at different stages of chip startup and operation, and throughout the life cycle of the chip. As the chip ages, the sensor data will reflect the changes, and the model will adjust the prediction according to the new data, so as to ensure that the setting of the working voltage is always good.

[0133] Through the above structure and mechanism, the system can dynamically adjust the working voltage without sacrificing the performance and stability of the chip, and achieve the minimization of power consumption and the reduction of test cost.

[0134] In the above embodiments of the present application, the plurality of sensors include: a process sensor for detecting the manufacturing process of the chip to obtain a process detection value, wherein the process detection value is used to represent the deviation value caused by the manufacturing process of the chip; a voltage sensor for detecting the current voltage of the corresponding circuit of the chip to obtain a voltage detection value, wherein the voltage detection value is used to represent the voltage drop from the power supply voltage of the circuit to the circuit; a temperature sensor for detecting the current temperature of the chip to obtain a temperature detection value; an aging sensor for detecting the aging state of the chip to obtain an aging detection value, wherein the aging detection value is used to represent the deviation value caused by the change of the chip over time.

[0135] In the embodiments of the present application, the method and device for adaptively adjusting the working voltage of the chip realize comprehensive monitoring of the state of the chip through a plurality of sensors (P, V, T, A sensors) integrated in the chip, so as to dynamically adjust the working voltage and achieve the purpose of reducing power consumption and improving energy efficiency. In the following, I will explain the functions of these sensors and their roles in the method in combination with the structure:

[0136] The process sensor is usually composed of special circuits designed on the chip, such as Ring Oscillator. These circuits contain transistors with different threshold voltages (Vth cell) and different types of metal wires, which are sensitive to process variations and can reflect the deviations in the chip manufacturing process, such as changes in transistor threshold voltage, changes in metal wire resistance, etc. The process sensor is used to monitor the manufacturing process of the chip in real time and obtain process detection values. These detection values reflect the performance differences of the chip due to manufacturing process deviations (such as different wafer batches, process nodes, etc.). Process detection values help identify the performance status of the chip under current process conditions, thereby adjusting the operating voltage to a better state.

[0137] The voltage sensor is designed to detect the real-time voltage of the internal circuit of the chip, usually by monitoring the difference (voltage drop) between the supply voltage of the chip and the actual operating voltage of the circuit. In the design, the voltage sensor may contain precise voltage comparators and analog-to-digital converters to ensure accurate measurement. The voltage sensor is used to detect the real-time voltage of the internal circuit of the chip and obtain voltage detection values, i.e. voltage drop values, reflecting the distribution and changes of the internal voltage of the chip. Voltage detection values are used to evaluate the voltage drop from the supply voltage of the chip to the internal circuit, which is crucial for determining the actual operating voltage of the circuit, thereby optimizing the voltage setting under different loads and conditions.

[0138] The temperature sensor can be a thermistor, diode or special temperature detection circuit integrated on the chip, which can sense the temperature change of the chip, usually changing the resistance or voltage value as the temperature rises. The temperature sensor is used to monitor the temperature of the chip in real time and obtain temperature detection values. Temperature is an important factor affecting the performance and power consumption of the chip. Changes in temperature detection values will cause fluctuations in chip performance. By monitoring temperature in real time and adjusting operating voltage, the chip can maintain good performance and minimum power consumption under various temperature conditions.

[0139] The aging sensor is used to monitor the aging state of the chip over time, which may include monitoring the change in transistor threshold voltage, degradation of capacitance, etc. These changes will gradually accumulate over time as the chip is used. The aging sensor is used to detect the aging degree of the chip and obtain aging detection values, reflecting the performance decline of the chip due to long-term use. Aging detection values take into account the impact of the chip's usage cycle, ensuring that even if the chip ages, its performance can be maintained by adjusting the operating voltage, avoiding wasted power consumption or premature failure.

[0140] The plurality of sensors collectively constitute a network for chip state monitoring. By acquiring dynamic information of the chip in terms of process, voltage, temperature, and aging in real time, the ML-Model can be used to predict and adjust the working voltage most suitable for the current state of the chip, thereby significantly reducing power consumption and saving testing costs while ensuring chip performance, improving the overall energy efficiency and reliability of the chip.

[0141] In the above embodiments of the present application, the process sensor includes a plurality of ring oscillators, each of which includes a threshold voltage unit and an interconnection unit ring. The ring oscillator outputs an oscillation frequency according to the output current of the threshold voltage unit and the signal propagation time of the interconnection unit ring, wherein the oscillation frequency is used to represent the process detection value. The threshold voltage power supply is used to reflect the manufacturing process according to the threshold voltage of the transistor. The interconnection unit ring is used to reflect the manufacturing process according to the layout between different signal lines.

[0142] By using a plurality of ring oscillators, each of which includes a threshold voltage unit and an interconnection unit ring. The output current of the threshold voltage unit can reflect the threshold voltage of the transistor, and the signal propagation time of the interconnection unit ring can reflect the layout between the signal lines, both of which are key parameters in chip manufacturing process. Different manufacturing processes will cause changes in threshold voltage and interconnection characteristics, which will be directly reflected in the oscillation frequency. Therefore, by monitoring the oscillation frequency, the manufacturing process of the chip can be accurately reflected, including the process fluctuations and process differences between different chips.

[0143] The above process sensor design does not require any modification or damage to the circuit of the chip, but integrates the ring oscillator at the edge or non-critical area of the chip, which can avoid affecting the function of the chip and ensure the long-term stability of the sensor. According to the design of the process sensor, the process sensor can continuously monitor the process state of the chip without interfering with the normal operation of the chip.

[0144] As the chip is used, the circuit will gradually age, which will further affect the threshold voltage and interconnection characteristics of the signal lines. The process sensor can detect the process changes caused by aging by continuously monitoring the oscillation frequency, so that the chip can still accurately adjust the working voltage during the aging process, ensuring performance while reducing power consumption.

[0145] Since the process sensor can monitor the process state of the chip in real time, it can be closely integrated with a dynamic voltage and frequency scaling (DVFS) system to realize real-time dynamic adjustment of the working voltage of the chip. This means that the chip can automatically adjust to a better working voltage under different workloads, temperatures, and aging levels, thereby ensuring performance while minimizing power consumption.

[0146] The application trains the relationship between the chip performance and the process, voltage, temperature, aging and other factors in advance by constructing a voltage model. In the process of using the chip, the lowest working voltage suitable for the current state can be quickly calculated through the real-time feedback of the process state of the process sensor, which not only reduces the test cost, but also improves the power efficiency and performance stability of the chip.

[0147] The design of the process sensor can provide accurate process state feedback and support adaptive voltage regulation of the chip. It can not only adapt to the fluctuations of the manufacturing process and the aging of the chip, but also realize dynamic power optimization, and has a significant advantage in test cost.

[0148] In the above-mentioned embodiments of the application, the system further comprises a voltage regulator configured to determine a voltage margin of the chip, wherein the voltage margin is used to offset the model error caused by the voltage model.

[0149] In the embodiments of the application, the voltage regulator is added to determine the voltage margin of the chip. The introduction of this structure has the following beneficial effects:

[0150] Since the ML-Model is trained based on data under specific test conditions and environments in an offline state, when the model is applied to the actual chip, it may encounter different situations from the training data set, resulting in model errors. The setting of the voltage margin can serve as a safety mechanism to ensure that the chip can still work stably even if the model prediction is not completely accurate, and will not have performance degradation or functional failure due to too low voltage.

[0151] In the actual working environment, the chip may face dynamic changes such as process deviation, temperature fluctuation, and uncertainty of aging degree. The voltage regulator monitors these factors in real time and dynamically adjusts the voltage margin according to the monitoring results, so that the chip can maintain a relatively good working state under various environments and further optimize the power consumption performance.

[0152] By introducing the voltage regulator, it can be used as a correction means for the test results of the voltage model. By combining real-time monitoring data and pre-set voltage margins, the prediction accuracy and stability under different working conditions are improved, ensuring high chip performance. By accurately adjusting the working voltage of the chip, the problem of too high voltage caused by model error in traditional methods is avoided, thereby effectively reducing the power consumption of the chip and prolonging the battery life of the device.

[0153] The voltage regulator described above can be an independent hardware module, which is easy to integrate in existing hardware structures, and its strategy and parameters can be optimized and upgraded according to the feedback of actual application, so as to maintain the advancement and competitiveness of the system. The addition of the voltage regulator not only enhances the robustness and accuracy of the model, but also simplifies the test process, reduces power consumption, and improves the reliability and efficiency of the entire system.

[0154] Embodiments of the present application can provide a system on chip, comprising: the system of any one of the above embodiments.

[0155] Embodiments of the present application can provide an electronic device, which can be any one of the electronic devices in the electronic device group. Alternatively, in the present embodiment, the electronic device can also be replaced by a terminal device such as a mobile terminal.

[0156] Alternatively, in the present embodiment, the electronic device can be located in at least one of the network devices in the computer network. The electronic device contains a processor and stores executable programs. The processor is used to run the programs, wherein the programs perform the method of any one of the above embodiments when running.

[0157] In the present embodiment, the computer terminal can execute the program code in the method.

[0158] The memory can be used to store software programs and modules, such as program instructions / modules corresponding to the method and device in the embodiments of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implements the method in the above embodiments. The memory can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory can further include a memory remotely arranged relative to the processor, which can be connected to the terminal A through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0159] The processor can call information and application programs stored in the memory through the transmission device to perform the following steps: in response to receiving a working voltage adjustment instruction of the chip, collecting a plurality of detection values of the chip, wherein different detection values are obtained by detecting the chip through different types of sensors; predicting the plurality of detection values by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the corresponding minimum working voltage of the chip at different working frequencies, and the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips in different working frequencies; and adjusting the current working voltage of the chip based on the frequency-voltage mapping relationship and a target working frequency of the chip, wherein the target working frequency is a working frequency to be reached by the chip.

[0160] Those skilled in the art can understand that all or part of the steps in the above-mentioned various methods of the embodiments can be completed by instructing the hardware related to the terminal device through programs, and the programs can be stored in a computer readable storage medium, which can include a flash disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0161] The embodiments of the present application also provide a computer readable storage medium. Optionally, in the embodiment, the above-mentioned computer readable storage medium can be used to save the program codes executed by the method provided by the above-mentioned embodiments.

[0162] Optionally, in the embodiment, the above-mentioned storage medium can be located in any one of the electronic devices in the group of electronic devices in the computer network, or in any one of the mobile terminals in the group of mobile terminals.

[0163] Optionally, in the embodiment, the computer readable storage medium is configured to store program codes for performing the following steps: in response to receiving a working voltage adjustment instruction of the chip, collecting a plurality of detection values of the chip, wherein different detection values are obtained by detecting the chip through different types of sensors; predicting the plurality of detection values by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe the corresponding minimum working voltage of the chip at different working frequencies, and the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips in different working frequencies; and adjusting the current working voltage of the chip based on the frequency-voltage mapping relationship and a target working frequency of the chip, wherein the target working frequency is a working frequency to be reached by the chip.

[0164] The embodiment of the present application further provides a computer program product. Optionally, the computer program product can include a computer program, and the computer program can implement the method provided by the above embodiment when executed by a processor.

[0165] The embodiment of the present application further provides a computer program product. Optionally, the computer program product can include a nonvolatile computer readable storage medium, and the nonvolatile computer readable storage medium can be used to store a computer program. The computer program can implement the method provided by the above embodiment when executed by a processor.

[0166] The embodiment of the present application further provides a computer program or instruction. Optionally, the computer program can implement the method provided by the above embodiment when executed by a processor.

[0167] The serial numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0168] In the above embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0169] In the several embodiments provided by the present application, it should be understood that the disclosed technology can be implemented in other ways. Of course, the embodiment described above is only a schematic, for example, the division of units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, unit or module, and can be electrical or other forms.

[0170] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the embodiment.

[0171] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software functional unit.

[0172] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0173] The above only describes the preferred embodiments of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present application.

Claims

1. A method of adjusting operating voltage of a chip, characterized by, The method comprises: in response to receiving a working voltage adjustment instruction of a chip, collecting a plurality of detection values of the chip, wherein different detection values are obtained by detecting the chip through different types of sensors, and the different types of sensors comprise a process sensor, a voltage sensor, a temperature sensor, and an aging sensor; predicting the plurality of detection values by using a voltage model to obtain a frequency-voltage mapping relationship of the chip, wherein the frequency-voltage mapping relationship is used to describe a corresponding minimum working voltage of the chip at different working frequencies, the voltage model is trained according to a plurality of sample detection values and sample minimum working voltages of sample chips in the different working frequencies, and the sample chips comprise a plurality of corner chips, and different corner chips correspond to different chip states; adjusting a current working voltage of the chip based on the frequency-voltage mapping relationship and a target working frequency of the chip, wherein the target working frequency is a working frequency to be reached by the chip.

2. The chip operating voltage adjustment method according to claim 1, wherein Adjusting the current working voltage of the chip based on the frequency-voltage mapping relationship and the target working frequency of the chip comprises: adjusting the current working frequency of the chip to the target working frequency, wherein the target working frequency is determined based on a current load of the chip; selecting the minimum working voltage corresponding to the target working frequency from the frequency-voltage mapping relationship; adjusting the current working voltage of the chip based on the minimum working voltage.

3. The chip operating voltage adjustment method according to claim 2, wherein Adjusting the current working voltage based on the minimum working voltage comprises: obtaining a voltage margin of the chip, wherein the voltage margin is used to offset a model error caused by the voltage model; determining a target working voltage based on a sum of the minimum working voltage and the voltage margin; adjusting the current working voltage of the chip to the target working voltage.

4. The chip operating voltage adjusting method according to claim 1, wherein The voltage model is obtained by adjusting model parameters of an initial voltage model by using a loss function, the loss function is constructed based on a test working voltage and the sample minimum working voltage, and the test working voltage is obtained by predicting the plurality of sample detection values by using the initial voltage model.

5. The chip operating voltage adjusting method according to claim 1, wherein In response to receiving a working voltage adjustment instruction of a chip, collecting a plurality of detection values of the chip comprises: in response to receiving the working voltage adjustment instruction of the chip, calling a software interface of the different types of sensors to read the plurality of detection values.

6. A chip operating voltage adjustment system characterized by comprising: The method comprises: a plurality of sensors connected to the chip, used to detect the chip to obtain a plurality of detection values, and the plurality of sensors comprise a process sensor, a voltage sensor, a temperature sensor, and an aging sensor; The voltage adjustment device is connected with the plurality of sensors, and is configured to, after receiving an operating voltage adjustment instruction of the chip, collect the plurality of detection values, and utilize a voltage model to predict the plurality of detection values to obtain a frequency-voltage mapping relationship of the chip, and based on the frequency-voltage mapping relationship and a target operating frequency of the chip, determine a current operating voltage of the chip, wherein the frequency-voltage mapping relationship is used to describe a minimum operating voltage of the chip at different operating frequencies, the voltage model is trained according to a plurality of sample detection values and sample minimum operating voltages of sample chips at the different operating frequencies, the target operating frequency is an operating frequency to be reached by the chip, and the sample chips include a plurality of corner chips corresponding to different chip states.

7. The chip operating voltage adjustment system according to claim 6, wherein The plurality of sensors include: a process sensor configured to detect a manufacturing process of the chip to obtain a process detection value, wherein the process detection value is used to represent a deviation value of the chip caused by the manufacturing process; a voltage sensor configured to detect a current voltage of a corresponding circuit of the chip to obtain a voltage detection value, wherein the voltage detection value is used to represent a voltage drop of the circuit from a power supply voltage of the chip to the circuit; a temperature sensor configured to detect a current temperature of the chip to obtain a temperature detection value; and an aging sensor configured to detect an aging state of the chip to obtain an aging detection value, wherein the aging detection value is used to represent a deviation value of the chip caused by a change over time.

8. The chip operating voltage adjustment system according to claim 7, wherein The process sensor includes: a plurality of ring oscillators, each of which includes a threshold voltage unit and an interconnection unit ring, and is configured to output an oscillation frequency according to an output current of the threshold voltage unit and a signal propagation time of the interconnection unit ring, wherein the oscillation frequency is used to represent the process detection value, the threshold voltage unit is used to reflect the manufacturing process according to different threshold voltages of transistors, and the interconnection unit ring is used to reflect the manufacturing process according to a layout between different signal lines.

9. The chip operating voltage adjustment system according to claim 6, wherein The system further includes: a voltage regulator configured to determine a voltage margin of the chip, wherein the voltage margin is used to offset a model error caused by the voltage model.

10. A system on chip, characterized by The system includes: any one of claims 7 to 9.

11. An electronic device, comprising: The system includes: a memory storing an executable program; a processor configured to run the program, wherein the program performs the method of any one of claims 1 to 6 when running.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored executable program, wherein the executable program controls a device where the storage medium is located to perform the method of any one of claims 1 to 6 when running.

13. A computer program product, characterised in that, The computer program or instructions include a computer program that, when executed by a processor, implements the method of any one of claims 1 to 6.

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