Storage system and information processing system

Abstract

The invention relates to a storage system and an information processing system to reduce power consumption. According to one embodiment, a memory system includes: a nonvolatile memory including a plurality of memory cells; and a memory controller having a first state in which write data transferred from an external host is written to the nonvolatile memory by a first number of bits per memory cell, and a second state in which write data transferred from the external host is written to the nonvolatile memory by a second number of bits per memory cell. Write data transmitted from an external host is written to the nonvolatile memory by a second number of bits per memory cell, the second number of bits being greater than the first number of bits. The memory controller is configured to transmit information relating to a transfer rate of write data to a host in response to a first request from the host. The information includes first information associated with the first state and second information associated with the second state.

Description

Technical Field

[0001] Embodiments relate to storage systems and information processing systems. Background Art

[0002] An information processing system including a host and a storage system connected to the host is known. The storage system includes a NAND flash memory as a nonvolatile memory and a memory controller for controlling the nonvolatile memory.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2021 / 0294654

[0006] Patent Document 2: U.S. Patent No. 11275620

[0007] Patent Document 3: U.S. Patent Application Publication No. 2021 / 0034536 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Reduce power consumption.

[0010] Technical solutions to solve problems

[0011] The storage system of the embodiment comprises: a nonvolatile memory including a plurality of storage cells; and a memory controller having a first state and a second state, wherein in the first state, write data transmitted from an external host is written to the nonvolatile memory in a manner of a first number of bits per storage cell, and in the second state, write data transmitted from an external host is written to the nonvolatile memory in a manner of a second number of bits per storage cell, the second number of bits being greater than the first number of bits. The memory controller is configured to send information related to a transmission rate of the write data to the host in response to a first request from the host. The information includes first information associated with the first state and second information associated with the second state. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram showing an example of the configuration of the information processing system according to the embodiment.

[0013] Figure 2 This is a block diagram showing an example of a connection configuration between a host and a memory controller according to an embodiment.

[0014] Figure 3This is a diagram showing an example of the data structure of the transfer rate information stored in the storage system according to the embodiment.

[0015] Figure 4 This is a circuit diagram showing an example of the configuration of the nonvolatile memory according to the embodiment.

[0016] Figure 5 FIG. 1 is a diagram showing a first example of threshold voltage distribution of a plurality of memory cell transistors according to the embodiment.

[0017] Figure 6 It is a diagram showing a second example of the threshold voltage distribution of a plurality of memory cell transistors according to the embodiment.

[0018] Figure 7 This is a sequence diagram showing an example of a series of processes including a transmission rate change process in the information processing system according to the embodiment.

[0019] Figure 8 This is a sequence diagram showing an example of a transmission rate change process in the information processing system according to the embodiment.

[0020] Fig. 9 It is a diagram showing an example of the data structure of the transfer rate information stored in the storage system according to the modification.

[0021] Description of Reference Numerals

[0022] 1…Information Processing Systems

[0023] 2…Host

[0024] 3… Storage System

[0025] 6…Equipment interface circuit

[0026] 10…Memory Controller

[0027] 5.11…Control circuit

[0028] 12…Non-volatile memory interface circuit

[0029] 13…Host interface circuit

[0030] 14… Volatile memory

[0031] 15…Buffer memory

[0032] 16, 16A…Transmission rate information

[0033] 20…Non-volatile memory

[0034] 41, 51…Signal processing unit

[0035] 41R, 51R…Receiver

[0036] 41T, 51T…Transmission unit

[0037] 42, 52…Protocol control unit

[0038] 43, 53…Data transceiver DETAILED DESCRIPTION

[0039] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In addition, in the following description, components having the same function and configuration are marked with common reference numerals. In addition, when multiple components having a common reference numeral are to be distinguished, a suffix is ​​marked on the common reference numeral to distinguish them. In addition, when there is no need to distinguish multiple components, only the common reference numeral is marked on the multiple components without a suffix.

[0040] 1. Implementation Method

[0041] 1.1 Composition

[0042] 1.1.1 Information Processing System

[0043] The configuration of the information processing system according to the embodiment will be described.

[0044] Figure 1 1 is a block diagram showing an example of the configuration of an information processing system according to an embodiment. Figure 1 As shown, the information processing system 1 includes a host 2 and a storage system 3 .

[0045] The host 2 is a data processing device that processes data using the storage system 3. The host 2 is, for example, a mobile SoC (System on a Chip) mounted on a smartphone.

[0046] The storage system 3 is a storage device such as UFS (Universal Flash Storage). The storage system 3 performs data writing, reading, and erasing according to a request from the host 2. For example, the storage system 3 supports a write acceleration function that complies with the UFS3.1 standard and the UFS4.0 standard.

[0047] The storage system 3 with the write acceleration function enabled writes data at a higher speed than the storage system 3 with the write acceleration function disabled, thereby improving the write performance. Hereinafter, the state of the storage system 3 with the write acceleration function enabled is also referred to as "high-speed mode". The state of the storage system 3 with the write acceleration function disabled is also referred to as "normal mode".

[0048] 1.1.2 Storage System

[0049] Next, continue to refer to Figure 1 , the internal structure of the storage system 3 is described. The storage system 3 includes a memory controller 10 and a non-volatile memory 20.

[0050] The memory controller 10 is constituted by an integrated circuit such as a SoC (System-on-a-Chip), for example. The memory controller 10 controls the nonvolatile memory 20 based on a request from the host 2 .

[0051] Specifically, for example, the memory controller 10 writes write data to the nonvolatile memory 20 based on a write request from the host 2. In addition, the memory controller 10 reads read data from the nonvolatile memory 20 based on a read request from the host 2. Furthermore, the memory controller 10 sends data based on the read data to the host 2.

[0052] The nonvolatile memory 20 is, for example, a NAND flash memory. The nonvolatile memory 20 includes a plurality of blocks BLK (BLK0 to BLK3). Each block BLK includes a plurality of storage cells. Each storage cell stores data in a nonvolatile manner. The block BLK is, for example, a unit of erasing data.

[0053] 1.1.3 Memory Controller

[0054] Next, continue to refer to Figure 1 , the internal structure of the memory controller 10 is described. The memory controller 10 includes: a control circuit 11, a non-volatile memory interface circuit (NVMI / F) 12, a host interface circuit (host I / F) 13, a volatile memory 14, and a buffer memory 15. The functions of the control circuit 11, the non-volatile memory interface circuit 12, the host interface circuit 13, the volatile memory 14, and the buffer memory 15 described below can be implemented by any of dedicated hardware, a processor that executes a program, or a combination thereof.

[0055] The control circuit 11 is a circuit that controls the entire memory controller 10. The control circuit 11 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory).

[0056] The nonvolatile memory interface circuit 12 is responsible for communication between the memory controller 10 and the nonvolatile memory 20. The nonvolatile memory interface circuit 12 is connected to the nonvolatile memory 20 via a memory bus MB. The memory bus MB complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or ONFI (Open NAND flash interface).

[0057] The host interface circuit 13 is responsible for communication with the host 2. The host interface circuit 13 complies with M-PHY, for example. TM And connect with host 2.

[0058] The volatile memory 14 is, for example, an SRAM (Static Random Access Memory). When the storage system 3 is started, the data stored in the volatile memory 14 is initialized with the value stored in the non-volatile memory 20. The volatile memory 14 stores information on the data transmission rate between the host 2 and the storage system 3. Specifically, for example, the volatile memory 14 stores the transmission rate information 16. In addition, the volatile memory 14 may also be a DRAM (Dynamic Random Access Memory). When the volatile memory 14 is composed of DRAM, the volatile memory 14 is connected to the memory controller 10 via a bus that complies with the DRAM interface standard.

[0059] The transmission rate information 16 stores an optimum transmission rate according to the state of the storage system 3 as capability information. The transmission rate information 16 may be stored in the nonvolatile memory 20. The details of the transmission rate information 16 will be described later.

[0060] The buffer memory 15 is, for example, an SRAM. The buffer memory 15 buffers data between the host 2 and the nonvolatile memory 20. Specifically, the buffer memory 15 temporarily stores write data and read data.

[0061] 1.1.4 Host

[0062] Next, continue to refer to Figure 1 , the internal structure of the host 2 is described. The host 2 includes a control circuit 5 and a device interface circuit (device I / F) 6. The functions of the control circuit 5 and the device interface circuit 6 described below can be implemented by dedicated hardware, a processor executing a program, or any combination thereof.

[0063] The control circuit 5 is a circuit for controlling the entire host computer 2. The control circuit 5 includes, for example, a processor such as a CPU, a ROM, and a RAM.

[0064] The device interface circuit 6 is responsible for communication with the storage system 3. The device interface circuit 6 complies with M-PHY TM And connected to the host interface circuit 13 of the memory controller 10.

[0065] 1.1.5 Connection between host and memory controller

[0066] Figure 2 1 is a block diagram showing an example of a connection structure between a host and a memory controller according to an embodiment of the present invention. Figure 2 , an example of the connection structure between the device interface circuit 6 of the host 2 and the host interface circuit 13 of the memory controller 10 is shown. The host interface circuit 13 includes a signal processing unit 41, a protocol control unit 42, and a data transceiver unit 43. The device interface circuit 6 includes a signal processing unit 51, a protocol control unit 52, and a data transceiver unit 53. The host interface circuit 13 of the memory controller 10 is connected via communication paths LA1, LA2, LB1, and LB2. The communication paths LA1, LA2, LB1, and LB2 are physical channels for data transmission and reception.

[0067] First, the configuration of the host interface circuit 13 will be described.

[0068] The signal processing unit 41 is a circuit corresponding to the physical layer. The signal processing unit 41 complies with, for example, M-PHY TM The signal processing unit 41 includes a receiving unit 41R and a transmitting unit 41T.

[0069] The receiving unit 41R receives a signal from the transmitting unit 51T via the communication paths LA1 and LA2 . The receiving unit 41R extracts a packet from the signal received from the transmitting unit 51T and transfers the packet to the protocol control unit 42 .

[0070] The transmission unit 41T generates a signal based on the data packet received from the protocol control unit 42. The transmission unit 41T transmits the generated signal to the reception unit 51R via the communication paths LB1 and LB2.

[0071] The protocol control unit 42 is a circuit corresponding to the data link layer, the network layer, and the transport layer. The protocol control unit 42 complies with, for example, Unipro TMThe protocol control unit 42 generates a data packet based on the data received from the data transceiver unit 43, and transmits it to the transmitter 41T of the signal processing unit 41. The protocol control unit 42 extracts data from the data packet received from the receiver 41R of the signal processing unit 41, and transmits it to the data transceiver unit 43. In addition, the protocol control unit 42 controls the number of channels and frequency for the receiver 41R to receive signals, and the number of channels and frequency for the transmitter 41T to send signals.

[0072] The data transceiver unit 43 functions as an interface between the host interface circuit 13 and various circuits in the memory controller 10. The data transceiver unit 43 transmits data transmitted from the protocol control unit 42 to various circuits in the memory controller 10. The data transceiver unit 43 transmits data received from various circuits in the memory controller 10 to the protocol control unit 42.

[0073] Next, the configuration of the device interface circuit 6 will be described.

[0074] The signal processing unit 51 is a circuit corresponding to the physical layer. The signal processing unit 51 complies with, for example, M-PHY TM The signal processing unit 51 includes a receiving unit 51R and a transmitting unit 51T.

[0075] The receiving unit 51R receives a signal from the transmitting unit 41T via the communication paths LB1 and LB2 . The receiving unit 51R extracts a packet from the signal received from the transmitting unit 41T and transfers the packet to the protocol control unit 52 .

[0076] The transmission unit 51T generates a signal based on the data packet received from the protocol control unit 52. The transmission unit 51T transmits the generated signal to the reception unit 41R via the communication paths LA1 and LA2.

[0077] The protocol control unit 52 is a circuit corresponding to the data link layer, the network layer, and the transport layer. The protocol control unit 52 is, for example, compliant with Unipro TM The protocol control unit 52 generates a data packet based on the data received from the data transceiver unit 53, and transmits it to the transmitter 51T of the signal processing unit 51. The protocol control unit 52 extracts data from the data packet received from the receiver 51R of the signal processing unit 51, and transmits it to the data transceiver unit 53. In addition, the protocol control unit 52 controls the number of channels and frequency for the receiver 51R to receive signals, and the number of channels and frequency for the transmitter 51T to send signals.

[0078] The data transceiver 53 functions as an interface between the device interface circuit 6 and various circuits in the host 2. The data transceiver 53 transmits data transmitted from the protocol control unit 52 to various circuits in the host 2. The data transceiver 53 transmits data received from various circuits in the host 2 to the protocol control unit 52.

[0079] 1.1.6 Transmission rate information

[0080] Figure 3 This is a diagram showing an example of the data structure of the transfer rate information stored in the storage system according to the embodiment.

[0081] like Figure 3 As shown in FIG. 1 , the transmission rate information 16 stores a parameter A corresponding to the high-speed mode and a parameter B corresponding to the normal mode as parameters for determining the transmission rate. The parameters A and B respectively include a frequency and a number of channels corresponding to the transmission rate (Rx transmission rate) when the storage system 3 receives data from the host 2, and a frequency and a number of channels corresponding to the transmission rate (Tx transmission rate) when the storage system 3 sends data to the host 2.

[0082] Specifically, parameter A includes the frequency f_r1 and the number of channels n_r1 corresponding to the Rx transmission rate in high-speed mode, and the frequency f_t1 and the number of channels n_t1 corresponding to the Tx transmission rate in high-speed mode. In addition, parameter B includes the frequency f_r2 and the number of channels n_r2 corresponding to the Rx transmission rate in normal mode, and the frequency f_t2 and the number of channels n_t2 corresponding to the Tx transmission rate in normal mode.

[0083] The Rx transmission rate and Tx transmission rate in the same mode are set independently of each other. That is, the frequency f_r1 and the number of channels n_r1 are set independently of the frequency f_t1 and the number of channels n_t1, respectively. The frequency f_r2 and the number of channels n_r2 are set independently of the frequency f_t2 and the number of channels n_t2, respectively.

[0084] The Tx transmission rate in the high-speed mode may be equal to or different from the Tx transmission rate in the normal mode.

[0085] The Rx transmission rate in high-speed mode is set to be higher than the Rx transmission rate in normal mode. That is, the Rx transmission rate determined by the frequency f_r1 and the number of channels n_r1 is higher than the Rx transmission rate determined by the frequency f_r2 and the number of channels n_r2. Specifically, for example, when the number of channels n_r1 is equal to the number of channels n_r2, the frequency f_r1 is higher than the frequency f_r2. When the frequency f_r1 is equal to the frequency f_r2, the number of channels n_r1 is 2 and the number of channels n_r2 is 1. In addition, the above-mentioned combination of frequencies f_r1 and f_r2 and numbers of channels n_r1 and n_r2 is only an example, and can be set to any value within the range where the Rx transmission rate in high-speed mode is higher than the Rx transmission rate in normal mode.

[0086] 1.1.7 Non-volatile Memory

[0087] Next, the configuration of the nonvolatile memory 20 will be described. Figure 4 1 is a circuit diagram showing an example of the configuration of a nonvolatile memory according to an embodiment of the present invention. Figure 4 In FIG. 1 , the structure of block BLK0 is shown as an example. The structures of other blocks BLK1 to BLK3 are the same as that of block BLK0. Block BLK0 includes, for example, four string units SU0 to SU3. Figure 4 In FIG. 1 , the configuration of the string units SU2 and SU3 is shown in a simplified manner.

[0088] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0, BL1, ..., and BLm (m is an integer greater than or equal to 2). The NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2.

[0089] The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The selection transistors ST1 and ST2 are respectively used to select the string unit SU in various processes.

[0090] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. A selection transistor ST1 is connected between one end of the memory cell transistors MT0 to MT7 connected in series and the associated bit line BL. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

[0091] In the same block BLK, the gates of the multiple selection transistors ST1 included in the string units SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3. The control gates of the multiple memory cell transistors MT0 to MT7 are commonly connected to the word lines WL0 to WL7. The gates of the multiple selection transistors ST2 are commonly connected to the selection gate line SGS.

[0092] Bit lines BL0 to BLm are shared by a plurality of blocks BLK0 to BLK3. The same bit line BL is connected to NAND strings NS corresponding to the same column address. Word lines WL0 to WL7 are provided in each of blocks BLK0 to BLK3. Source line SL is shared by a plurality of blocks BLK0 to BLK3, for example.

[0093] A collection of multiple memory cell transistors MT connected to a common word line WL in one string unit SU is called a unit group CU, for example, and is used as a data writing unit. For example, the storage capacity of a unit group CU including memory cell transistors MT each storing 1 bit of data is defined as "1 page of data". That is, 1 page of data is a data area having a 1-bit data column with a number of columns corresponding to the number of memory cell transistors MT in the unit group CU. 1 page of data is used as a data reading unit, for example. The unit group CU can have a storage capacity of more than 2 pages of data depending on the number of bits of data stored in the memory cell transistor MT.

[0094] In addition, the circuit structure of the block BLK described above is only an example and is not limited to this. For example, the number of bit lines BL is not limited to more than 3, and can also be 1 or 2. The number of blocks BLK included in the non-volatile memory 20 can be designed to be any number. The number of string units SU included in each block BLK can be designed to be any number. The number of storage cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0095] 1.1.8 Threshold voltage distribution

[0096] The plurality of memory cell transistors MT have different threshold voltage distributions according to the number of bits of stored data. Figure 5 1 is a schematic diagram showing a first example of threshold voltage distribution of a plurality of memory cell transistors MT according to the embodiment. Figure 6 1 is a schematic diagram showing a second example of the threshold voltage distribution of the plurality of memory cell transistors MT according to the embodiment. The first example corresponds to the case where each of the plurality of memory cell transistors MT stores 1-bit data. The second example corresponds to the case where each of the plurality of memory cell transistors MT stores 3-bit data.

[0097] First, refer to Figure 5 , the first example is explained.

[0098] When a plurality of memory cell transistors MT store 1-bit data, the threshold voltage distribution is divided into two. In order of threshold voltage from low to high, the two threshold voltage distributions are called "Er" state and "A" state.

[0099] The "Er" state in the above threshold voltage distribution corresponds to the erased state of the memory cell transistor MT. The threshold voltage in the "Er" state is less than the voltage VA. The threshold voltage in the "A" state is greater than the voltage VA and less than the voltage VREAD. The voltage VREAD is the voltage applied to the non-selected word line during the read process. When the gate is applied with the voltage VREAD, the memory cell transistor MT becomes conductive regardless of the stored data. The relationship between these voltage values ​​is VA<VREAD.

[0100] The two threshold voltage distributions described above correspond to different 1-bit data. That is, the memory cell transistor MT included in the "Er" state stores data "1". The memory cell transistor MT included in the "A" state stores data "0".

[0101] The threshold voltage distribution formed when the plurality of memory cell transistors MT store 1-bit data in this manner is realized by an SLC (Single Level Cell) writing process.

[0102] Next, refer to Figure 6 , the second example is explained.

[0103] When a plurality of memory cell transistors MT store 3-bit data, the distribution of the threshold voltage is divided into 8. In order of the threshold voltage from low to high, the 8 threshold voltage distributions are called "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state and "S7" state.

[0104] The "S0" state in the above threshold voltage distribution corresponds to the erased state of the memory cell transistor MT. The threshold voltage in the "S0" state is less than voltage VS1. The threshold voltage in the "S1" state is greater than voltage VS1 and less than voltage VS2. The threshold voltage in the "S2" state is greater than voltage VS2 and less than voltage VS3. The threshold voltage in the "S3" state is greater than voltage VS3 and less than voltage VS4. The threshold voltage in the "S4" state is greater than voltage VS4 and less than voltage VS5. The threshold voltage in the "S5" state is greater than voltage VS5 and less than voltage VS6. The threshold voltage in the "S6" state is greater than voltage VS6 and less than voltage VS7. The threshold voltage in the "S7" state is greater than voltage VS7 and less than voltage VREAD. The relationship between these voltage values ​​is VS1<VS2<VS3<VS4<VS5<VS6<VS7<VREAD.

[0105] The above-mentioned 8 threshold voltage distributions correspond to different 3-bit data respectively. That is, the memory cell transistor MT contained in the "S0" state stores data "111". The memory cell transistor MT contained in the "S1" state stores data "110". The memory cell transistor MT contained in the "S2" state stores data "100". The memory cell transistor MT contained in the "S3" state stores data "000". The memory cell transistor MT contained in the "S4" state stores data "010". The memory cell transistor MT contained in the "S5" state stores data "011". The memory cell transistor MT contained in the "S6" state stores data "001". The memory cell transistor MT contained in the "S7" state stores data "101".

[0106] The threshold voltage distribution formed when the plurality of memory cell transistors MT store 3-bit data in this manner is realized by TLC (Triple Level Cell) writing processing.

[0107] 1.2 Action

[0108] Next, the operation of the information processing system according to the embodiment will be described.

[0109] 1.2.1 Write Processing

[0110] According to the TLC write process, the same number of memory cell transistors MT can store three times the data as in the case of the SLC write process. Figure 5 and Figure 6 As shown in FIG. 1 , the threshold voltage distribution formed by the SLC write process is a simpler distribution than the threshold voltage distribution formed by the TLC write process. Therefore, when writing data of the same size to the nonvolatile memory 20, the time required for the SLC write process (tProg(SLC)) is shorter than the time required for the TLC write process (tProg(TLC)).

[0111] Therefore, in the storage system 3 in high-speed mode, for example, SLC write processing is performed from the viewpoint of write speed. In addition, in the storage system 3 in normal mode, for example, TLC write processing is performed from the viewpoint of storage capacity. Thus, when writing the same data, the storage system 3 in high-speed mode can notify the host 2 of a write completion notification faster than the storage system 3 in normal mode.

[0112] Furthermore, after the data written by the SLC write process in the high-speed mode is read out from the nonvolatile memory 20 by the background process during a period when there is no request from the host 2, for example, the data is written back to the nonvolatile memory 20 by the write process (for example, the TLC write process) having a higher data integration degree than the SLC write process. The background process is a process that is spontaneously executed by the memory controller 10 without depending on a request from the host 2. Thus, the problem of a reduction in the storage capacity of the nonvolatile memory 20 due to the SLC write process in the high-speed mode is avoided.

[0113] 1.2.2 A series of processes including transmission rate change processing

[0114] Figure 7 This is a sequence diagram showing an example of a series of processes including a transmission rate change process in the information processing system according to the embodiment.

[0115] First, the host 2 and the storage system 3 perform communication establishment processing to establish communication via the communication path (S1). As a result, the signal processing units 41 and 51 are initialized. In this case, the data transmission rate between the host 2 and the storage system 3 is set to an initial value. In other words, the parameter corresponding to the transmission rate is set to the initial parameter INI. The initial parameter INI can be the same as the parameter A or B, or it can be a parameter different from the parameters A and B. In addition, just after the communication with the host 2 is established, the state of the storage system 3 is the normal mode.

[0116] Next, the host 2 and the storage system 3 execute a transfer rate information read process (S2). Specifically, the host 2 issues a transfer rate information read request and sends it to the storage system 3. The storage system 3 sends the transfer rate information 16 to the host 2 in response to the transfer rate information read request.

[0117] The host 2 determines the transmission rate corresponding to the state of the storage system 3 based on the transmission rate information 16 received through the process of S2. Specifically, since the state of the storage system 3 is the normal mode, the host 2 selects the parameter B corresponding to the normal mode from the transmission rate information 16. Then, the host 2 and the storage system 3 perform the transmission rate change process (S3). As a result, the parameter corresponding to the transmission rate of data between the host 2 and the storage system 3 is changed from the initial parameter INI to the parameter B.

[0118] The host 2 and the storage system 3 execute a write process and a read process based on the transfer rate changed by the process of S3 (S4).

[0119] Specifically, the host 2 issues a write request and sends it together with the write data to the storage system 3. The write data is transmitted from the host 2 to the storage system 3 at a frequency f_r2 and a channel number n_r2 corresponding to the Rx transmission rate in the normal mode. The storage system 3 executes a TLC write process corresponding to the normal mode according to the write request and writes the data to the non-volatile memory 20.

[0120] In addition, the host 2 issues a read request and sends it to the storage system 3. According to the read request, the storage system 3 reads data from the nonvolatile memory 20. Then, the storage system 3 sends the read data to the host 2. The read data is transmitted from the storage system 3 to the host 2 at a frequency f_t2 and a channel number n_t2 corresponding to the Tx transmission rate in the normal mode.

[0121] Next, the host 2 decides to write data at a higher speed. In response, the host 2 and the storage system 3 execute a mode change process (S5). As a result, the state of the storage system 3 is changed from the normal mode to the high-speed mode.

[0122] The host 2 determines the transmission rate corresponding to the state of the storage system 3 based on the transmission rate information 16 received in the process of S2. Specifically, since the state of the storage system 3 is changed to the high-speed mode in the process of S5, the host 2 selects the parameter A corresponding to the high-speed mode from the transmission rate information 16. Then, the host 2 and the storage system 3 perform the transmission rate change process (S6). As a result, the parameter corresponding to the transmission rate of data between the host 2 and the storage system 3 is changed from parameter B to parameter A.

[0123] The host 2 and the storage system 3 execute a write process and a read process based on the transfer rate changed by the process of S6 ( S7 ).

[0124] Specifically, the host 2 issues a write request and sends it together with the write data to the storage system 3. The write data is transmitted from the host 2 to the storage system 3 at a frequency f_r1 and a channel number n_r1 corresponding to the Rx transmission rate in the high-speed mode. The storage system 3 executes the SLC write process corresponding to the high-speed mode according to the write request and writes the data to the non-volatile memory 20.

[0125] In addition, the host 2 issues a read request and sends it to the storage system 3. The storage system 3 reads data from the nonvolatile memory 20 according to the read request. Then, the storage system 3 sends the read data to the host 2. The read data is transmitted from the storage system 3 to the host 2 at a frequency f_t1 and a channel number n_t1 corresponding to the Tx transmission rate in the high-speed mode.

[0126] When the write process and the read process of S7 are completed, the host 2 decides to return the state of the storage system 3 to the normal mode. In response to this, the host 2 selects parameter B corresponding to the normal mode based on the transmission rate information 16 received through the process of S2. Then, the host 2 and the storage system 3 perform the transmission rate change process (S8). As a result, the parameter corresponding to the data transmission rate between the host 2 and the storage system 3 is changed from parameter A to parameter B.

[0127] Next, the host 2 and the storage system 3 execute a mode change process (S9). As a result, the state of the storage system 3 is changed from the high-speed mode to the normal mode.

[0128] Then, the host 2 and the storage system 3 execute writing and reading processes based on the transfer rate changed by the process of S9 (S10). The writing and reading processes of S10 are the same as the writing and reading processes of S4.

[0129] As described above, the host 2 and the storage system 3 select an appropriate transfer rate according to the state of the storage system 3 and execute a series of processes.

[0130] 1.2.3 Transmission rate change processing

[0131] Figure 8 This is a sequence diagram showing an example of a transmission rate change process in the information processing system according to the embodiment. Figure 8 Corresponds to Figure 7 Details of the processing of S3, S6 and S8 in Figure 8 , details of the communication between the control circuit 5, the protocol control unit 52 and the signal processing unit 51 in the host 2, and the control circuit 11, the protocol control unit 42 and the signal processing unit 41 in the memory controller 10 during the transmission rate change process are shown.

[0132] First, the control circuit 5 of the host 2 issues a request to change the transmission rate and transmits it to the protocol control unit 52 via the data transceiver unit 53 (S11). The request to change the transmission rate includes, for example, information on the frequency and number of channels corresponding to the desired transmission rate.

[0133] When receiving the request to change the transmission rate, the protocol control unit 52 instructs the signal processing unit 51 to inquire the memory controller 10 whether the transmission rate can be changed (S12). Specifically, for example, the protocol control unit 52 generates an inquiry packet inquiring whether the transmission rate can be changed and sends it to the signal processing unit 51.

[0134] When receiving the inquiry packet generated by the process of S12 , the signal processing unit 51 generates an inquiry signal based on the inquiry packet and transmits it to the signal processing unit 41 of the memory controller 10 ( S13 ).

[0135] When receiving the inquiry signal generated by the process of S13, the signal processing unit 41 detects the inquiry packet from the inquiry signal and sends it to the protocol control unit 42 (S14).

[0136] When receiving the inquiry packet detected in the process of S14, the protocol control unit 42 checks whether the transfer rate can be changed (S15). Specifically, the protocol control unit 42 checks whether the memory controller 10 supports the frequency and number of channels corresponding to the transfer rate desired by the host 2.

[0137] The protocol control unit 42 instructs the signal processing unit 41 to respond to the inquiry from the host 2 ( S16 ). Specifically, for example, the protocol control unit 42 generates a response packet including the confirmation result based on the process of S15 and transmits it to the signal processing unit 41 .

[0138] When receiving the response data packet generated by the process of S16, the signal processing unit 41 generates a response signal based on the response data packet and transmits it to the signal processing unit 51 of the host 2 (S17).

[0139] When receiving the response signal generated by the process of S17, the signal processing unit 51 detects a response data packet from the response signal and sends it to the protocol control unit 52 (S18).

[0140] When receiving the response packet detected by the process of S18, the protocol control unit 52 confirms the response to the inquiry of whether the transfer rate can be changed (S19). Specifically, the protocol control unit 52 understands whether the memory controller 10 supports the frequency and number of channels corresponding to the transfer rate desired by the host 2 based on the response packet.

[0141] When the memory controller 10 corresponds to the frequency and the number of channels corresponding to the transfer rate desired by the host 2, the protocol control unit 52 instructs the signal processing unit 51 to stop transmitting data to the memory controller 10 at the current transfer rate and start changing the setting to a new transfer rate (S20). In addition, the protocol control unit 52 generates a transfer stop packet and sends it to the signal processing unit 51. The transfer stop packet instructs to stop transmitting data from the memory controller 10 to the host 2 at the current transfer rate.

[0142] When receiving the transfer stop packet generated by the process of S20 , the signal processing unit 51 generates a transfer stop signal based on the stop packet and transmits it to the signal processing unit 41 of the memory controller 10 ( S21 ).

[0143] When receiving the instruction to stop transmission and change settings generated by the process of S20, the signal processing unit 51 stops transmitting data to the memory controller 10 and changes the transmission rate settings (S22). Thus, the transmission rate settings in the signal processing unit 51 are changed.

[0144] When receiving the transmission stop signal generated by the process of S21, the signal processing unit 41 detects a transmission stop packet from the transmission stop signal and sends it to the protocol control unit 42 (S23).

[0145] When receiving the transmission stop data packet detected by the process of S23, the protocol control unit 42 instructs the signal processing unit 41 to stop transmitting data to the host 2 at the current transmission rate and start changing the setting to a new transmission rate (S24). In addition, the protocol control unit 42 may also set the transmission rate for which the changeability is confirmed by the process of S15 as the new transmission rate of the setting change target.

[0146] When receiving the transmission stop and setting change instruction generated by the process of S24, the signal processing unit 41 stops transmitting data to the host 2 and changes the transmission rate setting (S25). Thus, the transmission rate setting in the signal processing unit 41 is changed.

[0147] After the process of S25, the signal processing unit 41 notifies the protocol control unit 42 that the setting change of the transmission rate is completed (S26).

[0148] The protocol control unit 42 transmits the notification received from the signal processing unit 41 through the process of S26 to the control circuit 11 ( S27 ).

[0149] Similarly, after the process of S22, the signal processing unit 51 notifies the protocol control unit 52 that the setting change of the transmission rate is completed (S28).

[0150] The protocol control unit 52 transmits the notification received from the signal processing unit 51 through the process of S28 to the control circuit 5 ( S29 ).

[0151] After the processing of S27 and S29, the transmission rate change processing ends.

[0152] 1.3 Effects of implementation methods

[0153] According to the embodiment, the memory controller 10 is configured to send the transfer rate information 16 including information on the transfer rate of write data to the host 2 in response to a transfer rate information read request from the host 2. The transfer rate information 16 includes the frequency f_r1 and the number of channels n_r1 associated with the high-speed mode of the storage system 3, and the frequency f_r2 and the number of channels n_r2 associated with the normal mode. Thus, the host 2 can identify the optimal transfer rate when the storage system 3 operates in the high-speed mode and the optimal transfer rate when the storage system 3 operates in the normal mode.

[0154] In addition, the writing performance of the storage system 3 is limited by the time tProg required for the writing process. That is, if the transmission rate is sufficiently higher than the speed of the writing process, the transmission rate will not contribute to the writing performance. Therefore, an excessively high transmission rate will not only not contribute to the improvement of the writing performance, but will also cause an increase in power consumption, and is therefore not preferred.

[0155] According to the embodiment, the host 2 can change the transfer rate according to the state of the storage system 3. Specifically, when the storage system 3 is operated in the normal mode, the host 2 applies a transfer rate lower than the transfer rate applied in the high-speed mode. Therefore, it is possible to reduce power consumption while maintaining the maximum write performance corresponding to the state of the storage system 3.

[0156] 2. Modifications, etc.

[0157] Various modifications can be applied to the above-described embodiment.

[0158] 2.1 Variations

[0159] In the above-mentioned embodiment, the case where the number of channels and the frequency are stored as parameters related to the optimal transmission rate in the transmission rate information 16 in association with the state of the storage system 3 is described, but the present invention is not limited thereto. For example, the parameter related to the optimal transmission rate may be stored in association with the number of bits written to each storage unit by the write process.

[0160] Fig. 9 It is a diagram showing an example of the data structure of the transfer rate information stored in the storage system according to the modification.

[0161] like Fig. 9 As shown, the frequency f_r1 and the number of channels n_r1 corresponding to the Rx transmission rate in the high-speed mode, and the frequency f_t1 and the number of channels n_t1 corresponding to the Tx transmission rate in the high-speed mode are the same as those in the embodiment. Figure 3The transmission rate information 16 shown is similar. That is, the frequency f_r1 and the number of lanes n_r1 corresponding to the Rx transmission rate in the high-speed mode, and the frequency f_t1 and the number of lanes n_t1 corresponding to the Tx transmission rate in the high-speed mode are included in the parameter A. The parameter A is associated with the SLC write process.

[0162] In the transmission rate information 16A, the parameters corresponding to the Rx transmission rate in the normal mode are further classified into two parameters B and C. Parameters B and C are associated with the TLC write process and the QLC (Quadruple Level Cell) write process, respectively. The QLC write process is a write process that causes one memory cell transistor MT to store 4 bits of data. That is, when writing data of the same size to the nonvolatile memory 20, the time required for the QLC write process (tProg(QLC)) is longer than the time required for the TLC write process (tProg(TLC)).

[0163] Parameter B includes the frequency f_r2_1 and the number of channels n_r2_1 corresponding to the Rx transmission rate in the normal mode when performing TLC write processing. Parameter C includes the frequency f_r2_2 and the number of channels n_r2_2 corresponding to the Rx transmission rate in the normal mode when performing QLC write processing. In addition, the frequency f_t2 and the number of channels n_t2 corresponding to the Tx transmission rate in the normal mode are included in parameters B and C.

[0164] The Rx transmission rate in high-speed mode is set to be higher than the Rx transmission rate in normal mode. That is, the Rx transmission rate determined by the frequency f_r1 and the number of channels n_r1 is higher than the Rx transmission rate determined by the frequency f_r2_1 and the number of channels n_r2_1 and the Rx transmission rate determined by the frequency f_r2_2 and the number of channels n_r2_2. In addition, the Rx transmission rate in normal mode when performing TLC write processing is set to be higher than the Rx transmission rate in normal mode when performing QLC write processing.

[0165] By sending the above-mentioned transmission rate information 16A from the storage system 3 to the host 2, the host 2 can grasp the optimal transmission rate corresponding to the number of bits written to each storage unit by the write process. Thus, when the state of the storage system 3 is the normal mode, the host 2 can transmit data at different transmission rates when the storage system 3 is caused to perform TLC write processing and when the storage system 3 is caused to perform QLC write processing. Therefore, by selecting a transmission rate corresponding to the length of time required for the write process, the increase in power consumption during data transmission can be further suppressed.

[0166] 2.2 Others

[0167] In addition, in the above-mentioned embodiment, the case where the frequency and the number of channels are stored as the transmission rate information 16 is described, but the present invention is not limited thereto. For example, information indicating a mode of a prescribed transmission rate may also be stored in the transmission rate information 16. Specifically, for example, when the storage system 3 is UFS, "HS-G5B2Lane" and "HS-G4B1Lane" may be stored as parameters A and B of the transmission rate information 16, respectively.

[0168] In addition, in the above-mentioned embodiment, the storage system 3 is described as a UFS, but it is not limited to this. For example, the storage system 3 may also be an SD card. TM In this case, the communication between the device interface circuit 6 and the host interface circuit 13 may also comply with PCIe TM (Peripheral Component Interconnect express, peripheral component interconnect express).

[0169] In addition, in the above-mentioned embodiment, the following case is envisioned: two-channel communication paths LA1 and LA2 are provided as physical communication paths for the memory controller 10 to receive data from the host 2, and two-channel communication paths LB1 and LB2 are provided as physical communication paths for the memory controller 10 to send data to the host 2, but the present invention is not limited thereto. For example, the communication path for the memory controller 10 to receive data from the host 2 and the communication path for the memory controller 10 to send data to the host 2 may each be provided with three or more channels.

[0170] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A storage system comprising: a nonvolatile memory comprising a plurality of memory cells; and A memory controller having a first state and a second state, wherein in the first state, write data transmitted from an external host is written into the nonvolatile memory in a manner of a first bit number per storage cell, and in the second state, write data transmitted from an external host is written into the nonvolatile memory in a manner of a second bit number per storage cell, the second bit number being different from the first bit number, The memory controller is configured to send information on a transfer rate of the write data to the host in response to a first request from the host, The information includes: first information associated with the first state; and Second information associated with the second state.

2. The storage system according to claim 1, The first information and the second information each include at least one of the number of channels and the frequency of a bus used to transmit the write data from the host.

3. The storage system according to claim 2, The first information includes the first channel number and the first frequency, The second information includes the second channel number and the second frequency, When the first number of channels is equal to the second number of channels, the first frequency is higher than the second frequency. When the first frequency is equal to the second frequency, the first number of channels is greater than the second number of channels.

4. The storage system according to claim 1, The memory controller is configured as follows: In the first state, the write data is received from the host at a first transfer rate, In the second state, the write data is received from the host at a second transfer rate that is different from the first transfer rate.

5. The storage system according to claim 4, The memory controller is configured as follows: In the first state, data is sent to the host at a third transmission rate that is independent of the first transmission rate, In the second state, data is transmitted to the host at a fourth transmission rate independent of the second transmission rate.

6. The storage system according to claim 4, The first bit number is smaller than the second bit number, The first transmission rate is higher than the second transmission rate.

7. The storage system according to claim 1, The first bit number is smaller than the second bit number, The memory controller in the first state is configured as follows: In response to a write request from the host, a first write process is executed to write the write data into the nonvolatile memory in the form of the first number of bits per storage unit. After the first write process is completed, the host is notified of the completion of the write process, After the notification, the write data is read from the nonvolatile memory, and a second write process is performed to write the write data into the nonvolatile memory in the form of the second number of bits per memory cell.

8. The storage system according to claim 7, The memory controller in the first state is configured to execute the second write process independently of a request from the host.

9. The storage system according to claim 7, The time for writing the write data into the nonvolatile memory by the first write process is shorter than the time for writing the write data into the nonvolatile memory by the second write process.

10. The storage system according to claim 7, The first bit number is 1.

11. The storage system according to claim 1, The memory controller further has a third state, in which the write data is written into the nonvolatile memory in a manner of a third number of bits per storage cell. The information further includes third information associated with the third state, The third bit number is different from the first bit number and the second bit number.

12. An information processing system comprising: Host; and Storage systems, The storage system comprises: A non-volatile memory including a plurality of storage units; and A memory controller having a first state and a second state, wherein in the first state, write data transmitted from the host is written into the nonvolatile memory in a manner of a first bit number per storage unit, and in the second state, write data transmitted from the host is written into the nonvolatile memory in a manner of a second bit number per storage unit, the second bit number being different from the first bit number, The memory controller is configured to send information on a transfer rate of the write data to the host in response to a first request from the host, The information includes: first information associated with the first state; and Second information associated with the second state.

13. The information processing system according to claim 12, The first information and the second information each include at least one of the number of channels and the frequency of a bus used to transmit the write data from the host.

14. The information processing system according to claim 12, The main mechanism is composed of: When the memory controller is operated in the first state, the write data is sent to the memory controller at a first transfer rate based on the first information, When the memory controller is operated in the second state, the write data is transmitted to the memory controller at a second transfer rate different from the first transfer rate based on the second information.

15. The information processing system according to claim 14, The first bit number is smaller than the second bit number, The first transmission rate is higher than the second transmission rate.

16. The information processing system according to claim 12, The first bit number is smaller than the second bit number, The memory controller in the first state is configured as follows: In response to a write request from the host, a first write process is executed to write the write data into the nonvolatile memory in the form of the first number of bits per storage unit. After the first write process is completed, the host is notified of the completion of the write process, After the notification, the write data is read from the nonvolatile memory, and a second write process is performed to write the write data into the nonvolatile memory in the form of the second number of bits per memory cell.

17. The information processing system according to claim 16, The memory controller in the first state is configured to execute the second write process independently of a request from the host.

18. The information processing system according to claim 16, The time for writing the write data into the nonvolatile memory by the first write process is shorter than the time for writing the write data into the nonvolatile memory by the second write process.

19. The information processing system according to claim 16, The first bit number is 1.

20. The information processing system according to claim 12, The storage system is a universal flash memory.

21. The information processing system according to claim 20, The first state is a state in which the write acceleration function is enabled. The second state is a state in which the write acceleration function is disabled.

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