A cache management method, device, controller and medium of a storage array

Abstract

The application relates to the technical field of storage, in particular to a cache management method and device of a storage array, a controller and a medium. The method comprises the following steps: mapping a storage array into a virtual logical address space according to a namespace; dividing the virtual logical address space into virtual logical address groups; determining the activity degree of cached data in the virtual logical address groups according to the storage state corresponding to the virtual logical address groups; and determining a target virtual logical address group which needs to be stored into the storage array according to the activity degree. Therefore, the application can effectively solve the problem of low data reading and writing efficiency of the storage array data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a cache management method and device of a storage array, a controller and a medium. BACKGROUND

[0002] An independent redundant storage array can combine multiple physical hard disks into a logical hard disk, and provide higher storage performance than a single hard disk by accessing multiple physical hard disks in parallel. In addition, data redundancy protection is also provided for the storage array, that is, the write data is encoded by a redundant computing unit to generate redundant check information, and finally the check information and the original write data are saved in the storage array together to facilitate data recovery after a fault occurs.

[0003] In the prior art, the execution logic of the NVMe master is not designed based on the redundant storage array, but is managed by a remote host, so that the entire data end cannot take advantage of the independent redundant storage array, resulting in a long processing time and low data processing efficiency. SUMMARY

[0004] Therefore, the embodiments of the present application provide a cache management method and device of a storage array, a controller and a medium, which can effectively solve the problem of low data read / write efficiency of the storage array and the like.

[0005] In a first aspect, the embodiments of the present application provide a cache management method of a storage array, applied to a storage array controller, comprising:

[0006] mapping the storage array into a virtual logical address space according to a namespace, and dividing the virtual logical address space into a virtual logical address group;

[0007] determining the activity level of the cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group;

[0008] determining the target virtual logical address group that needs to be stored in the storage array according to the activity level.

[0009] In some embodiments, dividing the virtual logical address space into a virtual logical address group comprises:

[0010] dividing the virtual logical address space according to a preset number of namespaces to obtain a number of virtual logical address subspaces equal to the preset number;

[0011] dividing each continuous logical address block in the virtual logical address subspace into a namespace array according to a redundancy mode of the storage array; dividing the namespace array into a plurality of virtual logical address groups by taking a row of the logical address blocks in the namespace array as a stripe, wherein the number of the logical address blocks in the stripe is the same as the number of redundancy group members in the storage array, and the virtual logical address group comprises one or more stripes.

[0012] In some embodiments, the determining of the target virtual logical address group that needs to be stored in the storage array according to the activity degree comprises:

[0013] determining target cache data in the target virtual logical address group that needs to be stored in the storage array according to the storage state.

[0014] In some embodiments, the storage state comprises a read-write state flag corresponding to each logical address block in the virtual logical address group.

[0015] The determining of the target cache data in the target virtual logical address group that needs to be stored in the storage array according to the storage state comprises:

[0016] determining cache data of a logical address block corresponding to a read-write state flag in the target virtual logical address group as the target cache data.

[0017] In some embodiments, the method further comprises:

[0018] In the writing of the target cache data into the storage array, performing redundancy calculation on cache data in each logical address block in the stripe to obtain check data and write the check data into a check block in the stripe; and setting a read-write state flag corresponding to the check block to the write state.

[0019] In some embodiments, the method further comprises updating the corresponding storage state according to a read-write operation on each virtual logical address group corresponding to a namespace in the cache respectively, and specifically comprising:

[0020] if the data stored in the logical address block in the cache is first data, setting a read-write state flag corresponding to the logical address block to a write state, wherein the first data is write data sent by a remote host;

[0021] if the data stored in the logical address block in the cache is second data, setting a read-write state flag corresponding to the logical address block to a read state, wherein the second data is empty data or read data read from the storage array.

[0022] In some embodiments, the storage state comprises a full-write flag corresponding to each virtual logical address group.

[0023] The method further comprises:

[0024] determining whether each read-write state flag corresponding to each logical address block in the virtual logical address group is in the write state, to obtain a block number of the logical address block whose read-write state flag is in the write state;

[0025] if the block number is greater than a preset threshold, determining that a full-write flag corresponding to the virtual logical address group is in a full-write state;

[0026] The method further comprises: taking the virtual logical address group corresponding to the full-write flag in the full-write state as the target virtual logical address group.

[0027] In some embodiments, the determining, according to the storage state, of target cache data in the target virtual logical address group that needs to be stored in the storage array comprises:

[0028] cache data in a target logical address block in the target virtual logical address group as the target cache data; wherein the target logical address block is a logical address block in the target virtual logical address group corresponding to the read-write state flag in the write state.

[0029] In some embodiments, the determining, according to the activity level, of a target virtual logical address group that needs to be stored in the storage array comprises:

[0030] determining the virtual logical address group with a low activity level as the target virtual logical address group;

[0031] and / or, when the cache space is full, determining the virtual logical address group with an intermediate activity level as the target virtual logical address group.

[0032] In some embodiments, the storage state comprises a number of activity factor flags corresponding to each virtual logical address group;

[0033] The method further comprises: updating the corresponding storage state according to the read-write operation command of each namespace corresponding to the virtual logical address group in the cache respectively, specifically comprising:

[0034] setting the corresponding activity factor flag value according to the frequency of receiving the read-write operation command of the virtual logical address group.

[0035] In some embodiments, the setting the corresponding activity factor flag value according to the frequency of receiving the read-write operation command of the virtual logical address group comprises:

[0036] counting according to the virtual logical address group as the object according to a preset frequency and counting period;

[0037] In the counting period, according to whether the read-write operation command is received by the virtual logical address group, the active factor flag value is updated according to a preset updating rule.

[0038] In some embodiments, the updating of the active factor flag value in the counting period according to whether the read-write operation command is received by the virtual logical address group comprises:

[0039] If the read-write operation command is not received in the counting period, each bit of the active factor flag value is searched according to a set bit order, and a second state value is written in the bit corresponding to the first state value; wherein the value of each bit of the active factor flag value is the first state value at the initial state.

[0040] If the read-write operation command is received in the counting period, each bit of the active factor flag value is searched according to an order opposite to the set bit order, and a first state value is written in the bit corresponding to the second state value.

[0041] In some embodiments, the determination of the activity level of the cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group comprises:

[0042] If the number of each bit of the active factor flag value corresponding to the virtual logical address group is the second state value, the activity level of the cached data in the virtual logical address group is determined as a low activity level.

[0043] If the number of each bit of the active factor flag value corresponding to the virtual logical address group is the first state value, the activity level of the cached data in the virtual logical address group is determined as a high activity level.

[0044] The number of bits of the active factor flag value whose number is the first state value is counted.

[0045] If the number of bits is greater than a preset number, the activity level of the cached data in the virtual logical address group is determined as an intermediate activity level.

[0046] In some embodiments, the virtual logical address group is the granularity of the read-write operation command.

[0047] The storage state comprises a number of lock flag bits equal to the number of virtual logical address groups.

[0048] The method further comprises:

[0049] setting a lock flag corresponding to the current virtual logical address group to a lock state when operating the current virtual logical address group according to the read-write operation command;

[0050] delaying a read-write operation command accessing the virtual logical address group in the lock state.

[0051] In some embodiments, the target virtual logical address group needing to be stored in the storage array is determined according to the activity level.

[0052] According to the virtual logical address group and a preset logical address mapping relationship, a target logical address in the storage array to which the target cache data is stored is determined.

[0053] The target cache data is written into the storage array according to the target logical address.

[0054] In a second aspect, embodiments of the present application provide a cache management device of a storage array, comprising: an address group division module, an activity level determination module and a disk falling module.

[0055] The address group division module is configured to map the storage array into a virtual logical address space according to a namespace, and divide the virtual logical address space into virtual logical address groups.

[0056] The activity level determination module is configured to determine an activity level of cache data in the virtual logical address group according to a storage state corresponding to the virtual logical address group.

[0057] The disk falling module is configured to determine a target virtual logical address group needing to be stored in the storage array according to the activity level.

[0058] In a third aspect, embodiments of the present application provide a control system of a storage array, comprising: a redundancy module, a non-volatile memory interface controller, a cache and a non-volatile storage control module; one end of the non-volatile memory interface controller is configured to connect a remote host, and the other end is connected to the redundancy module, the redundancy module is connected to a storage array through the non-volatile storage control module; the non-volatile memory interface controller is configured to process connection with the remote host, and maintain and manage a command queue between the remote host; the non-volatile storage control module interacts with the storage array to read and write data through a direct memory access technology; and the redundancy module is connected to the cache.

[0059] The redundancy module implements a cache management method of a storage array provided in the first aspect of the present application.

[0060] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium storing a computer program, which, when executed on a processor, implements the cache management method of the storage array according to the first aspect of the present application.

[0061] The embodiments of the present application have the following beneficial effects:

[0062] The embodiments of the present application map the storage array into a virtual logical address space according to a namespace, divide the virtual logical address space into virtual logical address groups, determine the activity degree of the cache data in the virtual logical address groups according to the storage state corresponding to the virtual logical address groups, and determine the target virtual logical address group to be stored in the storage array according to the activity degree. The remote host of the present application performs read and write access to the storage array according to the namespace. The present application further divides the virtual logical address space mapped by the namespace into virtual logical address groups, and determines to store the cache data in the virtual logical address groups into the storage array according to the activity degree. The present application manages the virtual logical address by grouping, thereby ensuring that there is enough cache space available in the cache, and speeding up the processing speed of the read and write operation commands. In addition, the cache data is stored according to the activity degree, which further ensures that there is enough cache space available. Thus, the present application can effectively solve the problem of low data read and write efficiency of the storage array. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0064] Figure 1 A structural block diagram of the storage array controller of the embodiments of the present application is shown;

[0065] Figure 2 Another structural block diagram of the storage array controller of the embodiments of the present application is shown;

[0066] Figure 3 A flowchart of the cache management method of the storage array of the embodiments of the present application is shown;

[0067] Figure 4 A redundancy group schematic diagram in the cache management method of the storage array of the embodiments of the present application is shown;

[0068] Figure 5 A namespace array schematic diagram in the cache management method of the storage array of the embodiments of the present application is shown;

[0069] Figure 6 Fig. 1 shows a flow chart of the cache management method of the storage array according to an embodiment of the present application, in which the active factor flag is all 0;

[0070] Figure 7 Fig. 2 shows a schematic diagram of the LBAG to be cleared in the cache management method of the storage array according to an embodiment of the present application, in which the active factor flag is all 0;

[0071] Figure 8 Fig. 3 shows a flow chart of the cache management method of the storage array according to an embodiment of the present application, in which the cache space corresponding to the current namespace is not enough for use;

[0072] Figure 9 Fig. 4 shows a schematic diagram of the cache management device of the storage array according to an embodiment of the present application;

[0073] Figure 10 Fig. 5 shows a schematic diagram of the namespace array in the namespace-based cache management method according to an embodiment of the present application;

[0074] Figure 11 Fig. 6 shows a schematic diagram of the namespace group in the namespace-based cache management method according to an embodiment of the present application;

[0075] Figure 12 Fig. 7 shows a schematic diagram of the division of the controller memory in the namespace-based cache management method according to an embodiment of the present application;

[0076] Figure 13 Fig. 8 shows a schematic diagram of the stripe in the data read-write method of the storage array according to an embodiment of the present application.

[0077] Main element symbol explanation:

[0078] 100 - storage array controller; 200 - non-volatile storage array; 300 - remote host; 110 - storage interface control module; 111 - message analysis module; 112 - command queue processing module; 113 - processor; 120 - redundancy module; 130 - non-volatile storage control module; 140 - controller memory; 150 - protocol offload engine; 910 - address group division module; 920 - activity determination module; 930 - disk writing module. DETAILED DESCRIPTION

[0079] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application.

[0080] The components of the application embodiments described and illustrated herein can be arranged and designed in a wide variety of different configurations. Therefore, the following detailed description of the application, read with reference to the accompanying drawings, is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of applications. The description of the embodiments of applications based herein will allow for all embodiments that can be made without doing inventive work falling within the scope of protection of the application.

[0081] Hereinafter, the terms "include", "have", and their conjugates herein can only mean to indicate a certain characteristic, number, step, operation, element, component or a combination thereof, and should not be construed as excluding the existence or possibility of adding one or more other characteristics, numbers, steps, operations, elements, components or combinations thereof. In addition, the terms "first", "second", "third", and the like are used only to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0082] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the application belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the contextual meaning in the relevant technical fields and will not be interpreted in an idealized or overly formal sense, unless clearly defined in various embodiments of the application.

[0083] Some embodiments of the application are described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0084] The following first introduces the key words involved in the application:

[0085] PCIe: peripheral component interconnect express, high-speed serial computer expansion bus standard.

[0086] NVMe: non volatile memory express, non-volatile high-speed transmission bus.

[0087] NVMe oF specification: the non-volatile memory express over fabrics (NVMe oF) specification is a storage network protocol. At present, the storage device based on NVMe oF usually adopts a multi-node architecture (the node can also be understood as a kind of controller) to realize the access of the host to the storage device, so as to improve the reliability and continuity of the storage service. The NVMe oF specification is a high-speed storage protocol based on the NVMe protocol, and NVMe oF is used to access NVMe storage media across a network. NVMe oF adds fabric-related commands based on NVMe, so that the application scenario of NVMe is not limited to one device, but can be extended to cross-network communication. Wherein, the so-called "fabric" refers to the network between the host and the storage medium. The typical form of fabric is, for example, Ethernet, fiber channel, InfiniBand (IB), direct memory access RDMA, etc.

[0088] SSD: Solid State Drive, solid state drive.

[0089] HBM: High Bandwidth Memory, high bandwidth memory.

[0090] The storage array in the present application includes a non-volatile storage array, and the embodiments of the present application are described based on the non-volatile storage array.

[0091] Figure 1 A structural block diagram of a storage array controller of an embodiment of the present application is shown. Exemplarily, the storage array controller 100 includes a storage interface control module 110, a redundancy module 120, a non-volatile storage control module 130 and a controller memory 140.

[0092] The redundancy module 120 is connected to the storage interface control module 110, the non-volatile storage control module 130 and the controller memory 140 respectively. Exemplarily, the controller memory 140 can adopt HBM.

[0093] The storage interface control module 110 is in communication connection with a remote host 300, and is used to receive and analyze the message data sent by the remote host 300 to obtain an operation command, and transmit the operation command to the redundancy module 120 after scheduling management based on a namespace.

[0094] Further, as Figure 2As shown, the storage interface control module 110 includes a packet parsing module 111, a command queue processing module 112, and a processor 113. The storage array controller 100 also includes a protocol offload engine 150.

[0095] The protocol offload engine 150 is configured to receive a protocol packet of a preset protocol type sent by the remote host 300, parse the protocol packet, and send the parsed packet data to the packet parsing module 111 in the storage interface control module 110.

[0096] The processor 113 is connected to the packet parsing module 111 and the command queue processing module 112.

[0097] The packet parsing module 111 is configured to receive and parse the packet data sent by the remote host 300 to obtain an operation command, send a data transfer type operation command to the command queue processing module 112, and send a non-data transfer type operation command to the processor 113.

[0098] The processor 113 is configured to establish a connection with the remote host 300 according to the operation command, and configure a scheduling function parameter of the command queue processing module 112.

[0099] The command queue processing module 112 is configured to store the operation command in a corresponding namespace command queue according to an accessed target namespace, perform scheduling management, and sequentially transmit the operation command to the redundancy module 120.

[0100] The redundancy module 120 is configured to write data into the controller memory 140 after performing redundancy calculation, and manage a logical address space of the non-volatile storage array 200 and the controller memory 140 based on the namespace.

[0101] The non-volatile storage control module 130 is communicatively connected to the non-volatile storage array 200, and is configured to map the controller memory 140 to implement data interaction with the non-volatile storage array 200 in response to a data transmission request of the redundancy module 120.

[0102] Exemplarily, taking a write command as an example, the storage array controller 100 of the embodiment of the present application is introduced. In the example, the storage interface control module 110 adopts an NVMe-oF controller, the non-volatile storage control module 130 adopts an NVMe-PCIe host, the protocol offload engine 150 adopts a TOE module (TCP / IP Offload Engine), and the controller memory 140 adopts an HBM. The specific processing process of the storage array controller 100 includes the following steps:

[0103] S111, the TOE module receives a protocol packet of a preset protocol type sent by the remote host 300, parses the protocol packet, and sends the parsed protocol packet data to the NVMe-oF controller. The protocol packet of the preset protocol type can be a TCP / IP / Ethernet packet, and the protocol packet data is a data part in the TCP / IP / Ethernet packet.

[0104] S112, the message parsing module 111 in the NVMe-oF controller receives and parses the protocol packet data sent by the remote host 300, obtains an operation command, and sends the data transmission type operation command to the IOQ processing module. The operation command includes a PDU (Protocol Data Unit), and the operation command is determined to be of the data transmission type according to the PDU, that is, the operation command is a write operation command.

[0105] S113, the IOQ processing module stores the write operation command in the corresponding namespace command queue according to the accessed target namespace, performs scheduling management, and sequentially transmits the write operation command to the redundancy module 120. In addition, the write operation command can also be added to a read-write command queue, a priority command queue, or the like. When the IOQ processing module executes the write operation command of the write data, the IOQ processing module sends an instruction command to the redundancy module 120 to instruct the redundancy module 120 to prepare an idle first cache sub-space to receive the to-be-written data.

[0106] S114, the redundancy module 120 queries the cache state table to determine whether there is enough cache space in the controller memory 140 to receive the to-be-written data.

[0107] The redundancy module 120 needs to determine whether the controller memory 140 has the address space of the corresponding LBA block. If it does, but the LBA block is in the state of the last command not being completed, the write command is temporarily processed, and the corresponding LBA block is unlocked; if the controller memory 140 does not have the address space of the corresponding LBA block, the redundancy module 120 allocates a free first cache subspace in the controller memory 140 according to the target logical address of the write operation command, and returns an R2T command to the remote host 300, the R2T command being used to instruct the remote host 300 to send the data to be written.

[0108] If there is not enough cache space, the data in the corresponding namespace is actively written to the disk to free up cache space.

[0109] S115, after the remote host 300 receives the R2T command, the data to be written is also sent out in the form of a TCP / IP / Ethernet packet, and then parsed by the TOE module and the packet parsing module 111, and sent to the redundancy module 120 by the IOQ processing module.

[0110] S116, the redundancy module 120 performs data block division and check block calculation according to the current redundancy mode of the non-volatile storage array 200.

[0111] First, the redundancy module 120 needs to perform data integrity verification on the data to be written, and verify whether the data is consistent according to the DIF (Data Integrity Field).

[0112] After the integrity verification, the redundancy calculation is performed, such as k+m, the data is divided into k parts, and m parts of check data are calculated according to the k parts of data coding, and the k+m parts of data obtained after the redundancy calculation are written to the controller memory 140.

[0113] The corresponding CQ (Completion Queque) is sent to the remote host 300 to notify the remote host 300 that the data writing is completed. Since the redundancy module 120 has completed the data integrity verification, the reliability of the data to be written in the cache is guaranteed, so the remote host 300 can be directly notified that the data writing is completed, without waiting for the data to be actually written to the non-volatile storage array 200 (NVME hard disk). When the integrity verification at the non-volatile storage array 200 fails in the subsequent writing process, the data in the controller memory 140 is read again.

[0114] S117, the redundancy module 120 generates a writing command to inform the NVMe-PCIe host of the cache address of the k+m parts of data (the data to be written after the redundancy calculation and the check data).

[0115] S118, the NVMe-PCIe host maps the corresponding first cache subspace as the memory of the NVMe-PCIe host.

[0116] For example, the cache addresses of k+m pieces of data are A1-A5, the NVMe-PCIe host writes the first address A1 and the data length into the DMA register of the corresponding namespace in the NVMe hard disk, each namespace corresponds to a register, and the register address is exchanged when the NVMe-PCIe host and the NVMe hard disk are initialized to establish a DMA connection.

[0117] When a DMA register in the NVMe hard disk is in an enabled state, the NVMe hard disk can directly read k+m pieces of data in the cache mapped by the corresponding NVMe-PCIe host through the first address A1 and the data length written in the register by the NVMe-PCIe host.

[0118] After the data reading is completed, the NVMe hard disk writes a DMA completion identifier into the DMA register of the NVMe-PCIe host.

[0119] S119, the NVMe-PCIe host sends a disk flushing completion notification in response to the DMA completion, to inform the redundancy module 120 that the cache space of A1-A5 has been released, and the cache space can be used by the redundancy module 120 continuously.

[0120] Exemplarily, the storage array controller 100 of the embodiment of the present application is introduced below taking a read command as an example, and the specific processing process of the storage array controller 100 includes the following steps:

[0121] S121, the TOE module parses the received TCP / IP / Ethernet packet and sends the parsed packet data (data part) to the NVMe-oF controller.

[0122] S122, the message parsing module 111 in the NVMe-oF controller unpacks the packet data to obtain an operation command, the operation command includes a PDU (Protocol Data Unit, protocol data unit), and according to the PDU, it is determined that the operation command is of a data transmission type (read operation command), and then the read operation command is sent to the IOQ processing module (command queue processing module 112).

[0123] S123, the IOQ processing module adds the received read operation command to the command queue for management and scheduling, such as a read-write command queue, a priority command queue, or an NS (NameSpace, namespace) command queue.

[0124] When the read operation command is executed, a command is sent to the redundancy module 120 to indicate the redundancy module 120 to check whether there is an address space of the corresponding LBA block in the controller memory 140, if there is, and if it is not in the locked state, directly read data from the address space of the corresponding LBA block in the controller memory 140; if there is, and the corresponding LBA block is in the locked state, the command is temporarily suspended; if there is no corresponding LBA block address space in the controller memory 140, a second cache sub-space is prepared and the related data is read.

[0125] At the same time, the IOQ processing module generates a command to read continuous addresses in the same namespace and delivers it to the redundancy module 120.

[0126] S124, the redundancy module 120 queries the cache state table to see if there is enough cache space to receive the data to be read.

[0127] If there is, the NVMe-PCIe host is instructed to read data from the NVMe hard disk, and the address of the second cache sub-space receiving the data and the target address of the data to be read are informed.

[0128] If there is no enough cache space, the data in the corresponding namespace is preferentially sent to the remote host 300 to free up cache space.

[0129] S125, the NVMe-PCIe host sends a command to the NVMe hard disk to read data, and maps the cache space as the memory of the NVMe-PCIe host to receive the data to be read.

[0130] S126, after the NVMe hard disk prepares the data to be read, the first address and length of the data are written into the DMA register of the NVMe-PCIe host.

[0131] S127, the NVMe-PCIe host responds to the DMA register enable, reads data directly into the memory of the NVMe hard disk according to the data address and data length written by the NVMe hard disk, and notifies the redundancy module 120 to release the related cache after reading.

[0132] S128, the redundancy module 120 performs data block merging or data recovery according to the current array redundancy mode, and sends it to the remote host 300.

[0133] In order to improve the efficiency of the redundancy module 120 in processing data in the controller memory 140 based on the namespace, the application embodiment further provides a cache management method, device, controller and medium of a storage array. In the application embodiment, the redundancy module implements a cache management method of a storage array provided by the application.

[0134] The cache management method of the storage array will be described below in combination with some specific embodiments.

[0135] Figure 3 A flow chart of the cache management method of the storage array according to an embodiment of the present application is shown. In the embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (referred to as cache) according to the current redundancy mode and the number of NS (Name Space). The cache management method of the storage array according to an embodiment of the present application includes the following steps:

[0136] S210, mapping the non-volatile storage array 200 into a virtual logical address space according to a name space, and dividing the virtual logical address space into virtual logical address groups. The logical addresses of the non-volatile storage array 200 are one-to-one mapped to obtain a virtual logical address space, which includes virtual logical addresses (referred to as VIR_LBA addresses) corresponding to all logical addresses (referred to as LBA addresses, Logical Block Address) in the non-volatile storage array 200. In the embodiment of the present application, there is a mapping relationship between the VIR_LBA addresses and the LBA addresses of the non-volatile storage array 200, and the relationship between the LBA addresses and the PBA addresses (Physics Block Address) in the non-volatile storage array 200 is handled by the controller in the non-volatile storage array 200 after landing, which is not limited in the present application. The storage array controller 100 in the present application is an external controller of the non-volatile storage array 200.

[0137] In an embodiment, the present application supports HMB (Host Memory Buffer) technology. The memory of the storage array controller 100 is opened to the controller of the non-volatile storage array 200 to store the FTL (Flash Translation Layer) table. When the non-volatile storage array 200 is a DRAMless hard disk, enabling this function can significantly improve the performance of the storage array.

[0138] Further, dividing the virtual logical address space into virtual logical address groups includes:

[0139] According to a preset number of name spaces, the virtual logical address space is divided to obtain a number of virtual logical address subspaces equal to the preset number.

[0140] That is, the redundancy module 120 allocates a fixed VIR_LBA address space (virtual logical address subspace) to each name space, as shown in Table 1.

[0141] Table 1 Name space and VIR_LBA address space

[0142] Namespace VIR_LBA address NameSpace 1 VIR_LBA0 - VIR_LBA99 NameSpace 2 VIR_LBA100 - VIR_LBA249 … … NameSpace x VIR_LBAm - VIR_LBAn

[0143] Each VIR_LBA address of each namespace establishes a fixed mapping with the LBA address of the non-volatile storage array 200, as shown in Table 2, the LBA address of NS1 in the non-volatile storage array 200 is LBA1050-LBA1149.

[0144] Table 2 Mapping relationship between VIR_LBA address and LBA address in non-volatile storage array

[0145] VIR_LBA address of NS1 LBA address in storage array NS1 - VIR_LBA0 LBA 1050 NS1 - VIR_LBA2 LBA 1051 … … NS1 - VIR_LBA99 LBA 1149

[0146] For example, when receiving a write data command for NS1, the size of the write data is 10, the virtual logical address allocated for the write data command is VIR_LBA0-VIR_LBA9, and sufficient cache space is applied to VIR_LBA0-VIR_LBA9 from the controller memory 140 (for example, HBM High Bandwidth Memory) to prepare to receive the write data, VIR_LBA0-VIR_LBA9 is mapped to the logical address LBA1050-LBA1059 of the non-volatile storage array 200 (for example, SSD hard disk). Further, each continuous logical address block in the virtual logical address subspace is divided into a namespace array according to the redundancy mode of the non-volatile storage array 200; a row of logical address blocks in the namespace array as a stripe, wherein the number of logical address blocks in the stripe is the same as the number of redundancy group members in the non-volatile storage array 200, the namespace array is divided into a plurality of virtual logical address groups, and the virtual logical address group includes one or more stripes.

[0147] If the current redundancy mode is k+m, that is, there are k+m i members in a redundancy group, as shown in Figure 4 SSD1-SSDi is a redundancy group.

[0148] In order to improve performance, the namespace array is divided into a plurality of virtual logical address groups in the embodiment of the application. That is, the continuous VIR_LBA address space in a namespace is defined as a VIR_LBA group, denoted as VIR_LBAG. And when the array is a redundancy array, each VIR_LBAG is divided according to the current redundancy mode.

[0149] According to the current redundancy mode, the cache array is divided as Figure 5a VIR LBA group in a namespace under a certain redundancy group is divided into a namespace array, each row in the namespace array is a stripe, the number of LBA BLOCKs (logical address blocks, also known as LBA blocks) in the stripe is determined by the number of redundancy group members, and the VIR LBA address of the namespace is one-to-one corresponding to the LBA address of the SSD disk. The number of LBA BLOCKs in each column is related to the total VIR LBA capacity allocated to the current NS, the overall capacity of the cache, and the actual storage service characteristics. For example, a certain NS may be mainly small random IO, so the number of LBA_BLOCK blocks in the array can be designed to be small, and the same cache space can be divided into more VIR_LBAGs. The VIR_LBAG in the cache of the device supporting the redundancy feature is at least one row in the cache. Figure 5 In other cases, multiple stripes can also be divided into a VIR_LBAG for management and operation according to requirements.

[0150] The space size of a VIR_LBAG and the number of LBA_BLOCKs are fixed and do not change even if individual members of the redundancy group fail (such as a certain SSD member is damaged and cannot be used, but the entire redundancy group can still recover data).

[0151] S220, determining the activity level of the cache data in the virtual logical address group according to the storage state corresponding to the virtual logical address group.

[0152] S230, determining a target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the activity level.

[0153] In order to ensure that the cache space has sufficient free space, the application falls the data with low activity level. It can be understood that the target virtual logical address group that needs to be stored in the non-volatile storage array 200 is determined according to the activity level, including:

[0154] The virtual logical address group with low activity level is determined as the target virtual logical address group.

[0155] When the cache space is full, the virtual logical address group with intermediate activity level can also be determined as the target virtual logical address group.

[0156] Further, the target virtual logical address group that needs to be stored in the non-volatile storage array 200 is determined according to the activity level, including:

[0157] The target cache data that needs to be stored in the non-volatile storage array 200 in the target virtual logical address group is determined according to the storage state.

[0158] Furthermore, the determining of the target virtual logical address group to be stored in the non-volatile storage array 200 according to the activity level includes:

[0159] The target logical address for storing the target cache data in the non-volatile storage array 200 is determined according to the virtual logical address group and the preset logical address mapping relationship.

[0160] The target cache data is written into the non-volatile storage array 200 according to the target logical address.

[0161] In one embodiment, the storage status includes a read / write status flag corresponding one-to-one to each logical address block in the virtual logical address group.

[0162] Exemplarily, in an embodiment of the present application, an LBAG status table (also known as a virtual logical address group status table) is used to record the allocation and usage of VIR_LBAG in each namespace. That is, the storage status is stored in the LBAG status table. The activity level of the cached data in the virtual logical address group is determined based on the storage status recorded in the LBAG status table. The LBAG status table includes read-write status flags that correspond one-to-one to each logical address block (LBA_BLOCK) in the virtual logical address group. The number of LBA_BLOCKs in the current virtual logical address group requires multiple read-write status flags, and each LBA_BLOCK corresponds to a 1-bit read-write status flag, as shown in Table 3.

[0163] Table 3 LBAG status table 1

[0164]

[0165] The step of determining target cache data in the target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the storage state includes:

[0166] The cached data in the logical address block corresponding to the read / write status flag in the target virtual logical address group is determined as the target cached data. That is, within the target virtual logical address group, the logical address block corresponding to the read / write status flag in the write state is first determined to obtain the target logical address block, and the cached data in the target logical address block is determined as the target cached data. The target cached data is stored in the non-volatile storage array 200 to complete the write to disk.

[0167] Furthermore, the method further includes: updating the corresponding storage status according to the read and write operations on the virtual logical address groups corresponding to the namespaces in the cache, specifically including:

[0168] If the data stored in the cache by the logical address block is first data, a read-write state flag corresponding to the logical address block is set to a write state, the first data being write data sent by the remote host 300. For example, if the data in the logical address block is write data from the NVMe-oF controller, the read-write state flag corresponding to the logical address block is set to 1, indicating a write state. Therefore, when the current virtual logical address group needs to be flushed, the data in the logical address block with the read-write state flag set to 1 must be flushed.

[0169] If the data stored in the cache by the logical address block is second data, a read-write state flag corresponding to the logical address block is set to a read state; the second data being empty data or read data read from the non-volatile storage array 200. For example, if the data in the logical address block is read data from the SSD or the logical address block is currently not written with data, the read-write state flag corresponding to the logical address block is set to 0, indicating a read state. Therefore, when the current virtual logical address group needs to be flushed, the data in the logical address block with the read-write state flag set to 0 is not flushed.

[0170] Further, the method further comprises:

[0171] When the target cache data is written into the non-volatile storage array 200, the cache data in each logical address block in the stripe is subjected to redundancy calculation to obtain check data and write the check data into a check block in the stripe; and a read-write state flag corresponding to the check block is set to the write state.

[0172] In the redundancy mode, when the IOQ processing module transmits write data to the redundancy module 120, the write data is only divided according to the current redundancy mode and stored in the corresponding data block cache, and the check calculation is not performed at present, the corresponding check block is empty, and the check data is calculated and filled into the corresponding check block when it needs to be flushed, the read-write state flag corresponding to the check block for storing the check data is forcibly set to 1 to indicate that the LBA_BLOCK needs to be flushed. For example, the current redundancy mode is k+m, the write data is stored in k data LBA_BLOCKs in a stripe, and the read-write state flag is set to 1, m check blocks are temporarily empty and the check data does not come from the NVMe-oF controller, but the check data is calculated when it needs to be flushed, written into the check block, and the corresponding read-write state flag is set to 1, indicating that the LBA_BLOCK needs to be flushed.

[0173] In an embodiment, the storage state comprises a full-write flag corresponding to each virtual logical address group. One virtual logical address group corresponds to one full-write flag. The full-write flag is stored by using 1 bit.

[0174] The method further comprises:

[0175] determining whether each read-write state flag corresponding to each logical address block in the virtual logical address group is in the write state, to obtain a block number of logical address blocks whose read-write state flags are in the write state. If the block number is greater than a preset threshold, the full-write flag corresponding to the virtual logical address group is determined to be in the full-write state. For example, when in the write state, the full-write flag is set to 1, indicating that the cache space corresponding to the virtual logical address group is in a full-write state or is about to be in the full-write state.

[0176] The method further includes: taking the virtual logical address group corresponding to the full-write flag in the full-write state as the target virtual logical address group, i.e., the virtual logical address group that needs to be flushed to the disk, and then determining the target cache data that needs to be flushed according to the read-write state flag.

[0177] For example, the number of 1s in each read-write state flag in the virtual logical address group is counted, and when the number exceeds a preset threshold (e.g., 2 / 3 of the logical address blocks), the full-write flag is set to 1 to indicate that the virtual logical address group has been filled and can be flushed to the disk. In an embodiment, the storage state includes a corresponding number of activity factor flags corresponding to each virtual logical address group. One virtual logical address group corresponds to one activity factor flag, and the size of the activity factor flag is 1-n bit.

[0178] The method further includes: updating the corresponding storage state according to the read-write operation command for each namespace corresponding virtual logical address group in the cache, specifically including:

[0179] According to the frequency of receiving the read-write operation command for the virtual logical address group, the corresponding activity factor flag value is set. The greater the frequency of read-write operation, the more active the virtual logical address group is.

[0180] Further, the setting of the corresponding activity factor flag value according to the frequency of receiving the read-write operation command for the virtual logical address group includes:

[0181] According to the preset frequency and counting period, counting is performed on the virtual logical address group as the object;

[0182] In the counting period, according to whether the read-write operation command is received for the virtual logical address group, the activity factor flag value is updated according to a preset update rule.

[0183] Further, the updating of the activity factor flag value according to whether the read-write operation command is received for the virtual logical address group in the counting period according to the preset update rule includes:

[0184] If the read-write operation command is not received in the counting period, each bit of the active factor flag value is retrieved according to the set bit sequence, and a second state value is written in the bit corresponding to the first state value.

[0185] If the read-write operation command is received in the counting period, each bit of the active factor flag value is retrieved according to a sequence opposite to the set bit sequence, and a first state value is written in the bit corresponding to the second state value.

[0186] For example, after a virtual logical address group is allocated, the active factor flag value of the active factor flag bit is set as all 1s by default. Whether each bit of the active factor flag value is set as 0 depends on a continuously naturally accumulated counter. The running frequency (i.e., the speed of counting) of the counter can be set. A certain technical period is set based on the counter. If the counter overflows without receiving any read or write operation for the current virtual logical address group, one bit of the active factor flag value is set as 0. If the counter receives a read or write operation for the current virtual logical address group in one counting period, the counter is reset to zero and re-counted, and one 0 bit of the active factor flag value is flipped to 1.

[0187] For example, the active factor flag value is set as 3 bits, and the counting period of the counter is t. The counter naturally accumulates from 0. When the counting period t is elapsed, the counter reaches the maximum value and overflows. After the current virtual logical address group is allocated, the active factor flag value is set as 111, and the counter starts counting. When the counting period t is elapsed without receiving a read or write operation for the current virtual logical address group, the active factor is flipped to 110. The counter is reset to zero and re-counted. When the counting period t is again elapsed without receiving a read or write operation for the current virtual logical address group, the active factor flag value is flipped to 100. The counter is reset to zero and re-counted. Before the counting period is ended, if a read or write operation for the current virtual logical address group is received, the active factor flag value is flipped to 110, and so on. That is, when the active factor flag value receives a read or write command in the counting period, the value of the 0 bit is flipped to 1, and so on. When the active factor flag value is all 1s, no overflow occurs, and the all 1s are maintained. When no read or write operation command is received in the counting period, the value of the 1 bit is flipped to 0, and so on. When the active factor flag value is all 0s, no overflow occurs, and the all 0s are maintained.

[0188] Further, the determining the activity level of the cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group comprises:

[0189] If each digit of the active factor flag value corresponding to the virtual logical address group is the second state value, the activity level of the cached data in the virtual logical address group is determined as a low activity level.

[0190] If each digit of the active factor flag value corresponding to the virtual logical address group is the first state value, the activity level of the cached data in the virtual logical address group is determined as a high activity level.

[0191] The number of digits of the active factor flag value whose digits are the first state value is counted.

[0192] If the number of digits is greater than a preset number, the activity level of the cached data in the virtual logical address group is determined as an intermediate activity level.

[0193] The size of the active factor flag value represents the activity of the virtual logical address group, i.e., the hotness of the data. The greater the active factor flag value, the more active the virtual logical address group. Active data is preferably retained in the cache. An active factor flag value of all 0s indicates that the virtual logical address group is no longer active, and a write-to-SSD operation command needs to be submitted. When the cache space is insufficient, the cached data in the virtual logical address group with an intermediate activity of non-all 0s can also be initiated to be written to the disk according to the activity level.

[0194] In the embodiments of the present application, the active factor flag value is used to represent the activity level of the data of the current virtual logical address group. Data with a high activity level is retained in the cache, which reduces the frequent operations on the SSD disk after the active data is written to the disk, thereby reducing the wear of the SSD disk and enhancing the service life of the SSD disk. At the same time, the bandwidth demand of the back-end PCIe channel is also reduced, and the performance of the active data IO command is greatly improved.

[0195] In an embodiment, the virtual logical address group is the granularity of read-write operation commands.

[0196] The storage state includes a number of lock flag bits equal to the number of virtual logical address groups. One virtual logical address group corresponds to one lock flag bit, for example, the size of the lock flag bit is 1 bit.

[0197] The method further includes:

[0198] When the current virtual logical address group is operated according to the read-write operation command, the lock flag corresponding to the current virtual logical address group is set to the lock state; and the read-write operation command accessing the virtual logical address group in the lock state is delayed. That is, when a read-write operation command operates the current virtual logical address group, the virtual logical address group is in the lock state before the read-write operation command is completed, for example, the lock flag is set to 1 to indicate the lock state. When a subsequent read-write operation command accessing the virtual logical address group in the lock state is received, the subsequent read-write operation command is delayed to prevent the two read-write operation commands from conflicting and causing the data of the virtual logical address group to be confused.

[0199] The granularity of each read-write operation command when operated is a virtual logical address group. Even if the current applied cache space is only a logical address block in the virtual logical address group, the entire virtual logical address group is locked until the current command is completed, and the next read-write operation command for the current virtual logical address group can be executed. Thus, although the speed of I / O execution is sacrificed, a large amount of repeated and frequent redundant calculation and access wear of the SSD are reduced.

[0200] The cache management method of the storage array of the embodiment of the application is introduced below in combination with an example. In the example, the storage state includes a read-write state flag, a full-write flag, an activity factor flag, and a lock flag, as shown in Table 4.

[0201] Table 4 LBAG state table two

[0202]

[0203] The activity factor flag of the current virtual logical address group is all 0, indicating that the current virtual logical address group has been inactive for a long time and needs to be cleared, as shown in Table 4. Figure 6 The method includes the following steps:

[0204] S301, the redundancy module 120 checks the activity factor flag of the virtual logical address group, and determines that the virtual logical address group is in a low activity level when the activity factor flag is all 0.

[0205] S302, for the virtual logical address group in the low activity level, the redundancy module 120 calculates the redundancy check data according to the data of each LBA_BLOCK in the stripe and writes the redundancy check data into the LBA_BLOCK corresponding to the check block, and sets the read-write state flag of the LBA_BLOCK corresponding to the check block to 1.

[0206] S303, for the low active level of virtual logical address group, the redundancy module 120 will read and write state flag position 1 LBA_BLOCK in the cache data as the target cache data, submit the write SSD disk operation instruction, and write the target cache data to the disk. After the disk is written, the target cache data needs to be cleared, and then the read and write state flag position 0 is set.

[0207] For example, the current redundancy mode is 4+2, 4 data blocks and 2 redundancy check blocks, and the number of members in a strip in the namespace is 6. Therefore, the number of members in a strip in the corresponding virtual logical address group is also 6.

[0208] As shown in Figure 7 The virtual logical address group with all 0 active factor flag bits to be written to the disk is calculated according to the data in the logical address blocks: LBA_BLOCK5, LBA_BLOCK2, LBA_BLOCK1, LBA_BLOCK0. The calculated check data is written to the check blocks LBA_BLOCK4 and LBA_BLOCK3, and the read and write flags of LBA_BLOCK4 and LBA_BLOCK3 are set to 1. Therefore, the current read and write flags are changed from 100001 to 111001. Then, according to the read and write flags, the SSD write operation instruction is issued, and the data of LBA_BLOCK5, LBA_BLOCK4, LBA_BLOCK3 and LBA_BLOCK0 with read and write flags of 1 are written to the SSD. After the disk is written, the cache occupied by the virtual logical address group is released.

[0209] Next, the cache management method of the storage array of the embodiment of the application will be introduced in combination with another example. When the cache space corresponding to the current namespace is not enough for use, the virtual logical address group that can be cleared needs to be arranged as soon as possible to release the cache space to store the data of other read / write commands, as shown in Figure 8 The specific steps are as follows:

[0210] S401, the redundancy module 120 detects that the cache space corresponding to the current namespace is not enough for use.

[0211] S402, the redundancy module 120 checks the full-write flag corresponding to each virtual logical address group in the LBAG state table, and selects the virtual logical address group with the full-write flag of 1 as the target virtual logical address group to be written to the disk.

[0212] S403, the redundancy module 120 checks the active factor flag value of the active factor flag corresponding to the target virtual logical address group, determines the active level of the target virtual logical address group according to the active factor flag value, and selects the target virtual logical address group with a low active level.

[0213] S404, for the target virtual logical address group of low activity level, the redundancy module 120 calculates the redundancy check data according to the data of each LBA_BLOCK of the strip and writes it into the LBA_BLOCK corresponding to the check block. In addition, the read-write state flag of the LBA_BLOCK corresponding to the check data is also set to 1.

[0214] S405, for the target virtual logical address group of low activity level, the redundancy module 120 takes the cache data in the LBA_BLOCK with the read-write state flag set to 1 as the target cache data, submits a write SSD disk operation instruction, and writes the target cache data to the disk. After writing to the SSD disk, the target cache data is cleared. In addition, after sending the data read from the non-volatile storage array 200 to the remote host 300, the cache data of the LBA_BLOCK with the read-write state flag set to 0 is also directly cleared.

[0215] Figure 9 A structural schematic diagram of a cache management device of a storage array according to an embodiment of the present application is shown. The cache management device of the storage array includes an address group division module 910, an activity level determination module 920, and a disk writing module 930.

[0216] The address group division module 910 is configured to map the non-volatile storage array 200 to a virtual logical address space according to a namespace, and divide the virtual logical address space into virtual logical address groups.

[0217] The activity level determination module 920 is configured to determine the activity level of the cache data in the virtual logical address group according to the storage state corresponding to the virtual logical address group.

[0218] The disk writing module 930 is configured to determine a target virtual logical address group that needs to be stored in the non-volatile storage array 200 according to the activity level.

[0219] It can be understood that the device of the embodiment corresponds to the cache management method of the storage array of the above-mentioned embodiments, and the optional items in the above-mentioned embodiments are also applicable to the present embodiment, so they will not be described again here.

[0220] In order to improve the management efficiency of the redundancy module on the controller memory, the present application further provides a cache management method, a storage array controller, a device, an equipment and a medium. In the embodiment of the present application, the redundancy module implements a namespace-based cache management method of the present application.

[0221] In a namespace-based cache management method of an embodiment of the present application, for simplicity, the cache in the redundancy module 120 is not separately divided into read and write cache spaces, and the data in the cache space can come from the remote host 300 or the nonvolatile storage array 200. The cache is only divided and managed by namespaces, and each namespace is allocated a separate cache for storing data. The namespaces belonging to different hard disks can write data in parallel, and the independent namespace cache can prevent data of a namespace from occupying all the cache and slowing down the overall read and write speed.

[0222] The namespace-based cache management method will be described below in combination with some specific embodiments.

[0223] In an embodiment of the present application, the redundancy module 120 performs cache management on the controller memory 140 (referred to as cache) according to the current redundancy mode and the number of NSs (Name Spaces). Exemplarily, the namespace-based cache management method includes the following steps:

[0224] S2210. According to the namespace to be accessed by an access command, a cache region is allocated for the access command in the static cache subspace.

[0225] The controller memory 140 in an embodiment of the present application includes a static cache space. Understandably, the static cache space is divided according to the number of namespaces by using a preset capacity allocation rule, to obtain a static cache subspace corresponding to each namespace, as shown in Table 1. Thus, the static cache subspace is obtained. For example, a certain device supports i NSs (Name Spaces), and the static cache space is divided into i NSs, as shown in Table 2-1. Each namespace corresponds to a static cache subspace. Thus, it is ensured that each NS has a certain cache space, and once a read or write operation command accesses the NS, the remote host 300 can be immediately notified that there is enough cache space, to instruct the remote host 300 to send write data; and the command cannot be responded to because the cache space is used up by other NSs.

[0226] Table 2-1 Correspondence between namespaces and static cache subspaces

[0227] Namespace Static cache space NS1 Static cache subspace 1 NS2 Static cache subspace 2 … … NSi Static cache subspace i

[0228] Further, the static cache space is divided according to the number of namespaces by using a preset capacity allocation rule, including:

[0229] The static cache space is evenly divided according to the number of namespaces to obtain each static cache subspace, and the static cache subspace is fixed.

[0230] Alternatively, the static cache subspaces can also be divided according to preset capacity ratios of the respective namespaces, for example, a ratio of the static cache space occupied by each namespace is set, and a fixed static cache subspace is divided for each namespace according to the ratio. However, the static cache subspace is fixed in capacity once divided and will not be adjusted according to the actual use of the cache, nor will it change because of whether the NS is valid.

[0231] Further, the non-volatile storage array 200 is mapped into a virtual logical address space according to the respective namespaces. All logical addresses of the non-volatile storage array 200 are mapped equally to obtain a virtual logical address space. The virtual logical address space includes virtual logical addresses (referred to as VIR_LBA addresses) corresponding one-to-one to the respective logical addresses (referred to as LBA addresses) in the non-volatile storage array 200, as shown in Table 2-2.

[0232] Table 2-2 Mapping relationship between VIR_LBA addresses and LBA addresses in the non-volatile storage array

[0233] VIR_LBA address LBA address in storage array VIR_LBA0 LBA0 VIR_LBA1 LBA1 … … VIR_LBAi LBAi

[0234] The virtual logical address space is divided according to the number of namespaces to obtain a virtual logical address subspace corresponding one-to-one to each of the namespaces. Thus, each virtual logical address subspace is obtained. The virtual logical address subspace includes a plurality of virtual logical addresses, as shown in Table 2-3.

[0235] Table 2-3 Correspondence between namespaces and virtual logical address subspaces

[0236] Namespace Virtual logical address subspace NS1 VIR_LBA0 - VIR_LBA99 NS2 VIR_LBA100 - VIR_LBA249 … … NSi VIR_LBAm - VIR_LBAn

[0237] Further, the namespace to be accessed according to the access command is allocated a cache region in the static cache subspace for the access command, comprising:

[0238] S3211, a virtual logical address subspace is obtained according to the namespace matching.

[0239] S3212, a target virtual logical address is allocated for the access command from the virtual logical address subspace.

[0240] S3213, the cache region is allocated for the target virtual logical address from the static cache subspace corresponding uniquely to the namespace.

[0241] In order to improve performance and facilitate management, the allocation granularity of the virtual logical address subspace corresponding to the NS is set according to the redundancy mode of the SSD hard disk (non-volatile storage array 200), and the virtual logical address subspace is further divided into multiple stripes according to the number of members of the redundancy group in the SSD hard disk. Specifically, according to the redundancy mode of the non-volatile storage array 200, the virtual logical address subspace is divided into a namespace array, and a row of virtual logical addresses in the namespace array is a stripe, as shown in Figure 10 .

[0242] Further, in step S3212, the target virtual logical address is allocated for the access command from the virtual logical address subspace, including:

[0243] When the access command is to access any virtual logical address in the stripe, the stripe is allocated as the target virtual logical address for the access command. It can be understood that when the access command accesses any virtual logical address in the stripe, the entire stripe where the virtual logical address is located is allocated for the access command, and a cache region of the entire stripe size is applied from the corresponding static cache subspace. Therefore, the static cache subspace should be set to an integer multiple of the stripe length. For example, a read command for NS1 is received to read the data corresponding to VIR_LBA3, and the entire stripe where VIR_LBA3 is located needs to apply the corresponding cache region from the static cache subspace in NS1.

[0244] In step S3213, the cache region is allocated for the target virtual logical address from the static cache subspace corresponding to the namespace, including:

[0245] If the cache region is not matched according to the stripe, a cache region is allocated for the stripe from the static cache subspace corresponding to the namespace according to the capacity size of the stripe.

[0246] In an embodiment, in order to improve data processing speed, the method of the embodiment of the application further includes: dividing each namespace located in the hard disk group of the non-volatile storage array 200 into a namespace group. The cache region is allocated for the access command in the static cache subspace according to the namespace to be accessed by the access command, including:

[0247] The access commands located in different namespace groups are executed in parallel, and the cache region is allocated for the corresponding access command in the corresponding static cache subspace according to the respective namespaces to be accessed. For example, Figure 11As shown, a schematic diagram of the NS group (NS Group) is shown, wherein NameSpace1, NameSpace2 and NameSpace3 belong to NS Group1, NameSpace4, NameSpace5 and NameSpace6 belong to NS Group2, different namespace groups can be accessed in parallel due to different hard disk groups stored therein without affecting each other, and therefore limiting the dynamic space usage of a single namespace group is beneficial to improve the overall processing efficiency of the array system.

[0248] S3220, receiving read / write target data of the non-volatile storage array 200 based on the access command and caching to the cache area. Wherein, the static cache sub-space is obtained by dividing the static cache space in the controller memory 140 according to the namespace.

[0249] In an embodiment, in order to improve the speed of reading data, the present application also supports pre-reading data. The method further comprises:

[0250] S3310, if the access command is a read command for reading a first virtual logical address, determining the stripe where the first virtual logical address is located according to the first virtual logical address.

[0251] S3320, reading read data corresponding to the stripe in the non-volatile storage array 200; mapping logical addresses of the non-volatile storage array 200 according to each virtual logical address corresponding to the stripe to obtain read data in the non-volatile storage array 200 according to the logical addresses of the non-volatile storage array 200.

[0252] S3330, caching the read data to the cache area corresponding to the stripe as pre-reading data for subsequent reading of other addresses in the stripe except the first virtual logical address.

[0253] For example, a read command for NS1 is received to read data corresponding to VIR_LBA3, and a corresponding cache area needs to be applied from the static cache sub-space in NS1 for the entire stripe where VIR_LBA3 is located. Only the data corresponding to VIR_LBA3 can be read, or a pre-reading operation can be performed to read all the data corresponding to the entire stripe from the non-volatile storage array 200 to the corresponding cache area. When the data of VIR_LBA4 in the stripe is read in the subsequent command, it can be directly read from the cache area, thereby improving the efficiency of reading data.

[0254] In an embodiment, the controller memory 140 further comprises a dynamic shared cache space, as shown. Figure 12

[0255] The method further comprises: ​

[0256] When the static cache sub-space corresponding to the namespace is in a full state, a preset capacity of storage area is applied for the namespace from the dynamic shared cache space.

[0257] Further, the method further comprises:

[0258] According to the current capacity of the space, the current capacity of the space group, and preset space capacity threshold and space group capacity threshold, it is determined whether to pass the application. The current capacity of the space is the current capacity of the static cache sub-space obtained by the namespace; the current capacity of the space group is the sum of the current capacities of the static cache sub-spaces obtained by each namespace included in the namespace group.

[0259] Exemplarily, if the current capacity of the space group corresponding to the namespace group does not reach the space group capacity threshold, and the current capacity of the space corresponding to the namespace does not reach the space capacity threshold, it is determined that the application is passed, that is, the storage area is allowed to be allocated from the dynamic shared cache space, otherwise the application is not passed.

[0260] That is, in order to prevent a large amount of occupation of dynamic space by a certain namespace from affecting the use of other namespaces, in the embodiment of the application, a water line of the dynamic space that can be applied for is set for each namespace and the namespace group in which the namespace is located. The application of the dynamic space by all the namespaces belonging to the same namespace group is limited by the water line (i.e. threshold) of the namespace itself and the namespace group to which the namespace belongs. When a namespace applies for dynamic space, touches any one of the water lines, no dynamic space will be allocated to it.

[0261] Further, the method further comprises:

[0262] When the static cache sub-space is in a full state, if it is determined that the application is not passed, the write data and the pre-read data in the static cache sub-space corresponding to the namespace are cleaned. The namespace needs to release the cache space occupied by some completed commands in the namespace in order to execute a command. For the cache of a write command, the back end is triggered to fall to the disk as soon as possible; for the cache space of a read command, the pre-read data is cleaned.

[0263] The namespace-based cache management method of the embodiment of the application will be introduced below in combination with an example of a write command, and specifically includes the following steps:

[0264] S3401, the redundancy module 120 receives a write command, allocates an idle virtual logical address VIR_LBA according to the namespace accessed by the current write command and the length of the data to be written, and the first address is recorded.

[0265] S3402, the redundancy module 120 determines whether the first address belongs to a stripe which has allocated cache region according to the cache status table. If the stripe has allocated cache region, step S3403 is performed, otherwise, step S3404 is performed.

[0266] S3403, the redundancy module 120 sends R2T (Ready to Transfer, indicating that the cache region is ready) to the remote host 300 to instruct the remote host 300 to send the data to be written.

[0267] S3404, the redundancy module 120 determines whether there is a free cache region in the static cache sub-region of the namespace corresponding to the stripe. If there is a free cache region, step S3405 is performed, otherwise, step S3406 is performed.

[0268] S3405, the redundancy module 120 allocates a usable fixed cache region for the stripe from the static cache sub-region corresponding to the namespace.

[0269] S3406, the redundancy module 120 determines whether the dynamic shared cache space applied by the currently accessed NS triggers a preset water line (including a space capacity threshold and a space group capacity threshold). If it triggers, the cache cleaning is performed and the released cache space is allocated to the stripe. If it does not trigger, the corresponding shared cache region is allocated to the stripe from the dynamic shared cache space.

[0270] S3407, R2T (Ready to Transfer, indicating that the cache region is ready) is sent to the remote host 300 to instruct the remote host 300 to send the data to be written, and the received data to be written is stored in the second address (physical address of the cache space) corresponding to the first address (VIR_LBA of the NS) of the allocated cache region.

[0271] In order to improve the data read and write processing speed of the storage array, for example, in order to improve the speed of determining the first cache sub-space and the second cache sub-space in the controller memory, the present application further provides a storage array data read and write method. The redundancy module in the present application implements a storage array data read and write method of the present application.

[0272] The storage array data read and write method will be described below in combination with some specific embodiments.

[0273] In the redundancy module 120 of the present application, the controller memory 140 (referred to as cache) is managed according to the current redundancy mode and the number of NS (NameSpace, namespace). The storage array data read and write method includes the following steps:

[0274] S4210, according to the index of the target address stripe in the access command to the storage array in the cache space management table, determine the corresponding cache address space.

[0275] Further, the embodiments of the application according to each of the namespace will be described as the non-volatile storage array 200 is mapped to a virtual logical address space. For each logical address of the non-volatile storage array 200, there is a unique virtual logical address (Vir_LBA for short) corresponding to it in the virtual logical address space. The virtual logical address is determined to access the corresponding logical address in the non-volatile storage array 200.

[0276] According to the number of each namespace, the virtual logical address space is divided to obtain a virtual logical address subspace corresponding to each of the namespace. Thus, the virtual logical address subspace is divided, as shown in Table 3-1.

[0277] Table 3-1: Correspondence between namespace and virtual logical address subspace

[0278] Namespace Virtual logical address subspace NameSpace 1 VIR_LBA0 - VIR_LBA99 NameSpace 1 VIR_LBA100 - VIR_LBA249 … … NameSpace x VIR_LBAm - VIR_LBAn

[0279] Further, in order to improve performance and facilitate management, according to the redundancy mode of the non-volatile storage array 200, the virtual logical address subspace corresponding to the namespace is divided into a namespace array, and a row of virtual logical addresses in the namespace array is a stripe. Thus, the target address stripe is obtained. That is, the allocation granularity of VIR_LBA in NS is set according to the redundancy mode of the SSD hard disk (SSD hard disk in the non-volatile storage array 200), and the VIR_LBA in NS is divided into LBA stripes according to the number of members in the redundancy group in the SSD hard disk, as shown in Table 3-2. Figure 13

[0280] Further, the determination of the corresponding cache address space according to the index of the target address stripe in the cache space management table comprises:

[0281] S4211, according to the access command to the non-volatile storage array 200, determine the target namespace and target virtual logical address accessed thereby. The target namespace and target virtual logical address are included in the access command.

[0282] S4212, according to the target namespace and target virtual logical address, determine the target address stripe.

[0283] In one embodiment, the determination of the corresponding cache address space according to the index of the target address stripe in the cache space management table comprises:

[0284] ​According to the index, the cache address space is matched in the cache space management table;

[0285] If the matching fails, the cache address space is allocated for the target address strip from the controller memory 140;

[0286] If the matching succeeds, the index is obtained, and the corresponding cache address space in the cache space management table is obtained.

[0287] Further, in order to facilitate the management of the cache space, in the embodiment of the application, the cache space management table is established according to the index of the strip. It can be understood that the method further comprises: according to the serial number of the target address strip, the allocated cache address space is stored in the cache space management table. When the cache space (cache address space) is allocated for a certain strip from the controller memory, the address of the cache space is written into the cache space management table, as shown in Table 3-2, the cache space management table records the physical address (Physics Block Address, physical block address, abbreviated as physical address, PBA) of the controller memory corresponding to each strip.

[0288] Table 3-2 Cache space management table

[0289]

[0290]

[0291] When the cache needs to be searched, first, the index of the strip to which the virtual logical address corresponding to the access command is mapped is determined based on the access command, and then whether the cache space is allocated for the strip is queried in the cache space management table according to the index of the strip. The application takes NS as the management unit, takes the index of the strip in which the virtual logical address is located as the KEY, and takes each physical address allocated for the strip as the Value, to construct a key-value pair. When the read-write command needs to search the data stored in the cache space, it can be quickly hit.

[0292] S4220, according to the cache address space, the read-write data determined based on the access command of the non-volatile storage array 200 is cached to the controller memory 140.

[0293] When any VIR_LBA in a stripe is used, the entire stripe where the VIR_LBA is located will also be allocated a virtual logical address, and a cache space of the entire stripe size will be applied. For example, when a write data command for NS1 is received, the data length is 5, and virtual logical addresses VIR_LBA0-VIR_LBA4 are allocated. Since VIR_LBA is allocated and managed in units of stripes, stripe 1 is allocated to the current write data command, and sufficient cache space is applied to the stripe from the controller memory for caching the write data to be received. The received write data is cached to the cache space corresponding to LBA0-LBA4.

[0294] S4230, if the access command is a read command, target data and pre-read data are read according to the target address stripe and cached to the controller memory.

[0295] In an embodiment, in order to greatly reduce the latency of a read command, the embodiment of the application supports pre-reading data. It can be understood that the caching of read and write data based on the access command for the non-volatile storage array 200 to the controller memory 140 according to the cache address space includes:

[0296] If the access command is a read command, the virtual logical address segment of the target data and the adjacent continuous virtual logical address segment are obtained according to the target address stripe;

[0297] The target data and the pre-read data are read from the non-volatile storage array 200 according to the virtual logical address segment and cached to the controller memory.

[0298] S4240, the target data is sent.

[0299] The target data requested by the read command is sent to the host, and the target data and the pre-read data are retained in the controller memory 140 for subsequent access commands related to the virtual logical address segment to be read directly from the controller memory 140.

[0300] For example, when a read command is received, a command for reading related continuous addresses is generated according to the target access address of the read command, and is transmitted to the redundancy module 120 (EC / RAID). The redundancy module 120 reads data from the non-volatile storage array 200 according to the related continuous addresses, and caches the read data to the controller memory 140. When the IOQ processor 113 subsequently receives a command for accessing the related continuous addresses, the above data can be quickly taken from the controller memory 140, thereby greatly reducing the latency of the read command.

[0301] In an embodiment, the method further includes:

[0302] If the access command is a read command, a target address stripe to which a virtual logical address segment to be accessed according to the read command belongs is determined;

[0303] A target cache address space in the cache space management table is matched according to an index of the target address stripe;

[0304] If the matching is successful, pre-read data is read from the target cache address space according to a cache address to be accessed according to the read command.

[0305] In an embodiment, the application not only supports write termination, greatly reduces write latency, but also identifies the activity level of data in the controller memory 140 to reduce wear on the SSD hard disk. Understandably, the method further includes: writing write data cached in the controller memory 140 to the non-volatile storage array 200 according to the activity level of the data. Under the premise of the write termination mechanism, the application enables the redundancy module 120 to identify the activity level of the data in the controller memory 140, temporarily store active data in the cache space, and not perform disk writing. When subsequent write commands update the data, the cache space can be directly completed, reducing wear on the SSD hard disk.

[0306] In an embodiment, the application supports the write summary function. When the redundancy module 120 writes data corresponding to a write command to the controller memory 140 managed by the redundancy module 120, the redundancy module 120 can send command completion information CQ to the remote host 300, without waiting for the data to be actually written to the SSD disk, thereby greatly reducing write latency. Understandably, in step S4220, the caching of read-write data determined based on an access command to the non-volatile storage array 200 to the controller memory 140 according to the cache address space includes:

[0307] If the read-write data is write data, after the write data is cached to the controller memory 140, command completion information is sent to the remote host 300.

[0308] Further, if the read-write data is write data, after the write data is cached to the controller memory 140, command completion information is sent to the remote host 300, including:

[0309] Performing integrity verification on the write data.

[0310] If the verification fails, prompt information of a data write error is sent to the remote host 300;

[0311] If the verification passes, command completion information is sent to the remote host 300.

[0312] In one embodiment, the application not only supports write termination, greatly reduces write latency, but also identifies the activity level of data in the controller memory 140 to reduce wear on the SSD hard disk. Understandably, the method further comprises: writing the write data cached in the controller memory 140 to the non-volatile storage array 200 according to the activity level of the data. Under the premise of the write termination mechanism, the application enables the redundancy module 120 to identify the activity level of the data in the controller memory 140, temporarily store the active data in the cache space, and not perform disk writing. When the data is updated by a subsequent write command, the update can be directly completed in the cache space, reducing wear on the SSD hard disk.

[0313] The storage array data read-write method of the application embodiment is introduced below in combination with an example of a write command, specifically including the following steps:

[0314] S4301, the redundancy module 120 receives a write command, determines the mapped stripe according to the namespace and target virtual logical address accessed by the current write command.

[0315] S4302, queries whether the stripe is in the cache according to the index of the stripe in the established cache space management table. If the stripe is in the cache, it indicates that the cache address space (for example, PBAx-PBAy) has been allocated for the stripe, and step S4304 is performed; if not, it indicates that no cache address space has been allocated for the stripe, and step S4303 is performed.

[0316] S4303, applies for cache address space in the controller memory 140 for the stripe, for example, PBAx-PBAy.

[0317] S4304, sends R2T (Ready to Transfer, indicating that the cache address space is ready) to the host to instruct the remote host 300 to send the data to be written.

[0318] S4305, the redundancy module 120 performs integrity check on the data to be written. If the check fails, a CQ with an error prompt is sent to the remote host 300; if the check passes, a CQ with a completion status (corresponding to command completion information) is sent and step S4306 is performed.

[0319] S4306, stores the data to be written after integrity check in the allocated cache address space.

[0320] The storage array data read-write method of the application embodiment is introduced below in combination with an example of a read command, specifically including the following steps:

[0321] S4401, the redundancy module 120 receives a read command, and determines a mapped stripe according to a namespace and a target virtual logical address accessed by the current read command.

[0322] S4402, whether the stripe is in the cache is queried in the cache space management table according to an index of the stripe. If the stripe is in the cache, step S4404 is executed, and if not, step S4403 is executed.

[0323] S4403, a cache address space, for example, PBA m-PBA n, is applied for the stripe in the controller memory 140.

[0324] S4404, whether a physical address corresponding to the virtual logical address of the stripe is used is judged. If used, it indicates that pre-read data already exists, and the pre-read data cached in the physical address is directly read as read data.

[0325] If not used, a pre-read command for reading data corresponding to the entire stripe is initiated to the SSD hard disk, and the read pre-read data is stored in the allocated cache address space.

[0326] S4405, read data in the physical address corresponding to the target virtual logical address is returned to the remote host 300.

[0327] The application also provides a terminal device. Illustratively, the terminal device includes a processor and a memory. The memory stores a computer program. The processor runs the computer program, so that the terminal device executes the functions of each module in the above-mentioned cache management method of a storage array or the above-mentioned cache management device of a storage array.

[0328] The processor can be an integrated circuit chip with a signal processing capability. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU), and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or at least one of the above. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps, and logic block diagrams in the embodiments of the application.

[0329] The memory can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), and the like. Among them, the memory is used to store a computer program, and the processor can execute the computer program correspondingly after receiving an execution instruction.

[0330] The application further provides a computer readable storage medium for storing the computer program used in the terminal device. For example, the computer readable storage medium can include, but is not limited to, a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0331] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other ways. The apparatus embodiments described above are only schematic, for example, the flow charts and block diagrams in the drawings show the possible implementation architectures, functions and operations of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flow chart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that, in alternative implementation ways, the functions noted in the block can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flow chart, and the combination of blocks in the structural diagram and / or flow chart, can be implemented by a dedicated hardware-based system for executing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0332] In addition, each functional module or unit in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0333] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.

[0334] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A cache management method for a storage array, characterized in that: Applied to a storage array controller, the storage array controller includes a storage interface control module, a redundancy module, a non-volatile storage control module, and a controller memory, the method includes: Mapping the storage array into a virtual logical address space according to the namespace, wherein the logical addresses of the storage array are mapped one-to-one to obtain the virtual logical address space; Dividing the virtual logical address space into virtual logical address groups, wherein continuous logical address blocks in the virtual logical address space are divided into a namespace array according to the redundancy mode of the storage array, a row of the logical address blocks is regarded as a stripe, wherein the number of logical address blocks in the stripe is the same as the number of redundant group members in the storage array, and the virtual logical address group includes one or more stripes; Determining the activity level of cached data in the virtual logical address group according to the storage state corresponding to the virtual logical address group; Determining a target virtual logical address group that needs to be stored in the storage array according to the activity level specifically includes: determining target cache data in the target virtual logical address group that needs to be stored in the storage array according to the storage state.

2. The cache management method for a storage array according to claim 1, wherein: The storage status includes a read / write status flag corresponding to each logical address block in the virtual logical address group; The determining, according to the storage state, target cache data in the target virtual logical address group that needs to be stored in the storage array includes: The cache data of the logical address block corresponding to the read / write status flag bit in the target virtual logical address group is in the write state is determined as the target cache data.

3. The cache management method for a storage array according to claim 2, wherein: The method further comprises: When writing the target cache data into the storage array, redundancy calculation is performed on the cache data in each logical address block in the stripe to obtain verification data and write it into the verification block in the stripe; and the read-write status flag corresponding to the verification block is set to the write state.

4. The cache management method for a storage array according to claim 2, wherein: The method further includes: updating the corresponding storage status according to the read and write operations of the virtual logical address groups corresponding to the namespaces in the cache, specifically including: If the data stored in the cache of the logical address block is first data, setting the read / write status flag corresponding to the logical address block to a write state, wherein the first data is write data sent by the remote host; If the data stored in the cache of the logical address block is second data, the read / write status flag corresponding to the logical address block is set to a read state; the second data is empty data or read data read from the storage array.

5. The cache management method for a storage array according to claim 3, wherein: The storage status includes a full flag corresponding to each virtual logical address group; The method further comprises: Determine whether each read / write status flag corresponding to each logical address block in the virtual logical address group is in the write state, and obtain the number of logical address blocks whose read / write status flag is in the write state; If the number of blocks is greater than a preset threshold, determining that the full flag corresponding to the virtual logical address group is in a full state; The method further includes: using the virtual logical address group corresponding to the full flag being in the full state as the target virtual logical address group.

6. The cache management method for a storage array according to claim 1, wherein: The step of determining the target virtual logical address group to be stored in the storage array according to the activity level includes: determining the virtual logical address group with a low activity level as the target virtual logical address group; And / or, when the cache space is full, the virtual logical address group of the middle activity level is determined as the target virtual logical address group.

7. The cache management method for a storage array according to claim 1, wherein: The storage state includes a number of activity factor flag bits corresponding to each virtual logical address group; The method further includes: updating corresponding storage states according to read and write operation commands of the virtual logical address groups corresponding to each namespace in the cache, specifically including: According to the frequency of receiving the read and write operation commands for the virtual logical address group, the corresponding activity factor flag value is set.

8. The cache management method for a storage array according to claim 7, wherein: The step of setting the corresponding activity factor flag value according to the frequency of the read and write operation commands received by the virtual logical address group includes: Counting objects based on the virtual logical address group according to a preset frequency and counting period; During the counting period, the activity factor flag value is updated according to a preset updating rule based on whether the virtual logical address group receives a read or write operation command.

9. The cache management method for a storage array according to claim 8, wherein: The updating of the activity factor flag value according to a preset updating rule based on whether the virtual logical address group receives a read or write operation command within the counting period includes: If the read / write operation command is not received within the counting period, the respective digits of the activity factor flag value are retrieved according to the set digit order, and the second state value is updated and written to the digit corresponding to the first state value; wherein, in the initial state, the values ​​of the respective digits of the activity factor flag value are all the first state values; If the read / write operation command is received within the counting cycle, the respective digits of the activity factor flag value are retrieved in the reverse order of the set digits, and the first state value is updated and written to the digit corresponding to the first second state value.

10. The cache management method of a storage array according to claim 9, wherein: The determining, according to the storage state corresponding to the virtual logical address group, the activity level of cached data in the virtual logical address group includes: If the numbers of all digits in the activity factor flag value corresponding to the virtual logical address group are all the second state values, the activity level of the cached data in the virtual logical address group is determined to be a low activity level; If the numbers on each digit of the activity factor flag value corresponding to the virtual logical address group are all the first state values, the activity level of the cached data in the virtual logical address group is determined to be a high activity level; Counting the number of digits of each digit of the activity factor flag value that are the first state value; If the number of digits is greater than a preset number, the activity level of the cached data in the virtual logical address group is determined to be an intermediate activity level.

11. The cache management method for a storage array according to any one of claims 1 to 10, characterized in that: The virtual logical address group is the granularity of the read and write operation commands; The storage state includes a number of lock flag bits equal to the number of groups of virtual logical address groups; The method further comprises: When operating the current virtual logical address group according to the read / write operation command, setting the lock flag bit corresponding to the current virtual logical address group to a locked state; Delaying the read and write operation commands accessing the virtual logical address group in the locked state.

12. The cache management method for a storage array according to claim 1, wherein: The step of determining the target virtual logical address group to be stored in the storage array according to the activity level includes: Determining a target logical address for storing the target cache data in the storage array according to the virtual logical address group and a preset logical address mapping relationship; The target cache data is written into the storage array according to the target logical address.

13. A cache management device for a storage array, characterized in that: include: Address group division module, activity level determination module, and disk storage module; An address group division module is configured to map a storage array into a virtual logical address space according to a namespace, and to divide the virtual logical address space into virtual logical address groups; the address group division module is specifically configured to: map the logical addresses of the storage array one-to-one to obtain a virtual logical address space; divide the virtual logical address space into a number of virtual logical address subspaces equal to the preset number according to a preset number of namespaces; divide each continuous logical address block in the virtual logical address subspace into a namespace array according to a redundancy mode of the storage array; use a row of the logical address blocks in the namespace array as a stripe, and divide the namespace array into a plurality of virtual logical address groups, wherein the number of logical address blocks in the stripe is the same as the number of redundant group members in the storage array, and the virtual logical address group includes one to multiple stripes; an activity level determination module, configured to determine the activity level of cached data in the virtual logical address group according to a storage state corresponding to the virtual logical address group; The disk placement module is used to determine the target virtual logical address group that needs to be stored in the storage array according to the activity level; the disk placement module is specifically used to determine the target cache data in the target virtual logical address group that needs to be stored in the storage array according to the storage status.

14. A storage array controller, characterized in that: include: Redundancy module, storage interface control module, controller memory and non-volatile storage control module; The redundancy module is respectively connected to the storage interface control module, the non-volatile storage control module and the controller memory; The storage interface control module is in communication with a remote host, and is configured to receive and parse message data sent by the remote host to obtain operation commands, schedule and manage the operation commands based on the namespace, and transmit the commands to the redundancy module; the non-volatile storage control module is in communication with the storage array, and responds to data transmission requests from the redundancy module by mapping the controller memory to implement data interaction with the storage array; The redundancy module implements the cache management method for the storage array according to any one of claims 1-12.

15. A computer-readable storage medium, characterized in that The computer program is stored therein, and when the computer program is executed on a processor, the cache management method for the storage array according to any one of claims 1 to 12 is implemented.

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