System and method for dual-bios booting of a spatial high-performance processor

Abstract

The application provides a system and method for dual-BIOS starting of a spatial high-performance processor, comprising: a controller, configured to read a BIOS program before the processor is powered on, check the correctness of the BIOS program, correct BIOS program data errors if any, and forward the BIOS program that passes the check to the processor through an interface converter after the processor is powered on; the controller is also configured to control the power supply and reset of the processor, monitor the starting state and running state of the processor; and update the memory based on an update instruction; a memory, comprising a first BIOS memory and a second BIOS memory, configured to store the BIOS program and the check result of the controller; and a processor, configured to receive the BIOS program of the controller; the application can realize error detection and correction of single-bit errors, and can timely discover and correct single-bit errors through updating, thus meeting the demand of complex computing tasks and ensuring the stability and reliability of the system.

Description

Technical Field

[0001] This invention belongs to the field of high-performance processor technology, specifically to a system and method for dual BIOS booting of a space high-performance processor. Background Technology

[0002] The Basic Input / Output System (BIOS) is firmware built into the computer's motherboard. Its main functions include hardware detection and initialization, system settings, boot management, and providing a basic interface for interaction between the operating system and the hardware. It plays a crucial role in the computer's boot process. The BIOS is typically stored in non-volatile memory such as PROM, EPROM, EEPROM, FRAM, MRAM, and FLASH. In space applications, such as computer systems on satellites or spacecraft, the BIOS memory is susceptible to single-event effects, causing single-event upsets (SEUs). Incorrectly modified instructions or data in the BIOS program can lead to errors during computer startup, preventing the computer from booting. To ensure system reliability and stability, multi-mode redundant memory, such as dual BIOS, and radiation hardening measures are often employed.

[0003] Current dual-BIOS technology achieves this by installing two physically independent BIOS chips on the motherboard, using a backup method to prevent the primary BIOS from being damaged by virus attacks, software malfunctions, or update errors. The system prioritizes the primary BIOS during startup, and automatically switches to the backup BIOS if an error or corruption is detected. However, current technology typically only verifies the correctness of the BIOS and cannot automatically repair errors during the boot process. If a BIOS problem exists, the relevant applications can only be run and repaired after the operating system has booted. In space applications, high-energy particles (such as cosmic rays) can easily cause simultaneous damage to both BIOSes. In this case, the system will fail to boot and must be returned to the factory for repair, which is difficult to implement in space applications. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a system and method for dual BIOS booting of a high-performance space processor, which solves the technical problems of poor reliability and difficulty in repair of BIOS space applications in the existing related technologies.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A space-based high-performance processor dual-BIOS boot system, comprising:

[0007] The controller is used to read the BIOS program and verify its correctness before the processor is powered on. If there are errors in the BIOS program data, the controller corrects the errors. After the processor is powered on, the controller forwards the verified BIOS program to the processor via an interface converter. The controller is also used to control the processor's power supply and reset, monitor the processor's startup and running states, and update the memory based on update instructions.

[0008] The memory, including a first BIOS memory and a second BIOS memory, is used to store the BIOS program and the controller's verification results; and

[0009] The processor is used to receive the BIOS program from the controller.

[0010] Furthermore, the controller includes an uploading program caching module, a Hamming code verification module, a Hamming code decoding module, a status monitoring module, a CRC verification module, and a data selection module;

[0011] The betting program cache module is used to temporarily store the betting program, receive external program input or data selection module program input, and output to the Hamming code verification module.

[0012] The Hamming code verification module is used to verify the correctness of the Hamming code of the BIOS program data. It receives the Hamming code-encoded BIOS program data from the above program cache module. If the verification is correct, the BIOS program data is written to the BIOS memory. If the verification is incorrect, no data is written.

[0013] The Hamming code decoding module is used to read program data from the BIOS memory, parse valid data in the Hamming code, locate and correct erroneous data, and output the correct or corrected valid data to the CRC check module and the data selection module.

[0014] The status monitoring module is used to monitor the processor's operating status, control the processor power supply, and reset the processor.

[0015] The CRC verification module is used to verify the correctness of each data segment of BIOS, receive data from the Hamming code decoding module, and store the verification result in the CRC verification result memory.

[0016] The data selection module is used to select and judge data word by word based on the input of the betting program cache module, the Hamming code decoding module and the CRC check result storage, and output the selected data to the interface converter or the betting program cache module.

[0017] Furthermore, the CRC check result storage is used to store the CRC check results of multiple program segments.

[0018] Furthermore, the status monitoring module includes a timer, a counter, and a threshold comparator; the first BIOS memory and the second BIOS memory serve as backups for each other.

[0019] Furthermore, both the first and second BIOS memories are used to store BIOS programs encoded with Hamming code and CRC checksum.

[0020] A method for dual-booting IOS on a high-performance space processor includes the following steps:

[0021] Before the processor is powered on, the controller reads the BIOS program from the memory, verifies the correctness of the read BIOS program based on Hamming code and CRC, and stores the CRC verification result.

[0022] After the processor powers on, the controller reads the BIOS program from the memory according to the processor's read request, verifies and corrects erroneous data based on Hamming code, reads the stored CRC check result, selects data based on the CRC check result and the Hamming code check result, and forwards the data to the processor via the interface converter.

[0023] The controller periodically collects the processor's startup completion indication signal and normal operation indication signal, and monitors the processor's startup status and operation status based on the collected startup completion indication signal and normal operation indication signal, and controls the processor's power supply and reset based on the startup status and operation status.

[0024] If the processor is running normally or in a powered-off state, the controller updates the memory based on the update instruction, or if there is a BIOS program data error that cannot be corrected by itself, it receives external program input to update the memory.

[0025] Furthermore, the controller is also used to receive external program data. When the controller forwards the corrected or verified data to the processor, it selects the BIOS program data of the first BIOS memory or the second BIOS memory, or the external program data received by the controller, according to the following principles.

[0026] If the CRC check result of the first BIOS memory is correct, then the BIOS program data of the first BIOS memory is selected.

[0027] If the CRC check result of the first BIOS memory is incorrect, but the CRC check result of the second BIOS memory is correct, then the BIOS program data of the second BIOS memory is selected.

[0028] If the CRC check results of the first BIOS memory and the second BIOS memory are both incorrect, then the BIOS program data of the first BIOS memory or the second BIOS memory is selected based on the result of the Hamming code decoding module.

[0029] If the Hamming code result of the first BIOS memory is correct or the error has been corrected, then the first BIOS memory is selected. If the Hamming code result of the first BIOS memory is incorrect and the error has not been corrected, and the Hamming code result of the second BIOS memory is correct or the error has been corrected, then the BIOS program data of the second BIOS memory is selected.

[0030] If the Hamming code results of both the first BIOS memory and the second BIOS memory are incorrect and cannot be corrected, then the above-mentioned program cache module is read. If the above-mentioned program exists and the Hamming code result is correct or the error has been corrected, then the BIOS program data of the above-mentioned program cache module is selected.

[0031] Otherwise, stop selecting BIOS program data.

[0032] Furthermore, after power-on, the processor uses a counter to count from 0, and the counter is reset when a startup completion indication signal or a normal operation indication signal is received.

[0033] If no start-up completion indicator signal or normal operation indicator signal is received when the count value is greater than the threshold comparator value, a reset signal is sent.

[0034] If the number of reset signals sent exceeds the threshold, the power-on signal will be disconnected.

[0035] Furthermore, the prerequisite for the controller to output a power-on signal is that after receiving a control input power-on command and after the controller is powered on, it completes at least one CRC check on the first BIOS memory and the second BIOS memory, and writes the check result into the memory.

[0036] Furthermore, the update memory includes internal updates and external updates;

[0037] The internal update is as follows:

[0038] The controller reads the BIOS program from the memory and verifies the correctness of the BIOS program based on Hamming code and CRC. If the data of the BIOS program is incorrect, the block containing the incorrect data is marked, the incorrect data is corrected, and the corrected BIOS program data is stored.

[0039] Verify the corrected BIOS program data stored in the memory; if correct, write it to and update the memory.

[0040] The external update is:

[0041] The controller receives external program input and temporarily stores the external program.

[0042] Verify the external program in the temporary storage; if correct, write it to and update the memory.

[0043] Compared with the prior art, the present invention has the following beneficial technical effects:

[0044] This invention provides a system and method for dual-BIOS booting of a high-performance space processor, comprising: a controller, configured to read and verify the correctness of the BIOS program before the processor is powered on; correct BIOS program data errors if any are found; and forward the verified BIOS program to the processor via an interface converter after the processor is powered on; the controller is also configured to control the processor's power supply and reset, monitor the processor's boot and running states, and update the memory based on update instructions; a memory, including a first BIOS memory and a second BIOS memory, for storing the BIOS program and the controller's verification results; and a processor. This application is used to receive the BIOS program of the controller; it can realize error detection and correction of single bit errors, and can automatically switch to another data path when one data path fails to be corrected. When the data in the uploaded program cache module is valid, the reliability of the data is further enhanced by the three-path data selection mechanism. At the same time, it can monitor the processor's running status, perform a restart operation when the startup fails or an error occurs, and output the processor's running status in real time. This application effectively solves the problem of multi-bit errors that cannot be detected, and can promptly detect and correct single bit errors through updates, preventing the occurrence of multiple bit errors. This application not only meets the needs of complex computing tasks, but also ensures the stability and reliability of the system. Attached Figure Description

[0045] Figure 1 A system diagram of dual BIOS boot for a space high-performance processor according to an embodiment of the present disclosure is shown. Detailed Implementation

[0046] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0047] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0049] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0050] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0051] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0052] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0053] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0054] Figure 1 A system diagram of a dual-BIOS boot system for a space high-performance processor according to an embodiment of this disclosure is shown, such as... Figure 1 As shown, including

[0055] The controller is used to read the BIOS program and verify its correctness before the processor is powered on. If there are errors in the BIOS program data, the controller corrects the errors. After the processor is powered on, the controller forwards the verified BIOS program to the processor via an interface converter. The controller is also used to control the processor's power supply and reset, monitor the processor's startup and running states, and update the memory based on update instructions.

[0056] The memory, including a first BIOS memory and a second BIOS memory, is used to store the BIOS program and the controller's verification results; and

[0057] The processor is used to receive the BIOS program from the controller.

[0058] It should be noted that in this embodiment, the BIOS program is not stored in its original form, but rather as a version processed with Hamming code and CRC checksum. The original BIOS program is divided into multiple segments, with a segmentation interval of 128 characters. A CRC checksum is calculated for each program segment to obtain the CRC checksum result. The CRC checksum result and the BIOS program are sorted alternately. For example, the 128-character BIOS program is sorted first, then the corresponding CRC checksum result is sorted, then the 128-character BIOS program is sorted again, and so on, until the entire BIOS program and checksum result are sorted. Then, Hamming code encoding is applied to the sorted data to obtain the encoded data. The encoded data is stored in the first BIOS memory and the second BIOS memory.

[0059] In a preferred embodiment of this disclosure, the controller includes an uploading program caching module, a Hamming code verification module, a Hamming code decoding module, a status monitoring module, a CRC verification module, and a data selection module;

[0060] The betting program cache module is used to temporarily store the betting program, receive external program input or data selection module program input, and output to the Hamming code verification module.

[0061] The Hamming code verification module is used to verify the correctness of the Hamming code of the BIOS program data. It receives the Hamming code-encoded BIOS program data from the above program cache module. If the verification is correct, the BIOS program data is written to the BIOS memory. If the verification is incorrect, no data is written.

[0062] The Hamming code decoding module is used to read program data from the BIOS memory, parse valid data in the Hamming code, locate and correct erroneous data, and output the correct or corrected valid data to the CRC check module and the data selection module. Specifically, the Hamming code decoding module reads the Hamming code-encoded BIOS data from the memory, parses the valid data, recalculates the check bits, and compares them with the read check bits to detect whether there are errors in the data. If the check result is correct, it is output directly. If an error is found, a single bit error is located and corrected using the Hamming code algorithm, and the corrected valid data is output. If multiple bit errors occur, exceeding its correction capability, an error report is output.

[0063] The status monitoring module is used to monitor the processor's operating status, control the processor power supply, and reset the processor.

[0064] The CRC check module is used to check the correctness of each data segment of the BIOS, receive data from the Hamming code decoding module, and store the check result in the CRC check result memory.

[0065] The data selection module is used to select and judge data word by word based on the input of the betting program cache module, the Hamming code decoding module and the CRC check result storage, and output the selected data to the interface converter or the betting program cache module.

[0066] Specifically, such as Figure 1As shown, the controller employs a high-reliability controller with radiation-hardened characteristics. It includes an uploading program cache module, a Hamming code verification module, a Hamming code decoding module, a status monitoring module, a CRC verification module, and a data selection module. The uploading program cache module receives program input and is connected to both the Hamming code verification module and the data selection module. The Hamming code verification module is connected to both the first and second BIOS memories. The output signals of the first and second BIOS memories are connected to the Hamming code decoding module. The output signal of the Hamming code decoding module is connected to both the CRC module and the data selection module. The signal from the CRC module is transmitted to the data selection module via a CRC verification result memory. The output signal of the data selection module is connected to both the uploading program cache module and the interface converter. The interface converter inputs the received signal to the processor. The processor is a high-performance processor, typically a commercially available non-radiation-hardened chip.

[0067] Specifically, the Hamming code decoding module outputs the decoded data to the CRC module, which uses the CRC method to verify the correctness of the BIOS data and stores the verification result in the CRC verification result memory. The available space in the CRC verification result memory must be greater than the number of segments in the original BIOS program. According to the BIOS program storage rules, every 128-word BIOS program and its corresponding CRC check result are stored alternately. The decoding module sequentially calculates the CRC check result for each 128-word BIOS program. If it matches the CRC check result, it writes a 1 to the address corresponding to the segment number in the CRC verification result memory; if it does not match the CRC check result, it writes a 0 to the address corresponding to the segment number in the CRC verification result memory. This process is repeated to complete the CRC check of the entire BIOS program, and all check results are written to the CRC verification result memory. Further, the power supply receives a power-on signal, powering on the high-performance processor. After power-on, the high-performance processor boots up and sends a BIOS read request to the interface converter. The data communication interface of the high-performance processor can be EMMC or SPI, and the data communication interface of the high-reliability controller can be EMIF or SPI. The interface converter has EMIF, EMMC, and SPI interface conversion functions as well as address translation functions to enable communication between a highly reliable controller and a high-performance processor.

[0068] After the CRC check is completed, if the status monitoring module receives a power-on command from the control input, it outputs a power-on signal to the high-performance processor power supply. The conditions for the status monitoring module to output a power-on signal are: receiving a power-on command from the control input, and the high-reliability controller completing at least one CRC check on the first BIOS memory and the second BIOS memory after powering on, and writing the check result into the CRC check result memory.

[0069] The data selection module selects data character by character. The selection method involves reading the CRC check result of the current program segment from the CRC check result memory. If the CRC check result of the first BIOS memory is correct, the first BIOS memory is selected. If the CRC check result of the first BIOS memory is incorrect, but the CRC check result of the second BIOS memory is correct, the second BIOS memory is selected. If the CRC check results of both the first BIOS memory and memory 2 are incorrect, the selection is based on the result of the Hamming code decoding module. If the Hamming code result of the first BIOS memory is correct or the error has been corrected, the first BIOS memory is selected. If the Hamming code result of the first BIOS memory is incorrect and has not been corrected, but the Hamming code result of the second BIOS memory is correct or the error has been corrected, the second BIOS memory is selected. If the Hamming code results of both the first BIOS memory and memory 2 are incorrect and have not been corrected, the uploading program cache module is read. If the uploading program exists and the Hamming code result is correct or the error has been corrected, the uploading program cache module is selected. If none of the above conditions are met, data selection stops. Based on the above method, the data selection module forwards the corrected BIOS program data to the high-performance processor via the interface converter.

[0070] Preferably, in this embodiment of the disclosure, the CRC check result storage is used to store the CRC check results of multiple program segments. Specifically, Cyclic Redundancy Check (CRC) is an error detection method used to detect errors that may occur after data transmission or storage. It generates a check value (i.e., a CRC checksum) by performing a specific algorithm operation on a set of data. This check value is then transmitted or stored along with the data. At the receiving end, the same algorithm is applied to the received data to generate a new check value. If the newly generated check value is the same as the originally sent check value, then it can be considered that no error occurred during the data transmission or storage.

[0071] For scenarios requiring the processing of multiple program segments, such as different parts of a firmware update package or multiple records in a database, each program segment is typically subjected to a CRC check, and the CRC check result for each segment is stored. This storage of check results can be achieved using a dedicated "CRC check result storage," although in practical applications, this "storage" may not always refer to a physically independent storage device, but could be a region in memory, a table in a database, or a file in a file system, etc.

[0072] In other words, when data is read or used, the CRC value of the data can be recalculated and compared with the stored CRC value to quickly detect whether the data has been corrupted during storage or transmission. Furthermore, when data errors are detected, comparing the CRC check results can narrow down the problem area and help quickly pinpoint the source of data corruption.

[0073] Preferably, in this embodiment of the disclosure, the status monitoring module includes a timer, a counter, and a threshold comparator; specifically, the method for status monitoring by the controller status monitoring module is as follows:

[0074] After the high-performance processor powers on, its counter starts counting from 0. The counter resets upon receiving a startup completion indicator signal or a normal operation indicator signal. If the count value exceeds the threshold comparator value and no startup completion indicator signal or normal operation indicator signal is received, a reset signal is sent. If more than three reset signals are sent, the power-on signal is disconnected.

[0075] After the high-performance processor starts up, it sends a startup completion indication signal to the controller's status monitoring module. Failure to output this signal within the agreed-upon time indicates startup failure. During high-performance processor operation, it periodically sends a normal operation indication signal to the controller's status monitoring module. Failure to output this signal within the agreed-upon time indicates abnormal operation. The controller continuously monitors the high-performance processor's operating status and restarts it if startup fails or an abnormality occurs. If the number of restarts exceeds three, the power is shut off.

[0076] Preferably, in this embodiment of the disclosure, the first BIOS memory and the second BIOS memory serve as backups for each other; furthermore, both the first BIOS memory and the second BIOS memory are used to store BIOS programs encoded with Hamming code and CRC checksum.

[0077] This disclosure also provides a method for dual-BIOS booting of a space high-performance processor, including the following steps:

[0078] Before the processor is powered on, the controller reads the BIOS program from the memory, verifies the correctness of the read BIOS program based on Hamming code and CRC, and stores the CRC verification result.

[0079] After the processor powers on, the controller reads the BIOS program from the memory according to the processor's read request, verifies and corrects erroneous data based on Hamming code, reads the stored CRC check result, selects data based on the CRC check result and the Hamming code check result, and forwards the data to the processor via the interface converter.

[0080] The controller periodically collects the processor's startup completion indication signal and normal operation indication signal, and monitors the processor's startup status and operation status based on the collected startup completion indication signal and normal operation indication signal, and controls the processor's power supply and reset based on the startup status and operation status.

[0081] If the processor is running normally or in a powered-off state, the controller updates the memory based on the update instruction, or if there is a BIOS program data error that cannot be corrected by itself, it receives external program input to update the memory.

[0082] Specifically, the update instructions include control input update instructions and internal control update instructions. The control input update instructions are instructions received by the controller status monitoring module from external control inputs, i.e., external program inputs. They are passive update instructions, i.e., external update processes. The internal control update instructions are update instructions triggered by the timer of the controller status monitoring module at certain time intervals, i.e., internal update processes. The control input update instructions are a one-time trigger mechanism compared to the internal control update instructions.

[0083] Preferably, the controller is also used to receive external program data. When the controller forwards the corrected or verified data to the processor, it selects the program data of the BIOS in the first BIOS memory or the second BIOS memory, or the external program data received by the controller, according to the following principles.

[0084] If the CRC check result of the first BIOS memory is correct, then the BIOS program data of the first BIOS memory is selected.

[0085] If the CRC check result of the first BIOS memory is incorrect, but the CRC check result of the second BIOS memory is correct, then the BIOS program data of the second BIOS memory is selected.

[0086] If the CRC check results of the first BIOS memory and the second BIOS memory are both incorrect, then the BIOS program data of the first BIOS memory or the second BIOS memory is selected based on the result of the Hamming code decoding module.

[0087] If the Hamming code result of the first BIOS memory is correct or the error has been corrected, then the first BIOS memory is selected. If the Hamming code result of the first BIOS memory is incorrect and the error has not been corrected, and the Hamming code result of the second BIOS memory is correct or the error has been corrected, then the BIOS program data of the second BIOS memory is selected.

[0088] If the Hamming code results of both the first BIOS memory and the second BIOS memory are incorrect and cannot be corrected, then the above-mentioned program cache module is read. If the above-mentioned program exists and the Hamming code result is correct or the error has been corrected, then the BIOS program data of the above-mentioned program cache module is selected.

[0089] Otherwise, stop selecting BIOS program data.

[0090] In a preferred embodiment of this disclosure, after the processor is powered on, a counter is used to count from 0, and the counter is reset when a startup completion indication signal or a normal operation indication signal is received.

[0091] If no start-up completion indicator signal or normal operation indicator signal is received when the count value is greater than the threshold comparator value, a reset signal is sent.

[0092] If the number of reset signals sent exceeds the threshold, the power-on signal will be disconnected.

[0093] In a preferred embodiment of this disclosure, the prerequisite for the controller to output a power-on signal is that after receiving a control input power-on command and powering on, the controller completes at least one CRC check on the first BIOS memory and the second BIOS memory, and writes the check result into the memory.

[0094] In a preferred embodiment of this disclosure, the update memory includes internal updates and external updates;

[0095] The internal update is as follows:

[0096] The controller reads the BIOS program from the memory and verifies the correctness of the BIOS program based on Hamming code and CRC. If the data of the BIOS program is incorrect, the block containing the incorrect data is marked, the incorrect data is corrected, and the corrected BIOS program data is stored.

[0097] Verify the corrected BIOS program data stored in the memory; if correct, write it to and update the memory.

[0098] The external update is:

[0099] The controller receives external program input and temporarily stores the external program.

[0100] Verify the external program in the temporary storage; if correct, write it to and update the memory.

[0101] Specifically, when the processor is running normally or powered off, there are no read / write operations on the BIOS memory. The controller can use this time to verify and update the BIOS memory, periodically verifying and correcting single-bit errors to prevent multiple-bit errors. Alternatively, it can rewrite the BIOS program in case of a serious, uncorrectable error.

[0102] The first and second B IOS memories can perform internal and external updates. The internal update data path is as follows: from the data selection module, via the uploading program cache module and the Hamming code verification module to the first and second B IOS memories. The external update data path is as follows: from external program input, via the uploading program cache module and the Hamming code verification module to the first and second B IOS memories.

[0103] The internal update process is as follows: The high-reliability controller reads the BIOS program from memory and verifies its correctness based on Hamming codes and CRC checks. When an error is detected, the block containing the erroneous data is marked, and the erroneous data is corrected. The corrected BIOS program data is then written to the upload program cache module via the data selection module. If the program data is correct, it does not need to be written to the upload program cache module. The upload program cache module receives the corrected data and outputs it to the Hamming code verification module. The Hamming code verification module verifies the correctness of the Hamming code. If the verification is correct, the data is written to the BIOS memory to correct the erroneous data in the memory.

[0104] The external update process is as follows: The high-reliability controller receives external program input and temporarily stores the program in the upload program cache module. The upload program cache module receives data and outputs it to the Hamming code verification module. The Hamming code verification module verifies the correctness of the Hamming code in the data. If the verification is correct, the data is written to the BIOS memory to update the BIOS program in the memory.

[0105] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the scope of the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0106] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A system for dual-BIOS booting of a high-performance space processor, characterized in that, include The controller is used to read the BIOS program and verify its correctness before the processor is powered on. If there is a BIOS program data error, it corrects the BIOS program data error. After the processor is powered on, it forwards the verified BIOS program to the processor via the interface converter. It is also used to control the processor's power supply and reset, monitor the processor's startup and running status, and update the memory based on update instructions; the controller includes an uploading program cache module, a Hamming code verification module, a Hamming code decoding module, a status monitoring module, a CRC verification module, and a data selection module; The betting program cache module is used to temporarily store the betting program, receive external program input or data selection module program input, and output to the Hamming code verification module. The Hamming code verification module is used to verify the correctness of the Hamming code of the BIOS program data. It receives the BIOS program data encoded in Hamming code from the above-mentioned program cache module. If the verification is correct, the BIOS program data is written to the BIOS memory. If the verification is incorrect, no data is written. The Hamming code decoding module is used to read program data from the BIOS memory, parse valid data in the Hamming code, locate and correct erroneous data, and output the correct or corrected valid data to the CRC check module and the data selection module. The status monitoring module is used to monitor the processor's operating status, control the processor power supply, and reset the processor. The CRC check module is used to check the correctness of each data segment of the BIOS, receive data from the Hamming code decoding module, and store the check result in the CRC check result memory. The data selection module is used to select and judge data word by word based on the input of the betting program cache module, the Hamming code decoding module and the CRC check result storage, and output the selected data to the interface converter or the betting program cache module. The memory includes a first BIOS memory and a second BIOS memory, used to store the BIOS program and the controller's verification results; as well as The processor is used to receive the BIOS program from the controller.

2. The system for dual-BIOS booting of a high-performance space processor according to claim 1, characterized in that, The CRC check result storage is used to store the CRC check results of multiple program segments.

3. The system for dual BIOS booting of a high-performance space processor according to claim 1, characterized in that, The status monitoring module includes a timer, a counter, and a threshold comparator; the first BIOS memory and the second BIOS memory are backups of each other.

4. The system for dual BIOS booting of a high-performance space processor according to claim 3, characterized in that, Both the first BIOS memory and the second BIOS memory are used to store BIOS programs encoded with Hamming code and CRC checksum.

5. A method for dual-BIOS booting of a high-performance space processor, characterized in that, The system based on the dual BIOS boot of the space high-performance processor according to any one of claims 1-4 includes the following steps: Before the processor is powered on, the controller reads the BIOS program from the memory, verifies the correctness of the BIOS program based on Hamming code and CRC check, and stores the CRC check result; After the processor powers on, the controller reads the BIOS program from the memory according to the processor's read request, verifies and corrects erroneous data based on Hamming code, reads the stored CRC check result, selects data based on the CRC check result and Hamming code check result, and forwards the data to the processor via the interface converter. The controller periodically collects the processor's startup completion indication signal and normal operation indication signal, and monitors the processor's startup status and operation status based on the collected startup completion indication signal and normal operation indication signal, and controls the processor's power supply and reset based on the startup status and operation status. If the processor is running normally or in a powered-off state, the controller updates the memory based on the update instruction, or if there is a BIOS program data error that cannot be corrected by itself, it receives external program input to update the memory.

6. The method for dual BIOS booting of a high-performance space processor according to claim 5, characterized in that, The controller is also used to receive external program data. When the controller forwards the corrected or verified data to the processor, it selects the BIOS program data of the first BIOS memory or the second BIOS memory, or the external program data received by the controller, according to the following principles. If the CRC check result of the first BIOS memory is correct, then the BIOS program data of the first BIOS memory is selected; If the CRC check result of the first BIOS memory is incorrect and the CRC check result of the second BIOS memory is correct, then the BIOS program data of the second BIOS memory is selected. If the CRC check results of the first BIOS memory and the second BIOS memory are both incorrect, the BIOS program data of the first BIOS memory or the second BIOS memory is selected based on the result of the Hamming code decoding module. If the Hamming code result of the first BIOS memory is correct or the error has been corrected, then the first BIOS memory is selected. If the Hamming code result of the first BIOS memory is incorrect and the error has not been corrected, and the Hamming code result of the second BIOS memory is correct or the error has been corrected, then the BIOS program data of the second BIOS memory is selected. If the Hamming code results of both the first BIOS memory and the second BIOS memory are incorrect and cannot be corrected, then the uploading program cache module is read. If the uploading program exists and the Hamming code result is correct or the error has been corrected, then the BIOS program data of the uploading program cache module is selected. Otherwise, stop the selection of BIOS program data.

7. The method for dual BIOS booting of a high-performance space processor according to claim 5, characterized in that, After the processor is powered on, it uses a counter to count from 0. The counter is reset when a startup completion indication signal or a normal operation indication signal is received. If no start-up completion indicator signal or normal operation indicator signal is received when the count value is greater than the threshold comparator value, a reset signal is sent. If the number of reset signals sent exceeds the threshold, the power-on signal will be disconnected.

8. The method for dual BIOS booting of a high-performance space processor according to claim 5, characterized in that, The prerequisite for the controller to output a power-on signal is that after receiving a control input power-on command and powering on, the controller completes at least one CRC check on the first BIOS memory and the second BIOS memory, and writes the check result into the memory.

9. The method for dual BIOS booting of a high-performance space processor according to claim 5, characterized in that, The update memory includes internal updates and external updates; The internal update is as follows: The controller reads the BIOS program from the memory and verifies the correctness of the BIOS program based on Hamming code and CRC. If the data of the BIOS program is incorrect, the block containing the incorrect data is marked, the incorrect data is corrected, and the corrected BIOS program data is stored. Verify the corrected BIOS program data stored in the memory; if correct, write it to and update the memory. The external update is: The controller receives external program input and temporarily stores the external program. Verify the external program in the temporary storage; if correct, write it to and update the memory.

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