A method and system for realizing ultra-real-time behavioral-level timing simulation of medium and low frequency embedded systems

Abstract

The present invention provides a method and system for implementing medium- and low-frequency embedded super-real-time behavioral-level timing simulation, comprising loading and initializing a specified on-chip device according to target machine configuration information; setting a simulation time amplification factor for an IO instruction and a non-IO instruction statistical factor according to the minimum timing accuracy of the on-chip device; determining whether the current instruction is an IO instruction after each instruction is executed; when the number of non-IO instructions counted reaches a preset value, converting the currently counted non-IO instruction statistical factor into a simulation time parameter; when a simulation time condition is met, scheduling simulation events for devices that meet the simulation time condition in a simulation time scale order; exiting the scheduler after executing the currently passed simulation time; and executing the next round of instruction execution and simulation. The present invention has the advantages of high-precision timing simulation, efficient simulation scheduling, super-real-time performance, and the ability to meet user timing requirements, and has broad application prospects in the field of embedded system simulation.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded simulation, and in particular to a method for realizing medium and low frequency embedded ultra-real-time behavior-level timing simulation and a system applying the method. Background Art

[0002] Low- to medium-frequency embedded simulation is a technology specifically designed to simulate instruction cores in embedded systems, such as microcontrollers like the Cortex-M3 or Cortex-M4. These instruction cores typically operate at lower frequencies and play a crucial role in embedded systems. Using low- and medium-frequency embedded simulation, engineers can evaluate and optimize system performance during the design phase, ensuring stable operation and meeting specified performance requirements in real-world applications, even in resource-constrained environments with demanding real-time requirements. This simulation technology not only helps reduce hardware development costs and time but also improves product development success rates. By simulating various operations and signal processing within a simulation environment, engineers can promptly identify and resolve potential issues, ensuring product quality and reliability before production. Unfortunately, currently available low- and medium-frequency embedded simulation systems are either fast but inaccurate or accurate but slow, presenting challenges for users.

[0003] Behavioral simulation plays a crucial role in embedded system design, particularly in low- and medium-frequency applications. Using high-level languages ​​or specialized simulation tools, it simulates the behavior of a system or module at a highly abstract level, rather than simply replicating the hardware logic. This simulation approach allows engineers to deeply explore the system's operating logic, performance characteristics, and potential issues before physical hardware is manufactured. In behavioral simulation, engineers can build detailed behavioral models and simulate system responses under varying input conditions. This allows them to verify algorithm correctness, evaluate system performance metrics, and predict potential issues in real-world environments. This early verification not only reduces the workload of later hardware debugging but also significantly improves product reliability and stability. Furthermore, behavioral simulation facilitates cross-disciplinary team collaboration, enabling software developers, hardware engineers, and system architects to communicate and discuss ideas based on the same simulation model, accelerating the transition from concept to product. With the rapid development of the Internet of Things (IoT) and industrial automation, performance requirements for embedded systems are increasing. Behavioral simulation has become a key technology for ensuring design quality and shortening development cycles. However, most commercially available behavioral embedded simulation systems suffer from timing inaccuracies, creating challenges for engineers.

[0004] Timing-accurate simulation is a crucial technology for embedded system design verification. It ensures that the operations between components in the system, driven by clock signals, strictly adhere to the predetermined time sequence. This simulation method not only simulates the system's logical functions but also accurately describes signal changes within each clock cycle, thereby identifying potential problems caused by timing mismatches, such as timing violations and timing chaos. Timing-accurate simulation is particularly important in complex low- and medium-frequency embedded systems because it helps engineers identify and resolve timing-related issues early in the design process, avoiding costly corrections later during the hardware and software implementation phase. Through precise timing simulation, engineers can optimize system performance and ensure stable and reliable operation under various operating conditions. However, most timing-accurate embedded simulation systems currently available on the market run slowly, causing difficulties for engineers.

[0005] Beyond real-time simulation is a highly efficient simulation technology that runs simulation models at timescales faster than actual physical processes. It is particularly important in the development and verification of embedded systems. Leveraging powerful computing resources and optimized simulation algorithms, this technology accelerates the simulation of target system behavior, enabling engineers to observe the effects of long-term operation in a short period of time, significantly shortening development cycles. Beyond real-time simulation not only speeds up system testing but also improves its comprehensiveness and accuracy. It allows engineers to simulate extreme operating conditions and long-term operation in a virtual environment to assess system stability and reliability. Through beyond real-time simulation, engineers can promptly identify and resolve potential issues, ensuring optimal system performance in real-world applications. However, currently, there are no timing-accurate behavioral beyond real-time embedded simulation systems on the market. Summary of the Invention

[0006] In order to solve various problems existing in the prior art, the object of the present invention is to provide a method and system for realizing medium and low frequency embedded ultra-real-time behavioral level timing simulation.

[0007] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0008] A method for implementing low- to medium-frequency embedded ultra-real-time behavioral-level timing simulation, the method comprising the following steps:

[0009] Load and initialize the specified on-chip device according to the target machine configuration information;

[0010] Set the simulation time amplification factor of IO instructions and the statistical factor of non-IO instructions according to the minimum timing accuracy of the on-chip device;

[0011] Start the command core and transfer the program's running control to the command core;

[0012] After the instruction core executes each instruction, it determines whether the current instruction is an IO instruction;

[0013] When the number of non-IO instructions counted reaches a preset value, the current non-IO instruction statistical factor is converted into a simulation time parameter;

[0014] When the simulation time condition is reached, the instruction core starts the simulation scheduler and hands over the program's running control to the simulation scheduler;

[0015] The simulation scheduler schedules the simulation events of the devices that meet the simulation time conditions according to the simulation time scale sequence;

[0016] After the simulation scheduler finishes executing the currently passed simulation time, it exits the scheduler and hands over the program's running control to the main program, which clears the number of non-IO instructions.

[0017] Return to the step of starting the instruction core, hand over the program's running control to the instruction core again, and start the next round of instruction execution and simulation process.

[0018] According to a method for implementing low- to medium-frequency embedded ultra-real-time behavioral-level timing simulation provided by the present invention, system initialization is also performed:

[0019] Start the main program and pass in the target machine configuration information;

[0020] The main program loads and initializes the specified instruction core according to the target machine configuration information;

[0021] The main program initializes the environment of the simulation scheduler and sets the initial state of the simulation scheduler; wherein the simulation scheduler is a component for scheduling and executing device simulation events that meet the simulation time conditions in accordance with the simulation time scale sequence.

[0022] According to a method for implementing medium- and low-frequency embedded ultra-real-time behavioral-level timing simulation provided by the present invention, when judging whether the current instruction is an IO instruction, if the currently executed instruction is an IO instruction, the currently counted non-IO instruction statistical factor and simulation time amplification factor are converted into simulation time parameters; if the currently executed instruction is a non-IO instruction, the non-IO instruction statistical factor is updated according to the number of instructions executed.

[0023] According to a method for implementing ultra-real-time behavioral-level timing simulation for medium- and low-frequency embedded systems, a simulation time amplification factor is set for IO instructions based on the actual execution time and delay of the IO instructions. During the simulation process, whenever an IO instruction is encountered, the execution time in the simulation is calculated based on its execution time and the simulation time amplification factor, thereby improving simulation performance.

[0024] The simulation time amplification factor should be such that the execution time of the IO instruction in the simulation matches the execution time on the actual device.

[0025] According to a method for implementing ultra-real-time behavioral-level timing simulation of medium- and low-frequency embedded systems, a target instruction count is set for non-IO instructions based on the program's instruction structure and simulation requirements. During the simulation process, whenever the number of non-IO instructions executed reaches the preset target instruction count, a simulation scheduler is called to execute related simulation events. That is, the simulation performance is improved by calling the simulation scheduler after the number of statistical instructions reaches the target instruction count set on demand.

[0026] Among them, the target number of instructions should reflect the number of non-IO instructions executed by the program within a period of time, and be able to reduce the number of calls to the simulation scheduler while ensuring the accuracy of the simulation.

[0027] According to a method for implementing ultra-real-time behavioral-level timing simulation at a medium- and low-frequency embedded system, when the state of a device changes or a specific condition is met, a simulation event is triggered. This event is added to the event queue of the simulation scheduler and waits for scheduling execution.

[0028] The simulation scheduler sorts the events in the event queue according to the simulation time scale to ensure that they are executed in the order of their occurrence;

[0029] When the simulation time advances to the trigger time of an event, the simulation scheduler will take the event out of the event queue and call the corresponding handler for execution;

[0030] After executing the event, the simulation scheduler updates the state of the simulation system according to the execution result of the event and triggers new simulation events. These new events are added to the event queue and wait for subsequent scheduling execution.

[0031] According to a method for implementing ultra-real-time behavioral-level timing simulation for medium- and low-frequency embedded systems, the present invention continuously counts the number of non-IO instructions executed during the simulation process to evaluate the computational load during program execution, thereby indirectly reflecting time consumption.

[0032] When the number of non-IO instructions counted reaches the preset value, the statistical result is converted into simulation time parameters, which will be used in subsequent simulation scheduling and event processing.

[0033] The preset value is set according to the timing accuracy requirement of the simulation system and the target machine configuration information, and represents the number of non-IO instructions expected to be executed within a certain period of time.

[0034] A system for implementing ultra-real-time behavioral-level timing simulation for medium- and low-frequency embedded systems, the system being used to implement the above-mentioned method for implementing ultra-real-time behavioral-level timing simulation for medium- and low-frequency embedded systems, comprising:

[0035] Parameter parsing module, instruction core loading module, on-chip device set loading module, firmware library loading module, instruction execution module, the parameter parsing module is used to parse the various startup parameters passed in by the user, the instruction core loading module is used to open the specified target machine configuration file according to the parsing result of the first startup parameter, and then read the file content and load the specified model of instruction core according to the instruction configuration information in the file content; the on-chip device set loading module opens the specified target machine configuration file according to the parsing result of the first startup parameter, and then reads the file content and loads the specified on-chip device set component according to the on-chip device configuration information in the file content, and finally sets the io_time_scale global variable and noio_insn_cnt_threshold global variable according to the minimum timing accuracy requirements of the on-chip system; the firmware library loading module opens and loads the specified firmware program into the memory space of the simulation target machine according to the parsing result of the second startup parameter; the instruction execution module is used to start the operation of the instruction core, and the instruction core cyclically reads the firmware instructions in the memory of the simulation target machine to perform target machine instruction translation, target machine instruction execution, target machine instruction statistics, start the simulation scheduler, etc.

[0036] According to a system for implementing medium and low frequency embedded ultra-real-time behavioral-level timing simulation provided by the present invention, the first startup parameter includes -mathion_cfg, which is the simulation target machine configuration file selected for running. The file is a configuration file in json format and contains the instruction core model information and on-chip device configuration information required by the target machine.

[0037] According to a system for implementing medium- and low-frequency embedded ultra-real-time behavioral-level timing simulation provided by the present invention, the second startup parameter includes -firmware, which is the simulation firmware selected for running.

[0038] It can be seen that compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. By setting the simulation time amplification factor of IO instructions and the non-IO instruction statistical factor according to the minimum timing accuracy of the on-chip device, the present invention can ensure the timing accuracy during the simulation process and accurately simulate the real-time behavior in the embedded system, especially in application scenarios with strict timing requirements.

[0040] 2. When the number of non-IO instructions counted reaches a preset value, the present invention converts the current non-IO instruction statistical factor into a simulation time parameter, ensuring that the simulation time matches the actual time consumption during program execution, thereby improving the accuracy of the simulation.

[0041] 3. The present invention achieves efficient simulation scheduling through the collaborative work of the instruction core and the simulation scheduler. The instruction core is responsible for executing program instructions, while the simulation scheduler is responsible for scheduling simulation events for devices that meet the simulation time conditions according to the simulation time scale sequence, thereby improving simulation efficiency.

[0042] 4. The present invention dynamically adjusts the simulation process based on simulation time conditions. When the simulation time condition is reached, the instruction core starts the simulation scheduler and transfers program execution control to the simulation scheduler. After the simulation scheduler completes the currently entered simulation time, it exits and returns program execution control to the main program, making the simulation process more flexible and efficient.

[0043] 5. The present invention loads and initializes the specified on-chip device according to the target machine configuration information, and thus can support a variety of different on-chip devices, making the method more scalable and flexible when applied to different embedded systems.

[0044] 6. By setting parameters such as the simulation time amplification factor of IO instructions and the non-IO instruction statistical factor, the present invention can be configured according to specific needs, so that the method can adapt to the needs of different simulation scenarios and improve the flexibility and applicability of the simulation.

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 The present invention is a flowchart of a method embodiment for realizing low- to medium-frequency embedded ultra-real-time behavioral-level timing simulation.

[0047] Figure 2 This is a schematic diagram of an embodiment of a method for realizing medium and low frequency embedded ultra-real-time behavioral level timing simulation according to the present invention.

[0048] Figure 3 The present invention is a flowchart of a method embodiment for realizing low- to medium-frequency embedded ultra-real-time behavioral-level timing simulation. DETAILED DESCRIPTION

[0049] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0050] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0051] A method embodiment for realizing medium and low frequency embedded ultra-real-time behavioral level timing simulation

[0052] See also Figures 1 to 3 The present invention provides a method for realizing low- to medium-frequency embedded ultra-real-time behavioral-level timing simulation, the method comprising the following steps:

[0053] Step S1, loading and initializing the specified on-chip device according to the target machine configuration information;

[0054] Step S2, setting the simulation time amplification factor of the IO instruction and the non-IO instruction statistical factor according to the minimum timing accuracy of the on-chip device;

[0055] Step S3: Start the command core and transfer the program's running control to the command core;

[0056] Step S4: After executing each instruction, the instruction core determines whether the current instruction is an IO instruction;

[0057] Step S5: when the number of non-IO instructions counted reaches a preset value, converting the current non-IO instruction statistical factor into a simulation time parameter;

[0058] Step S6: When the simulation time condition is reached, the instruction core starts the simulation scheduler and hands over the program's running control to the simulation scheduler.

[0059] Step S7, the simulation scheduler schedules the simulation events of the devices that meet the simulation time conditions according to the simulation time scale sequence;

[0060] Step S8: After the simulation scheduler finishes executing the currently passed simulation time (sim_time), it exits the scheduler and hands over the program's running control to the main program. The main program clears the number of non-IO instructions (noio_insn_cnt_total);

[0061] Step S9, returns to the step of starting the instruction core, and again hands over the program's running control to the instruction core to start the next round of instruction execution and simulation process.

[0062] Before step S1, system initialization is also performed:

[0063] Start the main program of the medium and low frequency embedded ultra-real-time behavioral-level timing-accurate simulation system and pass in the target machine configuration information, such as the -firmware and -mathion_cfg startup parameters.

[0064] The main program loads and initializes the specified instruction core according to the instruction core configuration information in the target machine configuration file (mathion_cfg parameter), such as loading and initializing the cortex-m3 instruction core;

[0065] The main program initializes the environment of the simulation scheduler and sets the initial state of the simulation scheduler; wherein the simulation scheduler is a component for scheduling and executing device simulation events that meet the simulation time conditions in accordance with the simulation time scale sequence.

[0066] In the above step S1, the main program loads and initializes the specified on-chip device according to the on-chip device set configuration information in the target machine configuration file (mathion_cfg parameter), such as loading the stm32f103C8 on-chip device set.

[0067] In the above step S1, the main program sets the simulation time amplification factor of the IO instruction (io_time_scale global variable, for example, setting io_time_scale = 6) and the non-IO instruction statistical factor threshold (noio_insn_cnt_threshold global variable, for example, setting noio_insn_cnt_threshold = 5) according to the minimum timing accuracy of the on-chip device.

[0068] In the above steps S4 and S5, the instruction core translates and executes an instruction and determines whether the current instruction is an IO instruction. If the currently executed instruction is an IO instruction, the current non-IO instruction statistical factor (noio_insn_cnt_total) and the simulation time amplification factor are converted into simulation time parameters (sim_time = noio_insn_cnt_total + io_time_scale); if the currently executed instruction is a non-IO instruction, the non-IO instruction statistical factor (noio_insn_cnt_total) is increased by 1.

[0069] In the above step S5, if the counted number of non-IO instructions (noio_insn_cnt_total) reaches the instruction preset value (noio_insn_cnt_threshold), the current counted non-IO instruction statistical factor is converted into a simulation time parameter (sim_time = noio_insn_cnt_total); if the counted number of non-IO instructions does not reach the preset value, repeat step S4.

[0070] In this embodiment, when determining whether the current instruction is an IO instruction, if the currently executed instruction is an IO instruction, the currently counted non-IO instruction statistical factor and simulation time amplification factor are converted into simulation time parameters; if the currently executed instruction is a non-IO instruction, the non-IO instruction statistical factor is updated according to the number of instructions executed.

[0071] In this embodiment, for IO instructions, a simulation time amplification factor is set based on the actual execution time and delay of the IO instructions. During the simulation process, whenever an IO instruction is encountered, the execution time in the simulation is calculated based on its execution time and the simulation time amplification factor, and the simulation performance is improved by amplifying the simulation time.

[0072] The simulation time amplification factor should be such that the execution time of the IO instruction in the simulation matches the execution time on the actual device.

[0073] In this embodiment, for non-IO instructions, a target number of instructions is set according to the instruction structure of the program and the simulation requirements. During the simulation process, whenever the number of non-IO instructions executed reaches the preset target number of instructions, the simulation scheduler is called to execute related simulation events, that is, the simulation performance is improved by calling the simulation scheduler after the number of statistical instructions reaches the target number of instructions set on demand.

[0074] Among them, the target number of instructions should reflect the number of non-IO instructions executed by the program within a period of time, and be able to reduce the number of calls to the simulation scheduler while ensuring the accuracy of the simulation.

[0075] In this embodiment, when the state of a device changes or satisfies a certain condition, a simulation event is triggered, and this event is added to the event queue of the simulation scheduler, waiting for scheduling execution;

[0076] The simulation scheduler sorts the events in the event queue according to the simulation time scale to ensure that they are executed in the order of their occurrence;

[0077] When the simulation time advances to the trigger time of an event, the simulation scheduler will take the event out of the event queue and call the corresponding handler for execution;

[0078] After executing the event, the simulation scheduler updates the state of the simulation system according to the execution result of the event and triggers new simulation events. These new events are added to the event queue and wait for subsequent scheduling execution.

[0079] In this embodiment, the simulation scheduler is the core component of the simulation system. It is responsible for managing and scheduling the execution of all simulation events, including device state changes, data transmission, and signal triggering. By precisely controlling the execution order and timing of these events, the simulation scheduler ensures that the simulation process accurately reflects the behavior of the actual system.

[0080] In this embodiment, the simulation timescale is the basic unit used to measure time changes during the simulation process. It typically corresponds to the time unit of the actual system, but may also be scaled or accelerated based on simulation needs. During the simulation process, the simulation scheduler gradually advances the simulation time according to the simulation timescale and schedules the corresponding simulation events for execution.

[0081] Therefore, the simulation scheduler, which schedules simulation events for devices that meet the simulation time conditions according to the simulation time scale, is a crucial step in the simulation process. By optimizing the design and implementation of the simulation scheduler, we can improve the efficiency and accuracy of simulations, providing strong support for the design and optimization of actual systems.

[0082] During the simulation process of this embodiment, the number of non-IO instructions executed is continuously counted to evaluate the computing load during program execution, thereby indirectly reflecting the time consumption.

[0083] When the number of non-IO instructions counted reaches a preset value, the statistical result is converted into a simulation time parameter, and the converted simulation time parameter will be used in subsequent simulation scheduling and event processing.

[0084] The preset value is set according to the timing accuracy requirement of the simulation system and the target machine configuration information, and represents the number of non-IO instructions expected to be executed within a certain period of time.

[0085] Specifically, the method provided in this embodiment combines a specific embedded simulation instruction core (cortex-m3), a simulation scheduler (SYSTEMC), and a behavioral on-chip device, and divides the instructions executed by the instruction core into two situations: one is IO instructions and the other is non-IO instructions.

[0086] Among them, for IO instructions, the simulation performance is slow due to its access to on-chip device registers. In order to improve the simulation performance, the simulation time is magnified to improve the simulation performance; for non-IO instructions, the simulation scheduler is frequently scheduled, thereby reducing the simulation performance of the simulation system. At this time, the simulation scheduler is called after the number of instructions is counted to reach the target number of instructions set on demand to improve the simulation performance. The advantage of this is that it greatly improves the performance of the embedded simulation system to achieve super real-time while meeting the timing requirements of the embedded simulation system. The core of the technical solution of this embodiment is to perform different acceleration processing on the above two instruction classifications, so as to achieve accurate timing simulation of medium and low frequency embedded super real-time behavioral levels.

[0087] In actual application, the method of this embodiment first starts the main program to load the target machine instruction core to run. The instruction core divides the instructions into IO instructions and non-IO instructions. If the instruction core executes an IO instruction, the instruction core immediately converts the current number of instructions and the time magnification rate into simulation time parameters to start and call the simulation scheduler to run. The duration of the scheduler operation is the simulation time parameter passed in by the instruction core. During the scheduler operation, the on-chip device accurately executes the device event according to the simulation time scale line; if the instruction core executes a non-IO instruction, the instruction core counts the current number of instructions until the counted number of instructions reaches a preset number, and then converts the counted number of instructions into simulation time parameters to start and call the scheduler to run. The duration of the scheduler operation is the simulation time parameter passed in by the instruction core. During the scheduler operation, the on-chip device accurately executes the device event according to the simulation time scale line. When the scheduler is executed, the system enters the execution process of the instruction core again.

[0088] A system embodiment for realizing medium and low frequency embedded ultra-real-time behavioral timing simulation

[0089] A system for implementing ultra-real-time behavioral-level timing simulation for medium- and low-frequency embedded systems, the system being used to implement the above-mentioned method for implementing ultra-real-time behavioral-level timing simulation for medium- and low-frequency embedded systems, comprising:

[0090] Parameter parsing module, instruction core loading module, on-chip device set loading module, firmware library loading module, instruction execution module, the parameter parsing module is used to parse the various startup parameters passed in by the user, the instruction core loading module is used to open the specified target machine configuration file according to the parsing result of the first startup parameter, and then read the file content and load the specified model of instruction core according to the instruction configuration information in the file content. Different models of instruction cores support different instructions; the on-chip device set loading module opens the specified target machine configuration file according to the parsing result of the first startup parameter, and then reads the file content and loads the specified on-chip device set component according to the on-chip device configuration information in the file content, and finally according to the minimum timing accuracy requirements of the on-chip system. Request to set the io_time_scale global variable (set the time magnification factor of io instructions) and the noio_insn_cnt_threshold global variable (set the statistical factor threshold of non-io instructions); the simulation scheduler module is the core component of the simulation operation, responsible for managing and scheduling simulation events and controlling the execution process of the simulation; the firmware library loading module opens and loads the specified firmware program into the memory space of the simulation target machine according to the parsing result of the second startup parameter; the instruction execution module is used to start the operation of the instruction core, and the instruction core cyclically reads the firmware instructions in the memory of the simulation target machine to perform target machine instruction translation, target machine instruction execution, target machine instruction statistics, start the simulation scheduler, etc.

[0091] In this embodiment, the first startup parameter includes -mathion_cfg, which is a configuration file of the simulation target machine selected for running. The file is a configuration file in json format and contains the instruction core model information and on-chip device module configuration information required by the target machine.

[0092] In this embodiment, the second startup parameter includes -firmware, which is the simulation firmware selected for running.

[0093] In summary, the present invention can ensure the timing accuracy during the simulation process by setting the simulation time amplification factor of IO instructions and the non-IO instruction statistical factor according to the minimum timing accuracy of the on-chip device, and can accurately simulate the real-time behavior in the embedded system, especially in application scenarios with strict timing requirements.

[0094] When the number of non-IO instructions counted reaches a preset value, the present invention converts the current non-IO instruction statistical factor into a simulation time parameter, ensuring that the simulation time matches the actual time consumption during program execution, thereby improving the accuracy of the simulation.

[0095] The present invention realizes efficient simulation scheduling through the cooperative work of the instruction core and the simulation scheduler. The instruction core is responsible for executing program instructions, while the simulation scheduler is responsible for scheduling simulation events of devices that meet the simulation time conditions according to the simulation time scale sequence, thereby improving the efficiency of simulation.

[0096] The present invention dynamically adjusts the simulation process based on simulation time conditions. When the simulation time condition is reached, the instruction core starts the simulation scheduler and transfers program execution control to the simulation scheduler. After the simulation scheduler completes the currently entered simulation time, it exits and returns program execution control to the main program, making the simulation process more flexible and efficient.

[0097] The present invention loads and initializes a designated on-chip device according to target machine configuration information, and thus can support a variety of different on-chip devices, making the method more scalable and flexible when applied to different embedded systems.

[0098] By setting parameters such as the simulation time amplification factor of IO instructions and the non-IO instruction statistical factor, the present invention can be configured according to specific needs, so that the method can adapt to the needs of different simulation scenarios and improve the flexibility and applicability of the simulation.

[0099] It should be noted that a person skilled in the art will understand that the above-mentioned devices and methods can be implemented using computer-executable instructions and / or contained in processor control codes. The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any person skilled in the art within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the scope of protection of the present invention.

[0100] The above embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and replacements made by technicians in this field on the basis of the present invention fall within the scope of protection required by the present invention.

Claims

1. A method for realizing ultra-real-time behavioral-level timing simulation of medium and low frequency embedded systems, characterized in that: The method comprises the following steps: Load and initialize the specified on-chip device according to the target machine configuration information; Set the simulation time amplification factor of IO instructions and the statistical factor of non-IO instructions according to the minimum timing accuracy of the on-chip device; Start the command core and transfer the program's running control to the command core; After the instruction core executes each instruction, it determines whether the current instruction is an IO instruction; When the number of non-IO instructions counted reaches a preset value, the current non-IO instruction statistical factor is converted into a simulation time parameter; When the simulation time condition is reached, the instruction core starts the simulation scheduler and hands over the program's running control to the simulation scheduler; The simulation scheduler schedules the simulation events of the devices that meet the simulation time conditions according to the simulation time scale sequence; After the simulation scheduler finishes executing the currently passed simulation time, it exits the scheduler and hands over the program's running control to the main program, which clears the number of non-IO instructions. Return to the step of starting the instruction core, hand over the program's running control to the instruction core again, and start the next round of instruction execution and simulation process; Among them, when judging whether the current instruction is an IO instruction, if the currently executed instruction is an IO instruction, the currently counted non-IO instruction statistical factor and simulation time amplification factor are converted into simulation time parameters; if the currently executed instruction is a non-IO instruction, the non-IO instruction statistical factor is updated according to the number of executed instructions.

2. The method according to claim 1, characterized in that Also performs system initialization: Start the main program and pass in the target machine configuration information; The main program loads and initializes the specified instruction core according to the target machine configuration information; The main program initializes the environment of the simulation scheduler and sets the initial state of the simulation scheduler; wherein the simulation scheduler is a component for scheduling and executing device simulation events that meet the simulation time conditions in accordance with the simulation time scale sequence.

3. The method according to claim 1, wherein: For IO instructions, a simulation time amplification factor is set based on the actual execution time and delay of the IO instructions. During the simulation process, whenever an IO instruction is encountered, the execution time in the simulation is calculated based on its execution time and simulation time amplification factor, thereby improving simulation performance. The simulation time amplification factor should be such that the execution time of the IO instruction in the simulation matches the execution time on the actual device.

4. The method according to claim 1, wherein: For non-IO instructions, a target instruction count is set based on the program's instruction structure and simulation requirements. During the simulation process, whenever the number of non-IO instructions executed reaches the preset target instruction count, the simulation scheduler is called to execute related simulation events. This improves simulation performance by calling the simulation scheduler only after the number of statistical instructions reaches the target instruction count set on demand. Among them, the target number of instructions should reflect the number of non-IO instructions executed by the program within a period of time, and be able to reduce the number of calls to the simulation scheduler while ensuring the accuracy of the simulation.

5. The method according to claim 1, wherein: When the state of a device changes or a certain condition is met, a simulation event is triggered. This event will be added to the event queue of the simulation scheduler and wait for scheduling execution; The simulation scheduler sorts the events in the event queue according to the simulation time scale to ensure that they are executed in the order of their occurrence; When the simulation time advances to the trigger time of an event, the simulation scheduler will take the event out of the event queue and call the corresponding handler for execution; After executing the event, the simulation scheduler updates the state of the simulation system according to the execution result of the event and triggers new simulation events. These new events are added to the event queue and wait for subsequent scheduling execution.

6. The method according to any one of claims 1 to 5, characterized in that: During the simulation process, the number of non-IO instructions executed is continuously counted to evaluate the computational load during program execution, thereby indirectly reflecting the time consumption; When the number of non-IO instructions counted reaches the preset value, the statistical result is converted into simulation time parameters, which will be used in subsequent simulation scheduling and event processing. The preset value is set according to the timing accuracy requirement of the simulation system and the target machine configuration information, and represents the number of non-IO instructions expected to be executed within a certain period of time.

7. A system for implementing low- to medium-frequency embedded ultra-real-time behavioral timing simulation, characterized in that: The system is used to implement the method for realizing medium- and low-frequency embedded ultra-real-time behavioral-level timing simulation as described in any one of claims 1 to 6, comprising: Parameter parsing module, instruction core loading module, on-chip device set loading module, firmware library loading module, instruction execution module, the parameter parsing module is used to parse the various startup parameters passed in by the user, the instruction core loading module is used to open the specified target machine configuration file according to the parsing result of the first startup parameter, and then read the file content and load the specified model of instruction core according to the instruction configuration information in the file content; the on-chip device set loading module opens the specified target machine configuration file according to the parsing result of the first startup parameter, and then reads the file content and loads the specified on-chip device set component according to the on-chip device configuration information in the file content, and finally sets the io_time_scale global variable and noio_insn_cnt_threshold global variable according to the minimum timing accuracy requirements of the on-chip system; the firmware library loading module opens and loads the specified firmware program into the memory space of the simulation target machine according to the parsing result of the second startup parameter; the instruction execution module is used to start the operation of the instruction core, and the instruction core cyclically reads the firmware instructions in the memory of the simulation target machine to translate the target machine instructions, execute the target machine instructions, count the target machine instructions, and start the simulation scheduler.

8. The system according to claim 7, characterized in that: The first startup parameter includes -mathion_cfg, which is the simulation target machine configuration file selected for running. The file is a configuration file in json format and contains the instruction core model information and on-chip device configuration information required by the target machine.

9. The system according to claim 7, characterized in that: The second startup parameter includes -firmware, which is the simulation firmware selected for running.

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