Life Assessment and Failure Prediction Method for Power Semiconductor Solder Layer

Abstract

The present invention discloses a method for life assessment and failure prediction of a power semiconductor welding layer, comprising the following steps: S1, collecting and acquiring chip design parameters, power semiconductor module sealing and testing process parameters, and power semiconductor module working condition monitoring data; S2, using a finite element analysis method to construct a heat transfer model, a mechanical stress model, and an electrical performance model based on the data acquired in S1; it relates to the field of power semiconductor technology, and by comprehensively considering chip design parameters, power semiconductor module sealing and testing process parameters, and working condition monitoring data, and constructing multiple physical models, the influence on the life of the welding layer is deeply analyzed from multiple dimensions of heat transfer, mechanical stress, and electrical performance. Compared with only a single thermal fatigue perspective, or a method that mainly relies on specific precursor parameters and uses neural network fitting, it can more comprehensively and accurately evaluate the remaining life of the welding layer, and provide more accurate life prediction information for the reliable operation of the power semiconductor module.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a method for evaluating the life span and predicting the failure of a power semiconductor welding layer. Background Art

[0002] Power semiconductors are a branch of semiconductors, mainly used for the conversion and control of electrical energy in power electronic equipment.

[0003] Publication No. CN106291299B discloses a power semiconductor module and a method for judging the thermal fatigue life of a power semiconductor module. The color of a thermal fatigue life judging component at a specified temperature changes as the number of temperature cycles experienced by the power semiconductor module increases. The thermal fatigue life of the power semiconductor module is judged based on the color of the thermal fatigue life judging component at a specified temperature.

[0004] Publication No. CN116432543B discloses a method for predicting the remaining life of a power semiconductor module, which determines the precursor parameters that characterize the aging process of the power semiconductor module during an accelerated aging test; sets a comprehensive loss function to iteratively train the convolutional neural network to obtain a trained remaining life prediction model.

[0005] However, the above application still has the following problems: CN106291299B evaluates the thermal fatigue life intuitively and qualitatively by observing the color, mainly focusing on the judgment of the thermal fatigue life, and only paying attention to the aging effect caused by temperature cycling. The application scope is relatively narrow, and it can only roughly give the life situation from the perspective of thermal fatigue. It is unable to deeply analyze other factors, such as the comprehensive influence of mechanical stress and electrical properties on the life of the welding layer. The core of CN116432543B is to build a model using specific precursor parameters and convolutional neural network training methods, focusing on the data obtained from accelerated aging tests, and conducting life prediction around the precursor parameters. It involves relatively few specific physical processes inside the power semiconductor module, such as heat transfer, stress distribution, and details of electrical performance changes. The prediction accuracy of the power semiconductor welding layer life needs to be improved. Summary of the invention

[0006] In order to solve the technical problems existing in the background technology, the present invention proposes a method for evaluating the life span and predicting the failure of a power semiconductor welding layer.

[0007] The method for evaluating the life span and predicting the failure of a power semiconductor welding layer proposed by the present invention comprises the following steps:

[0008] S1. Collect and obtain chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data;

[0009] S2. Based on the data obtained in S1, a heat transfer model, a mechanical stress model and an electrical performance model are constructed using a finite element analysis method;

[0010] S3. Construction of fatigue life model: Based on the stress and strain data of the welding layer output by the mechanical stress model and the cumulative damage theory of Miner criterion, the stress cycles experienced by the welding layer under different working cycles are statistically analyzed. Combined with the SN curve of the welding material, the fatigue damage accumulation value of the welding layer is calculated to predict its remaining life based on mechanical fatigue.

[0011] Thermal life model establishment: The welding layer temperature data obtained through the heat transfer model is used to establish a thermal life model by using the Arrhenius equation, by monitoring the relationship between the performance changes of the welding layer material and temperature and time, to predict the life loss of the welding layer caused by thermal aging;

[0012] Construction of comprehensive life fusion model: By combining the electrical performance model, fatigue life model, and thermal life model, a weighted or multi-factor coupling algorithm is used to construct a comprehensive life fusion model, which is used to predict the overall life of the welding layer;

[0013] S4, during the operation of the power semiconductor module, real-time data collection and transmission through sensors;

[0014] The data collected in real time in S5 and S4 are calculated according to the comprehensive life model. When the remaining life of the welding layer is lower than the preset safety threshold, the system will issue a failure warning signal.

[0015] Preferably, in S1, a box plot method is used to identify and eliminate outliers in chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data.

[0016] Preferably, in S2, a heat transfer model is constructed: based on chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data, a heat transfer model is constructed using a finite element analysis method, the heat transfer model is used to simulate the distribution of heat in the power semiconductor module under different working conditions, and the heat transfer model is used to predict the heat load of the welding layer;

[0017] Mechanical stress model construction: Based on the heat transfer model, chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data, the finite element analysis method is used to construct a mechanical stress model. The mechanical stress model is used to simulate stress changes under different working conditions. The mechanical stress model is used to evaluate whether the structural strength of the welding layer can withstand stress changes;

[0018] Electrical performance model construction: Based on chip design parameters and power semiconductor module working condition monitoring data, the finite element analysis method is used to construct the electrical performance model. The electrical performance model is used to simulate the electrical stress of the welding layer under different voltage and current conditions. Combined with the material's electromigration threshold parameters, the material's electromigration threshold parameters can be obtained through S1. The electrical performance model is used to predict the impact of electrical stress on the life of the welding layer.

[0019] Preferably, in S2, for the heat transfer model, the mechanical stress model and the electrical performance model, multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models and multiple finite element electrical performance sub-models are constructed based on different assumptions or parameter ranges, and the output results of the multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models and multiple finite element electrical performance sub-models are used as training data to construct a random forest model;

[0020] When the operating parameters of a new power semiconductor module are given, such as the actual operating temperature, applied external force, voltage and current conditions, these parameters are input into the trained random forest model, and the model can output the integrated prediction results of heat transfer, mechanical stress or electrical performance. The use of random forest models can reduce the deviation and variance of a single model, thereby improving the model's simulation capabilities for complex physical phenomena such as heat distribution, stress changes, and electrical stress conditions, thereby improving the simulation capabilities and prediction accuracy of the corresponding physical phenomena.

[0021] Preferably, in S2, the heat transfer model is divided into a plurality of finite element heat transfer sub-models according to different material thermal conductivity assumptions, heat distribution under different heat dissipation methods, and different external environment temperature boundary conditions;

[0022] The mechanical stress model is divided into multiple finite element mechanical stress sub-models according to different assumptions based on the mechanical properties of the material, different degrees of fit between the chip and the substrate, and whether there is a gap between the chip and the substrate;

[0023] The electrical performance model is divided into multiple finite element electrical performance sub-models based on different conductivity assumptions and different electric field distribution assumptions;

[0024] Preferably, in S2, the model parameters in the heat transfer model, the mechanical stress model and the electrical performance model are generated in the following manner:

[0025] For the heat transfer model, the thermal conductivity of different materials, parameters related to the heat dissipation method, and the external ambient temperature boundary condition parameters are encoded;

[0026] For the mechanical stress model, the parameters related to the mechanical properties of the material, the quantitative parameters of the tightness of the chip and the substrate, and the binary parameters indicating whether there is a gap, 0 for no gap and 1 for a gap, are encoded;

[0027] For the electrical performance model, the conductivity assumption value and parameters related to the electric field distribution are encoded;

[0028] After encoding the parameters of the heat transfer model, the mechanical stress model and the electrical performance model, a plurality of coding combinations are randomly generated, each coding combination represents a set of parameters of the heat transfer model, the mechanical stress model and the electrical performance model;

[0029] For multiple sets of coding combinations, they are applied to the heat transfer model, mechanical stress model and electrical performance model to obtain the predicted results of heat transfer, mechanical stress and electrical performance, which are then compared with the physical quantities actually measured to calculate multiple mean absolute errors;

[0030] Among the coding combinations corresponding to the multiple mean absolute errors, a random selection method based on probability is used to select X coding combinations;

[0031] 3≤X, and X is a positive integer;

[0032] Next, partial information is exchanged between the X coding combinations, and partial codes in each of the X coding combinations are randomly changed to generate multiple new coding combinations. Then, the method of random selection based on probability is used again to select X coding combinations, and partial information is exchanged between the X coding combinations, and partial codes in each of the X coding combinations are randomly changed to generate multiple new coding combinations. After multiple rounds of iterations, a coding combination corresponding to the minimum mean absolute error is obtained from the multiple new coding combinations retained in the last round of iteration, and it is decoded into the optimal parameter combination of the heat transfer model, the mechanical stress model and the electrical performance model.

[0033] Preferably, the method of random probability selection is as follows:

[0034] Assume there are n coding combinations, recorded as , the mean absolute error corresponding to each coding combination is ; Calculate the sum of multiple mean absolute errors S, S≠0:

[0035] ;

[0036] Then calculate the proportion of the mean absolute error of each encoding combination to the total:

[0037] Next, the inverse proportional weighting method is used to regenerate the proportion of the mean absolute error of each coding combination to the total, and then multiple probability intervals are generated based on the proportion of the mean absolute error of each coding combination to the total. The smaller the mean absolute error, the larger the probability interval generated:

[0038] Assume that the inverse proportional weighting method is used, the generated probability is P, and the coding combination is The corresponding probability interval is , coding combination The corresponding probability interval is , and so on, the coding combination The corresponding probability interval is , j is an index variable used to traverse and calculate the sum of the probabilities of the previous coding combinations;

[0039] Randomly generate a number between 0 and 1, determine the probability interval that the number falls into, determine the mean absolute error corresponding to the probability interval, determine the coding combination corresponding to the mean absolute error, select the coding combination, randomly generate a number between 0 and 1 and repeat it X times to obtain X coding combinations.

[0040] Preferably, in S5, for the preset safety threshold of failure warning, a long short-term memory network algorithm is used to dynamically adjust the threshold:

[0041] The monitoring data of the welding layer of the power semiconductor module per unit time is collected as input, and the long short-term memory network algorithm is trained to predict the state change of the welding layer.

[0042] If the long short-term memory network algorithm predicts that the remaining life of the welding layer will decrease faster than the set threshold in the future, the safety threshold will be lowered to Y times the original safety threshold to issue a warning signal more timely and improve the reliability of the system.

[0043] 0.6<Y<1.

[0044] A method for designing an IGBT chip, wherein the design of the IGBT chip further comprises the following steps:

[0045] S1, IGBT chip adopts trench gate and field stop layer structure design;

[0046] S2, the front side of the IGBT chip adopts the front side carrier storage layer design;

[0047] S3, IGBT chips use Dummy and SN designs;

[0048] The terminal design of S4 and IGBT chips adopts a field limiting ring + field plate structure, combined with SiN and polyimide double-layer passivation.

[0049] In the present invention, the proposed method for evaluating the life span and predicting the failure of a power semiconductor welding layer has the following beneficial technical effects:

[0050] 1. By comprehensively considering chip design parameters, power semiconductor module packaging and testing process parameters, and working condition monitoring data, and building multiple physical models, the impact on the life of the welding layer is deeply analyzed from multiple dimensions such as heat transfer, mechanical stress, and electrical performance. Compared with only a single thermal fatigue perspective, or mainly relying on specific precursor parameters using neural network fitting methods, it can more comprehensively and accurately evaluate the remaining life of the welding layer, and provide more accurate life prediction information for the reliable operation of power semiconductor modules.

[0051] 2. During the operation of the power semiconductor module, sensors are used to collect data in real time, and the parameters of each model can be updated in real time, so that the life prediction can be dynamically adjusted as the actual working conditions change. This feature overcomes the limitation that the relatively static color judgment method cannot track changes in real time. The long short-term memory network algorithm is used to dynamically adjust the preset safety threshold of the failure warning, and the threshold is flexibly changed according to the predicted rate of decline of the remaining life of the welding layer. Compared with the warning method with a fixed threshold, it can issue a failure warning signal more timely, avoid missing the best maintenance time due to unreasonable threshold settings, further ensure the reliability of the operation of the power semiconductor module, and reduce the losses caused by the failure of the welding layer.

[0052] 3. A unique method based on coding combination, probabilistic random selection and multiple rounds of iterations is used to determine the optimal parameter combination of the heat transfer model, mechanical stress model and electrical performance model. Compared with the method of determining parameters using a specific network training method, it can effectively reduce model deviation and variance, thereby improving the accuracy of the entire life assessment and prediction, making the prediction results more in line with actual conditions.

[0053] 4. For the heat transfer model, mechanical stress model and electrical performance model, multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models and multiple finite element electrical performance sub-models are constructed based on different assumptions or parameter ranges, and the output results of multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models and multiple finite element electrical performance sub-models are used as training data to construct a random forest model; when the operating parameters of a new power semiconductor module are given, these parameters are input into the trained random forest model, and the random forest model outputs the integrated prediction results of heat transfer, mechanical stress or electrical performance. The use of the random forest model can reduce the deviation and variance of a single model, thereby improving the model's simulation capability for complex physical phenomena, such as heat distribution, stress changes and electrical stress conditions, thereby improving the simulation capability and prediction accuracy of the corresponding physical phenomena.

[0054] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0056] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0057] like Figure 1 The power semiconductor solder layer life assessment and failure prediction method shown includes the following steps:

[0058] S1. Collect and obtain chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data;

[0059] Chip design parameter acquisition: Extract key information from chip design documents, including IGBT chip trench gate structure details (such as trench depth, width, spacing), field stop layer parameters (thickness, doping concentration), carrier storage layer design parameters (N+ layer injection dose, position), Dummy and SN design-related values ​​(such as reduced effective channel density ratio) and chip size (cell size, wafer thickness) changes. These parameters will be used for subsequent thermal, electrical, and mechanical performance analysis, because different chip structures determine the current distribution, heat generation and conduction path during operation, which in turn affects the stress on the welding layer. Record terminal design information, such as the number and size of field limiting rings, field plate structure parameters, and passivation layer materials and thickness (specific parameters of SiN and polyimide double-layer passivation). They are related to the chip electric field distribution and leakage control. A stable electric field can ensure that the welding layer is in a relatively normal electrical stress environment, avoiding local overheating or electromigration caused by abnormal electric fields that affect the life of the welding layer.

[0060] Acquisition of power semiconductor module packaging and testing process parameters: In terms of bonding process, the bonding wire material (type, diameter), bonding pressure, temperature, and time parameters are sorted out. These directly affect the bonding quality, and poor bonding quality may cause the chip to displace or vibrate during operation, and additional mechanical force will be transmitted to the welding layer. For example, excessive bonding pressure may damage the chip surface, and the friction between the chip and the welding layer will increase during subsequent work, accelerating the wear of the welding layer. For the welding process, the welding material composition, melting point, welding temperature curve (preheating, peak temperature, holding time, cooling rate), welding equipment parameters (such as power, welding head size and shape), and low void rate chip mounting process optimization The void rate monitoring data is recorded in detail. Improper welding temperature curve may lead to uneven internal structure of the welding layer and generate residual stress, and voids are obstacles to heat conduction, which will cause local overheating and reduce the thermal fatigue life of the welding layer. Collect injection molding process parameters, such as the thermal expansion coefficient, fluidity, injection pressure, temperature, and mold structure of the injection molding material. The injection molding process affects the sealing and integrity of the module package. If the sealing is not good, external moisture and impurities will intrude and corrode the welding layer, change its material properties, and reduce reliability.

[0061] Acquisition of power semiconductor module working condition monitoring data: In actual application scenarios, sensors are used to collect the working temperature (including the temperature distribution near the welding layer, multiple thermocouples or infrared thermometers can be used to monitor different positions), current (total current and branch current of each chip, using Hall current sensors), and voltage (voltage between each pin, using voltage probes) parameters of the power semiconductor module in real time. These data reflect the real-time operating status of the module. The working temperature is the key factor affecting the thermal stress of the welding layer. Current and voltage fluctuations will cause changes in electromagnetic force and generate mechanical stress on the welding layer. At the same time, excessive current may lead to aggravated local overheating.

[0062] S2. Construction of heat transfer model: Based on chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data, a heat transfer model is constructed using the finite element analysis method. The heat transfer model is used to simulate the distribution of heat in the power semiconductor module under different working conditions. The heat transfer model is used to predict the heat load of the welding layer.

[0063] The heat transfer model is divided into multiple finite element heat transfer sub-models based on different material thermal conductivity assumptions, heat distribution under different heat dissipation methods (natural heat dissipation, forced air cooling, water cooling), and different external ambient temperature boundary conditions.

[0064] For example, considering the possible nonlinear changes in thermal conductivity of different materials (such as chips, substrates, and solder layers) in power semiconductor modules in different temperature ranges, finite element sub-models are constructed for different situations in which the thermal conductivity is assumed to be a constant, changes linearly with temperature, and changes nonlinearly according to a specific empirical formula.

[0065] Mechanical stress model construction: Based on the heat transfer model, chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data, the finite element analysis method is used to construct a mechanical stress model. The mechanical stress model is used to simulate stress changes under different working conditions. The mechanical stress model is used to evaluate whether the structural strength of the welding layer can withstand stress changes;

[0066] The mechanical stress model is divided into multiple finite element mechanical stress sub-models based on different assumptions based on the mechanical properties of the material, different degrees of fit between the chip and the substrate, and whether there is a gap between the chip and the substrate.

[0067] For example, it is assumed that the welding material exhibits different deformation characteristics of elasticity, elastoplasticity, and complete plasticity under different stress levels, and a sub-model is constructed based on this, because in reality, when the welding layer is subjected to stresses of different magnitudes, its mechanical behavior is complex and changeable.

[0068] According to the different degrees of fit between the chip and the substrate, and whether there is a gap between the chip and the substrate, the corresponding finite element sub-model is constructed, because these factors will significantly affect the transfer and distribution of stress.

[0069] Electrical performance model construction: Based on chip design parameters and power semiconductor module working condition monitoring data, the finite element analysis method is used to construct the electrical performance model. The electrical performance model is used to simulate the electrical stress of the welding layer under different voltage and current conditions. Combined with the material's electromigration threshold parameters, which can be obtained through S1, the electrical performance model is used to predict the impact of electrical stress on the life of the welding layer;

[0070] The electrical performance model is divided into multiple finite element electrical performance sub-models based on different conductivity assumptions and different electric field distribution assumptions.

[0071] For example, considering that the conductivity of welding materials may change due to the electromigration effect after working for a long time, sub-models with different assumptions such as constant conductivity, linear change at a certain rate, and change following a complex functional relationship are constructed.

[0072] Divided according to different electric field distribution assumptions. For example, for the welding layer under different voltage and current conditions, it is assumed that the electric field is uniformly distributed and has different sub-models with local concentration, so as to cover a variety of possible electric stress distribution scenarios.

[0073] S3. Construction of fatigue life model: Based on the stress and strain data of the welding layer output by the mechanical stress model and the cumulative damage theory of Miner criterion, the stress cycles experienced by the welding layer in different working cycles (such as startup, operation, and shutdown) are statistically analyzed. Based on the obtained stress amplitude, average stress, and number of cycles data, combined with the SN curve of the welding material (obtained through material experiments, reflecting the fatigue life of the material under different stress levels), the fatigue damage accumulation value of the welding layer is calculated to predict its remaining life based on mechanical fatigue;

[0074] Thermal life model establishment and construction: The Arrhenius equation is used to obtain the welding layer temperature data through the heat transfer model, considering the effect of temperature on the chemical reaction rate of the welding material. High temperature accelerates material aging, such as oxidation and diffusion chemical reactions inside the welding material, resulting in performance degradation. By monitoring the relationship between the performance changes of the welding layer material (such as hardness, toughness, and conductivity indicators) and temperature and time, a thermal life model is established to predict the life loss of the welding layer due to thermal aging;

[0075] Construction of comprehensive life fusion model: By combining the electrical performance model, fatigue life model, and thermal life model, a weighted or multi-factor coupling algorithm is used to construct a comprehensive life fusion model. The comprehensive life fusion model is used to predict the overall life of the welding layer more accurately.

[0076] S4, during the operation of the power semiconductor module, real-time data collection and transmission through sensors;

[0077] After receiving the sensor data, the heat transfer model, the mechanical stress model, and the electrical performance model update parameters, and input the updated parameter data of the heat transfer model, the mechanical stress model, and the electrical performance model into the fatigue life model and the thermal life model, and the fatigue life model and the thermal life model update parameters, and input the updated parameter data of the fatigue life model and the thermal life model into the comprehensive life fusion model, and the comprehensive life fusion model predicts the overall life of the welding layer;

[0078] Furthermore, in S4, rule-based reasoning or case-based reasoning algorithms are used to combine the real-time temperature, stress and electrical performance data of the welding layer to determine whether local overheating, stress concentration or electrical breakdown failure modes have occurred, thereby achieving real-time fault diagnosis. In this way, potential problems can be discovered in advance and measures can be taken before the welding layer completely fails.

[0079] S5. According to the calculation results of the comprehensive life model, when the remaining life of the welding layer is lower than the preset safety threshold, the system sends a failure warning signal.

[0080] By comprehensively considering chip design parameters, power semiconductor module packaging and testing process parameters, and working condition monitoring data, and constructing multiple physical models, the impact on the life of the welding layer is deeply analyzed from multiple dimensions such as heat transfer, mechanical stress, and electrical performance. Compared with only a single thermal fatigue perspective, or mainly relying on specific precursor parameters using neural network fitting methods, it can more comprehensively and accurately evaluate the remaining life of the welding layer, and provide more accurate life prediction information for the reliable operation of power semiconductor modules.

[0081] Furthermore, in S1, a box plot method is used to identify and eliminate outliers in the chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data.

[0082] Further, in S2, for the heat transfer model, the mechanical stress model, and the electrical performance model, multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models, and multiple finite element electrical performance sub-models are constructed based on different assumptions or parameter ranges, and the output results of the multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models, and multiple finite element electrical performance sub-models are used as training data to construct a random forest model;

[0083] When the operating parameters of a new power semiconductor module are given (such as actual operating temperature, applied external force, voltage and current conditions), these parameters are input into the trained random forest model, and the model can output the integrated prediction results of heat transfer, mechanical stress or electrical performance. The use of random forest models can reduce the deviation and variance of a single model, thereby improving the model's simulation capabilities for complex physical phenomena (such as heat distribution, stress changes, and electrical stress conditions), thereby improving the simulation capabilities and prediction accuracy of the corresponding physical phenomena.

[0084] Furthermore, in S2, the model parameters in the heat transfer model, the mechanical stress model and the electrical performance model are generated in the following manner:

[0085] For the heat transfer model, the thermal conductivity of different materials (assumed to be a constant, linearly varying with temperature, or nonlinearly varying according to a specific empirical formula), parameters related to the heat dissipation method (such as wind speed for air cooling, water flow rate for water cooling), and external ambient temperature boundary condition parameters are encoded.

[0086] For the mechanical stress model, the parameters related to the mechanical properties of the material (such as the values ​​of the elastic modulus and Poisson's ratio assumed under different deformation characteristics), the quantitative parameters of the tightness of the chip and the substrate (such as the magnitude of the bonding pressure), and the binary parameters indicating whether there is a gap (0 means no gap, 1 means there is a gap) are encoded;

[0087] For the electrical performance model, the conductivity assumption value (such as constant value, linear change rate) and electric field distribution related parameters (such as the quantitative value of the electric field concentration degree) are encoded;

[0088] After encoding the parameters of the heat transfer model, the mechanical stress model and the electrical performance model, a plurality of coding combinations are randomly generated, each coding combination represents a set of parameters of the heat transfer model, the mechanical stress model and the electrical performance model;

[0089] For multiple sets of coding combinations, they are applied to the heat transfer model, mechanical stress model and electrical performance model to obtain the predicted results of heat transfer, mechanical stress and electrical performance, which are then compared with the physical quantities actually measured to calculate multiple mean absolute errors;

[0090] Among the coding combinations corresponding to the multiple mean absolute errors, a random selection method based on probability is used to select X coding combinations;

[0091] 3≤X, and X is a positive integer;

[0092] Next, partial information is exchanged between the X coding combinations, and partial codes in each of the X coding combinations are randomly changed to generate multiple new coding combinations. Then, the method of random selection based on probability is used again to select X coding combinations, and partial information is exchanged between the X coding combinations, and partial codes in each of the X coding combinations are randomly changed to generate multiple new coding combinations. After multiple rounds of iterations, a coding combination corresponding to the minimum mean absolute error is obtained from the multiple new coding combinations retained in the last round of iteration, and it is decoded into the optimal parameter combination of the heat transfer model, the mechanical stress model and the electrical performance model.

[0093] By exchanging partial information between X coding combinations and randomly changing partial codes in each of the X coding combinations, multiple new coding combinations are generated, which has the following beneficial effects:

[0094] Avoid local optimal solutions:

[0095] When searching for the best parameter combination for the heat transfer model, mechanical stress model, and electrical performance model, if the selection is based only on the initially generated coding combination, it may fall into the local optimal solution. By exchanging partial information between X coding combinations and randomly changing some codes, the original local optimal state can be broken and more parameter space can be explored.

[0096] Increase the diversity of parameter combinations:

[0097] This approach can greatly increase the diversity of parameter combinations. Each information exchange and encoding change generates new encoding combinations, which may represent previously undiscovered and potentially better model parameter configurations.

[0098] Furthermore, the method of probabilistic random selection is as follows:

[0099] Assume there are n coding combinations, recorded as , the mean absolute error corresponding to each coding combination is ; Calculate the sum of multiple mean absolute errors S, S≠0:

[0100] ;

[0101] Then calculate the proportion of the mean absolute error of each encoding combination to the total:

[0102] Next, the inverse proportional weighting method is used to regenerate the proportion of the mean absolute error of each coding combination to the total, and then multiple probability intervals are generated based on the proportion of the mean absolute error of each coding combination to the total. The smaller the mean absolute error, the larger the probability interval generated:

[0103] Assume that the inverse proportional weighting method is used, the generated probability is P, and the coding combination is The corresponding probability interval is , coding combination The corresponding probability interval is , and so on, the coding combination The corresponding probability interval is , j is an index variable used to traverse and calculate the sum of the probabilities of the previous coding combinations;

[0104] Randomly generate a number between 0 and 1, determine the probability interval that the number falls into, determine the mean absolute error corresponding to the probability interval, determine the coding combination corresponding to the mean absolute error, select the coding combination, randomly generate a number between 0 and 1 and repeat X times to obtain X coding combinations.

[0105] A unique method based on coding combination, probabilistic random selection and multiple rounds of iterations is used to determine the optimal parameter combination of the heat transfer model, mechanical stress model and electrical performance model. Compared with the method of determining parameters using a specific network training method, it can effectively reduce model deviation and variance, thereby improving the accuracy of the entire life assessment and prediction, making the prediction results more in line with actual conditions.

[0106] The probabilistic random selection method generates a probability interval based on the proportion of the mean absolute error corresponding to each coding combination to the total. The coding combination with a smaller mean absolute error has a larger probability interval and a higher probability of being selected, thus avoiding single selection bias. This method combines randomness and determinism to a certain extent. On the one hand, it calculates the probability interval based on the mean absolute error, which is a deterministic way of evaluating model performance; on the other hand, the final selection is to determine the coding combination by randomly generating numbers that fall within a certain probability interval, which introduces randomness. This combination makes the parameter combination selection process both directional based on performance evaluation and random to explore a wider range of possibilities, which helps to find a more suitable model parameter combination in the optimization process and improve the model's simulation ability and prediction accuracy for complex physical phenomena.

[0107] Furthermore, in S3, instead of using a weighted or multi-factor coupling algorithm, the electrical performance model, fatigue life model, and thermal life model can be combined with a Bayesian model fusion algorithm to construct a comprehensive life fusion model.

[0108] Furthermore, in S5, for the preset safety threshold of failure warning, a long short-term memory network algorithm is used to dynamically adjust the threshold:

[0109] The monitoring data of the welding layer of the power semiconductor module per unit time is collected as input, and the long short-term memory network algorithm is trained to predict the state change of the welding layer.

[0110] If the long short-term memory network algorithm predicts that the remaining life of the welding layer will decrease faster than the set threshold in the future, the safety threshold will be lowered to Y times the original safety threshold to issue a warning signal more timely and improve the reliability of the system.

[0111] 0.6<Y<1.

[0112] During the operation of the power semiconductor module, sensors are used to collect data in real time, and the parameters of each model can be updated in real time, so that the life prediction can be dynamically adjusted as the actual working conditions change. This feature overcomes the limitation that the relatively static color judgment method cannot track changes in real time. The long short-term memory network algorithm is used to dynamically adjust the preset safety threshold of the failure warning, and the threshold is flexibly changed according to the predicted rate of decline of the remaining life of the welding layer. Compared with the warning method with a fixed threshold, it can issue a failure warning signal more timely, avoid missing the best maintenance time due to unreasonable threshold settings, further ensure the reliability of the operation of the power semiconductor module, and reduce the losses caused by the failure of the welding layer.

[0113] In summary, compared with the prior art, the present invention has significant advantages in accuracy, comprehensiveness, real-time performance and timely warning in terms of life assessment and failure prediction of power semiconductor welding layers, and can better meet the needs of power semiconductor module life management in actual engineering applications.

[0114] The above-mentioned power semiconductor soldering layer life assessment and failure prediction method can be applied to the following IGBT chip, because the IGBT chip itself is a power semiconductor device.

[0115] An IGBT chip design method comprises the following steps:

[0116] S1. Adopt trench gate and field stop layer structure design, by eliminating JFET effect, JFET is junction field effect transistor effect, increasing surface channel density, improving near-surface carrier concentration, reducing drift region thickness, optimizing field stop layer doping concentration and back P+ doping concentration, adjusting injection efficiency, adjusting tail current and loss during shutdown, so as to achieve high current density and low saturation conduction voltage drop Vcesat, and adjusting the ratio of conduction loss and switching loss according to different frequency application requirements to reduce temperature rise;

[0117] In the IGBT chip structure, "back P +" means that P-type impurities (such as boron) are doped on the back side of the chip (opposite to the front side, usually the side of the substrate), and the impurity atoms carry a positive charge (indicated by "+"). This doping forms a P-type region.

[0118] Vcesat refers to the saturation conduction voltage drop of the IGBT chip.

[0119] S2. Using the front carrier storage layer design method, a certain dose of N+ layer is injected under the emitter PBody to form a barrier layer between the N+ and N- drift regions, further increasing the carrier concentration at the front PN junction position to achieve a lower IGBT saturation conduction voltage drop Vcesat.

[0120] The emitter PBody is an area of ​​the IGBT chip.

[0121] S3. Use Dummy and SN design methods to reduce the effective channel density to meet the short-circuit capability required by IPM and enhance the robustness of the chip. Dummy and SN designs mainly change the electrical characteristics of the chip by adjusting certain structural parameters of the chip.

[0122] IPM is an intelligent power module of IGBT chip.

[0123] S4. Design the terminal of IGBT chip, adopt the structure of field limiting ring + field plate, optimize the terminal and layout design, and combine SiN and polyimide double-layer passivation to achieve high blocking voltage, low leakage current and high reliability;

[0124] IGBT chip, or insulated gate bipolar transistor chip, is a power semiconductor device widely used in the field of power electronics. In semiconductor chip design, the Dummy structure is an auxiliary structure that does not directly participate in the main function of the chip. SN design refers to the design for a specific sub-region inside the chip or related to some special doping N-type, N-type. In IGBT chip design, SN design involves special treatment of the N-type region inside the chip. SiN is the chemical formula of silicon nitride.

[0125] In actual production:

[0126] The Taiko thinning process is applied to the thickness of the IGBT chip to obtain a thinner wafer thickness, achieve a double reduction in saturation on-voltage drop and turn-off loss, and achieve a maximum transient operating junction temperature of 175°C;

[0127] Taiko thinning is a wafer thinning technology used in the semiconductor chip manufacturing process.

[0128] The cell size of the IGBT chip is reduced from 6um to 2.4um, which improves the power density from about 100A / cm² to about 200A / cm², and reduces the IGBT chip area by more than 40%;

[0129] Adopting the trench FS ultra-thin film process, the static on-state voltage drop, turn-off loss, short-circuit capability of the IGBT structure and the on-state voltage drop, reverse recovery loss, surge capability, and high-temperature leakage current of the FRD structure are comprehensively designed according to application requirements;

[0130] Trench FS is a process used to manufacture power semiconductor devices, especially insulated gate bipolar transistors (IGBTs).

[0131] The gate bus and finger of the IGBT chip are laid out, and the source pad is laid out to ensure the uniformity of the gate signal and achieve uniform conduction of the chip.

[0132] Gate bus is the gate bus and Finger is the finger-like structure.

[0133] In a chip design method, first of all, the specific operations and expected effects of using trench gate and field stop layer structure design are clearly pointed out, eliminating the JFET effect and adjusting the doping concentration to optimize the performance. This is an improvement on the core part of the chip structure.

[0134] Secondly, the front carrier storage layer design reduces the saturation conduction voltage drop by a unique way of injecting the N+ layer, which is an improvement in carrier management. The Dummy and SN designs improve the short-circuit capability and solve the important needs of motor application scenarios. The field limiting ring + field plate structure and double-layer passivation design of the terminal ensure the high reliability of the chip. The improvement of the taiko thinning process in chip thickness has brought about a series of optimizations in conduction voltage drop and turn-off loss. The reduction in cell size and the increase in power density are improvements in chip size and performance. The trench FS ultra-thin film process reflects the process improvement through the comprehensive design of multi-dimensional indicators from the perspective of the overall process.

[0135] Finally, the design of the gate and source layout ensures uniform conductivity of the chip, ensuring good performance of the chip from a layout perspective.

[0136] Meanwhile, the contents not described in detail in this specification belong to the prior art known to those skilled in the art.

[0137] In the embodiments provided by the present invention, it should be understood that the disclosed system or method can be implemented in other ways. For example, the above-described embodiments of the invention are only illustrative, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation.

[0138] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, and may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0139] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0140] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the basic features of the present invention.

[0141] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can replace or change the technical solution and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for evaluating the life span and predicting failure of a power semiconductor welding layer, characterized in that: The following steps are involved: S1. Collect and obtain chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data; S2. Based on the data obtained in S1, a heat transfer model, a mechanical stress model and an electrical performance model are constructed using a finite element analysis method; In S2, the heat transfer model is constructed: based on the chip design parameters, the power semiconductor module packaging and testing process parameters, and the power semiconductor module working condition monitoring data, the heat transfer model is constructed using the finite element analysis method. The heat transfer model is used to simulate the distribution of heat in the power semiconductor module under different working conditions. The heat transfer model is used to predict the heat load of the welding layer; Mechanical stress model construction: Based on the heat transfer model, chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data, the finite element analysis method is used to construct a mechanical stress model. The mechanical stress model is used to simulate stress changes under different working conditions. The mechanical stress model is used to evaluate whether the structural strength of the welding layer can withstand stress changes; Electrical performance model construction: Based on chip design parameters and power semiconductor module working condition monitoring data, the finite element analysis method is used to construct an electrical performance model. The electrical performance model is used to simulate the electrical stress of the welding layer under different voltage and current conditions. Combined with the electromigration threshold parameters of the material, the electrical performance model is used to predict the impact of electrical stress on the life of the welding layer; S3. Construction of fatigue life model: Based on the stress and strain data of the welding layer output by the mechanical stress model and the cumulative damage theory of Miner criterion, the stress cycles experienced by the welding layer under different working cycles are statistically analyzed. Combined with the SN curve of the welding material, the fatigue damage accumulation value of the welding layer is calculated to predict its remaining life based on mechanical fatigue. Thermal life model establishment: The welding layer temperature data obtained through the heat transfer model is used to establish a thermal life model by using the Arrhenius equation, by monitoring the relationship between the performance changes of the welding layer material and temperature and time, to predict the life loss of the welding layer caused by thermal aging; Construction of comprehensive life fusion model: By combining the electrical performance model, fatigue life model, and thermal life model, a weighted or multi-factor coupling algorithm is used to construct a comprehensive life fusion model, which is used to predict the overall life of the welding layer; S4, during the operation of the power semiconductor module, real-time data collection and transmission through sensors; The data collected in real time in S5 and S4 are calculated according to the comprehensive life model. When the remaining life of the welding layer is lower than the preset safety threshold, the system will issue a failure warning signal.

2. The method for evaluating the life span and predicting the failure of a power semiconductor welding layer according to claim 1, characterized in that: In S1, the box plot method is used to identify and eliminate outliers in the chip design parameters, power semiconductor module packaging and testing process parameters, and power semiconductor module working condition monitoring data.

3. The method for evaluating the life span and predicting the failure of a power semiconductor welding layer according to claim 1, characterized in that: In S2, for the heat transfer model, the mechanical stress model, and the electrical performance model, multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models, and multiple finite element electrical performance sub-models are constructed based on different assumptions or parameter ranges, and the output results of the multiple finite element heat transfer sub-models, multiple finite element mechanical stress sub-models, and multiple finite element electrical performance sub-models are used as training data to construct a random forest model; When the operating parameters of a new power semiconductor module are given, these parameters are input into the trained random forest model, which then outputs the prediction results of integrated heat transfer, mechanical stress or electrical performance.

4. The method for evaluating the life span and predicting failure of a power semiconductor welding layer according to claim 1 or 3, characterized in that: In S2, the heat transfer model is divided into multiple finite element heat transfer sub-models based on different material thermal conductivity assumptions, heat distribution under different heat dissipation methods, and different external environment temperature boundary conditions; The mechanical stress model is divided into multiple finite element mechanical stress sub-models according to different assumptions based on the mechanical properties of the material, different degrees of fit between the chip and the substrate, and whether there is a gap between the chip and the substrate; The electrical performance model is divided into multiple finite element electrical performance sub-models based on different conductivity assumptions and different electric field distribution assumptions.

5. The method for evaluating the life span and predicting the failure of a power semiconductor welding layer according to claim 4, characterized in that: In S2, the model parameters in the heat transfer model, mechanical stress model, and electrical performance model are generated in the following way: For the heat transfer model, the thermal conductivity of different materials, parameters related to the heat dissipation method, and the external ambient temperature boundary condition parameters are encoded; For the mechanical stress model, the parameters related to the mechanical properties of the material, the quantitative parameters of the tightness of the chip and the substrate, and the binary parameters indicating whether there is a gap, 0 for no gap and 1 for a gap, are encoded; For the electrical performance model, the conductivity assumption value and parameters related to the electric field distribution are encoded; After encoding the parameters of the heat transfer model, the mechanical stress model and the electrical performance model, a plurality of coding combinations are randomly generated, each coding combination represents a set of parameters of the heat transfer model, the mechanical stress model and the electrical performance model; For multiple sets of coding combinations, they are applied to the heat transfer model, mechanical stress model and electrical performance model to obtain the predicted results of heat transfer, mechanical stress and electrical performance, which are then compared with the physical quantities actually measured to calculate multiple mean absolute errors; Among the coding combinations corresponding to the multiple mean absolute errors, a random selection method based on probability is used to select X coding combinations; 3≤X, and X is a positive integer; Next, partial information is exchanged between the X coding combinations, and partial codes in each of the X coding combinations are randomly changed to generate multiple new coding combinations. Then, the method of random selection based on probability is used again to select X coding combinations, and partial information is exchanged between the X coding combinations, and partial codes in each of the X coding combinations are randomly changed to generate multiple new coding combinations. After multiple rounds of iterations, a coding combination corresponding to the minimum mean absolute error is obtained from the multiple new coding combinations retained in the last round of iteration, and it is decoded into a parameter combination of the heat transfer model, the mechanical stress model and the electrical performance model.

6. The method for evaluating the life span and predicting the failure of a power semiconductor welding layer according to claim 5, characterized in that: The method of probabilistic random selection is as follows: Assume there are n coding combinations, recorded as , the mean absolute error corresponding to each coding combination is ; Calculate the sum of multiple mean absolute errors S, S≠0: ； Then calculate the proportion of the mean absolute error of each encoding combination to the total: Next, the inverse proportional weighting method is used to regenerate the proportion of the mean absolute error of each coding combination to the total, and then multiple probability intervals are generated based on the proportion of the mean absolute error of each coding combination to the total. The smaller the mean absolute error, the larger the probability interval generated: Assume that the inverse proportional weighting method is used, the generated probability is P, and the coding combination is The corresponding probability interval is , coding combination The corresponding probability interval is , and so on, the coding combination The corresponding probability interval is , j is an index variable used to traverse and calculate the sum of the probabilities of the previous coding combinations; Randomly generate a number between 0 and 1, determine the probability interval that the number falls into, determine the mean absolute error corresponding to the probability interval, determine the coding combination corresponding to the mean absolute error, select the coding combination, randomly generate a number between 0 and 1 and repeat it X times to obtain X coding combinations.

7. The method for evaluating the life span and predicting the failure of a power semiconductor welding layer according to claim 1, characterized in that: In S5, for the preset safety threshold of failure warning, the long short-term memory network algorithm is used to dynamically adjust the threshold: Collect the monitoring data of the welding layer of the power semiconductor module per unit time as input, and train the long short-term memory network algorithm to predict the state change of the welding layer; If the long short-term memory network algorithm predicts that the remaining life of the welding layer will decrease faster than the set threshold in the future, the safety threshold is reduced to Y times the original safety threshold, 0.6<Y<1.

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