Link equal-length design method and device, electronic device, equipment and storage medium

Abstract

The invention provides a link equal-length design method and device, an electronic device, equipment and a storage medium, and the method comprises the steps: continuously obtaining the current first delay information of a first target device which needs to be subjected to system-level equal length in a packaging signal design file according to a set time interval, and synchronizing the current first delay information to a PCB main body signal design file, and continuously acquiring current second delay information of a second target device which needs to be subjected to system-level isometric operation in the PCB main body signal design file according to a set time interval, and synchronizing the current second delay information to the packaging signal design file. In this way, the side with the link equal-length design can continuously and automatically obtain the time delay information of the opposite end, so that the total time delay information of the whole system-level link can be continuously obtained, the timeliness and convenience of obtaining the time delay information of the opposite end by a packaging signal design side and a PCB main body signal design side are improved, repeated interaction delay is not needed, the design pressure is reduced, and the design efficiency is improved. The design efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a link equal length design method, device, electronic device and equipment, and storage medium. Background Art

[0002] In the field of integrated circuit design, the package substrate is a structure in the package. Its essence is a circuit board. The top is connected to the DIE through structures such as Bump (metal bump), and the bottom is connected to the PCB (Printed Circuit Board) through structures such as BGA Ball (Ball Grid Array Package). The package substrate provides various power and signal connection channels from the chip to the PCB.

[0003] The design of the package substrate includes two relatively independent processes: package signal design and PCB body signal design. Some signals have high requirements for signal integrity and synchronization, so these signal links need to be processed at the system level.

[0004] There are two main ways to process equal length at the system level. One is that the package signal design side extracts the delay from the PCB design file and then imports it into the package design file, and all equal lengths are completed during the package signal design process; or the PCB main body signal design side extracts the delay from the package design file and then imports it into the PCB design file, and all equal lengths are completed during the PCB main body signal design process. The second is that the package signal design side and the PCB main body signal design side each perform internal equal length, so there is no need to extract delay.

[0005] However, for the first method, during the design process, the design is constantly updated and optimized, and the delay is constantly changing, which leads to the need for repeated interactive delays during the design process. At the same time, since the equal-length design is always completed by one party, this puts a lot of design pressure on the party that is equalizing the length. For the second method, in order to ensure that the length is equal internally, each side will use the longest link length of all the signals that need to be equalized as the basis for equalization (only in this way can the internal length be guaranteed). This will result in that when the system is equalized, the equal length of the entire link is based on the sum of the longest link lengths of the two-level package signal design and PCB main body signal design. This will greatly increase the system-level link after equalization, thereby affecting the signal quality. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a link equal length design method, device, electronic device and equipment, and storage medium to improve the timeliness and convenience of the package signal design side and the PCB main body signal design side in obtaining the delay information of the other end, and improve the efficiency of link equal length design.

[0007] An embodiment of the present application provides an application in a link equal length design system, the link equal length design system comprising a first device, and the method comprising: obtaining, through the first device, first delay information of a first target device that needs to be equal in length at the system level in a package signal design file, and synchronizing the first delay information into a PCB main signal design file; and obtaining, through the first device, second delay information of a second target device that needs to be equal in length at the system level in the PCB main signal design file, and synchronizing the second delay information into the package signal design file; wherein the first target device and the second target device are two devices that can be connected by pins to form a system-level link that needs to be equal in length; obtaining, through the first device, the current first delay information of the first target device at a set time interval, and synchronizing the current first delay information with the PCB main signal design file. When the first delay information recorded in the package signal design file is different from the first delay information recorded in the package signal design file, the first delay information in the PCB main signal design file is updated to the current first delay information; and, the current second delay information of the second target device is obtained through the first device at a set time interval, and when the current second delay information is different from the second delay information recorded in the package signal design file, the second delay information in the package signal design file is updated to the current second delay information, so as to design the length of the link connected to each pin of the first target device according to the second delay information recorded in the package signal design file, and / or, design the length of the link connected to each pin of the second target device according to the first delay information recorded in the PCB main signal design file, so that the system-level link formed by the pin connection of the first target device and the second target device is of equal length.

[0008] In the above implementation scheme, the first delay information of the first target device that needs to be equalized at the system level in the package signal design file is obtained and synchronized to the PCB main signal design file, and the second delay information of the second target device that needs to be equalized at the system level in the PCB main signal design file is obtained and synchronized to the package signal design file. After that, the first delay information of the first target device that needs to be equalized at the system level in the package signal design file is continuously obtained at a set time interval, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, it is synchronized to the PCB main signal design file, and the second delay information of the second target device that needs to be equalized at the system level in the PCB main signal design file is continuously obtained at a set time interval, and when the current second delay information is different from the second delay information recorded in the package signal design file, it is synchronized to the package signal design file. In this way, when performing link equal length design, if the package signal design side or the PCB main signal design side performs the link equal length design separately, the side performing the link equal length design can continuously and automatically obtain the delay information of the other end, so as to continuously obtain the total delay information of the entire system-level link, thereby improving the timeliness and convenience of the package signal design side and the PCB main signal design side in obtaining the delay information of the other end, without the need for repeated interactive delays, and the side performing the link equal length design can start the system-level link equal length design after finding that the delay information of the other end is stable, which can effectively reduce the number of design updates on the side performing the link equal length design, reduce design pressure, and improve design efficiency. If the package signal design side and the PCB main body signal design side independently perform link equal length design, since the package signal design side and the PCB main body signal design side can each automatically and continuously obtain the delay information of the other end, the total delay information of the entire system-level link can be continuously obtained, thereby improving the timeliness and convenience of the package signal design side and the PCB main body signal design side in obtaining the delay information of the other end. Therefore, when the link equal length design is performed independently, the link with the largest total delay in the system-level link can be used for equal length design, instead of using the longest link in each design file to perform equal length design separately. This can make the system-level link length after equal length reasonable and reduce the impact on signal quality.

[0009] Further, the obtaining of the first delay information of the first target device that needs to be system-level equal length in the package signal design file includes: obtaining the link information of the link connected to all the pins of the first target device in the package signal design file, and calculating the first delay information based on the link information; the obtaining of the second delay information of the second target device that needs to be system-level equal length in the PCB main body signal design file includes: obtaining the link information of the link connected to all the pins of the second target device in the PCB main body signal design file, and calculating the second delay information based on the link information; the obtaining of the current first delay information of the first target device according to the set time interval includes: obtaining the current link information of the link connected to all the pins of the first target device in the package signal design file, and calculating the current first delay information based on the current link information; the obtaining of the current second delay information of the second target device according to the set time interval includes: obtaining the current link information of the link connected to all the pins of the second target device in the PCB main body signal design file, and calculating the current second delay information based on the current latest link information; wherein, the link information includes: the line length of the link in each wiring layer, the thickness and relative dielectric constant of each stacked layer passed by the link.

[0010] In the above implementation, the first delay information is calculated by obtaining the link information of the link connected to all the pins of the first target device, and the second delay information is calculated by obtaining the link information of the link connected to all the pins of the second target device, and the link information includes the line length of the link in each wiring layer, the thickness of each stacking layer through which the link passes, and the relative dielectric constant. In this way, since the delay of the link is related to the line length of the link in each wiring layer, the thickness of each stacking layer through which the link passes, and the relative dielectric constant, the determination of the first delay information and the second delay information can be achieved more accurately.

[0011] Furthermore, before obtaining the first delay information of the first target device that needs to be system-level equalized in the package signal design file, and obtaining the second delay information of the second target device that needs to be system-level equalized in the PCB main signal design file, the method also includes: obtaining the first pin information of the first target device in the package signal design file, and obtaining the second pin information of the second target device in the PCB main signal design file; and determining that the first pin information matches the second pin information.

[0012] In the above implementation, before obtaining the first delay information and the second delay information, it is first determined whether the first pin information of the first target device matches the second pin information of the second target device. If they match, it indicates that the first target device and the second target device can be connected to form a system-level link. Only then are the first delay information and the second delay information obtained. This can avoid meaningless acquisition of the first delay information and the second delay information and reduce the generation of invalid overhead.

[0013] Further, determining that the first pin information matches the second pin information includes: determining whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, and determining whether identification information of each pin in the first pin information corresponds one-to-one with identification information of each pin in the second pin information; when the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, determining that the first pin information matches the second pin information.

[0014] In the above implementation, by judging the consistency of the number of pins in the first pin information and the number of pins in the second pin information, and judging whether the identification information of each pin corresponds one to one, it is possible to more accurately determine whether the first pin information and the second pin information can match.

[0015] Furthermore, determining that the first pin information matches the second pin information includes: determining the position of each pin in the first pin information and each pin in the second pin information in the same manner; and determining that the first pin information matches the second pin information when the positions of each pin in the first pin information and each pin in the second pin information correspond one-to-one after the positions are determined.

[0016] In the above implementation, by determining the position of each pin in the first pin information and each pin in the second pin information in the same manner, and then determining that the first pin information matches the second pin information when the positions of each pin in the first pin information and each pin in the second pin information correspond one to one after the positions are determined, it is determined that the first pin information matches the second pin information. In this way, it is possible to more accurately determine whether the first pin information and the second pin information can match based on the relative position.

[0017] Furthermore, the positions of each pin in the first pin information and each pin in the second pin information are determined in the same manner, including: determining the position coordinates of each pin in the first pin information with the center of the first target device as the origin; and determining the position coordinates of each pin in the second pin information with the center of the second target device as the origin.

[0018] It can be understood that when designing an integrated circuit, the design structures of the devices in the PCB and the devices in the chip are basically corresponding. Therefore, in the above implementation method, the position coordinates of each pin in the first pin information are determined by taking the center of the first target device as the origin, and the position coordinates of each pin in the second pin information are determined by taking the center of the second target device as the origin. In this way, based on the position coordinates of each pin of the first target device and the position coordinates of each pin of the second target device, it is possible to more accurately determine whether the first pin information and the second pin information can match.

[0019] Further, determining that the first pin information matches the second pin information includes: determining whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, and determining whether the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, and determining the position of each pin in the first pin information and each pin in the second pin information in the same manner; when the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, and the positions of each pin in the first pin information and each pin in the second pin information correspond one-to-one, determining that the first pin information matches the second pin information.

[0020] In the above implementation, the consistency of the number of pins in the first pin information and the number of pins in the second pin information, the correspondence of the identification information of the pins in the first pin information and the identification information of the pins in the second pin information, and the correspondence of the positions of the pins in the first pin information and the pins in the second pin information are used to jointly determine whether the first pin information matches the second pin information. In this way, the matching accuracy of the first pin information and the second pin information is further improved, meaningless acquisition of the first delay information and the second delay information is avoided, and the generation of invalid overhead is reduced.

[0021] Furthermore, before obtaining the first delay information of the first target device that needs to be system-level equalized in the package signal design file, and obtaining the second delay information of the second target device that needs to be system-level equalized in the PCB main signal design file, the method also includes: obtaining a selected delay information expression type; the delay information expression type includes a duration type and a length type; correspondingly, the first delay information, the second delay information, the current first delay information, and the current second delay information are represented by the delay information expression type.

[0022] In the above implementation, by first selecting the delay information expression type and then synchronizing the first delay information and the second delay information, it can be represented according to the selected delay information expression type, so that the expression of the delay information on the package signal design side and the PCB main signal design side is unified, which facilitates the subsequent equal length design of the link.

[0023] Furthermore, the link equal length design system also includes a second device running the package signal design file and a third device running the PCB main signal design file; the first device is respectively connected to the second device and the third device in communication; the first device obtains the current first delay information of the first target device at a set time interval, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, the first delay information in the PCB main signal design file is updated to the current first delay information; and the first device obtains the current second delay information of the second target device at a set time interval, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, the first delay information in the PCB main signal design file is updated to the current first delay information. When the second delay information before the target device is different from the second delay information recorded in the package signal design file, updating the second delay information in the package signal design file to the current second delay information includes: receiving, through the first device, the current link information of the link connected to all the pins of the first target device in the package signal design file transmitted by the second device at a set time interval, and calculating the current first delay information according to the current link information of the link, and when the current first delay information is different from the first delay information recorded in the PCB main body signal design file, sending the current first delay information to the second device, so that the second device updates the PCB main body The first delay information in the signal design file is updated to the current first delay information; after calculating the current first delay information according to the current link information of the link, the current link information of the link connected to all pins in the second target device in the PCB main body signal design file is received from the third device at a set time interval, and the current second delay information is calculated according to the current link information of the link, and when the current second delay information is different from the second delay information recorded in the package signal design file, the current second delay information is sent to the third device, so that the third device updates the second delay information in the package signal design file to the current after calculating the current second delay information according to the current link information of the link, receiving the current link information of the link connected to all pins in the first target device in the package signal design file from the second device again at a set time interval through the first device, and calculating the current first delay information according to the current link information of the link, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, sending the current first delay information to the second device, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information.

[0024] In the above implementation, during the polling process, before receiving the current link information of the link connected to all pins of the second target device in the PCB main signal design file transmitted by the third device at a set time interval each time, it is necessary to first complete the operation of receiving the current link information of the link connected to all pins of the first target device in the package signal design file transmitted by the second device, and calculating the current first delay information according to the current link information of the link. Similarly, during the polling process, before receiving the current link information of the link connected to all pins of the first target device in the package signal design file transmitted by the second device at a set time interval each time, it is necessary to first complete the operation of receiving the current link information of the link connected to all pins of the second target device in the PCB main signal design file transmitted by the third device at a set time interval, and calculating the current second delay information according to the current link information of the link. In this way, each acquisition of data in the second device and the issuance of delay information must rely on the last acquisition of data in the third device to allow execution; similarly, each acquisition of data in the third device and the issuance of delay information must rely on the last acquisition of data in the second device to allow execution. In this way, when either the second device or the third device has an abnormality and cannot obtain data normally, the subsequent process will not be triggered, thereby not causing a large amount of delayed information to be received after the abnormal device recovers, thereby avoiding transmission congestion.

[0025] Furthermore, the length of the link connected to each pin of the first target device is designed according to the second delay information recorded in the package signal design file, and the length of the link connected to each pin of the second target device is designed according to the first delay information recorded in the PCB main signal design file, so that the system-level link formed by the first target device and the second target device through pin connection is equal in length, including: according to the current second delay information recorded in the package signal design file, the link connected to each pin of the first target device is designed to be equal in length; according to the current first delay information recorded in the PCB main signal design file, the link connected to each pin of the second target device is designed to be equal in length.

[0026] In the above implementation, since the package signal design side and the PCB main body signal design side can each automatically and continuously obtain the delay information of the other end, and thus can continuously obtain the total delay information of the entire system-level link, when each independently performs link equal length design, the link with the largest total delay in the system-level link can be used for equal length design, instead of using the longest link in each design file to perform equal length design respectively. This can make the length of the system-level link after equal length reasonable and reduce the impact on signal quality.

[0027] The embodiment of the present application also provides a link equal length design device, including: a first device applied to a link equal length design system, including: an initialization module, used to obtain first delay information of a first target device that needs to be equal length at the system level in a package signal design file, and synchronize the first delay information into a PCB main signal design file; and obtain second delay information of a second target device that needs to be equal length at the system level in the PCB main signal design file, and synchronize the second delay information into the package signal design file; wherein the first target device and the second target device are two devices that can be connected by pins to form a system-level link that needs to be equal length; a dynamic update module, used to obtain the current first delay information of the first target device at a set time interval, and synchronize the current first delay information with the first delay information recorded in the PCB main signal design file; When the information is different, the first delay information in the PCB main signal design file is updated to the current first delay information; and the current second delay information of the second target device in the PCB main signal design file is obtained according to the set time interval, and when the current second delay information is different from the second delay information recorded in the package signal design file, the second delay information in the package signal design file is updated to the current second delay information, so as to design the length of the link connected to each pin of the first target device according to the second delay information recorded in the package signal design file, and / or, design the length of the link connected to each pin of the second target device according to the first delay information recorded in the PCB main signal design file, so that the system-level link formed by the pin connection of the first target device and the second target device is of equal length.

[0028] An embodiment of the present application also provides an electronic device, including a printed circuit board and a chip arranged on the printed circuit board; the chip includes a first target device that needs to be equal in length at the system level, and the printed circuit board includes a second target device that needs to be equal in length at the system level; wherein the pins of the first target device and the second target device are interconnected, and the system-level links formed after the pins of the first target device and the second target device are interconnected are of equal length, and the length of the system-level link is designed according to any one of the link equal length design methods.

[0029] An embodiment of the present application also provides an electronic device, comprising: a processor, a memory and a communication module; the communication module is used to communicate with an external device; the processor is used to execute one or more programs stored in the memory to implement any of the above-mentioned link equal length design methods.

[0030] A computer-readable storage medium is also provided in an embodiment of the present application. The computer-readable storage medium stores one or more programs. The one or more programs can be executed by one or more processors to implement any of the above-mentioned link equal length design methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A flowchart of a link equal length design method provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram of the structure of a packaging substrate provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a process for dynamically updating delay information provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of the structure of a link equal length design device provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0038] In order to improve the timeliness and convenience of obtaining the opposite-end delay information by the package signal design side and the PCB main body signal design side, and improve the efficiency of link equal length design, a link equal length design method applied to a link equal length design system is provided in an embodiment of the present application. The link equal length design system includes a first device.

[0039] See also Figure 1 As shown, Figure 1 A schematic diagram of a flow chart of a link equal length design method provided in an embodiment of the present application, including:

[0040] S101: Obtain, through the first device, first delay information of a first target device that needs to be system-level equal in length in a package signal design file, and synchronize the first delay information into a PCB main signal design file; and, obtain, through the first device, second delay information of a second target device that needs to be system-level equal in length in the PCB main signal design file, and synchronize the second delay information into the package signal design file.

[0041] The first target device and the second target device are two devices that can be connected through pins to form a system-level link of equal length.

[0042] In the embodiment of the present application, the first target device can be a BGA Ball or LGA (Land Grid Array) solder joint used to connect to the PCB board in the package signal design file. The second target device can be a BGA Ball or LGA solder joint used to connect to the chip in the PCB main body signal design file.

[0043] In an embodiment of the present application, a package signal design file refers to a file used for chip package design, and a PCB main signal design file refers to a file used for signal design on a PCB. Both can be used by engineers on the package signal design side and engineers on the PCB main signal design side to complete chip package design and PCB main signal design, respectively.

[0044] For example, see Figure 2 As shown, Figure 2 A packaging substrate using BGA Ball for connection is shown. Figure 2 The red circle in the figure is the Bump, the blue rectangle is the substrate, and the gray circle is the BGA Ball. The package signal design file is used to implement the package from DIE to BGA Ball in the figure, and the PCB body signal design file is used to implement the design of each signal link from BGA Ball to PCB board in the figure.

[0045] In an embodiment of the present application, the first device can obtain link information of the link connected to all pins of the first target device in the package signal design file, and calculate the first delay information based on the link information; and can obtain link information of the link connected to all pins of the second target device in the PCB main signal design file, and calculate the second delay information based on the link information.

[0046] In the embodiment of the present application, the link information may include the line length of the link in each wiring layer, the thickness and relative dielectric constant of each stacked layer through which the link passes.

[0047] Exemplarily, the delay information of the signal can be: signal line delay plus signal hole delay, the signal line delay is related to the link length and the relative dielectric constant of the medium in the layer where the link is located, and the signal hole delay is related to the height of the signal hole (i.e. the thickness of the stack through which the link passes) and the relative dielectric constant of the medium of the stack through which it passes. If a link passes through multiple stacks, then the delay information of the link can be obtained by adding up the signal line delay and signal hole delay of all the stacks passed.

[0048] For example, the signal line delay of each layer can be equal to the line length of each wiring layer divided by the propagation speed of the signal in the layer; and the signal hole delay of each layer can be equal to the thickness of each stacked layer divided by the propagation speed of the signal in the stacked layer. The propagation speed of the signal in any layer can be: where v p is the propagation speed of the signal, μ r is the relative magnetic permeability of the medium, ε r is the relative dielectric constant of the stack. Since the medium used in the packaging design is usually a non-ferromagnetic material, the relative magnetic permeability of the medium is usually 1, so the propagation speed of the signal in any layer can also be simplified to:

[0049] It can be understood that for ferromagnetic materials, when obtaining link information, the relative magnetic permeability of the laminated medium can also be obtained.

[0050] Based on the above method, the first delay information and the second delay information can be determined relatively quickly and accurately.

[0051] In the embodiment of the present application, after executing step S101, the package signal design side and the PCB main body signal design side each have the delay information of the other end. At this time, the embodiment of the present application considers that the initialization is completed, and then proceeds to step S102, that is, to perform regular delay information update and synchronization, so that the package signal design side and the PCB main body signal design side can be updated and synchronized to the latest delay information of the other end in time, so as to perform equal length design of the link.

[0052] S102: obtaining the current first delay information of the first target device at a set time interval through the first device, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, updating the first delay information in the PCB main signal design file to the current first delay information; and obtaining the current second delay information of the second target device at a set time interval through the first device, and when the current second delay information is different from the second delay information recorded in the package signal design file, updating the second delay information in the package signal design file to the current second delay information.

[0053] In the embodiment of the present application, the set time interval can be set by an engineer according to actual needs, or it can be pre-set when designing the program code for implementing the method provided in the embodiment of the present application. Exemplarily, the set time interval can be 0.1 second to 1 minute.

[0054] In the embodiment of the present application, the manner in which the first device obtains the current first delay information of the first target device can refer to the description of obtaining the first delay information of the first target device in step S101 above, which will not be repeated here. The manner in which the first device obtains the current second delay information of the second target device can refer to the description of obtaining the second delay information of the second target device in step S101 above, which will not be repeated here.

[0055] In a feasible implementation of the embodiment of the present application, the package signal design file and the PCB main signal design file may not be set in the first device. In this case, a database or storage space may be configured in the first device to record the first delay information and the second delay information obtained each time. Therefore, each time the current first delay information is obtained: it can be compared with the first delay information recorded in the first device. If they are consistent, it means that the current first delay information is the same as the first delay information recorded in the PCB main signal design file; if they are inconsistent, it means that the current first delay information is different from the first delay information recorded in the PCB main signal design file. The current first delay information can be used to overwrite the originally stored first delay information in the database or storage space, and the current first delay information is sent to the PCB main signal design file to update the first delay information. And, each time the current second delay information is obtained: it can be compared with the second delay information recorded in the second device. If they are consistent, it means that the current second delay information is the same as the second delay information recorded in the package signal design file; if they are inconsistent, it means that the current second delay information is different from the second delay information recorded in the package signal design file, and the current second delay information can be used to overwrite the originally stored second delay information in the database or storage space, and the current second delay information can be sent to the package signal design file to update the second delay information.

[0056] In another feasible implementation of the embodiment of the present application, the package signal design file and the PCB main signal design file may also not be set in the first device. Assume that the package signal design file is set in the second device, the PCB main signal design file is set in the third device, and the second device and the third device belong to the link equal length design system of the embodiment of the present application. At this time, every time the first device obtains the current first delay information: the first delay information recorded in the PCB main signal design file can be obtained from the third device with the PCB main signal design file, and compared with the current first delay information. If consistent, it means that the current first delay information is the same as the first delay information recorded in the PCB main signal design file; if inconsistent, it means that the current first delay information is different from the first delay information recorded in the PCB main signal design file, and the current first delay information can be sent to the PCB main signal design file of the third device to update the first delay information. And, every time the current second delay information is obtained: the second delay information recorded in the package signal design file can be obtained from the second device with the package signal design file, and compared with the current second delay information. If they are consistent, it means that the current second delay information is the same as the second delay information recorded in the package signal design file; if they are inconsistent, it means that the current second delay information is different from the second delay information recorded in the package signal design file, and the current second delay information can be sent to the package signal design file of the second device to update the second delay information.

[0057] In another feasible implementation of the embodiment of the present application, the package signal design file can be set in the first device, and the PCB main signal design file can be set in the third device. At this time, the first device can be used to perform link design on the package signal design side. At this time, the first device can obtain the local package signal design file, thereby obtaining the current first delay information, and obtain the first delay information recorded in the PCB main signal design file from the third device. If the two are inconsistent, the current first delay information can be sent to the third device to update the first delay information recorded in the PCB main signal design file. The first device can also obtain the current link information of the link connected to all pins in the second target device from the third device, and calculate the current second delay information based on the current link information of the link, and compare it with the locally stored second delay information. If it is inconsistent, the locally stored second delay information is updated.

[0058] In another feasible implementation of the embodiment of the present application, the PCB main signal design file can be set in the first device, and the package signal design file can be set in the second device. At this time, the first device can be used to perform link design on the package signal design side. At this time, the first device can obtain the local PCB main signal design file, thereby obtaining the current second delay information, and obtain the second delay information recorded in the package signal design file from the second device. If the two are inconsistent, the current second delay information can be sent to the second device to update the second delay information recorded in the package signal design file. The first device can also obtain the current link information of the link connected to all pins in the first target device from the second device, and calculate the current first delay information based on the current link information of the link, and compare it with the locally stored first delay information. If it is inconsistent, the locally stored first delay information is updated.

[0059] In another feasible implementation of the embodiment of the present application, both the package signal design file and the PCB main body signal design file can be set in the first device. At this time, the first device can be used for link design on the package signal design side, and can also be used for link equal length design on the PCB main body signal design side. At this time, the first device can obtain the local package signal design file to obtain the current first delay information, and compare it with the locally stored first delay information. If the two are inconsistent, the locally stored first delay information can be updated to the current first delay information. The first device can also obtain the local PCB main body signal design file to obtain the current second delay information, and compare it with the locally stored second delay information. If the two are inconsistent, the locally stored second delay information can be updated to the current second delay information.

[0060] In the embodiment of the present application, before executing step S101, a matching detection between the first target device and the second target device may be performed first, and then step S101 is performed only when the matching detection passes, so as to reduce unnecessary overhead.

[0061] In an embodiment of the present application, a method for performing a matching detection between a first target device and a second target device may include: obtaining first pin information of the first target device in a package signal design file, and obtaining second pin information of the second target device in a PCB main signal design file, and then determining whether the first pin information matches the second pin information.

[0062] In a feasible implementation of the embodiment of the present application, it can be determined whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, and whether the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information; if the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, it is determined that the first pin information matches the second pin information. In other cases, it is determined that the first pin information does not match the second pin information.

[0063] In a feasible implementation of the embodiment of the present application, the positions of the pins in the first pin information and the pins in the second pin information may be determined in the same manner. When the positions of the pins in the first pin information and the pins in the second pin information correspond one-to-one after the positions are determined, it is determined that the first pin information matches the second pin information. If the positions of the pins in the first pin information and the pins in the second pin information do not correspond one-to-one after the positions are determined, it is determined that the first pin information does not match the second pin information.

[0064] Exemplarily, the process of determining the position of each pin in the first pin information and each pin in the second pin information in the same manner may include: determining the position coordinates of each pin in the first pin information with the center of the first target device as the origin; determining the position coordinates of each pin in the second pin information with the center of the second target device as the origin. At this time, if the position coordinates of each pin correspond to each other and are the same, it can be determined that the first pin information matches the second pin information.

[0065] It can be understood that when designing an integrated circuit, the design structures of the devices in the PCB and the devices in the chip are basically corresponding. Therefore, in the above implementation method, the position coordinates of each pin in the first pin information are determined by taking the center of the first target device as the origin, and the position coordinates of each pin in the second pin information are determined by taking the center of the second target device as the origin. In this way, based on the position coordinates of each pin of the first target device and the position coordinates of each pin of the second target device, it is possible to more accurately determine whether the first pin information and the second pin information can match.

[0066] In a feasible implementation of the embodiment of the present application, it is also possible to determine whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, and whether the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, and determine the position of each pin in the first pin information and each pin in the second pin information in the same way; when the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, and the positions of each pin in the first pin information and each pin in the second pin information correspond one-to-one, it is determined that the first pin information matches the second pin information. In other cases, it is determined that the first pin information does not match the second pin information.

[0067] In this way, the consistency of the number of pins in the first pin information and the number of pins in the second pin information, the correspondence of the identification information of the pins in the first pin information and the identification information of the pins in the second pin information, and the correspondence of the positions of the pins in the first pin information and the pins in the second pin information are used to jointly determine whether the first pin information matches the second pin information, which can further improve the matching accuracy of the first pin information and the second pin information, avoid meaningless acquisition of the first delay information and the second delay information, and reduce the generation of invalid overhead.

[0068] In a feasible implementation of an embodiment of the present application, before executing step S101, a selected delay information expression type can also be obtained. Among them, the delay information expression type includes a duration type and a length type. Thereafter, the first delay information, the second delay information, the current first delay information, and the current second delay information are all represented by the selected delay information expression type. In this way, the delay information can be represented according to the selected delay information expression type, so that the expression of the delay information on the package signal design side and the PCB main body signal design side is unified, which facilitates the subsequent equal length design of the link.

[0069] In a feasible implementation of the embodiment of the present application, when the package signal design file is set in the second device, the PCB main body signal design file is set in the third device, and the second device and the third device belong to the link equal length design system of the embodiment of the present application, before executing step S101, it can also include: receiving a connection request from the second device through the first device, and establishing a communication connection with the second device when there is no connection with other second devices; receiving a connection request from the third device, and establishing a communication connection with the third device when there is no connection with other third devices. In this way, the first device only connects to one second device and one third device at the same time, thereby only completing the synchronization of the delay information of the package signal design side and the PCB main body signal design side of one package substrate, reducing the mismatch between the package signal design side and the PCB main body signal design side of different package substrates, reducing the execution risk of erroneous tasks, and improving the reliability of the solution.

[0070] In actual application, one side of the link design (such as the package signal design side or the PCB main body signal design side) may experience a long period of software freeze and be unable to receive data, while the other side continues to update data. At this time, since the delay information synchronization is continuously performed regularly in step S102, the side where the freeze occurs may generate a large amount of delay information to be received and processed in the freeze device, which will cause information transmission blockage, and then lead to information loss or software crash. To this end, in a feasible implementation of the embodiment of the present application, for step S102, when the link equal length design system also includes a second device running the package signal design file and a third device running the PCB main body signal design file, it can be set to:

[0071] The first device receives the current link information of the link connected to all the pins of the first target device in the package signal design file transmitted by the second device at a set time interval, calculates the current first delay information according to the current link information of the link, and sends the current first delay information to the second device when the current first delay information is different from the first delay information recorded in the PCB main signal design file, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information;

[0072] After calculating the current first delay information according to the current link information of the link, receiving the current link information of the link connected to all pins in the second target device in the PCB main signal design file from the third device at a set time interval, and calculating the current second delay information according to the current link information of the link, and sending the current second delay information to the third device when the current second delay information is different from the second delay information recorded in the package signal design file, so that the third device updates the second delay information in the package signal design file to the current second delay information;

[0073] After calculating the current second delay information based on the current link information of the link, the current link information of the link connected to all pins in the first target device in the package signal design file is received from the second device again at a set time interval through the first device, and the current first delay information is calculated based on the current link information of the link, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, the current first delay information is sent to the second device, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information.

[0074] That is, the acquisition of the current first delay information and the acquisition of the current second delay information can be regarded as two operation steps, which are continuously executed in a cycle. In the entire cycle, if any operation step fails to be completed, the next operation step cannot be executed. In this way, the problem of transmission congestion can be avoided.

[0075] For example, see Figure 3 As shown:

[0076] Operation step 1: Receive the current link information of the link connected to all pins of the first target device in the package signal design file from the second device through the first device, and calculate the current first delay information based on the current link information of the link, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, send the current first delay information to the second device, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information. When the current first delay information is the same as the first delay information recorded in the PCB main signal design file, end this operation step.

[0077] Operation step 2: Receive the current link information of the link connected to all pins in the second target device in the PCB main signal design file from the third device through the first device, and calculate the current second delay information based on the current link information of the link, and when the current second delay information is different from the second delay information recorded in the package signal design file, send the current second delay information to the third device, so that the third device updates the second delay information in the package signal design file to the current second delay information. When the current second delay information is the same as the second delay information in the package signal design file, end this operation step.

[0078] Operation step 1 and operation step 2 are executed in a continuous cycle, each execution is separated by the set time interval, and if any operation step is not completed, the next operation step will not be performed.

[0079] In an embodiment of the present application, the length of the link connected to each pin of the first target device can be designed according to the second delay information recorded in the package signal design file, and / or the length of the link connected to each pin of the second target device can be designed according to the first delay information recorded in the PCB main signal design file, so that the system-level link formed by the pin connection of the first target device and the second target device is of equal length.

[0080] It can be understood that in a feasible implementation of the embodiment of the present application, the package signal design side can design the length of the link connected to each pin of the first target device according to the latest second delay information recorded in the package signal design file, so that the system-level links constituted by the first target device and the second target device are of equal length.

[0081] In another feasible implementation of the embodiment of the present application, the PCB main signal design side can also design the length of the link connected to each pin of the second target device according to the latest first delay information recorded in the PCB main signal design file, so that the system-level links constituted by the second target device and the first target device are of equal length.

[0082] In another feasible implementation of the embodiment of the present application, the package signal design side may design the links connected to the pins of the first target device to be equal in length according to the current second delay information recorded in the package signal design file, and the PCB main body signal design side may design the links connected to the pins of the second target device to be equal in length according to the current first delay information recorded in the PCB main body signal design file.

[0083] It can be understood that in the above three feasible implementations, the package signal design side can obtain the current first delay information of the first target device according to the package signal design file, and then obtain the latest total delay of each system-level link composed of the first target device and the second target device in combination with the recorded current second delay information, and then the link length design of the link connected to each pin of the first target device can be performed based on the maximum total delay of each system-level link. Exemplarily, assuming that the maximum total delay of each system-level link is Lmax, and the second delay information corresponding to the link of a certain package signal design side is L1, then when the package signal design side performs link equal length design alone, the link can be designed as Lmax-L1.

[0084] In an embodiment of the present application, the relevant operations for implementing delayed signal acquisition and synchronization can be set to an independent program implementation, recorded as program A. For the package signal design side and the PCB main body signal design side, a peer program that interacts with program A can be designed respectively, recorded as B_pkg and B_pcb respectively, which are used to establish a connection with program A and provide program A with link information of the first target device and link information of the second target device. B_pkg can be embedded in the package signal design software, and B_pcb can be embedded in the PCB main body signal design software. It can be understood that when the package signal design software and the PCB main body signal design software support direct interaction, the functions of program A can also be directly written into the package signal design software and the PCB main body signal design software.

[0085] Based on the link equal length design method provided in the embodiment of the present application, the first delay information of the first target device that needs to be equal at the system level in the package signal design file is obtained and synchronized to the PCB main signal design file, and the second delay information of the second target device that needs to be equal at the system level in the PCB main signal design file is obtained and synchronized to the package signal design file. After that, the first delay information of the first target device that needs to be equal at the system level in the package signal design file is continuously obtained at a set time interval, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, it is synchronized to the PCB main signal design file, and the second delay information of the second target device that needs to be equal at the system level in the PCB main signal design file is continuously obtained at a set time interval, and when the current second delay information is different from the second delay information recorded in the package signal design file, it is synchronized to the package signal design file. In this way, when performing link equal length design, if the package signal design side or the PCB main signal design side performs the link equal length design separately, the side performing the link equal length design can continuously and automatically obtain the delay information of the other end, so as to continuously obtain the total delay information of the entire system-level link, thereby improving the timeliness and convenience of the package signal design side and the PCB main signal design side in obtaining the delay information of the other end, without the need for repeated interactive delays, and the side performing the link equal length design can start the system-level link equal length design after finding that the delay information of the other end is stable, which can effectively reduce the number of design updates on the side performing the link equal length design, reduce design pressure, and improve design efficiency. If the package signal design side and the PCB main body signal design side independently perform link equal length design, since the package signal design side and the PCB main body signal design side can each automatically and continuously obtain the delay information of the other end, the total delay information of the entire system-level link can be continuously obtained, thereby improving the timeliness and convenience of the package signal design side and the PCB main body signal design side in obtaining the delay information of the other end. Therefore, when the link equal length design is performed independently, the link with the largest total delay in the system-level link can be used for equal length design, instead of using the longest link in each design file to perform equal length design separately. This can make the system-level link length after equal length reasonable and reduce the impact on signal quality.

[0086] Based on the same inventive concept, the present application also provides a link equal length design device 400. Figure 4 As shown, Figure 4 Shows the use of Figure 1The link equal length design device of the method shown. It should be understood that the specific functions of the device 400 can be referred to the description above, and the detailed description is appropriately omitted here to avoid repetition. The device 400 includes at least one software function module that can be stored in a memory in the form of software or firmware or solidified in the operating system of the device 400. Specifically:

[0087] See also Figure 4 As shown, the apparatus 400 is applied to the first device of the link equal length design system, and includes: an initialization module 401 and a dynamic update module 402. Among them:

[0088] Initialization module 401 is used to obtain first delay information of a first target device that needs to be equal in length at the system level in a package signal design file, and synchronize the first delay information into a PCB main body signal design file; and obtain second delay information of a second target device that needs to be equal in length at the system level in the PCB main body signal design file, and synchronize the second delay information into the package signal design file; wherein the first target device and the second target device are two devices that can be connected by pins to form a system-level link that needs to be equal in length;

[0089] The dynamic update module 402 is used to obtain the current first delay information of the first target device according to a set time interval, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, update the first delay information in the PCB main signal design file to the current first delay information; and obtain the current second delay information of the second target device in the PCB main signal design file according to the set time interval, and when the current second delay information is different from the second delay information recorded in the package signal design file, update the second delay information in the package signal design file to the current second delay information.

[0090] Among them, the package signal design side and the PCB main signal design side can design the length of the link connected to each pin of the first target device according to the second delay information recorded in the package signal design file, and / or design the length of the link connected to each pin of the second target device according to the first delay information recorded in the PCB main signal design file, so that the system-level link formed by the pin connection of the first target device and the second target device is of equal length.

[0091] In a feasible implementation manner of an embodiment of the present application, the initialization module 401 is specifically used to: obtain link information of the link connected to all pins of the first target device in the package signal design file, and calculate the first delay information based on the link information; and obtain link information of the link connected to all pins of the second target device in the PCB main body signal design file, and calculate the second delay information based on the link information.

[0092] The dynamic update module 402 is specifically used to: obtain the current link information of the link connected to all pins of the first target device in the package signal design file according to the set time interval, and calculate the current first delay information based on the current link information; and obtain the current link information of the link connected to all pins of the second target device in the PCB main signal design file according to the set time interval, and calculate the current second delay information based on the current latest link information.

[0093] The link information includes: the line length of the link in each wiring layer, the thickness and relative dielectric constant of each stacked layer through which the link passes.

[0094] In a feasible implementation of the embodiment of the present application, the device 400 may also include a matching module, which is used to obtain the first delay information of the first target device that needs to be system-level equal length in the package signal design file in the initialization module 401, and, before obtaining the second delay information of the second target device that needs to be system-level equal length in the PCB main signal design file, obtain the first pin information of the first target device in the package signal design file, and obtain the second pin information of the second target device in the PCB main signal design file to determine that the first pin information matches the second pin information.

[0095] In an optional embodiment of this feasible implementation method, the matching module is specifically used to: determine whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, and determine whether the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information; when the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, determine that the first pin information matches the second pin information.

[0096] In another optional embodiment of this feasible implementation method, the matching module is specifically used to: determine the position of each pin in the first pin information and each pin in the second pin information in the same way; after the position is determined, when the positions of each pin in the first pin information and each pin in the second pin information correspond one-to-one, determine that the first pin information matches the second pin information.

[0097] In this optional embodiment, the matching module is specifically used to: determine the position coordinates of each pin in the first pin information with the center of the first target device as the origin; determine the position coordinates of each pin in the second pin information with the center of the second target device as the origin.

[0098] In another optional embodiment of this feasible implementation mode, the matching module is specifically used to: determine whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, and determine whether the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, and determine the position of each pin in the first pin information and each pin in the second pin information in the same way; when the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, and the positions of each pin in the first pin information and each pin in the second pin information correspond one-to-one, determine that the first pin information matches the second pin information.

[0099] In a feasible implementation of the embodiment of the present application, the device 400 may also include a delay information expression type determination module, which is used to obtain the first delay information of the first target device that needs to be system-level equal length in the package signal design file in the initialization module 401, and before obtaining the second delay information of the second target device that needs to be system-level equal length in the PCB main signal design file, obtain the selected delay information expression type; the delay information expression type includes a duration type and a length type; correspondingly, the first delay information, the second delay information, the current first delay information, and the current second delay information are represented by the delay information expression type.

[0100] In a feasible implementation of the embodiment of the present application, the link equal length design system further includes a second device running the package signal design file and a third device running the PCB main body signal design file; the first device is respectively communicated with the second device and the third device; the dynamic update module 402 is specifically used for:

[0101] Receiving, by the first device, the current link information of the link connected to all the pins of the first target device in the package signal design file transmitted by the second device at a set time interval, and calculating the current first delay information according to the current link information of the link, and sending the current first delay information to the second device when the current first delay information is different from the first delay information recorded in the PCB main signal design file, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information;

[0102] After calculating the current first delay information according to the current link information of the link, receiving the current link information of the link connected to all the pins in the second target device in the PCB main body signal design file from the third device at a set time interval, and calculating the current second delay information according to the current link information of the link, and when the current second delay information is different from the second delay information recorded in the package signal design file, sending the current second delay information to the third device, so that the third device updates the second delay information in the package signal design file to the current second delay information;

[0103] After calculating the current second delay information based on the current link information of the link, the current link information of the link connected to all pins in the first target device in the package signal design file is received from the second device again at a set time interval through the first device, and the current first delay information is calculated based on the current link information of the link, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, the current first delay information is sent to the second device, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information.

[0104] In a feasible implementation of the embodiment of the present application, designing the length of the link connected to each pin of the first target device according to the second delay information recorded in the package signal design file, and designing the length of the link connected to each pin of the second target device according to the first delay information recorded in the PCB body signal design file, so that the system-level link formed by the first target device and the second target device through pin connection is equal in length may include:

[0105] According to the current second delay information recorded in the package signal design file, the links connected to the pins of the first target device are designed to be equal in length; according to the current first delay information recorded in the PCB main signal design file, the links connected to the pins of the second target device are designed to be equal in length.

[0106] It should be understood that, for the sake of brevity, some of the contents described in the method embodiments will not be repeated in the device embodiments.

[0107] An embodiment of the present application also provides an electronic device, including a PCB and a chip arranged on the PCB.

[0108] In the embodiment of the present application, the electronic device may be a package substrate, or a board or other device including a package substrate. Therefore, the structure of the electronic device may also refer to Figure 2 The structure of the package substrate shown in FIG. Among them, the chip arranged on the PCB is a chip obtained by packaging DIE, including Figure 2 The DIE, Bump, substrate and BGA Ball in the chip. In actual applications, the chip can also be packaged by LGA or other methods. In this case, there is no BGA Ball but LGA solder joints.

[0109] In the embodiment of the present application, other components besides the chip may be arranged on the PCB.

[0110] In an embodiment of the present application, the chip of the electronic device includes a first target device that needs to be equal in length at the system level, and the PCB includes a second target device that needs to be equal in length at the system level. The pins of the first target device and the second target device are interconnected, and the system-level link formed after the pins of the first target device and the second target device are interconnected is equal in length, and the length of the system-level link is designed according to the link equal length design method provided in the embodiment of the present application.

[0111] In an embodiment of the present application, an electronic device is also provided, which may include the aforementioned electronic device.

[0112] In an embodiment of the present application, the electronic device may include other devices in addition to the aforementioned electronic devices, for example, it may also include an external communication interface, such as a USB (Universal Serial Bus) interface, a CAN (Controller Area Network) bus interface, etc.; for another example, it may also have information display components such as a display screen, but this is not a limitation.

[0113] In the embodiment of the present application, another electronic device is also provided. Figure 5As shown, it may include a processor 501, a memory 502 and a communication module 503; the communication module 503 is used to communicate with an external device; the processor is used to execute one or more programs stored in the memory to implement the above-mentioned link equal length design method.

[0114] It can be understood that the processor 501 can be a processor core or a processor chip, or other circuits that can be configured and run by programs. The memory 502 can be a RAM (Random Access Memory), a ROM (Read-Only Memory), a flash memory, etc., but it is not limited thereto. The communication module 503 can be a module that can realize communication connection with external devices, such as a USB interface, a CAN bus interface, a Bluetooth module, etc.

[0115] It is understandable. Figure 5 The structure shown is for illustration only. The electronic device may also include Figure 5 For example, there may be an internal communication bus for realizing communication between the processor 501, the memory 502, and the communication module 503; for another example, there may be an information display component such as a display screen, but this is not a limitation.

[0116] In the embodiments of the present application, the two electronic devices provided above may be servers or intelligent terminals, such as smart phones, hosts, etc.

[0117] Based on the same inventive concept, this embodiment also provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more programs for implementing the above steps are stored, and the one or more programs can be executed by one or more processors to implement the above link equal length design method. No further details will be given here.

[0118] To facilitate understanding of the solution of the embodiment of the present application, an exemplary explanation is given below by taking the case where both the software for package signal design and PCB main body signal design are EDA (Electronic design automation) software as an example.

[0119] In this embodiment, the following programs are designed: A program, an independent program. B_pkg program, embedded in the EDA software for package signal design. B_pcb program, embedded in the EDA software for PCB main body signal design. A program is designed as a windowable program, and its main functions are: visualizing the connection status between the package design file and the PCB main body signal design; setting delay parameters (such as delay information expression type); performing delay information calculation in the background; performing delay information storage in the background; performing data transmission and reception between the B_pkg program and the B_pcb program in the background, etc. The B_pkg program and the B_pcb program are background programs, and their main functions are: obtaining link information in the design file; obtaining material parameters in the design file (such as the thickness and relative dielectric constant of each laminate); performing data transmission and reception with the A program; modifying the database data of the design file, etc.

[0120] The specific implementation process is as follows:

[0121] Step 1: Open the package design file in the EDA software, select the package connection command in the B_pkg program to start the connection tool, select the first target device (such as BGA Ball) that needs to be combined with equal-length signals, and then immediately start the B_pkg data interaction program in the background and send a connection request to the A program to request a connection. After receiving the request, the A program determines whether there is already a PKG connection in the A program (that is, whether there are other package design files that have been connected). If so, it sends data to B_pkg to reject the connection. After receiving the data, B_pkg prints information to inform the designer that there is already a PKG connection and the request fails; if not, the A program establishes a communication connection with B_pkg to facilitate subsequent data transmission, and then B_pkg obtains the information of all pins (pins) of the first target device (that is, the number of pins, identification information, relative position, etc.) and transmits it to A. After receiving the pin information, A saves the information. After the connection is successful, the A window automatically pops up and displays the name of the package design file and its connection status.

[0122] Step 2: Open the PCB main signal design file in the EDA software, select the PCB connection command in the B_pcb program to start the connection tool, select the second target device (such as BGA Ball) that needs to be combined with equal-length signals, and then immediately start the B_pcb data interaction program in the background and send a connection request to the A program to request a connection. After receiving the request, the A program determines whether there is already a PCB connection in the A program (that is, whether there are other PCB main signal design files that have been connected). If so, it sends data to B_pcb to reject the connection. After receiving the data, B_pcb prints information to inform the designer that there is already a PCB connection and the request fails; if not, B_pcb obtains the information of all pins of the second target device (that is, the number of pins, identification information, relative position, etc.) and transmits it to A.

[0123] Step 3: A's background program matches the pin information obtained in step 1 with the pin information obtained in step 2. If the match fails, the connection is not made, and A transmits data to B_pcb to reject the connection. B_pcb prints information to inform the designer that the device does not match the connection failure. If the match is successful, A establishes a connection with B_pcb and saves the pin information of B_pcb. After the connection is successful, A automatically pops up a window and displays the name of the PCB main signal design file and its connection status.

[0124] The matching method is as described above and will not be described again here.

[0125] Step 4: Select delay type (delay information expression type) in the window of A. You can select time or length. The units of the package design file and the pcb main signal design file have been obtained from the database in steps 1 and 2 and have been displayed in the window of A. Therefore, the engineer can select the delay type, or directly select the default value (such as time), or automatically select the unit based on the units obtained in steps 1 and 2. Subsequent data interaction is processed by the background program of A program, B_pkg, and B_pcb. After the data interaction, the background program directly modifies the database of the design file, which will not affect the normal use of the design software. After the selection is completed, data synchronization begins.

[0126] Step 5: Delay initialization is performed in the background. The detailed process is as follows: ①A program sends instructions to B_pkg to obtain the line length of the signal link connected to all pins of the first target device selected in step 1 in each wiring layer, the thickness and relative dielectric constant of each stack of the package signal design file (the relative dielectric constant of the stack is generally set by the designer in EDA), and then B_pkg transmits the obtained data to A. A's background program calculates the package delay into data of the PCB specified unit (time or length) based on the above data and the delaytype specified in the A window, and then A stores the delay and transmits it to B_pcb. After receiving the delay information, B_pcb modifies the database information of the PCB main signal design file and adds all package delays to the database. ②A program sends instructions to B_pcb to obtain the line length of the signal link connected to all pins of the device selected in step 2 in each wiring layer, the thickness and relative dielectric constant of each stack of the design file (the relative dielectric constant of the stack is generally set by the designer in EDA), and then B_pcb transmits the obtained data to A. A's background program uses the above data and the delay type specified in the A window to calculate the delay of the pcb into data (time or length) of the package specified unit, and then A stores the delay and transmits it to B_pkg. After receiving the delay data, B_pkg modifies the database information of the package signal design file and adds all pcb delays to the database; ③ At this point, the delays of the package and PCB design files are the delays after the integration of the package and PCB levels, and the initialization is completed.

[0127] At this time, in the package signal design file, the total delay of a signal is equal to the link delay inside the package signal design file plus the signal link delay in the PCB. In the PCB body signal design file, the total delay of a signal is equal to the signal link delay inside the PCB body signal design file plus the package signal link delay. When equal length is performed, the EDA software can automatically calculate and display the total delay.

[0128] In this embodiment, the calculation of delay can be completed by the background of A, thereby reducing the pressure on the EDA design software and avoiding interference with the normal operation of the software.

[0129] Step 6: After initialization, program A has stored the delay information of the package signal design side and the delay information of the pcb main body signal design side in its own database. After that, program A will send data packet requests to B_pkg and B_pcb at regular intervals (such as 0.1 seconds), so that B_pkg and B_pcb programs will send the latest link information of the package signal design file and the pcb main body signal design file (the same as in step 5) to A. After that, ① after receiving the data from B_pkg, program A will convert the latest link information into the current delay, and then compare it with the delay data on the package signal design side in the self-built database of program A. If the delay has changed, the changed data will be filtered out, and then the delay information of the self-built database will be updated and the current delay will be transmitted to B_pcb, which will update the delay on the package signal design side in the database of the PCB main signal design file; ② after receiving the link information from B_pcb, program A will convert the latest design file data into the current delay, and then compare it with the delay data on the pcb main signal design side in the self-built database of program A. If the delay has changed, the changed data will be filtered out, and then the delay information of the self-built database will be updated and the current delay will be transmitted to B_pkg, which will update the delay on the pcb main signal design side in the database of the package design file. If the data has not changed, no modification or update will be made.

[0130] It can be understood that the above update process can refer to Figure 3 The method shown is continuously cycled to prevent transmission congestion.

[0131] Step 7: Based on the above steps, you can select signal links in the package signal design file and the PCB body signal design file for equal length design.

[0132] The design method can be to perform equal length design based on the signal link with the longest total delay.

[0133] The scheme and method of the embodiment of the present application directly interconnect the transmission line equal length information of the EDA design software commonly used in the package signal design and the PCB main body signal design, and realize the modification of the transmission line length of either party in the design file of the two parties. The data in the design file of the other party will be automatically updated, making the full-link equal length design process from bump to device simple, eliminating frequent data and personnel interactions, improving work efficiency, and accelerating the design process.

[0134] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0135] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0136] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0137] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0138] As used herein, a plurality refers to two or more than two.

[0139] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for designing equal link lengths, characterized in that: Applied to a link equal length design system, the link equal length design system includes a first device, and the method includes: Acquire, through the first device, first delay information of a first target device that needs to be equal in length at the system level in the package signal design file, and synchronize the first delay information into the PCB main signal design file; and acquire, through the first device, second delay information of a second target device that needs to be equal in length at the system level in the PCB main signal design file, and synchronize the second delay information into the package signal design file; wherein, the first target device and the second target device are two devices that can be connected by pins to form a system-level link that needs to be equal in length; The first device obtains the current first delay information of the first target device at a set time interval, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, the first delay information in the PCB main signal design file is updated to the current first delay information; and the first device obtains the current second delay information of the second target device at a set time interval, and when the current second delay information is different from the second delay information recorded in the package signal design file, the second delay information in the package signal design file is updated to the current second delay information, so as to design the length of the link connected to each pin of the first target device according to the second delay information recorded in the package signal design file, and / or, design the length of the link connected to each pin of the second target device according to the first delay information recorded in the PCB main signal design file, so that the system-level link formed by the pin connection of the first target device and the second target device is of equal length.

2. The link equal length design method according to claim 1, characterized in that: The obtaining of the first delay information of the first target device that needs to be system-level equal length in the package signal design file includes: obtaining link information of the link connected to all pins of the first target device in the package signal design file, and calculating the first delay information according to the link information; The obtaining of the second delay information of the second target device that needs to be system-level equal length in the PCB main body signal design file includes: obtaining link information of the link connected to all pins of the second target device in the PCB main body signal design file, and calculating the second delay information according to the link information; The obtaining the current first delay information of the first target device at the set time interval includes: obtaining the current link information of the link connected to all the pins of the first target device in the package signal design file, and calculating the current first delay information according to the current link information; The obtaining the current second delay information of the second target device at the set time interval includes: obtaining the current link information of the link connected to all the pins of the second target device in the PCB main signal design file, and calculating the current second delay information according to the current latest link information; The link information includes: the line length of the link in each wiring layer, the thickness and relative dielectric constant of each stacked layer through which the link passes.

3. The link equal length design method according to claim 1, characterized in that: Before obtaining first delay information of a first target device that needs to be equalized at the system level in the package signal design file, and obtaining second delay information of a second target device that needs to be equalized at the system level in the PCB main body signal design file, the method further includes: Acquire the first pin information of the first target device in the package signal design file, and acquire the second pin information of the second target device in the PCB main body signal design file; Determine whether the first pin information matches the second pin information.

4. The link equal length design method as claimed in claim 3, characterized in that: Determining that the first pin information matches the second pin information includes: Determine whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, and determine whether the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information; When the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, it is determined that the first pin information matches the second pin information.

5. The link equal length design method as claimed in claim 3, characterized in that: Determining that the first pin information matches the second pin information includes: Determine the position of each pin in the first pin information and each pin in the second pin information in the same manner; When the positions of the pins in the first pin information and the positions of the pins in the second pin information correspond one to one after the positions are determined, it is determined that the first pin information matches the second pin information.

6. The link equal length design method as claimed in claim 5, characterized in that: Determining the position of each pin in the first pin information and each pin in the second pin information in the same manner includes: Determine the position coordinates of each pin in the first pin information with the center of the first target device as the origin; The position coordinates of each pin in the second pin information are determined with the center of the second target device as the origin.

7. The link equal length design method as claimed in claim 3, characterized in that: Determining that the first pin information matches the second pin information includes: Determine whether the number of pins in the first pin information is consistent with the number of pins in the second pin information, determine whether the identification information of each pin in the first pin information corresponds to the identification information of each pin in the second pin information, and determine the position of each pin in the first pin information and each pin in the second pin information in the same manner; When the number of pins in the first pin information is consistent with the number of pins in the second pin information, and the identification information of each pin in the first pin information corresponds one-to-one with the identification information of each pin in the second pin information, and the position of each pin in the first pin information and each pin in the second pin information corresponds one-to-one, it is determined that the first pin information matches the second pin information.

8. The link equal length design method according to claim 1, characterized in that: Before obtaining the first delay information of the first target device that needs to be equalized at the system level in the package signal design file, and obtaining the second delay information of the second target device that needs to be equalized at the system level in the PCB main body signal design file, the method further includes: obtaining a selected delay information expression type; the delay information expression type includes a duration type and a length type; Correspondingly, the first delay information, the second delay information, the current first delay information, and the current second delay information are represented using the delay information expression type.

9. The link equal length design method according to any one of claims 1 to 8, characterized in that: The link equal length design system also includes a second device running the package signal design file and a third device running the PCB main body signal design file; the first device is respectively connected to the second device and the third device for communication; Acquire the current first delay information of the first target device at a set time interval through the first device, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, update the first delay information in the PCB main signal design file to the current first delay information; And, obtaining the current second delay information of the second target device according to the set time interval through the first device, and when the current second delay information is different from the second delay information recorded in the package signal design file, updating the second delay information in the package signal design file to the current second delay information, including: Receiving, by the first device, the current link information of the link connected to all the pins of the first target device in the package signal design file transmitted by the second device at a set time interval, and calculating the current first delay information according to the current link information of the link, and sending the current first delay information to the second device when the current first delay information is different from the first delay information recorded in the PCB main signal design file, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information; After calculating the current first delay information according to the current link information of the link, receiving the current link information of the link connected to all the pins in the second target device in the PCB main body signal design file from the third device at a set time interval, and calculating the current second delay information according to the current link information of the link, and when the current second delay information is different from the second delay information recorded in the package signal design file, sending the current second delay information to the third device, so that the third device updates the second delay information in the package signal design file to the current second delay information; After calculating the current second delay information based on the current link information of the link, the current link information of the link connected to all pins in the first target device in the package signal design file is received from the second device again at a set time interval through the first device, and the current first delay information is calculated based on the current link information of the link, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, the current first delay information is sent to the second device, so that the second device updates the first delay information in the PCB main signal design file to the current first delay information.

10. The link equal length design method according to any one of claims 1 to 8, characterized in that: The method further comprises: designing the length of a link connected to each pin of the first target device according to the second delay information recorded in the package signal design file; and designing the length of a link connected to each pin of the second target device according to the first delay information recorded in the PCB main body signal design file, so that the system-level link formed by the first target device and the second target device through pin connection is of equal length, including: According to the current second delay information recorded in the package signal design file, the links connected to the pins of the first target device are designed to be equal in length; According to the current first delay information recorded in the PCB main body signal design file, the links connected to the pins of the second target device are designed to be equal in length.

11. A link equal length design device, characterized in that: The first device used in the link equal length design system includes: An initialization module is used to obtain first delay information of a first target device that needs to be equal in length at the system level in a package signal design file, and synchronize the first delay information into a PCB main signal design file; and obtain second delay information of a second target device that needs to be equal in length at the system level in the PCB main signal design file, and synchronize the second delay information into the package signal design file; wherein the first target device and the second target device are two devices that can be connected by pins to form a system-level link that needs to be equal in length; A dynamic update module is used to obtain the current first delay information of the first target device at a set time interval, and when the current first delay information is different from the first delay information recorded in the PCB main signal design file, update the first delay information in the PCB main signal design file to the current first delay information; and obtain the current second delay information of the second target device in the PCB main signal design file at a set time interval, and when the current second delay information is different from the second delay information recorded in the package signal design file, update the second delay information in the package signal design file to the current second delay information, so as to design the length of the link connected to each pin of the first target device according to the second delay information recorded in the package signal design file, and / or, design the length of the link connected to each pin of the second target device according to the first delay information recorded in the PCB main signal design file, so that the system-level link formed by the pin connection of the first target device and the second target device is equal in length.

12. An electronic device, characterized in that: It comprises a printed circuit board and a chip arranged on the printed circuit board; the chip comprises a first target device that needs to be equal in length at the system level, and the printed circuit board comprises a second target device that needs to be equal in length at the system level; wherein the pins of the first target device and the second target device are interconnected, and the system-level links formed after the pins of the first target device and the second target device are interconnected are of equal length, and the length of the system-level link is designed according to the link equal length design method described in any one of claims 1-10.

13. An electronic device, characterized in that: include: A processor, a memory and a communication module; the communication module is used to communicate with an external device; The processor is used to execute one or more programs stored in the memory to implement the link equal length design method as described in any one of claims 1-10.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the link equal length design method as described in any one of claims 1-10.

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