Display panel, driving method and display device

Abstract

The invention discloses a display panel, a driving method and a display device, and relates to the technical field of display. A first clock signal line; a second clock signal line; the scanning driving circuits are electrically connected with the corresponding row of pixel circuits, and each scanning driving circuit comprises a starting unit, an output unit, a charging unit, a clamping unit, a first control node, a second control node and an output node; the starting unit is electrically connected with the first control node; the output unit is electrically connected with the first control node and the output node, the output node is electrically connected with the pixel circuit, the charging unit is electrically connected with the second control node, the clamping unit is electrically connected with the second control node and the output node, and the clamping unit is electrically connected with the pixel circuit. Therefore, the control of the GOA driving circuit on driving output in the process of scanning multiple rows of pixel circuits can be improved, and then the display stability of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a driving method and a display device. Background Art

[0002] In existing display panels, GOA (Gate Driven on Array) technology is often used. By setting a cascaded GOA driving circuit, the driving signal can be adjusted to control the forward scanning and reverse scanning of the pixel circuit row. However, according to the current GOA cascade circuit, it is difficult to control the driving output, which easily causes the output fluctuation of the scanning driving circuit, thereby affecting the display stability of the display panel. Summary of the invention

[0003] The embodiments of the present application provide a display panel, a driving method and a display device, which can improve the control of the GOA driving circuit over the driving output during the scanning process of multiple rows of pixel circuits, thereby improving the display stability of the display panel.

[0004] A first aspect of an embodiment of the present application provides a display panel, including:

[0005] Multiple rows of pixel circuits;

[0006] A first clock signal line;

[0007] a second clock signal line, wherein a first clock signal transmitted by the first clock signal line has a different timing from a second clock signal transmitted by the second clock signal line;

[0008] A plurality of scan driving circuits, each of which is electrically connected to a corresponding row of pixel circuits, and each of which comprises a start-up unit, an output unit, a charging unit, a clamping unit, a first control node, a second control node, and an output node;

[0009] The start-up unit is electrically connected to the first control node, and is used to receive a forward scan start-up signal or a reverse scan start-up signal to adjust the potential of the first control node;

[0010] One of the scan drive circuits corresponding to the pixel circuits in two adjacent rows is a first scan drive circuit, and the other is a second scan drive circuit, the output unit of the first scan drive circuit is electrically connected to the first clock signal line, the charging unit of the first scan drive circuit is electrically connected to the second clock signal line, the output unit of the second scan drive circuit is electrically connected to the second clock signal line, and the charging unit of the second scan drive circuit is electrically connected to the first clock signal line;

[0011] The output unit is electrically connected to the first control node and the output node respectively, the output node is electrically connected to the pixel circuit, the charging unit is electrically connected to the second control node, the charging unit is used to adjust the potential of the second control node based on the first clock signal or the second clock signal, and the clamping unit is electrically connected to the second control node and the output node respectively.

[0012] In some embodiments, the charging unit is used to transmit the first voltage signal to the second control node under the control of the first clock signal or the second clock signal;

[0013] The clamping unit is used to transmit the second voltage signal to the output node under the potential control of the first control node;

[0014] When the first voltage signal is at a low level, the second voltage signal is at a high level; when the first voltage signal is at a high level, the second voltage signal is at a low level; both the first voltage signal and the second voltage signal are constant voltage signals.

[0015] In some implementations, the scan driving circuit further includes:

[0016] a first control unit, the first control unit being electrically connected to the first control node and the second control node respectively;

[0017] The first control unit is used to receive a third clock signal, and the first control unit is used to transmit the third clock signal to the second control node under the potential control of the first control node.

[0018] In some implementations, the scan driving circuit further includes:

[0019] a second control unit, the second control unit being electrically connected to the first control node and the second control node respectively;

[0020] The second control unit is used to receive a fourth clock signal, and the second control unit is used to transmit the second voltage signal to the first control node under the control of the fourth clock signal and the potential of the second control node.

[0021] In some implementations, the scan driving circuit further includes:

[0022] A reset unit, the reset unit is electrically connected to the first control node, and the reset unit is used to transmit the second voltage signal to the first control node under the control of the reset signal.

[0023] In some implementations, the scan driving circuit further includes:

[0024] A first isolation unit is provided between the start unit and the first control node, and the first isolation unit is used to maintain the potential of the first control node under the control of the first clock signal or the second clock signal;

[0025] and / or,

[0026] The second isolation unit is disposed between the start-up unit and the first control node, and is used for maintaining the potential of the first control node under the control of the first voltage signal and the potential of the first control node.

[0027] In some embodiments, the output node of the scan driving circuit is electrically connected to the start-up unit of the scan driving circuit of the adjacent previous level, and the output node is used to transmit the reverse scan start-up signal to the start-up unit of the scan driving circuit of the adjacent previous level;

[0028] The output node of the scan driving circuit is electrically connected to the start-up unit of the next adjacent scan driving circuit, and the output node is used to transmit the positive scan start-up signal to the start-up unit of the next adjacent scan driving circuit.

[0029] In some embodiments, when the output unit is electrically connected to the first clock signal line, the third clock signal is the same as the second clock signal;

[0030] In a case where the output unit is electrically connected to the second clock signal line, the third clock signal is the same as the first clock signal.

[0031] In some embodiments, when the charging unit is electrically connected to the first clock signal line, the fourth clock signal is the same as the second clock signal;

[0032] In a case where the charging unit is electrically connected to the second clock signal line, the fourth clock signal is the same as the first clock signal.

[0033] In some embodiments, the charging unit includes a first transistor, a gate of the first transistor is electrically connected to the first clock signal line or the second clock signal line, and a source or a drain of the first transistor is used to receive the first voltage signal;

[0034] and / or,

[0035] The clamping unit includes a second transistor and a capacitor, the gate of the second transistor is electrically connected to the second control node, the source or drain of the second transistor is used to receive the second voltage signal, one end of the capacitor is electrically connected to the gate of the second transistor, and the other end of the capacitor is used to receive the second voltage signal.

[0036] In some embodiments, the low level pulse width of the second clock signal is within the time period of the high level pulse width of the first clock signal, and the low level pulse width of the first clock signal is within the time period of the high level pulse width of the second clock signal;

[0037] or,

[0038] The high level pulse width of the second clock signal is within the time period of the low level pulse width of the first clock signal, and the high level pulse width of the first clock signal is within the time period of the low level pulse width of the second clock signal.

[0039] A second aspect of an embodiment of the present application provides a method for driving a display panel, which is applied to the display panel according to any one of the first aspects, and the driving method includes:

[0040] transmitting the forward scanning start signal to the start unit to drive the plurality of rows of pixel circuits to perform forward scanning, wherein, during the forward scanning process, the start unit adjusts the potential of the first control node according to the forward scanning start signal, and the output unit is turned on under the control of the potential of the first control node; or

[0041] Transmitting the reverse scan start signal to the start unit to drive the plurality of rows of pixel circuits to perform reverse scan, wherein during the reverse scan, the start unit adjusts the potential of the first control node according to the reverse scan start signal, and the output unit is turned on under the control of the potential of the first control node;

[0042] The first clock signal is transmitted to the first clock signal line, and the second clock signal is transmitted to the second clock signal line, so that the output unit transmits the first clock signal or the second clock signal to the output node.

[0043] In some embodiments, the driving method further comprises:

[0044] transmitting a first voltage signal to the charging unit, so that the charging unit transmits the first voltage signal to the second control node under the control of the first clock signal or the second clock signal;

[0045] transmitting a second voltage signal to the clamping unit, so that the clamping unit transmits the second voltage signal to the output node under the potential control of the second control node;

[0046] When the first voltage signal is at a low level, the second voltage signal is at a high level; when the first voltage signal is at a high level, the second voltage signal is at a low level; both the first voltage signal and the second voltage signal are constant voltage signals.

[0047] In some embodiments, the driving method further comprises:

[0048] During the forward scanning process, transmitting the reverse scanning start signal to the start unit, so that the start unit transmits a third voltage signal to the first control node under the control of the reverse scanning start signal;

[0049] During the reverse scanning process, transmitting the forward scanning start signal to the start unit, so that the start unit transmits a fourth voltage signal to the first control node under the control of the forward scanning start signal;

[0050] Wherein, when the third voltage signal is at a low level, the fourth voltage signal is at a high level, and when the third voltage signal is at a high level, the fourth voltage signal is at a low level.

[0051] In some implementations, when the display panel includes a first control unit, and the first control unit is electrically connected to the first control node and the second control node respectively, the driving method further includes:

[0052] A third clock signal is transmitted to the first control unit, so that the first control unit transmits the third clock signal to the second control node under the potential control of the first control node.

[0053] In some implementations, when the display panel includes a second control unit, and the second control unit is electrically connected to the first control node and the second control node respectively, the driving method further includes:

[0054] The fourth clock signal and the second voltage signal are transmitted to the second control unit, so that the second control unit transmits the second voltage signal to the first control node under the control of the potential of the second control node and the fourth clock signal.

[0055] In some embodiments, when the number of rows of the scan driving circuit is an even number and two adjacent frames of display images correspond to the forward scan and the reverse scan, respectively, the clock signal transmission settings of the first clock signal line corresponding to the two adjacent frames of the display images are exchanged, and the clock signal transmission settings of the second clock signal line corresponding to the two adjacent frames of the display images are exchanged.

[0056] A third aspect of an embodiment of the present application provides a display device, comprising a display panel as described in any one of the first aspects.

[0057] In summary, a display panel provided by an embodiment of the present application includes: a plurality of rows of pixel circuits; a first clock signal line; a second clock signal line, wherein the first clock signal transmitted by the first clock signal line has a different timing from the second clock signal transmitted by the second clock signal line; a plurality of scan drive circuits, wherein the scan drive circuit is electrically connected to a corresponding row of pixel circuits, and the scan drive circuit includes a start unit, an output unit, a charging unit, a clamping unit, a first control node, a second control node, and an output node; the start unit is electrically connected to the first control node, and the start unit is used to receive a forward scan start signal or a reverse scan start signal to adjust the potential of the first control node; one of the scan drive circuits corresponding to two adjacent rows of pixel circuits One is a first scanning driving circuit, and the other is a second scanning driving circuit, the output unit of the first scanning driving circuit is electrically connected to the first clock signal line, the charging unit of the first scanning driving circuit is electrically connected to the second clock signal line, the output unit of the second scanning driving circuit is electrically connected to the second clock signal line, and the charging unit of the second scanning driving circuit is electrically connected to the first clock signal line; the output unit is electrically connected to the first control node and the output node respectively, the output node is electrically connected to the pixel circuit, the charging unit is electrically connected to the second control node, the charging unit is used to adjust the potential of the second control node based on the first clock signal or the second clock signal, and the clamping unit is electrically connected to the second control node and the output node respectively. The output unit and the charging unit in each scanning driving circuit are electrically connected to one of the first clock signal line and the second clock signal line respectively, the output units and charging units of adjacent rows are connected to different clock signal lines, and the output unit in each scanning driving circuit is electrically connected to each row of pixel circuits. The start unit adjusts the potential of the first control node based on the received forward scan start signal or reverse scan start signal, and the output unit outputs the first clock signal or the second clock signal to the output node under the potential control of the first control node, so that the forward scan or reverse scan of the multiple rows of pixel circuits can be realized only by changing the timing of the drive signal. The charging unit in each scan drive circuit is electrically connected to the clamping unit through the second control node. After the scan drive circuit performs forward or reverse scan on one of the rows, the output unit is closed under the action of the first control node, and the charging unit adjusts the potential of the second control node based on the clock signal, so that the clamping unit transmits a voltage signal to the output node to clamp the potential of the output node, so that the pixel circuit connected to the output node can be maintained in a reset state, and then the display stability of the display panel can be improved. In addition, by connecting one of the first clock signal line and the second clock signal line to the output unit as an output voltage, and the other to the charging unit as a control signal, a signal line can play different roles in different rows of the scan drive circuit, so that the number of signal lines in the display panel can be saved, and then the operation efficiency of the driver chip or processor can be improved.

[0058] Correspondingly, the display device and the display panel driving method provided in the embodiments of the present application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0060] Figure 1 A schematic structural block diagram of a display panel provided in an embodiment of the present application;

[0061] Figure 2 A schematic circuit diagram of a scan driving circuit provided in an embodiment of the present application;

[0062] Figure 3 A timing diagram of a scan driving circuit performing forward scanning provided in an embodiment of the present application;

[0063] Figure 4 A timing diagram of a scan driving circuit performing reverse scanning provided in an embodiment of the present application;

[0064] Figure 5 A schematic structural block diagram of another display panel provided in an embodiment of the present application;

[0065] Figure 6 A schematic structural block diagram of a scan driving circuit provided in an embodiment of the present application;

[0066] Figure 7 A timing diagram of another scan driving circuit performing forward scanning provided by an embodiment of the present application;

[0067] Figure 8 A schematic structural block diagram of another scan driving circuit provided in an embodiment of the present application;

[0068] Fig. 9 A timing diagram of another scan driving circuit performing forward scanning provided in an embodiment of the present application;

[0069] Fig.10 A schematic structural block diagram of another scan driving circuit provided in an embodiment of the present application;

[0070] Fig.11 A schematic structural block diagram of another scan driving circuit provided in an embodiment of the present application;

[0071] Fig.12 A schematic structural block diagram of another scan drive circuit provided in an embodiment of the present application;

[0072] Fig.13 A schematic structural block diagram of another scan drive circuit provided in an embodiment of the present application;

[0073] Fig.14 A schematic circuit diagram of another scan driving circuit provided in an embodiment of the present application;

[0074] Fig.15 A schematic structural block diagram of a scan drive circuit cascade provided in an embodiment of the present application;

[0075] Fig.16 A timing diagram of a forward scan performed by another scan driving circuit provided in an embodiment of the present application;

[0076] Fig.17 A timing diagram of another scan driving circuit performing reverse scanning provided in an embodiment of the present application;

[0077] Fig.18 A schematic flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0078] Fig.19 A diagram showing simulation results of a scan driving circuit provided in an embodiment of the present application performing forward scanning on a pixel circuit;

[0079] Fig. 20 A diagram showing simulation results of a scan driving circuit provided in an embodiment of the present application performing reverse scanning on a pixel circuit;

[0080] Fig.21 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0081] Among them, Figure 1 , Attachment Figure 2 , Attachment Figure 5 , Attachment Figure 6 , Attachment Figure 8 , Attachment Fig.10 , Attachment Fig.11 , Attachment Fig.12 , Attachment Fig.13 , Attachment Fig.14 , Attachment Fig.15 And attached Fig.21 The corresponding relationship between the component names and numbers is as follows:

[0082] 1000 display device;

[0083] 100 first clock signal line, 200 second clock signal line, 300 scanning driving circuit, 400 pixel circuit;

[0084] 301 startup unit, 302 output unit, 303 charging unit, 304 clamping unit, 305 first control node, 306 second control node, 307 output node, 308 first control unit, 309 second control unit, 310 reset unit, 311 first isolation unit, 312 second isolation unit. DETAILED DESCRIPTION

[0085] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0086] A first aspect of an embodiment of the present application provides a display panel, Figure 1 A schematic structural block diagram of a display panel provided in an embodiment of the present application, such as Figure 1 As shown, the display panel provided by the present application includes: multiple rows of pixel circuits 400; a first clock signal line 100; a second clock signal line 200, the first clock signal transmitted by the first clock signal line 100 and the second clock signal transmitted by the second clock signal line 200 have different timings; multiple scanning drive circuits 300, the scanning drive circuit 300 is electrically connected to a corresponding row of pixel circuits 400, and the scanning drive circuit 300 includes a start unit 301, an output unit 302, a charging unit 303, a clamping unit 304, a first control node 305, a second control node 306 and an output node 307.

[0087] refer to Figure 1, the start unit 301 is electrically connected to the first control node 305, and the start unit 301 is used to receive the forward scan start signal STV or the reverse scan start signal STD to adjust the potential of the first control node 305; one of the scan drive circuits 300 corresponding to the two adjacent rows of pixel circuits 400 is the first scan drive circuit 300, and the other is the second scan drive circuit 300, the output unit 302 of the first scan drive circuit 300 is electrically connected to the first clock signal line 100, the charging unit 303 of the first scan drive circuit 300 is electrically connected to the second clock signal line 200, and the second scan drive circuit 30 0 is electrically connected to the second clock signal line 200, and the charging unit 303 of the second scan driving circuit 300 is electrically connected to the first clock signal line 100; the output unit 302 is electrically connected to the first control node 305 and the output node 307 respectively, the output node 307 is electrically connected to the pixel circuit 400, the charging unit 303 is electrically connected to the second control node 306, the charging unit 303 is used to adjust the potential of the second control node 306 based on the first clock signal CB or the second clock signal CK, and the clamping unit 304 is electrically connected to the second control node 306 and the output node 307 respectively.

[0088] It should be noted that the display panel provided in the present application includes a first clock signal line 100, a second clock signal line 200, a plurality of scan drive circuits 300 and a plurality of rows of pixel circuits 400. The first clock signal line 100 and the second clock signal line 200 are connected to each scan drive circuit 300, and the scan drive circuit 300 is electrically connected to the pixel circuit 400 one-to-one. The timing of the first clock signal CB transmitted by the first clock signal line 100 and the second clock signal CK transmitted by the second clock signal line 200 are different. The scan drive circuit 300 includes a start unit 301, an output unit 302, a charging unit 303 and a clamping unit 304. The start unit 301 receives a forward scan start signal STV and a reverse scan start signal STD to realize forward scanning or reverse scanning of the display panel, and adjusts the potential of the first control node 305 based on the received start signal, such as Figure 1As shown, when the start unit 301 receives the forward scan start signal STV, it can transmit the CN signal to the first control node 305 to adjust the potential of the first control node 305. When the start unit 301 receives the reverse scan start signal STD, it can transmit the CNB signal to the first control node 305 to adjust the potential of the first control node 305, wherein both CN and CNB are constant voltage signals for adjusting the potential of the first control node 305, and in the forward scan stage or the reverse scan stage, the levels of CN and CNB are opposite. The output unit 302 is electrically connected to the pixel circuit 400 through the output node 307. At the same time, the output units 302 in the scan driving circuits 300 of adjacent rows receive different clock signals, such as the output unit 302 in the first row scan driving circuit 300 receives the first clock signal CB, the output unit 302 in the second row scan driving circuit 300 receives the second clock signal CK, and the output unit 302 in the third row scan driving circuit 300 receives the first clock signal, and so on. Under the potential control of the first control node 305, the output unit 302 can transmit the received clock signal to the output node 307 to scan the connected pixel circuit 400, and after the pixel circuit 400 is scanned, the output unit 302 can also be turned off under the potential control of the first control node 305, so that the clock signal will not be transmitted to the output node 307. By transmitting the forward scanning start signal STV or the reverse scanning start signal STD to the start unit 301, the start unit 301 can control the potential of the first control node 305 according to the different timings of the start signal, so that the output unit 302 of the scan start circuit of the current row can transmit the received clock signal, and then the forward and reverse scanning functions of the display panel can be realized by changing the timing of the start signal.

[0089] The charging unit 303 of each scan driving circuit 300 is electrically connected to the first clock signal line 100 or the second clock signal line 200, and the clock signal line connected to the charging unit 303 is different from the clock signal line connected to the output unit 302. The charging unit 303 controls the potential of the second node according to the received first clock signal CB or the second clock signal CK. The clamping unit 304 adjusts the potential of the output node 307 under the potential control of the second control node 306 to ensure the stability of the potential of the output node 307.

[0090] Each row of pixel circuits 400 will only be scanned once within the scanning time of a frame, and the scanning driving circuit 300 scans multiple rows of pixel circuits 400 in sequence. For one row of pixel circuits 400, after the scanning of the row of pixel circuits 400 is completed, when the next row of pixel circuits 400 is scanned, the row of pixel circuits 400 is in a reset state.

[0091] Since the clock signal received by the charging unit 303 is different from the clock signal received by the output unit 302, there is a situation where the output unit 302 receives a high level signal and the charging unit 303 receives a low level signal, or the output unit 302 receives a low level signal and the charging unit 303 receives a high level signal.

[0092] Taking the case where the scanning driving circuit 300 scans the pixel circuit 400 when the output node 307 is at a low level, and the pixel circuit 400 is in a reset state when the output node 307 is at a high level as an example, for a row of pixel circuits 400, when the output unit 302 transmits a low level signal to the output node 307, it is in a scanning state at this time, and the charging unit 303 can adjust the potential of the second control node 306 based on the received high level signal, so that the clamping unit 304 is closed and does not transmit a signal to the output node 307, thereby ensuring that the pixel circuit 400 is scanned normally. When the output unit 302 transmits a high level signal to the output node 307, the pixel circuit 400 is in a reset state at this time, and accordingly, the charging unit 303 can adjust the potential of the second control node 306 based on the received low level signal, and the clamping unit 304 transmits a voltage signal to the output node 307 to clamp the potential of the output node 307, so that the pixel circuit 400 connected to the output node 307 can be maintained in a reset state, which can improve the display stability of the display panel.

[0093] In addition, the charging unit 303 is controlled based on the second clock signal CK or the first clock signal CB, and the output unit 302 transmits the first clock signal CB or the second clock signal CK to the output node 307. Therefore, for a scan drive circuit, when one of the first clock signal line 100 and the second clock signal line 200 provides an output voltage to the output node 307, the other acts as a control signal, and the clock signal line acting as the control signal controls the charging unit 303 to adjust the potential of the second control node 306, and the potential of the second control node 306 can control the clamping unit 304 to clamp the potential of the output node 307. In the related art, the signal line that plays a control role and the signal line that acts as an output will not use the same signal line. The present application sets the first clock signal line 100 and the second clock signal line 200. When one of them is connected to the output unit 302, the other is connected to the charging unit 303, that is, each signal line plays a different role in different scan drive circuits 300, thereby saving the setting of the signal line in the display panel, thereby reducing the timing processing burden of the driver chip or processor in the display panel, and improving the operation efficiency.

[0094] For example, taking forward scanning as an example, Figure 2 A schematic circuit diagram of a scan drive circuit provided in an embodiment of the present application; Figure 1 and Figure 2 As shown, the start-up unit 301 includes a P-type transistor M1 and a P-type transistor M2, PU represents a first control node 305, PD represents a second control node 306, and OUT represents an output node 307. The gates of the transistors M1 and M2 receive STV and STD respectively, the sources of the transistors M1 and M2 receive CN and CNB respectively, and the drains of the transistors M1 and M2 are electrically connected to PU at the same time. The output unit 302 includes a P-type transistor M7 and a capacitor C1, the source of the transistor M7 is electrically connected to CB, and the drain of the transistor M7 is electrically connected to OUT. It should be noted that the respective functional units in the scan drive circuit 300 of adjacent rows are electrically connected to different clock signal lines. For example, if the output unit 302 in one row of the scan drive circuit 300 receives the first clock signal CB, the output unit 302 in the scan drive circuit 300 of the adjacent row receives the second clock signal CK, and the same is true for other unit modules or related circuit devices. The various specification drawings provided in this application only list one of the cases for indication.

[0095] Figure 3 A timing diagram of a scan driving circuit performing forward scanning provided in an embodiment of the present application can be applied to Figure 2 In the circuit diagram. Figure 1 , Figure 2 and Figure 3 As shown, taking the first row scanning driving circuit 300 in the plurality of scanning driving circuits 300 performing forward scanning as an example, in the P1 stage, STV is in a low level state, the transistor M1 is turned on, CN is at a constant low level, and the transistor M1 transmits CN to PU, so that the plate connected to the capacitor C1 and PU is negatively charged, and correspondingly, the other plate of the capacitor C1 is positively charged. At this time, it is equivalent to charging the capacitor C1, CB is in a high level state, the transistor M7 is turned on, and OUT outputs a high level, as shown in FIG. Figure 3 OUT <1> As shown, OUT <1> It indicates the output timing of the first row scanning driving circuit 300, therefore, the pixel circuit 400 electrically connected to the output node 307 is in a closed state.

[0096] In the P2 stage, this stage is to scan the pixel circuit 400. STV is at a high level, and the transistor M1 is turned off. At this time, due to the charging of the capacitor C1 in the P1 stage, PU is negatively charged, and the transistor M7 is turned on under the control of PU. CB passes through the transistor M7 to OUT. Since the capacitor C1 connects OUT and PU, and since OUT is at a high level in the P1 stage, and OUT suddenly changes from a high level to a low level, due to the bootstrap effect of the capacitor C1, the potential difference between the two ends of the capacitor C1 cannot change suddenly, and the potential of PU further decreases, and the |Vgs| of the transistor M7 is enlarged, so that CB can be amplified by the transistor M7 and output.

[0097] In the P3 phase, the pixel circuit 400 enters a reset state. STD is at a low level, the transistor M2 is turned on, and CNB is transmitted to PU. CNB is at a constant high level, and the PU voltage is set to a high level. The transistor M7 is turned off, and CB cannot be transmitted to OUT, and OUT is in a suspended state. Accordingly, the second row scanning driving circuit 300 executes the P2 phase, such as OUT <2> The second clock signal CK is at a low level, and the charging unit 303 adjusts the potential of PD based on the second clock signal CK, so that the clamping unit 304 clamps the potential of OUT to a high level state, so that the OUT output is stable at a high level state.

[0098] In the P4 phase, the pixel circuit 400 is kept in the reset state. STD and STV both maintain high level until the positive scanning phase ends, when STD outputs low level again. At this time, the scanning driving circuit 300 of the third row to the last row sequentially executes the P2, P3 and P4 phases, such as OUT <3> To OUT <n>shown.

[0099] Since the first signal transmission line and the second transmission signal line are connected to all row scanning driving circuits 300, and the output units 302 in the scanning driving circuits 300 of adjacent rows are connected to different transmission signal lines, the high and low level pulses between the first clock signal CB and the second clock signal CK correspond to each other in an alternating manner. When the first clock signal CB is in a high level state, the second clock signal CK is in a low level state. Although the transistor M7 is in the cut-off state under the action of PU, due to the P3 stage, the plate connected to PU of the capacitor C1 is positively charged, and the corresponding plate connected to OUT is negatively charged. However, due to the large potential difference between the source and the drain of the transistor M7, there is a possibility that the transistor M7 is broken down by the first clock signal CB. Therefore, under the action of the second clock signal CK, the charging unit 303 adjusts PD so that the clamping unit 304 pulls up the potential of OUT, thereby ensuring that the potential difference between the source and the drain of the transistor M7 is not too large to prevent the transistor M7 from being broken down, and can further stabilize the OUT output at a high level, so as to improve the control of the drive signal of the scan drive circuit 300 in the forward scanning stage, thereby ensuring the stability of the output of the pixel circuit 400, and then improving the display stability of the display panel.

[0100] Take reverse scanning as an example to illustrate this application. Figure 4 A timing diagram of a scan driving circuit performing reverse scanning provided in an embodiment of the present application can be applied to Figure 2 In the circuit diagram. Figure 4 As shown, OUT <n>Represents the last row of scanning drive circuit 300, OUT <n-1>and OUT <n-2>Represents the second to last row and the third to last row. Combined Figure 2 Taking the last row of scan driving circuits 300 among the multiple scan driving circuits 300 as an example, the output unit 302 in the last row of scan driving circuits 300 receives the second clock signal CK, and the corresponding charging unit 303 receives the first clock signal CB.

[0101] Combination Figure 1 and Figure 2 , taking the last row of scanning driving circuits 300 among the multiple scanning driving circuits 300 as an example, corresponding to the forward scanning stage, in the P1 stage, STD is in a low level state, and CNB is transmitted to the first control node 305. In the reverse scanning stage, CN is constantly at a high level, and CNB is constantly at a low level. The start unit 301 controls the output unit 302 to perform reverse scanning, and sequentially scans the pixel circuits 400 from the last row to the first row. This stage is similar to the P1 stage of the forward scanning, and will not be repeated.

[0102] In the P2 phase, STD is at a high level, and the scan driving circuit 300 scans the pixel circuit 400 . This phase is similar to the P1 phase of the forward scan and will not be described in detail.

[0103] In the P3 phase, STD is high, STV is low, transistor M1 is turned on, CN is constant high, transistor M1 transmits CN to PU, transistor M7 is turned off under the control of PU, the second clock signal CK cannot be output to OUT, and OUT is in a suspended state. <n-1>CB is at a low level, and the charging unit 303 adjusts the potential of PD based on CB, so that the clamping unit 304 clamps the potential of OUT to a high level state, thereby stabilizing the OUT output at a high level state.

[0104] In the P4 stage, the pixel circuit 400 is kept in a reset state. In the P4 stage of the forward scan, the second clock signal CK is in a high level state, and there is a possibility that CB is in a low level state. Therefore, the capacitor C1 is also likely to be broken down by the second clock signal CK. Under the action of the first clock signal CB, the charging unit 303 adjusts PD so that the clamping unit 304 pulls up the potential of OUT, thereby ensuring that the potential difference between the source and drain of the transistor M7 is not too large to prevent the transistor M7 from being broken down, and can further stabilize the OUT output at a high level, and can improve the control of the drive signal of the scan drive circuit 300 in the reverse scan stage, thereby ensuring the stability of the output of the pixel circuit 400, and then being able to improve the display stability of the display panel.

[0105] It should be noted that when the number of rows of the pixel circuit 400 is an even number, in order to ensure that the timing of the output of the pixel circuit 400 row initially scanned in the forward scanning or reverse scanning stage is consistent, that is, after executing a frame of forward scanning or reverse scanning, if the next frame is a scan in a different direction, the timing between the first clock signal CB and the second clock signal CK can be exchanged.

[0106] It is understandable that the embodiments of the present application provide a circuit structure based on a P-type transistor, but those skilled in the art may adaptively adjust the type of transistor or the unit structure without specific limitation.

[0107] In summary, a display panel provided by an embodiment of the present application includes a first clock signal line 100, a second clock signal line 200, a plurality of rows of pixel circuits 400, and a plurality of scan drive circuits 300, wherein the scan drive circuit 300 includes a start unit 301, an output unit 302, a charging unit 303, a clamping unit 304, a first control node 305, a second control node 306, and an output node 307. The output unit 302 and the charging unit 303 in each scan drive circuit 300 are electrically connected to one of the first clock signal line 100 and the second clock signal line 200, respectively, the output units 302 and the charging units 303 of adjacent rows are connected to different clock signal lines, and the output unit 302 in each scan drive circuit 300 is electrically connected to each row of pixel circuits 400. The start unit 301 adjusts the potential of the first control node 305 based on the received forward scan start signal STV or reverse scan start signal STD, and the output unit 302 outputs the first clock signal CB or the second clock signal CK to the output node 307 under the potential control of the first control node 305, so that the forward scan or reverse scan of the multiple rows of pixel circuits 400 can be realized only by changing the timing of the driving signal. The charging unit 303 in each scanning driving circuit 300 is electrically connected to the clamping unit 304 through the second control node 306. After the scanning driving circuit 300 performs forward or reverse scanning on one of the rows, the output unit 302 is turned off under the action of the first control node 305, and the charging unit 303 adjusts the potential of the second control node 306 based on the clock signal, so that the clamping unit 304 transmits a voltage signal to the output node 307 to clamp the potential of the output node 307, so that the pixel circuit 400 connected to the output node 307 can be maintained in a reset state, and then the display stability of the display panel can be improved. Furthermore, by connecting one of the first clock signal line 100 and the second clock signal line 200 to the output unit 302 to act as an output voltage and the other to the charging unit 303 to act as a control signal, one signal line can play different roles in different scanning drive circuits 300, thereby saving the number of signal lines in the display panel and further improving the computing efficiency of the driving chip or processor.

[0108] According to some embodiments, Figure 5 A schematic structural block diagram of another display panel provided in an embodiment of the present application; Figure 5 As shown, VGL represents the first voltage signal, VGH represents the second voltage signal, the charging unit 303 is used to transmit the first voltage signal VGL to the second control node 306 under the control of the first clock signal CB or the second clock signal CK; the clamping unit 304 is used to transmit the second voltage signal VGH to the output node 307 under the control of the potential of the first control node 305. Wherein, when the first voltage signal VGL is at a low level, the second voltage signal VGH is at a high level, and when the first voltage signal VGL is at a high level, the second voltage signal VGH is at a low level, and both the first voltage signal VGL and the second voltage signal VGH are constant voltage signals.

[0109] Exemplarily, the charging unit 303 is electrically connected to the first clock signal line 100 or the second clock signal line 200, and the charging units 303 in the scan driving circuits 300 of adjacent rows are connected to different clock signal lines, and the first voltage signal VGL is transmitted to the first control node 305, and the clamping unit 304 transmits the second voltage signal to the output node 307 under the potential control of the first control node 305. Figure 2 Taking a row scanning driving circuit 300 as an example, the charging unit 303 can transmit the first voltage signal VGL to PD based on the second clock signal CK or the first clock signal CB to adjust the potential of PD. In the P3 stage and the P4 stage, the clamping unit 304 transmits the second voltage signal VGH to OUT under the control of PD. The second voltage signal VGH can clamp the potential of OUT and maintain the pixel circuit 400 connected to the output node 307 in a reset state.

[0110] It can be understood that in the P3 stage, if the pixel circuit 400 is in a reset state when the output node 307 outputs a high level, the second voltage signal VGH can be a high level; if the pixel circuit 400 is in a reset state when the output node 307 outputs a low level, the second voltage signal VGH can be a low level, thereby clamping the output node 307.

[0111] It should be noted that if Figure 3 and Figure 4 As shown, during the forward scan, OUT <2> Than OUT <1> One beat slower, during the reverse scan, OUT <n-1>Than OUT <n>One beat slower, so the charging unit 303 and the clamping unit 304 in different rows of the scan driving circuit 300 have different working timings. Moreover, since the charging unit 303 is controlled based on the second clock signal CK or the first clock signal CB, and the clamping unit 304 is controlled based on the second control node 306, the first voltage signal VGL and the second voltage signal VGH are both set as constant voltage signals, and there is no need to set different first voltage signal VGL and second voltage signal VGH timings for each scan driving circuit 300, so that the charging unit 303 and the clamping unit 304 in all scan driving circuits 300 are connected to a signal line of the first voltage signal VGL and the second voltage signal VGH, thereby saving signal lines, simplifying the control of the signal timing by the driving chip or processor, and then improving the display stability of the display panel.

[0112] According to some embodiments, Figure 6 A schematic structural block diagram of a scan drive circuit provided in an embodiment of the present application; Figure 6 As shown, the scan driving circuit 300 further includes: a first control unit 308, and the first control unit 308 is electrically connected to the first control node 305 and the second control node 306 respectively.

[0113] The first control unit 308 is used to receive the third clock signal CLK3 , and the first control unit 308 is used to transmit the third clock signal CLK3 to the second control node 306 under the potential control of the first control node 305 .

[0114] It should be noted that the first control unit 308 can adjust the potential of the second control node 306 under the action of the first control node 305. The potential of the first control node 305 controls the output unit 302 at the same time, and the potential of the second control node 306 controls the clamping unit 304 at the same time. Figure 3 , Figure 4 and Figure 5 In the P2 phase, the scan driving circuit 300 scans the pixel circuit 400 electrically connected to the output node 307, that is, the output unit 302 transmits the first clock signal CB or the second clock signal CK to the output node 307 under the potential control of the first control node 305. Accordingly, the first control unit 308 can transmit the third clock signal CLK3 to the second control node 306 under the potential control of the first control node 305, so as to close the clamping unit 304, thereby preventing the clamping unit 304 from accidentally opening due to the potential of the second control node 306 being suspended when the clamping unit 304 includes an active switching device, causing the second voltage signal VGH to be input to the output node 307, thereby interfering with the scanning of the pixel circuit 400 by the scan driving circuit 300, and then affecting the display stability of the display panel.

[0115] For example, Figure 2 As shown, the first control unit 308 includes a P-type transistor M4, a gate of the transistor M4 is electrically connected to PU, a source of the transistor receives the third clock signal CLK3, a drain of the transistor M4 is electrically connected to PD, and a source of the transistor M4 is electrically connected to PU. Figure 7 Another timing diagram of a scan driving circuit 300 performing forward scanning provided in an embodiment of the present application can be applied to Figure 2 In the circuit structure of FIG. 300 , the scanning driving circuit 300 performs forward scanning as an example. Figure 2 , Figure 3 , Figure 5 and Figure 7 As shown, in the P2 phase, the transistor M7 and the transistor M4 are both turned on under the control of PU, and the third clock signal CLK3 is in a high level state. The transistor M7 transmits CB to OUT, and performs a forward scan on the connected pixel circuit 400. At the same time, the transistor M4 transmits the third clock signal CLK3 to PD, and the clamping unit 304 can be closed under the action of the high level, and the second voltage signal VGH is not transmitted to OUT. Moreover, since the first control unit 308 and the output unit 302 are both based on the potential control of the first control node 305, the first control unit 308 and the output unit 302 are set to the same type of transistors. When the output unit 302 is turned on, the first control unit 308 will also be turned on at the same time, so that the output unit 302 and the first control unit 308 achieve a chain control effect.

[0116] It can be understood that the reverse scan is the same as the forward scan and will not be described in detail.

[0117] According to some embodiments, Figure 8 A schematic structural block diagram of another scan driving circuit provided in an embodiment of the present application; Figure 8 As shown, the scan driving circuit 300 also includes: a second control unit 309, which is electrically connected to the first control node 305 and the second control node 306 respectively; wherein the second control unit 309 is used to receive the fourth clock signal CLK4, and the second control unit 309 is used to transmit the second voltage signal to the first control node 305 under the potential control of the fourth clock signal CLK4 and the second control node 306.

[0118] It should be noted that the second control unit 309 transmits the second voltage signal VGH to the first control node 305 under the common control of the fourth clock signal CLK4 and the potential of the second control node 306 to adjust the potential of the first control node 305. Figure 3 , Figure 4 and Figure 5 In the P4 phase, the pixel circuit 400 is in a reset state, and the output unit 302 should be turned off. At this time, the clamping unit 304 is turned on to transmit the second voltage signal VGH to the output node 307 to clamp the potential of the output node 307. However, if the output unit 302 includes an active switching device, the output unit 302 may be turned on by the residual charge of the first control node 305, so that the first clock signal CB or the second clock signal CK enters the output node 307, thereby affecting the state of the pixel circuit 400. Therefore, the second control unit 309 controls the potential of the first control node 305 while the clamping unit 304 clamps the output node 307, thereby further ensuring that the output unit 302 maintains the current state to keep the pixel circuit 400 in a reset state, thereby improving the display stability of the display panel. Moreover, in order to prevent the residual charge at the second control node 306 from controlling the second control unit 309, for example, in the P2 stage, if the second control unit 309 is turned on by the residual charge at the second control node 306, the second voltage signal VGH is transmitted to the first control node 305, affecting the working state of the output unit 302, thereby interfering with the scanning of the pixel circuit 400 by the scanning driving circuit 300, the fourth clock signal CLK4 is set based on the potential control of the second control node 306 to ensure the accuracy of the control of the second control unit 309.

[0119] For example, Figure 2 As shown, the second control unit 309 includes a P-type transistor M5 and a P-type transistor M6, the gate of the transistor M5 receives the fourth clock signal CLK4, the gate of the transistor M6 is electrically connected to PD, the source of the transistor M5 is electrically connected to the drain of the transistor M6, the drain of the transistor M5 is electrically connected to PU, and the source of the transistor M6 receives VGH. Fig. 9 A timing diagram of another scanning driving circuit performing forward scanning provided in an embodiment of the present application can be applied to Figure 2 In the circuit structure of FIG. 300 , the scanning driving circuit 300 performs forward scanning as an example. Figure 2 , Figure 3 , Figure 5 and Fig. 9 As shown, in the P4 stage, transistor M6 is turned on under the control of PD, transistor M5 is turned on or off under the timing control of the fourth clock signal CLK4, and transistor M7 transmits CB to OUT. At this time, transistor M7 is cut off under the action of PU, so that the CB signal received by the source of transistor M7 will not be transmitted to OUT. However, considering the residual charge of the first control node 305, when the CB signal is at a low level, transistor M7 may be turned on by PU, so that CB is transmitted to OUT, interfering with the reset state of the pixel circuit 400. Therefore, the fourth clock signal CLK4 can output a low-level pulse when the first clock signal CB is at a low level, so that transistor M5 is turned on, so that the second voltage signal VGH can be transmitted to PU through transistor M5 and transistor M6, pull up the potential of PU, and prevent transistor M7 from being turned on, thereby interfering with the reset state of the pixel circuit 400, and then affecting the display stability of the display panel.

[0120] It can be understood that the reverse scan is the same as the forward scan and will not be described in detail.

[0121] According to some embodiments, Fig.10 A schematic structural block diagram of another scan driving circuit provided in an embodiment of the present application; Fig.10 As shown, the scan driving circuit 300 further includes: a reset unit 310 , which is electrically connected to the first control node 305 , and is used for transmitting the second voltage signal VGH to the first control node 305 under the control of a reset signal Reset.

[0122] It should be noted that after each frame scan is completed, some charges will remain on the first control node 305. These residual charges will interfere with the output unit 302 in the next frame scan, thereby reducing the display stability of the display panel. Therefore, before the scan drive circuit 300 performs forward scanning or reverse scanning, a reset phase can be set to clear the residual charges on the first control node 305, so that the scan drive circuit 300 obtains a clean initialization state.

[0123] For example, Figure 2 As shown, the reset unit 310 includes a P-type transistor M0, the gate of the transistor M0 receives the reset signal Reset, the source of the transistor M0 receives the second voltage signal VGH, and the drain of the transistor is electrically connected to PU. Figure 3 and Figure 4 As shown in the P0 stage, in the P0 stage, the transistor M0 can transmit the second voltage signal VGH to PU under the action of the reset signal Reset, and initialize the potential of the PU node to a high level, so that the transistor M7 in the output unit 302 is closed and will not be opened by mistake.

[0124] According to some embodiments, Fig.11 A schematic structural block diagram of another scan driving circuit provided in an embodiment of the present application; Fig.11 As shown, the scan driving circuit 300 further includes: a first isolation unit 311, which is arranged between the start unit 301 and the first control node 305, and the first isolation unit 311 is used to maintain the potential of the first control node 305 under the control of the first clock signal CB or the second clock signal CK.

[0125] For example, Fig.14 A schematic circuit diagram of another scan driving circuit provided in an embodiment of the present application; Fig.14 As shown, the first isolation unit 311 includes a P-type transistor M9, the source of the transistor M9 is electrically connected to the start-up unit 301, the drain of the transistor M9 is electrically connected to the PU, the gate of the transistor M9 receives the second clock signal CK or the first clock signal CB, and when the output unit 302 receives the first clock signal CB, the gate of the transistor M9 receives the second clock signal CK, and when the output unit 302 receives the second clock signal CK, the gate of the transistor M9 receives the first clock signal CB. Figure 3 and Figure 4 Taking the case where the output unit 302 in the scan driving circuit 300 receives the first clock signal CB as an example, in the P3 and P4 stages, the transistor M7 in the output unit 302 should be in the off state. Since the first clock signal CB is in the low level state, the second clock signal CK is in the high level state. When the first clock signal CB is in the low level state, the transistor M7 is prevented from being accidentally turned on due to the leakage current of the transistor M1 and the transistor M2 in the start-up unit 301, so that the first clock signal CB is transmitted to OUT, interfering with the reset state of the pixel circuit 400. The transistor M9 can be turned off under the control of the second clock signal CK, and the transistor leakage current in the start-up unit 301 will not interfere with the transistor M7, thereby improving the stability of the reset state of the pixel circuit 400, and then improving the display stability of the display panel.

[0126] Fig.12 A schematic structural block diagram of another scan drive circuit provided in an embodiment of the present application; Fig.12 As shown, the scan driving circuit 300 may further include: a second isolation unit 312, which is arranged between the start unit 301 and the first control node 305, and the second isolation unit 312 is used to maintain the potential of the first control node 305 under the control of the first voltage signal VGL and the potential of the first control node 305.

[0127] For example, Fig.14 As shown, the second isolation unit 312 includes a P-type transistor M10, the gate of the transistor M10 receives the first voltage signal VGL, the source of the transistor M10 is electrically connected to PU, and the drain of the transistor M10 is electrically connected to the start-up unit 301. Figure 3 and Figure 4 , the output unit 302 includes a transistor M7 and a capacitor C1, the source of the transistor M7 receives the first clock signal CB, in the P2 stage, the transistor M7 is turned on under the control of the PU, and transmits the first clock signal CB to the OUT, at which time, the potential of the PU is controlled by the capacitor C1. Due to the bootstrap effect of the capacitor C1, when the first clock signal CB is transmitted to the OUT, the plate potential of the capacitor C1 connected to the OUT will drop, and the corresponding plate potential connected to the PU will also drop, so that the |Vgs| of the transistor M10 becomes smaller, and in the case of |Vth|>|Vgs|, the transistor M10 is turned off, so that it can play an isolation role, preventing the current on the drain side of the transistor M10 from interfering with the PU, thereby improving the stability of the scanning driving circuit 300 when scanning the pixel circuit 400, and then improving the display stability of the display panel.

[0128] Fig.13 A schematic structural block diagram of another scan drive circuit provided in an embodiment of the present application; Fig.13 As shown, the scan driving circuit 300 further includes a first isolation unit 311 and a second isolation unit 312 . The first isolation unit 311 is disposed between the reset unit 310 and the start unit 301 , and the second isolation unit 312 is disposed between the reset unit 310 and the first control node 305 .

[0129] It should be noted that the first isolation unit 311 and the second isolation unit 312 can be simultaneously arranged in the scanning drive circuit 300, so that the display panel provided in the present application can maintain the potential of the first control node 305 when the pixel circuit 400 is scanned or the pixel circuit 400 is in the reset stage, thereby ensuring the stability of the working state of the output unit 302, and then improving the display stability of the display panel.

[0130] According to some embodiments, Fig.15 A schematic structural block diagram of a scan drive circuit cascade provided in an embodiment of the present application; Fig.15 As shown, the output node 307 of the scan driving circuit 300 is electrically connected to the start-up unit 301 of the adjacent previous level scan driving circuit 300, and the output node 307 is used to transmit the reverse scan start signal STD to the start-up unit 301 of the adjacent previous level scan driving circuit 300; the output node 307 of the scan driving circuit 300 is electrically connected to the start-up unit 301 of the adjacent next scan driving circuit 300, and the output node 307 is used to transmit the forward scan start signal STV to the start-up unit 301 of the adjacent next scan driving circuit 300.

[0131] For example, Fig.15 In the figure, the scan driving circuit 300 of the mth row is electrically connected to the pixel circuit 400 of the nth row, the output node 307 in the scan driving circuit 300 of the mth row is connected to the start-up unit 301 in the scan driving circuit 300 of the m-1th row, and acts as STD. At the same time, the output node 307 in the scan driving circuit 300 of the mth row is connected to the start-up unit 301 in the scan driving circuit 300 of the m+1th row, and acts as STV.

[0132] It should be noted that the scanning driving circuit 300 scans multiple rows of pixel circuits 400 in sequence. Since the timing received by each row of the scanning driving circuit 300 is different, the STV and STD timings received by the mth row of the scanning driving circuit 300 and the m-1th row of the scanning driving circuit 300 are different. Fig.16 A timing diagram of another scan driving circuit 300 performing forward scanning provided in an embodiment of the present application is shown in FIG. Fig.17 A timing diagram of another scan driving circuit performing reverse scanning provided in an embodiment of the present application. Fig.16 and Fig.17 As shown, the present application connects all the scan driving circuits in a cascade manner, the STV in the initial scan driving circuit 300 is connected to the STV signal line, the STD in the scan driving circuit 300 of the last row is connected to the STD signal line, the STV of the scan driving circuit 300 of the middle row is provided by the OUT in the scan driving circuit 300 of the previous row, and the STD of the scan driving circuit 300 of the middle row is provided by the OUT in the scan driving circuit 300 of the next row. Therefore, the display panel provided by the present application does not need to provide the scan driving circuit 300 of each row with a signal line for starting the forward scan and a signal line for starting the reverse scan separately, thereby reducing the signal line setting in the display panel, and then reducing the timing processing burden of the driver chip or processor in the display panel, thereby improving the computing efficiency.

[0133] According to some embodiments, when the output unit 302 is electrically connected to the first clock signal line 100, the third clock signal CLK3 is the same as the second clock signal CK; when the output unit 302 is electrically connected to the second clock signal line 200, the third clock signal CLK3 is the same as the first clock signal CB.

[0134] Exemplary, combined Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig.13 and Fig.14 , when the output unit 302 is electrically connected to the first clock signal line 100, the source of the transistor M7 receives CB, and the third clock signal CLK3 received by the first control unit 308 can have the same timing as CK. Correspondingly, when the output unit 302 is electrically connected to the second clock signal line 200, the source of the transistor M7 receives CK, and the third clock signal CLK3 received by the first control unit 308 can have the same timing as CB. This can reduce the signal line settings in the display panel, thereby reducing the timing processing burden of the driver chip or processor in the display panel, and improving the operation efficiency.

[0135] According to some embodiments, when the charging unit 303 is electrically connected to the first clock signal line 100, the fourth clock signal CLK4 is the same as the second clock signal CK; when the charging unit 303 is electrically connected to the second clock signal line 200, the fourth clock signal CLK4 is the same as the first clock signal CB.

[0136] Exemplary, combined Figure 3 , Figure 4 , Figure 5 , Figure 8 , Fig. 9 , Fig.13 and Fig.14 , when the charging unit 303 is electrically connected to the first clock signal line 100, that is, the gate of the transistor M3 receives the first clock signal CB, the fourth clock signal CLK4 received by the second control unit 309 can have the same timing as the second clock signal CK. Correspondingly, when the charging unit 303 is electrically connected to the second clock signal line 200, the gate of the transistor M3 receives the second clock signal CK, and the fourth clock signal CLK4 received by the second control unit 309 can have the same timing as the first clock signal CB. This can reduce the signal line settings in the display panel, thereby reducing the timing processing burden of the driver chip or processor in the display panel, and improving the operation efficiency.

[0137] According to some embodiments, Figure 2 or Fig.14 As shown, the charging unit 303 includes a first transistor M3, the gate of the first transistor M3 is electrically connected to the first clock signal line 100 or the second clock signal line 200, and the source or drain of the first transistor M3 is used to receive the first voltage signal VGL; and / or, the clamping unit 304 includes a second transistor M8 and a capacitor C2, the gate of the second transistor M8 is electrically connected to the second control node 306, the source or drain of the second transistor M8 is used to receive the second voltage signal VGH, one end of the capacitor C2 is electrically connected to the gate of the second transistor M8, and the other end of the capacitor C2 is used to receive the second voltage signal VGH.

[0138] Exemplarily, the charging unit 303 includes a first transistor M3 , which may be a P-type transistor. Under the control of the second clock signal CK or the first clock signal CB, the first transistor M3 may transmit the first voltage signal VGL to PD to adjust the potential of the second control node 306 .

[0139] The clamp unit 304 includes a second transistor M8 , which may be a P-type transistor. The capacitor C2 is connected to the gate and source of the second transistor M8 . The source of the second transistor M8 receives the second voltage signal VGH. The drain of the second transistor M8 is electrically connected to OUT.

[0140] It should be noted that, combined with Figure 3 or Figure 4 In the P4 stage, the pixel circuit 400 is in a reset state. When the output unit 302 receives the first clock signal CB, the first transistor M3 is periodically turned on or off in the P4 stage based on the control of the second clock signal CK. When the first transistor M3 is turned on, the first transistor M3 can transmit the first voltage signal VGL to PD, and the first voltage signal VGL is a constant low level, so that the capacitor C2 can be charged, and because the first voltage signal VGL is a low level, the second transistor M8 is turned on under the control of PD, and VGH is transmitted to the output node 307, clamping the potential of the output node 307 to a high level. When the first transistor M3 is turned off, the capacitor C2 is discharged, and negative charge can be continuously provided to PD, so that the second transistor M8 is turned on under the control of PD. In the reset stage of the pixel circuit 400, the capacitor C2 can control the continuous conduction of the second transistor M8 through cyclic charging and discharging, and can continuously clamp the potential of OUT when the pixel circuit 400 is in the reset stage, thereby ensuring the stability of the pixel circuit 400, and then improving the display stability of the display panel.

[0141] According to some embodiments, the low-level pulse width of the second clock signal CK is within the time period of the high-level pulse width of the first clock signal CB, and the low-level pulse width of the first clock signal CB is within the time period of the high-level pulse width of the second clock signal CK; or, the high-level pulse width of the second clock signal CK is within the time period of the low-level pulse width of the first clock signal CB, and the high-level pulse width of the first clock signal CB is within the time period of the low-level pulse width of the second clock signal CK.

[0142] Exemplary, combined Figure 2 , Figure 3 and Figure 4 , the low-level pulse width of the second clock signal CK is within the time period of the high-level pulse width of the first clock signal CB, and the low-level pulse width of the first clock signal CB is within the time period of the high-level pulse width of the second clock signal CK, that is, the high-level pulse duty cycle of the first clock signal CB and the second clock signal CK is greater than the low-level pulse duty cycle, so that there are gaps in each stage of frame scanning of the scan driving circuit 300, such as from the P0 stage to the P1 stage, from the P1 stage to the P2 stage, and from the P2 stage to the P3 stage. In these gaps, CK and CB are both high.

[0143] It should be noted that, taking the first row scanning driving circuit 300 as an example, the output unit 302 in the scanning driving circuit 300 is connected to the first clock signal CB, the first clock signal CB provides an output voltage, and the second clock signal CK is connected to the charging unit 303, and the second clock signal CK serves as a control signal. Figure 3 As shown, taking the stage from P1 to P2 as an example, the charging unit 303 includes a transistor M3, and the second clock signal CK first appears a rising edge, thereby first turning off the transistor M3, at which time PU is in a low level state, the transistor M4 is turned on, and the third clock signal CLK3 high level signal enters PD, causing the transistor M8 to be turned off first, and then the first clock signal CB appears a falling edge, and the control transistor M7 outputs the first clock signal CB to the output node 307 to scan the pixel circuit 400 in the P2 stage. Therefore, widening the effective working level of the clock signal line serving as the control signal can prevent the clamping unit 304 and the output unit 302 from switching the working state at the same time to generate a timing error, resulting in an error in the voltage of the output node 307.

[0144] In addition, when the circuit structure is N-type transistors, since the conduction logic of N-type transistors is opposite to that of P-type transistors, it is necessary to exchange the high and low level logics of the first clock signal CB and the second clock signal CK. That is, the high level pulse width of the second clock signal CK is within the time period of the low level pulse width of the first clock signal CB, and the high level pulse width of the first clock signal CB is within the time period of the low level pulse width of the second clock signal CK.

[0145] A second aspect of the embodiments of the present application provides a method for driving a display panel, which is applied to any display panel in the first aspect. Fig.18 A schematic flow chart of a method for driving a display panel provided in an embodiment of the present application, combined with Figure 1 , the above driving method includes:

[0146] S110 , transmitting a forward scanning start signal STV to the start unit 301 , or transmitting a reverse scanning start signal STD to the start unit 301 .

[0147] For example, Figure 1 As shown, the present application can transmit a positive scan start signal STV to the start unit 301 through a driver chip or a processor in a display panel to drive the multi-row pixel circuit 400 to perform a positive scan phase. In the positive scan phase, the start unit 301 adjusts the potential of the first control node 305 according to the positive scan signal. After the start unit 301 receives STV, it adjusts the potential of the first control node 305.

[0148] Accordingly, the reverse scanning start signal STD is transmitted to the start unit 301 to drive the multi-row pixel circuit 400 to perform the reverse scanning stage. In the reverse scanning stage, the start unit 301 adjusts the potential of the first control node 305 according to the reverse scanning signal. After receiving STD, the start unit 301 adjusts the potential of the first control node 305.

[0149] S120 , transmitting the first clock signal CB to the first clock signal line 100 , and transmitting the second clock signal CK to the second clock signal line 200 .

[0150] Exemplary, combined Figure 1 After the startup unit 301 adjusts the potential of the first control node 305 according to STV or STD, the driving chip or processor can transmit the first clock signal CB to the first clock signal line 100 and transmit the second clock signal CK to the second clock signal line 200, so that the output unit 302 transmits the first clock signal CB or the second clock signal CK to the output node 307.

[0151] It should be noted that the output unit 302 and the charging unit 303 in each scan driving circuit 300 are respectively connected to different clock signal lines, and the clock signal lines connected to the output unit 302 and the charging unit 303 are also different between the scan driving circuits 300 in adjacent rows. That is, when the output unit 302 transmits the first clock signal CB transmitted by the first clock signal line 100 to the output node 307, the charging unit 303 receives the second clock signal CK transmitted by the second clock signal line 200. When the output unit 302 transmits the second clock signal CK transmitted by the second clock signal line 200 to the output node 307, the charging unit 303 receives the first clock signal CB transmitted by the first clock signal line 100.

[0152] After receiving the first clock signal CB or the second clock signal CK, the charging unit 303 adjusts the potential of the second control node 306 , so that the clamping unit 304 clamps the potential of the output node 307 according to the potential of the second control node 306 .

[0153] Fig.19 This is a simulation result diagram of the scan driving circuit provided in the embodiment of the present application performing forward scanning on the pixel circuit. Fig. 20 This is a simulation result diagram of the scanning driving circuit provided in the embodiment of the present application performing reverse scanning on the pixel circuit. Fig.19 and Fig. 20 As shown, in the forward scanning stage, OUT <1> To OUT <5> They represent the output of the 1st to 5th rows respectively. The 1st to 5th rows are outputted sequentially, and the interval between adjacent rows is the same. Correspondingly, in the reverse scanning stage, the 5th to 1st rows are outputted sequentially, and the interval between adjacent rows is the same.

[0154] The driving method of the display panel provided in the present application, for each scanning driving circuit 300, when one of the first clock signal CB or the second clock signal CK is transmitted to the output unit 302 to provide the output voltage to the corresponding pixel circuit 400, the other is transmitted to the charging unit 303 to act as a control signal, that is, for the first clock signal line 100 or the second clock signal line 200, each clock signal line provides both the output voltage and the control signal in the entire display panel. In the related art, the signal line that plays a control role and the signal line that acts as an output will not use the same signal line. Therefore, the driving method provided in the present application can save the setting of the signal line in the display panel, thereby reducing the timing processing burden of the driver chip or processor in the display panel, and improving the operation efficiency.

[0155] According to some embodiments, in combination Figure 5 The driving method provided in the embodiment of the present application also includes: transmitting a first voltage signal VGL to the charging unit 303, so that the charging unit 303 transmits the first voltage signal VGL to the second control node 306 under the control of the first clock signal CB or the second clock signal CK; transmitting a second voltage signal VGH to the clamping unit 304, so that the clamping unit 304 transmits the second voltage signal VGH to the output node 307 under the control of the potential of the second control node 306; wherein, when the first voltage signal VGL is at a low level, the second voltage signal VGH is at a high level, and when the first voltage signal VGL is at a high level, the second voltage signal VGH is at a low level, and the first voltage signal VGL and the second voltage signal VGH are both constant voltage signals.

[0156] It should be noted that if Figure 5 As shown, the first voltage signal VGL is transmitted to the charging unit 303, so that the charging unit 303 transmits the first voltage signal VGL to the second control node 306 under the control of the first clock signal CB or the second clock signal CK. The clamping unit 304 transmits the second voltage signal VGH to the output node 307 under the potential control of the second control node 306. Both the first voltage signal VGL and the second voltage signal VGH are constant voltage signals.

[0157] Exemplarily, the charging unit 303 is electrically connected to the first clock signal line 100 or the second clock signal line 200, and the charging units 303 in the scan driving circuits 300 of adjacent rows are connected to different clock signal lines, and the first voltage signal VGL is transmitted to the first control node 305, and the clamping unit 304 transmits the second voltage signal VGH to the output node 307 under the potential control of the first control node 305. Figure 2 Taking a row scanning driving circuit 300 as an example, the charging unit 303 can transmit the first voltage signal VGL to PD based on the second clock signal CK or the first clock signal CB to adjust the potential of PD. In the P3 stage and the P4 stage, the clamping unit 304 transmits the second voltage signal VGH to OUT under the control of PD. The second voltage signal VGH can clamp the potential of OUT and maintain the pixel circuit 400 connected to the output node 307 in a reset state.

[0158] like Figure 3 and Figure 4 As shown, during the forward scan, OUT <2> Than OUT <1> One beat slower, during the reverse scan, OUT <n-1>Than OUT <n>One beat slower, so the charging unit 303 and the clamping unit 304 in different rows of the scan driving circuit 300 have different working timings. Moreover, since the charging unit 303 is controlled based on the second clock signal CK or the first clock signal CB, and the clamping unit 304 is controlled based on the second control node 306, the first voltage signal VGL and the second voltage signal VGH are both set as constant voltage signals, and there is no need to set different first voltage signal VGL and second voltage signal VGH timings for each scan driving circuit 300, so that the charging unit 303 and the clamping unit 304 in all scan driving circuits 300 are connected to a signal line of the first voltage signal VGL and the second voltage signal VGH, thereby saving signal lines, simplifying the control of the signal timing by the driving chip or processor, and then improving the display stability of the display panel.

[0159] In some examples, the display panel provided by the present application is Fig.10 As shown, a reset unit 310 may also be included, and the reset unit 310 is electrically connected to the first control node 305. Figure 3 and Figure 4 Before the frame scan starts, a reset signal Reset can be provided to the reset unit 310. The reset unit 310 transmits a second voltage signal VGH to the first control node 305 based on Reset to initialize the level of the first control node 305 to prevent the residual charge on the first control node 305 from causing the output unit 302 to be falsely triggered.

[0160] According to some embodiments, Figure 5 As shown, the driving method provided in the embodiment of the present application also includes: in the process of forward scanning, transmitting the reverse scanning start signal STD to the start unit 301, so that the start unit 301 transmits the third voltage signal CNB to the first control node 305 under the control of the reverse scanning start signal STD; in the process of reverse scanning, transmitting the forward scanning start signal STV to the start unit 301, so that the start unit 301 transmits the fourth voltage signal CN to the first control node 305 under the control of the forward scanning start signal STV; wherein, when the third voltage signal CNB is at a low level, the fourth voltage signal CN is at a high level, and when the third voltage signal CN is at a high level, the fourth voltage signal CNB is at a low level.

[0161] Exemplary, combined Figure 2 and Figure 3 As shown, taking the forward scanning of the scan driving circuit 300 as an example, the start unit 301 includes a transistor M1 and a transistor M2, and the output unit 302 includes a transistor M7. In the P3 stage, STV is in a high level state, STD is in a low level state, CNB is transmitted to PU through the transistor M2, and CNB is a constant high level, so that the transistor M7 is turned off to prevent the PU node from being in a suspended state, causing the transistor M7 to be triggered incorrectly.

[0162] Accordingly, when the scan driving circuit 300 performs reverse scanning, Figure 2 and Figure 4 As shown, in the P3 phase, STV is in a low level state, STD is in a high level state, CN is transmitted to PU through the transistor M1, and CN is at a constant high level, thereby turning off the transistor M7.

[0163] According to some embodiments, in combination Figure 6 In the case where the display panel includes a first control unit 308, and the first control unit 308 is electrically connected to the first control node 305 and the second control node 306 respectively, the driving method further includes: transmitting a third clock signal CLK3 to the first control unit 308, so that the first control unit 308 transmits the third clock signal CLK3 to the second control node 306 under the potential control of the first control node 305.

[0164] For example, Figure 2 As shown, the first control unit 308 includes a P-type transistor M4, a gate of the transistor M4 is electrically connected to PU, a source of the transistor receives the third clock signal CLK3, a drain of the transistor M4 is electrically connected to PD, and a source of the transistor M4 is electrically connected to PU. Figure 7 Another timing diagram of a scan driving circuit performing forward scanning provided in an embodiment of the present application can be applied to Figure 2 In the circuit structure of FIG. 300 , the scanning driving circuit 300 performs forward scanning as an example. Figure 2 , Figure 3 , Figure 5 and Figure 7 As shown, in the P2 stage, the transistor M7 and the transistor M4 are both turned on under the control of PU, and the third clock signal CLK3 is in a high level state. The transistor M7 transmits CB to OUT, and performs a forward scan on the connected pixel circuit 400. At the same time, the transistor M4 transmits the third clock signal CLK3 to PD, and the clamping unit 304 can be closed under the action of the high level, and the second voltage signal VGH is not transmitted to OUT. In addition, since the first control unit 308 and the output unit 302 are both based on the potential control of the first control node 305, the first control unit 308 and the output unit 302 are set to the same type of transistors. When the output unit 302 is turned on, the first control unit 308 will also be turned on at the same time, so that the effect of interlocking control can be achieved.

[0165] It can be understood that the reverse scanning stage is the same as the forward scanning stage, and will not be described in detail here.

[0166] It should be noted that, when the output unit 302 is electrically connected to the first clock signal line 100, the timing of the third clock signal CLK3 can be the same as the second clock signal CK; when the output unit 302 is electrically connected to the second clock signal line 200, the timing of the third clock signal CLK3 can be the same as the first clock signal CB.

[0167] According to some embodiments, in combination Figure 8 In the case where the display panel includes a second control unit 309, and the second control unit 309 is electrically connected to the first control node 305 and the second control node 306 respectively, the driving method further includes: transmitting a fourth clock signal CLK4 and a second voltage signal VGH to the second control unit 309, so that the second control unit 309 transmits the second voltage signal VGH to the first control node 305 under the control of the potential of the second control node 306 and the fourth clock signal CLK4.

[0168] For example, Figure 2 As shown, the second control unit 309 includes a P-type transistor M5 and a P-type transistor M6, the gate of the transistor M5 receives the fourth clock signal CLK4, the gate of the transistor M6 is electrically connected to PD, the source of the transistor M5 is electrically connected to the drain of the transistor M6, the drain of the transistor M5 is electrically connected to PU, and the source of the transistor M6 receives the second voltage signal VGH. Fig. 9 A timing diagram of another scan driving circuit 300 performing forward scanning provided in an embodiment of the present application can be applied to Figure 2 In the circuit structure of FIG. 300 , the scanning driving circuit 300 performs forward scanning as an example. Figure 2 , Figure 3 , Figure 5 and Fig. 9 As shown, in the P4 stage, transistor M6 is turned on under the control of PD, transistor M5 is turned on or off under the timing control of the fourth clock signal CLK4, and transistor M7 transmits CB to OUT. At this time, transistor M7 is cut off under the action of PU, so that the CB signal received by the source of transistor M7 will not be transmitted to OUT. However, considering the residual charge of the first control node 305, when the CB signal is at a low level, transistor M7 may be turned on by PU, so that CB is transmitted to OUT, interfering with the reset state of the pixel circuit 400. Therefore, the fourth clock signal CLK4 can output a low-level pulse when CB is at a low level, so that transistor M5 is turned on, so that the second voltage signal VGH can be transmitted to PU through transistor M5 and transistor M6, pull up the potential of PU, and prevent transistor M7 from being turned on, thereby interfering with the reset state of the pixel circuit 400, and then affecting the display stability of the display panel.

[0169] It can be understood that the reverse scan is the same as the forward scan and will not be described in detail.

[0170] It should be noted that, when the charging unit 303 is electrically connected to the first clock signal line 100, the timing of the fourth clock signal CLK4 can be the same as the timing of the second clock signal CK; when the charging unit 303 is electrically connected to the second clock signal line 200, the timing of the fourth clock signal CLK4 can be the same as the timing of the first clock signal CB.

[0171] According to some embodiments, in combination Figure 1 , Figure 5 and Fig.15 When the number of rows of the scan driving circuit 300 is an even number and two adjacent frames of display images correspond to forward scanning and reverse scanning respectively, the clock signal transmission settings of the first clock signal line 100 corresponding to the two adjacent frames of display images are exchanged, and the clock signal transmission settings of the second clock signal line 200 corresponding to the two adjacent frames of display images are exchanged.

[0172] Exemplarily, in the stage where the scan driving circuit 300 performs forward scanning on the pixel circuit 400, if the first row of the scan driving circuit 300 transmits the first clock signal CB to the output node 307, the next row of the scan driving circuit 300 transmits the second clock signal CK to the output node 307, and the third row of the scan driving circuit 300 transmits the first clock signal CB to the output node 307, and so on. If the number of rows of the pixel circuit 400 is an even number, the last row of the pixel circuit 400 will receive the second clock signal CK. Correspondingly, the same is true for the case where the first row of the scan driving circuit 300 transmits the second clock signal CK to the output node 307, which will not be described in detail.

[0173] If the next frame scanning driving circuit 300 performs reverse scanning on the pixel circuits 400, scanning from the last row of pixel circuits 400 to the first row of pixel circuits 400, the timing of the clock signals transmitted by the first clock signal line 100 and the second clock signal line 200 needs to be exchanged.

[0174] It should be noted that, since the signal line is usually not changeable after being connected to the circuit, only the timing of signal transmission on the signal line can be adjusted. When the number of rows of the pixel circuit 400 is an even number, the output unit 302 in the first row scanning driving circuit 300 and the output unit 302 in the last row scanning driving circuit 300 are connected to different clock signal lines, and the corresponding received clock signal timings are also different. If the scanning directions of adjacent frames are opposite, Figure 3 or Figure 4 It can be seen that the first clock signal CB and the second clock signal CK differ by one beat. If the previous frame scans from the first row to the last row, and the next frame scans from the last row to the first row, in order to ensure that the scanning start timing of the initial row is consistent regardless of the forward scanning or reverse scanning stage, the timing of the clock signals transmitted on the first clock signal line 100 and the second clock signal line 200 can be exchanged.

[0175] A third aspect of the embodiments of the present application provides a display device, Fig.21 A schematic structural diagram of a display device provided in an embodiment of the present application, such as Fig.21 As shown, the display device 1000 includes: any display panel provided in the first aspect.

[0176] It should be noted that the display device 1000 provided in the embodiment of the present application can be applied to scenarios such as vehicle-mounted display, smart phones, computers, medical displays, televisions, smart wearable displays, etc., and the embodiment of the present application does not make specific limitations.

[0177] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.< / n> < / n> < / n> < / n>

Claims

1. A display panel, characterized in that: include: Multiple rows of pixel circuits; A first clock signal line; a second clock signal line, wherein a first clock signal transmitted by the first clock signal line has a different timing from a second clock signal transmitted by the second clock signal line; A plurality of scan driving circuits, each of which is electrically connected to a corresponding row of pixel circuits, and each of which comprises a start-up unit, an output unit, a charging unit, a clamping unit, a first control node, a second control node, and an output node; The start-up unit is electrically connected to the first control node, and is used to receive a forward scan start-up signal or a reverse scan start-up signal to adjust the potential of the first control node; One of the scan drive circuits corresponding to the pixel circuits in two adjacent rows is a first scan drive circuit, and the other is a second scan drive circuit, the output unit of the first scan drive circuit is electrically connected to the first clock signal line, the charging unit of the first scan drive circuit is electrically connected to the second clock signal line, the output unit of the second scan drive circuit is electrically connected to the second clock signal line, and the charging unit of the second scan drive circuit is electrically connected to the first clock signal line; The output unit is electrically connected to the first control node and the output node respectively, the output node is electrically connected to the pixel circuit, the charging unit is electrically connected to the second control node, the charging unit is used to adjust the potential of the second control node based on the first clock signal or the second clock signal, and the clamping unit is electrically connected to the second control node and the output node respectively.

2. The display panel according to claim 1, characterized in that: The charging unit is used for transmitting the first voltage signal to the second control node under the control of the first clock signal or the second clock signal; The clamping unit is used to transmit the second voltage signal to the output node under the potential control of the first control node; When the first voltage signal is at a low level, the second voltage signal is at a high level; when the first voltage signal is at a high level, the second voltage signal is at a low level; both the first voltage signal and the second voltage signal are constant voltage signals.

3. The display panel according to claim 2, characterized in that: The scanning driving circuit further includes: a first control unit, the first control unit being electrically connected to the first control node and the second control node respectively; The first control unit is used to receive a third clock signal, and the first control unit is used to transmit the third clock signal to the second control node under the potential control of the first control node.

4. The display panel according to claim 2, characterized in that: The scanning driving circuit further includes: a second control unit, the second control unit being electrically connected to the first control node and the second control node respectively; The second control unit is used to receive a fourth clock signal, and the second control unit is used to transmit the second voltage signal to the first control node under the control of the fourth clock signal and the potential of the second control node.

5. The display panel according to claim 2, characterized in that: The scanning driving circuit further includes: A reset unit, the reset unit is electrically connected to the first control node, and the reset unit is used to transmit the second voltage signal to the first control node under the control of the reset signal.

6. The display panel according to claim 2, characterized in that: The scanning driving circuit further includes: A first isolation unit is provided between the start unit and the first control node, and the first isolation unit is used to maintain the potential of the first control node under the control of the first clock signal or the second clock signal; and / or, The second isolation unit is disposed between the start-up unit and the first control node, and is used for maintaining the potential of the first control node under the control of the first voltage signal and the potential of the first control node.

7. The display panel according to claim 2, characterized in that: The output node of the scan driving circuit is electrically connected to the start-up unit of the scan driving circuit of the adjacent previous level, and the output node is used to transmit the reverse scan start-up signal to the start-up unit of the scan driving circuit of the adjacent previous level; The output node of the scan driving circuit is electrically connected to the start-up unit of the next adjacent scan driving circuit, and the output node is used to transmit the positive scan start-up signal to the start-up unit of the next adjacent scan driving circuit.

8. The display panel according to claim 3, characterized in that: When the output unit is electrically connected to the first clock signal line, the third clock signal is the same as the second clock signal; In a case where the output unit is electrically connected to the second clock signal line, the third clock signal is the same as the first clock signal.

9. The display panel according to claim 4, characterized in that: When the charging unit is electrically connected to the first clock signal line, the fourth clock signal is the same as the second clock signal; In a case where the charging unit is electrically connected to the second clock signal line, the fourth clock signal is the same as the first clock signal.

10. The display panel according to any one of claims 2 to 9, characterized in that: The charging unit comprises a first transistor, a gate of the first transistor is electrically connected to the first clock signal line or the second clock signal line, and a source or a drain of the first transistor is used to receive the first voltage signal; and / or, The clamping unit includes a second transistor and a capacitor, the gate of the second transistor is electrically connected to the second control node, the source or drain of the second transistor is used to receive the second voltage signal, one end of the capacitor is electrically connected to the gate of the second transistor, and the other end of the capacitor is used to receive the second voltage signal.

11. The display panel according to claim 10, characterized in that: The low level pulse width of the second clock signal is within the time period of the high level pulse width of the first clock signal, and the low level pulse width of the first clock signal is within the time period of the high level pulse width of the second clock signal; or, The high level pulse width of the second clock signal is within the time period of the low level pulse width of the first clock signal, and the high level pulse width of the first clock signal is within the time period of the low level pulse width of the second clock signal.

12. A method for driving a display panel, characterized in that: Applied to the display panel according to any one of claims 1 to 11, the driving method comprises: transmitting the forward scanning start signal to the start unit to drive the plurality of rows of pixel circuits to perform forward scanning, wherein, during the forward scanning process, the start unit adjusts the potential of the first control node according to the forward scanning start signal, and the output unit is turned on under the control of the potential of the first control node; or Transmitting the reverse scan start signal to the start unit to drive the plurality of rows of pixel circuits to perform reverse scan, wherein during the reverse scan, the start unit adjusts the potential of the first control node according to the reverse scan start signal, and the output unit is turned on under the control of the potential of the first control node; The first clock signal is transmitted to the first clock signal line, and the second clock signal is transmitted to the second clock signal line, so that the output unit transmits the first clock signal or the second clock signal to the output node.

13. The driving method according to claim 12, characterized in that: Also includes: transmitting a first voltage signal to the charging unit, so that the charging unit transmits the first voltage signal to the second control node under the control of the first clock signal or the second clock signal; transmitting a second voltage signal to the clamping unit, so that the clamping unit transmits the second voltage signal to the output node under the potential control of the second control node; When the first voltage signal is at a low level, the second voltage signal is at a high level; when the first voltage signal is at a high level, the second voltage signal is at a low level; both the first voltage signal and the second voltage signal are constant voltage signals.

14. The driving method according to claim 13, characterized in that: Also includes: During the forward scanning process, transmitting the reverse scanning start signal to the start unit, so that the start unit transmits a third voltage signal to the first control node under the control of the reverse scanning start signal; During the reverse scanning process, transmitting the forward scanning start signal to the start unit, so that the start unit transmits a fourth voltage signal to the first control node under the control of the forward scanning start signal; Wherein, when the third voltage signal is at a low level, the fourth voltage signal is at a high level, and when the third voltage signal is at a high level, the fourth voltage signal is at a low level.

15. The driving method according to claim 13, characterized in that: In a case where the display panel includes a first control unit, and the first control unit is electrically connected to the first control node and the second control node respectively, the driving method further includes: A third clock signal is transmitted to the first control unit, so that the first control unit transmits the third clock signal to the second control node under the potential control of the first control node.

16. The driving method according to claim 13, characterized in that: In a case where the display panel includes a second control unit, and the second control unit is electrically connected to the first control node and the second control node respectively, the driving method further includes: The fourth clock signal and the second voltage signal are transmitted to the second control unit, so that the second control unit transmits the second voltage signal to the first control node under the control of the potential of the second control node and the fourth clock signal.

17. The driving method according to any one of claims 12 to 16, characterized in that: When the number of rows of the scanning driving circuit is an even number and two adjacent frames of display images correspond to the forward scanning and the reverse scanning respectively, the clock signal exchange setting of the first clock signal line corresponding to the two adjacent frames of the display images, and the clock signal exchange setting of the second clock signal line corresponding to the two adjacent frames of the display images.

18. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 11.

Images