Source driving chip, mode control method and display device

Abstract

The application discloses a source driving chip, a mode control method and a display device. The source driving chip is connected with a timing controller, and comprises a state detection module, a logic control module and a first mode control module. The state detection module is used for detecting whether a lock signal output by the source driving chip to the timing controller is switched from a first level to a second level. The logic control module is used for controlling the first mode control module to open a first identification mode to perform first correctness verification on driving information of an image frame when the lock signal is switched from the first level to the second level, and controlling the first mode control module to close the first identification mode after a target condition is met. Through the working state control of the first identification mode, the dynamic power consumption of the source driving chip is reduced, and thus the energy consumption of the display device is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a source driving chip, a mode control method and a display device. BACKGROUND

[0002] With the development of display technology, users have higher and higher requirements on the energy consumption of display devices. Reducing the energy consumption of display devices helps to improve product competitiveness, promote environmental protection, prolong service life, and improve power efficiency, and therefore low-power display devices have become an important development direction of display technology. How to reduce the energy consumption of display devices is a subject that the industry has been committed to researching. SUMMARY

[0003] Embodiments of the present application provide a source driving chip, a mode control method and a display device. The working state control of the first identification mode reduces the dynamic power consumption of the source driving chip, thereby reducing the energy consumption of the display device.

[0004] Embodiments of the present application provide a source driving chip connected with a timing controller. The source driving chip includes a state detection module, a logic control module and a first mode control module. Wherein,

[0005] The state detection module is configured to detect whether a lock signal output from the source driving chip to the timing controller is switched from a first level to a second level.

[0006] The logic control module is configured to:

[0007] When the lock signal is switched from the first level to the second level, the first mode control module is controlled to open a first identification mode, and the driving information of an image frame is subjected to a first correctness verification.

[0008] After the target condition is met, the first mode control module is controlled to close the first identification mode.

[0009] Correspondingly, embodiments of the present application provide a mode control method applied to a source driving chip of a display device. The source driving chip is connected with a timing controller of the display device. The mode control method includes:

[0010] When a lock signal output from the source driving chip to the timing controller is switched from a first level to a second level, a first identification mode is opened, and the driving information of an image frame is subjected to a first correctness verification.

[0011] After the target condition is met, the first identification mode is closed.

[0012] Correspondingly, the embodiment of the present application provides a display device, which comprises the source driving chip.

[0013] In summary, when the source driving chip detects that the lock signal switches from the first level to the second level, i.e., from the low level to the high level, the first identification mode is enabled to check the correctness of the driving information of the image frame; after the target condition is met, the source driving chip disables the first identification mode and no longer checks the correctness of the driving information of the image frame until the lock signal switches from the first level to the second level again. In the embodiment of the present application, the first identification mode is not in a continuous working state, but is enabled when the level state of the lock signal switches, and then is disabled after the target condition is met. Through the working state control of the first identification mode, the dynamic power consumption of the source driving chip is reduced, thereby reducing the energy consumption of the display device. Moreover, the embodiment of the present application can be implemented based on the existing display device, without adding new devices in the display device, and has high compatibility with the existing display device. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram of a source driving chip provided by the embodiment of the present application;

[0015] Figure 2 is a schematic diagram of at least part of the content contained in an image frame provided by the embodiment of the present application;

[0016] Figure 3 is a schematic diagram of an instruction meaning provided by the embodiment of the present application;

[0017] Figure 4 is a flowchart of a mode control method provided by the embodiment of the present application;

[0018] Figure 5 is a flowchart of another mode control method provided by the embodiment of the present application;

[0019] Figure 6 is a schematic diagram of another source driving chip provided by the embodiment of the present application;

[0020] Figure 7 is a schematic diagram of a mode control method;

[0021] Figure 8 is a schematic diagram of a mode control method provided by the embodiment of the present application;

[0022] Figure 9 is a schematic diagram of a display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. The described technical solutions are only used to explain and describe the ideas of the present application, and should not be regarded as a limitation on the protection scope of the present application.

[0024] In addition, "multiple" in the embodiments of the present application refers to two or more than two. "First" and "second" and the like in the embodiments of the present application are used to distinguish different technical features, and do not represent any order, quantity or importance.

[0025] The various embodiments provided by the present application are similar, and the features in different embodiments can be combined with each other.

[0026] The description order of the following embodiments is not regarded as a limitation on the preferred order of the embodiments.

[0027] Please refer to Figure 1 , Figure 1 is a schematic diagram of a source driving chip provided by the embodiments of the present application. The source driving chip can be connected with a timing controller (TCON) of a display device, please refer to the following embodiments. The source driving chip is also called Source IC (Source Integrated Circuit) or Driver IC. As shown in Figure 1 The source driving chip 1100 includes a state detection module 1110, a logic control module 1120 and a first mode control module 1130.

[0028] The state detection module 1110 is configured to detect whether a lock signal output from the source driving chip 1100 to the timing controller is switched from a first level to a second level.

[0029] The logic control module 1120 is configured to: when the lock signal is switched from the first level to the second level, control the first mode control module 1130 to open a first identification mode, and perform a first correctness verification on driving information of an image frame; and after a target condition is met, control the first mode control module 1130 to close the first identification mode.

[0030] In the embodiments of the present application, the source driving chip 1100 can output a lock signal to the timing controller to indicate whether the source driving chip 1100 successfully locks the clock signal from the timing controller. The lock signal at a first level indicates that the source driving chip 1100 has not locked or has not successfully locked the clock signal; the lock signal at a second level indicates that the source driving chip 1100 has successfully locked the clock signal, and the display device can work normally. The first level is different from the second level, and the first level is less than the second level, for example, the first level is a low level and the second level is a high level. The embodiments of the present application do not exclude the possibility that the first level is greater than the second level, for example, the first level is a high level and the second level is a low level. Generally, after the display device is powered on and after the picture anomaly is recovered to normal, the lock signal is switched from the first level to the second level.

[0031] The state detection module 1110 in the source driving chip 1100 can continuously detect the level state of the lock signal. In some embodiments, after the source driving chip 1100 is powered on, the state detection module 1110 starts to detect the level state of the lock signal. That is, the state detection module 1110 is used to continuously detect the state of the lock signal after the source driving chip 1100 is powered on; wherein the state detection includes detecting whether the lock signal is switched from the first level to the second level and detecting whether the lock signal is switched from the second level to the first level. Alternatively, the state detection module 1110 is used to detect whether the lock signal is switched from the first level to the second level after the source driving chip 1100 is powered on; after the lock signal is switched from the first level to the second level, detecting whether the lock signal is switched from the second level to the first level; after the lock signal is switched from the second level to the first level, detecting whether the lock signal is switched from the first level to the second level; and so on. In the embodiments of the present application, the state detection module 1110 can continuously detect the level state switching of the lock signal, and when the lock signal is at the first level, detect whether the lock signal is switched from the first level to the second level; when the lock signal is at the second level, detect whether the lock signal is switched from the second level to the first level.

[0032] When the state detection module 1110 detects that the lock signal is switched from the first level to the second level, the logic control module 1120 in the source driving chip 1100 controls the first mode control module 1130 to start the first identification mode. The first identification mode includes performing first correctness verification on the driving information of the image frame. In some embodiments, the driving information includes at least one of a data start instruction and a polarity indication instruction. The data start instruction is used to indicate the starting display time of the image data, and the polarity indication instruction is used to indicate the driving polarity of the image data, which includes positive polarity and negative polarity. For example, Figure 2is a schematic diagram of at least part of the content contained in an image frame provided by an embodiment of the present application, and the meaning of each instruction in the image frame is as shown in Figure 3 The driving information of the image frame can include the CS instruction and the CMD instruction as shown in Figure 2 and Figure 3 The CS instruction includes the data start instruction described above, and the CMD instruction includes the polarity indication information. Of course, the driving information of the image frame can also include other instructions, such as the CE instruction as shown in Figure 2 and Figure 3 Embodiments of the present application do not limit this.

[0033] In some embodiments, the logic control module 1120 is further configured to, when the lock signal switches from the first level to the second level, control the first mode control module 1130 to start the first identification mode for the first image frame, so as to perform the first correctness verification on the driving information of the first image frame. In some embodiments, the logic control module 1120 is further configured to, when the lock signal switches from the first level to the second level, control the first mode control module 1130 to start the first identification mode for the first row data of the first image frame, so as to perform the first correctness verification on the first row data of the first image frame. The first image frame refers to the first image frame output by the source driving chip 1100 after the lock signal switches from the first level to the second level.

[0034] Of course, in actual applications, if the source driving chip 1100 detects that the lock signal switches from the first level to the second level, the first identification mode can also be started for any one or more rows of data of the first image frame output by the source driving chip 1100 after the lock signal switches from the first level to the second level. For example, the first identification mode can be started for the second row of data of the first image frame, or the first identification mode can be started for the first row of data to the tenth row of data of the first image frame, and embodiments of the present application do not limit this. In addition, in actual applications, if the source driving chip 1100 detects that the lock signal switches from the first level to the second level, the first identification mode can also be started for any one or more image frames output by the source driving chip 1100 after the lock signal switches from the first level to the second level. For example, the first identification mode can be started for the second image frame, or the first identification mode can be started for the first image frame to the third image frame. Embodiments of the present application do not limit this.

[0035] After the source driving chip 1100 opens the first identification mode, the source driving chip 1100 continues to detect whether the target condition is met. After the target condition is met, the logic control module 1120 in the source driving chip 1100 controls the first mode control module 1130 to close the first identification mode. In some embodiments, in the case that the first identification mode is opened for the first row of data of the first image frame output by the source driving chip 1100 after the source driving chip 1100 switches the lock signal from the first level to the second level, the logic control module 1120 in the source driving chip 1100 is further configured to control the first mode control module 1130 to close the first identification mode after entering the line blanking period of the second row of data of the first image frame. The first image frame refers to the first image frame output by the source driving chip 1100 after the lock signal switches from the first level to the second level.

[0036] The line blanking period can also be referred to as a horizontal blanking (HBK) period, which refers to a time interval in which a scanning point returns from the right edge of an image frame to the left edge during a scanning process, preparing to start a new row of scanning, and is used to ensure the correct display and synchronization of each row of data in the image frame. In the embodiments of the present application, the line blanking period of the second row of data can refer to a time interval in which the first row of data is scanned and is ready to enter the scanning of the second row of data, that is, the line blanking period of the second row of data can be located before the scanning of the second row of data. After entering the line blanking period of the second row of data of the first image frame, the source driving chip 1100 closes the first identification mode, that is, the embodiments of the present application can only open the first identification mode for the first row of data of the first image frame output by the source driving chip 1100 after the lock signal switches from the first level to the second level.

[0037] Of course, in actual applications, the target condition can also have other settings, and the target condition can be flexibly set according to needs, which is not limited in the embodiments of the present application. For example, in the case that the source driving chip 1100 opens the first identification mode for the first image frame output by the source driving chip 1100 after the lock signal switches from the first level to the second level, the target condition can also be set to enter the second image frame output by the source driving chip 1100, that is, the source driving chip 1100 closes the first identification mode after entering the second image frame. For example, the target condition can be set as a target opening time length, and the source driving chip 1100 closes the first identification mode after the opening time length of the first identification mode reaches the target opening time length.

[0038] In addition to the first identification mode, the source driving chip 1100 can also open a second identification mode. In some embodiments, as Figure 1As shown, the source driving chip 1100 further includes a second mode control module 1140. The logic control module 1120 is further configured to control the second mode control module 1140 to start the second identification mode after the source driving chip 1100 is powered on. The second identification mode includes a second correctness verification on the image data of the image frame.

[0039] In some embodiments, the period of the first correctness verification in the first identification mode is less than the period of the second correctness verification in the second identification mode. For example, the first identification mode can be a Bit mode, and the second identification mode can be a Packet mode. In the first identification mode, the first mode control module 1130 in the source driving chip 1100 performs the first correctness verification on the driving information of the image frame with a period of 1 UI. In the second identification mode, the second mode control module 1140 in the source driving chip 1100 performs the second correctness verification on the image data of the image frame with a period of 9 UI. 1 UI refers to one unit period, and 9 UI refers to nine unit periods. Generally, one unit period represents the time occupied by one bit of data, i.e., one period of the clock. For example, if the data size is 2G, 1 UI is the reciprocal of 2G. Of course, in actual applications, the period of the first correctness verification on the driving information in the first identification mode can also be greater than the period of the second correctness verification on the image data in the second identification mode. The embodiments of the present application do not limit this.

[0040] In summary, in the embodiments of the present application, when the source driving chip detects that the lock signal switches from the first level to the second level, e.g., from the low level to the high level, the first identification mode is started to perform the correctness verification on the driving information of the image frame. After the target condition is met, the source driving chip stops the first identification mode and no longer performs the correctness verification on the driving information of the image frame, until the lock signal switches from the first level to the second level again. In the embodiments of the present application, the first identification mode is not in a continuous working state, but is started when the level state of the lock signal switches, and then is stopped after the target condition is met. Through the working state control of the first identification mode, the dynamic power consumption of the source driving chip is reduced, thereby reducing the energy consumption of the display device. Moreover, the embodiments of the present application can be implemented based on the existing display device, without adding new devices in the display device, and the compatibility with the existing display device is high.

[0041] Please refer to Figure 4 , Figure 4 is a flowchart of a mode control method provided by the embodiments of the present application. The mode control method can be applied to a source driving chip of a display device, such as the source driving chip 1100 described above. Figure 1The source driving chip is connected with a timing controller of the display device. As shown in Figure 4 The mode control method can include the following steps:

[0042] Step 410: When the lock signal output by the source driving chip to the timing controller is switched from the first level to the second level, the first identification mode is started, and the driving information of the image frame is subjected to the first correctness verification.

[0043] Step 420: After the target condition is met, the first identification mode is closed.

[0044] In some embodiments, the step 410 includes: when the lock signal is switched from the first level to the second level, the first identification mode is started for the first image frame. The first image frame is the first image frame output by the source driving chip after the lock signal is switched from the first level to the second level.

[0045] In some embodiments, the step 410 includes: when the lock signal is switched from the first level to the second level, the first identification mode is started for the first row data of the first image frame; and the step 420 includes: after entering the line blanking period of the second row data of the first image frame, the first identification mode is closed.

[0046] In some embodiments, the mode control method further includes: after the source driving chip is powered on, the state of the lock signal is continuously detected. The state detection includes detecting whether the lock signal is switched from the first level to the second level and detecting whether the lock signal is switched from the second level to the first level.

[0047] In some embodiments, the first level is a low level, and the second level is a high level.

[0048] In some embodiments, the driving information includes at least one of a data start instruction and a polarity indication instruction. The data start instruction is used to indicate the starting display time of the image frame, and the polarity indication instruction is used to indicate the driving polarity of the image frame.

[0049] In some embodiments, the mode control method further includes: after the source driving chip is powered on, the second identification mode is started, and the image data of the image frame is subjected to the second correctness verification.

[0050] In some embodiments, the period of the first correctness verification is less than the period of the second correctness verification.

[0051] In summary, when the source driving chip detects that the lock signal switches from the first level to the second level, such as from the low level to the high level, the first identification mode is enabled to check the correctness of the driving information of the image frame. After the target condition is met, the source driving chip closes the first identification mode and no longer checks the correctness of the driving information of the image frame until the lock signal switches from the first level to the second level again. In the embodiment of the application, the first identification mode is not in a continuous working state, but is enabled when the level state of the lock signal switches, and then is closed after the target condition is met. Through the working state control of the first identification mode, the dynamic power consumption of the source driving chip is reduced, thereby reducing the energy consumption of the display device. Moreover, the embodiment of the application can be implemented based on the existing display device without adding new devices in the display device, and the compatibility with the existing display device is high.

[0052] It should be understood that the above mode control method is a method embodiment corresponding to the above source driving chip. The detailed introduction and description of each step in the above mode control method and the beneficial effects thereof can be referred to the embodiments of the above source driving chip, which will not be described herein.

[0053] Next, the mode control method provided by the embodiment of the application is introduced and described with an example.

[0054] Please refer to Figure 5 , Figure 5 is a flowchart of another mode control method provided by the embodiment of the application. The mode control method can be applied to the source driving chip 1100 shown in Figure 1 or Figure 6 . The source driving chip 1100 is connected with the timing controller of the display device, and includes a state detection module 1110, a logic control module 1120, a first mode control module 1130 and a second mode control module 1140. As shown in Figure 6 , the first mode control module 1130 and the second mode control module 1140 in the source driving chip 1100 input a digital voltage DVDD and output a digital signal. As shown in Figure 5 , the mode control method can include the following steps 501 to 508.

[0055] Step 501: The source driving chip 1100 is powered on.

[0056] Step 502: The state detection module 1110 detects whether the lock signal switches from the low level to the high level. If yes, step 503 is performed, otherwise step 502 is continued.

[0057] Step 503: The logic control module 1120 controls the first mode control module 1130 to enable bit mode for the first row of data in the first image frame, and performs a first correctness check on the driving information of the first row of data. The first image frame refers to the first image frame output by the source driver chip 1100 after the lock signal switches from low to high level, and the driving information includes CS and CMD instructions. The bit mode can refer to the aforementioned first recognition mode. In bit mode, the first mode control module 1130 in the source driver chip 1100 performs a first correctness check on the driving information at a cycle of 1 UI.

[0058] Step 504: After the row blanking period of the second row of data in the first image frame, the logic control module 1120 controls the first mode control module 1130 to turn off the bit mode.

[0059] Step 505: The status detection module 1110 detects whether the lock signal has switched from a high level to a low level. If yes, then step 502 is executed; otherwise, step 506 is executed. Step 505 can be executed simultaneously with step 503, or it can be executed after step 504; this embodiment does not limit this.

[0060] Step 506: The logic control module 1120 controls the second mode control module 1140 to enable packet mode, performing a second correctness check on the image data of the image frame. Step 506 can be executed after step 502 or after step 503; this embodiment does not limit this. The packet mode can be the aforementioned second identification mode. In packet mode, the second mode control module 1140 in the source driver chip 1100 performs a second correctness check on the image data at a cycle of 9 UI.

[0061] like Figure 7 As shown, in related technologies, bit mode and data packet mode are enabled for each row of data in an image frame. For example... Figure 8 As shown in the embodiment of this application, when the lock signal switches from low level to high level, the first row of data of the first image frame output by the source driver chip 1100 after the lock signal switches from low level to high level is enabled in both bit mode and data packet mode, while the other rows of data in the first image frame and other image frames are enabled in only data packet mode and the bit mode is disabled.

[0062] Please see Figure 9 , Figure 9 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 9As shown, the display device 1000 includes a source driving chip 1100 and a timing controller 1200, and the source driving chip 1100 is connected with the timing controller 1200. Generally, one display device can be driven by a plurality of source driving chips 1100, and the number of source driving chips 1100 in the display device is not limited in the embodiments of the present application. Figure 9 For the convenience of description, one source driving chip 1100 is taken as an example. For the steps performed by the source driving chip 1100, the modules included and the beneficial effects that can be achieved, please refer to the following embodiments, which will not be described here.

[0063] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0064] The above describes in detail a source driving chip, a mode control method and a display device provided by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples in this paper, and the above embodiment description is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description should not be understood as the limitation of the present application.

Claims

1. A source driving chip connected with a timing controller, characterized in that, The source driving chip comprises a state detection module, a logic control module and a first mode control module. The state detection module is configured to detect whether a lock signal output by the source driving chip to the timing controller is switched from a first level to a second level. The logic control module is configured to: control the first mode control module to start a first identification mode to perform a first correctness verification on driving information of an image frame when the lock signal is switched from the first level to the second level; and control the first mode control module to stop the first identification mode after a target condition is met. The logic control module is further configured to:

2. The source driving chip according to claim 1, wherein, control the first mode control module to start the first identification mode for a first image frame when the lock signal is switched from the first level to the second level, wherein the first image frame refers to a first image frame output by the source driving chip after the lock signal is switched from the first level to the second level. The logic control module is further configured to: control the first mode control module to start the first identification mode for first row data of the first image frame when the lock signal is switched from the first level to the second level; and control the first mode control module to stop the first identification mode after a line blanking period of second row data of the first image frame.

3. The source driving chip of claim 1, wherein: the state detection module is further configured to continuously detect a state of the lock signal after the source driving chip is powered on, wherein the state detection comprises detecting whether the lock signal is switched from the first level to the second level and detecting whether the lock signal is switched from the second level to the first level.

4. The source driving chip according to claim 1, wherein, The first level is a low level and the second level is a high level.

5. The source driving chip according to claim 1, wherein, The driving information comprises at least one of a data start instruction and a polarity indication instruction, wherein the data start instruction is used to indicate a start display time of the image frame and the polarity indication instruction is used to indicate a driving polarity of the image frame.

6. The source driving chip according to claim 1, wherein, The source driving chip further comprises a second mode control module. The logic control module is further configured to control the second mode control module to start a second identification mode to perform a second correctness verification on image data of the image frame after the source driving chip is powered on.

7. The source driving chip according to claim 6, wherein, The period of the first correctness verification is less than the period of the second correctness verification.

8. A mode control method applied to a source driving chip of a display device, the source driving chip being connected with a timing controller of the display device, characterized in that, The mode control method comprises: starting a first identification mode to perform a first correctness verification on driving information of an image frame when a lock signal output by the source driving chip to the timing controller is switched from a first level to a second level; stopping the first identification mode after a target condition is met. The first identification mode is started when the lock signal output by the source driving chip to the time sequence controller is switched from the first level to the second level, and the first identification mode comprises: starting the first identification mode for a first image frame when the lock signal is switched from the first level to the second level, wherein the first image frame refers to a first image frame output by the source driving chip after the lock signal is switched from the first level to the second level.

9. The mode control method of claim 8, wherein, the starting the first identification mode for the first image frame when the lock signal is switched from the first level to the second level comprises: starting the first identification mode for first row data of the first image frame when the lock signal is switched from the first level to the second level. the closing the first identification mode after the target condition is met comprises: closing the first identification mode after entering a line blanking period of second row data of the first image frame.

10. The mode control method according to claim 8, characterized by, The method further comprises: continuously detecting a state of the lock signal after the source driving chip is powered on, wherein the state detection comprises detecting whether the lock signal is switched from the first level to the second level and detecting whether the lock signal is switched from the second level to the first level.

11. The mode control method according to claim 8, wherein The method further comprises: starting a second identification mode after the source driving chip is powered on, and performing a second correctness verification on image data of the image frame.

12. The mode control method according to claim 11, wherein The period of the first correctness verification is less than the period of the second correctness verification.

13. A display device comprising: The display device comprises the source driving chip of any one of claims 1 to 7.

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