Gate driver

Abstract

A gate driver is provided. A gate driver according to an embodiment of the inventive concept includes a plurality of stages arranged in a first direction to output a scan signal, a clock signal line supplying a clock signal to the stages, and a power supply signal line supplying a power supply to the stages, a start signal line that does not intersect the clock signal line and the power signal line and supplies a start signal to a first stage of the stages; and an end signal line that does not intersect the clock signal line, the power signal line, and the start signal line and supplies an end signal to a last stage of the stages.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0114912, filed on August 30, 2023, which is hereby incorporated by reference for all purposes as fully set forth herein. Technical Field

[0003] The inventive concept relates to a gate driver and a display device including the same. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information is becoming prominent. In response to this, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0005] The display device includes a data driver for driving data lines, a gate driver for driving scan lines, and pixels connected to the scan lines and the data lines.

[0006] The gate driver may include a plurality of stages connected interdependently. Each of the stages may be connected to a corresponding scan line to supply a scan signal. To this end, the display device may include a plurality of signal lines that provide various signals to the plurality of stages.

[0007] Because the signal lines must be electrically connected to multiple stages, the signal lines may cross to be insulated from each other. In this case, parasitic capacitance may be generated where the signal lines cross each other. Such parasitic capacitance may cause distortion such as signal delay and signal interference. Summary of the invention

[0008] An object of the inventive concept is to provide a gate driver capable of minimizing parasitic capacitance between signal lines connected to respective stages and a display device including the same.

[0009] Another object of the inventive concept is to provide a gate driver capable of minimizing ripples in a final stage and a display device including the same.

[0010] The gate driver according to the embodiment of the present invention may include: a plurality of stages arranged in a first direction to output a plurality of scan signals; a clock signal line supplying a plurality of clock signals to the plurality of stages; a power signal line supplying power to the plurality of stages; a start signal line supplying a start signal to a first stage among the plurality of stages; and an end signal line supplying an end signal to a last stage among the plurality of stages. In a plan view, the start signal line may not overlap with the end signal line, the clock signal line, and the power signal line, and in a plan view, the end signal line may not overlap with the start signal line, the clock signal line, and the power signal line.

[0011] According to an embodiment, when a start signal is supplied to a start signal line, an end signal may be supplied to an end signal line.

[0012] According to an embodiment, after the scan signal is supplied to the last stage, an end signal may be further supplied.

[0013] According to an embodiment, the clock signal line and the power signal line may be arranged between the start signal line and the end signal line in a second direction different from the first direction.

[0014] According to an embodiment, the first direction may be a direction connecting an upper side and a lower side of the gate driver, and the second direction may be a direction connecting a left side and a right side of the gate driver.

[0015] According to an embodiment, the first stage may be arranged on the upper side of the gate driver and the last stage may be arranged on the lower side of the gate driver, and the start signal line may be arranged closest to the multiple stages in the second direction, and the end signal line may be arranged farthest from the multiple stages in the second direction.

[0016] According to an embodiment, each of the multiple stages may have a first input terminal connected to a start signal line or a carry signal line of a previous stage and a second input terminal connected to an end signal line or a carry signal line of a next stage, and in each of the stages, the first input terminal may be located above the second input terminal.

[0017] According to an embodiment, the first stage may be arranged on the lower side of the gate driver and the last stage may be arranged on the upper side of the gate driver, and the start signal line may be arranged farthest from the multiple stages in the second direction, and the end signal line may be arranged closest to the multiple stages in the second direction.

[0018] According to an embodiment, each of the plurality of stages may have a first input terminal connected to a start signal line or a carry signal line of a previous stage and a second input terminal connected to an end signal line or a carry signal line of a next stage, and in each of the stages, the first input terminal may be located below the second input terminal.

[0019] According to an embodiment, each of the clock signal line and the power signal line may include a first metal layer extending in a first direction and a second metal layer extending in a second direction, and the second metal layer is located in a different layer from the first metal layer.

[0020] According to an embodiment, the start signal line and the end signal line may be formed of a first metal layer.

[0021] According to an embodiment, the start signal line and the end signal line may be formed of a second metal layer.

[0022] A display device according to an embodiment of the present invention may include: a pixel unit including pixels connected to a scan line and a data line; a data driver supplying a data signal to the data line; and a gate driver including outputting a scan signal to each level of the scan line and a signal line connected to each level. The signal line may include: a clock signal line supplying a clock signal to each level; a power signal line supplying power to each level; a start signal line supplying a start signal to the first level of each level; and an end signal line supplying an end signal to the last level of each level. In a plan view, the start signal line may not overlap with the end signal line, the clock signal line, and the power signal line, and in a plan view, the end signal line may not overlap with the start signal line, the clock signal line, and the power signal line.

[0023] According to an embodiment, when a start signal is supplied to a start signal line, an end signal may be supplied to an end signal line.

[0024] According to an embodiment, after the scan signal is supplied to the last stage, an end signal may be further supplied to the end signal line.

[0025] According to an embodiment, the clock signal line and the power signal line may be arranged between the start signal line and the end signal line.

[0026] According to an embodiment, the first stage may be arranged on the upper side of the pixel unit and the last stage may be arranged on the lower side of the pixel unit, and the start signal line may be arranged closest to each stage and the end signal line may be arranged farthest from each stage.

[0027] According to an embodiment, each of the stages may have a first input terminal connected to a start signal line or a carry signal line of a previous stage and a second input terminal connected to an end signal line or a carry signal line of a next stage, and in each of the stages, the first input terminal may be located above the second input terminal.

[0028] According to an embodiment, the first stage may be arranged on the lower side of the pixel unit and the last stage may be arranged on the upper side of the pixel unit, and the start signal line may be arranged farthest from each stage and the end signal line may be arranged closest to each stage.

[0029] According to an embodiment, each of the stages may have a first input terminal connected to a start signal line or a carry signal line of a previous stage and a second input terminal connected to an end signal line or a carry signal line of a next stage, and in each of the stages, the first input terminal may be located below the second input terminal.

[0030] The objects of the inventive concept are not limited to the above objects, and those skilled in the art can clearly understand other technical objects not mentioned from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0032] Figure 1 is a diagram illustrating a display device according to an embodiment of the inventive concept.

[0033] Figure 2 is a diagram showing an embodiment of a stage included in a gate driver.

[0034] Figure 3 According to the embodiment Figure 2 The circuit diagram of the stage circuit is shown in .

[0035] Figure 4 Is shown driving Figure 3 The waveform diagram of this level of method is shown in .

[0036] Figure 5 is a diagram illustrating a gate driver according to an embodiment of the inventive concept.

[0037] Figure 6 is a diagram illustrating a connection relationship between signal lines and stages according to an embodiment of the inventive concept.

[0038] Figure 7 is a diagram illustrating a connection relationship between signal lines and stages according to an embodiment of the inventive concept.

[0039] Figure 8 is shown to be supplied to Figure 5 Illustration of the start signal and end signal of the gate driver and the corresponding scan signal.

[0040] Fig. 9 is a diagram illustrating a gate driver according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0041] Hereinafter, various embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the inventive concept. The inventive concept may encompass various different forms and is not limited to the embodiments described herein.

[0042] In order to clearly describe the inventive concept, parts not related to the description are omitted, and throughout the specification, the same or similar components are represented by the same reference numerals. Therefore, the reference numerals described above can also be used in other drawings.

[0043] In addition, for convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore the inventive concept is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly indicate layers and regions.

[0044] In addition, in the description, the expression "same" may mean "substantially the same". That is, it may be the same enough to convince a person of ordinary skill in the art that it is the same. In other expressions, "substantially" may be omitted.

[0045] Some embodiments about functional blocks, units, and / or modules are described in the attached drawings. It should be understood by those skilled in the art that the blocks, units, and / or modules are physically implemented by logic circuits, single components, microprocessors, hard-wired circuits, memory elements, line connections, and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and optionally, driven by firmware and / or software. In addition, each block, unit, and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs certain functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of the inventive concept, blocks, units, and / or modules can be physically divided into two or more interacting single blocks, units, and / or modules. In addition, in some embodiments, without departing from the scope of the inventive concept, blocks, units, and / or modules can be physically merged into more complex blocks, units, and / or modules.

[0046] The term "connection" between two components may refer to both electrical connection and physical connection, but the inventive concept is not limited thereto. For example, "connection" used based on a circuit diagram may refer to electrical connection, and "connection" used based on a cross-sectional view and a plan view may refer to physical connection.

[0047] Although the terms first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical spirit of the present invention, the first component described below may be the second component.

[0048] Meanwhile, the inventive concept is not limited to the embodiments disclosed below, and can be modified and implemented in various forms. In addition, each of the embodiments disclosed below can be implemented alone or in combination with at least one of the other embodiments.

[0049] Figure 1is a diagram illustrating a display device according to an embodiment of the inventive concept.

[0050] refer to Figure 1 , the display device 100 according to an embodiment of the inventive concept may include a pixel unit 110 (or a display panel), a data driver 120, a gate driver 130, and a timing controller 140. The above components may be implemented as separate integrated circuits, and two or more of the above components may be integrated and implemented as one integrated circuit. In addition, the gate driver 130 may be formed within the pixel unit 110.

[0051] The data lines DL1 to DLm may be arranged to extend in a first direction DR1. For example, the first direction DR1 may be a direction connecting the upper side and the lower side of the pixel unit 110 (or the gate driver 130). Alternatively, the first direction DR1 may be a direction connecting the left side and the right side of the pixel unit 110, or may refer to a different direction.

[0052] The scan lines SL1 to SLn may be arranged to extend in a second direction DR2. The second direction DR2 may be a direction perpendicular to the first direction DR1. The second direction DR2 may be a direction connecting the left and right sides of the pixel unit 110 (or the gate driver 130). Alternatively, the second direction DR2 may be a direction connecting the upper and lower sides of the pixel unit 110, or may refer to a different direction.

[0053] The pixel unit 110 may include pixels PX connected to scan lines SL1, SL2, ..., and SLn and data lines DL1, DL2, ..., and DLm, where n and m may be natural numbers. As an example, the pixels PX may be arranged in various known ways.

[0054] When a scan signal is supplied to the scan lines SL1 to SLn, the pixels PX may be selected in units of horizontal lines (as an example, the pixels PX connected to the same scan line may be classified into one horizontal line (or pixel row)). The pixel PX selected by the scan signal may receive a data signal from a data line (any one of DL1 to DLm) connected to the pixel PX. The pixel PX receiving the data signal may generate light having a predetermined brightness according to the voltage of the data signal.

[0055] The data driver 120 may receive the output data Dout and the data driving signal DCS from the timing controller 140. The data driving signal DCS may include a sampling signal and / or a timing signal required for driving the data driver 120. The data driver 120 may generate a data signal based on the data driving signal DCS and the output data Dout. As an example, the data driver 120 may generate an analog data signal based on the grayscale of the output data Dout.

[0056] The gate driver 130 may receive a scan driving signal SCS from the timing controller 140. The scan driving signal SCS may include at least one scan start signal and a clock signal required for driving the gate driver 130. The gate driver 130 may generate a scan signal by shifting the scan start signal in response to the clock signal, and then supply the scan signal to the scan lines SL1 to SLn.

[0057] The gate driver 130 may include a plurality of stages, each connected to the scan lines SL1 to SLn. Each stage may include a shift register, and each of the stages may supply a scan signal to the scan line (any one of SL1 to SLn) connected to the stage while a scan start signal is shifted.

[0058] In an embodiment, the gate driver 130 may be formed together with the pixel PX during the process of forming the pixel unit 110. For example, the gate driver 130 may be an oxide semiconductor thin film transistor gate driver circuit (OSG) type or an amorphous silicon thin film transistor gate driver circuit (ASG) type, and may be formed within the pixel unit 110.

[0059] The timing controller 140 may receive input data Din and a control signal CS from the host system through an interface. As an example, the timing controller 140 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS may include various signals including a clock signal.

[0060] The timing controller 140 may generate a scan driving signal SCS and a data driving signal DCS based on the control signal CS. The scan driving signal SCS and the data driving signal DCS may be supplied to the gate driver 130 and the data driver 120, respectively.

[0061] The timing controller 140 may rearrange the input data Din to match the specification of the display device 100. In addition, the timing controller 140 may correct the input data Din to generate the output data Dout and supply the output data Dout to the data driver 120. In an embodiment, the timing controller 140 may correct the input data Din in response to an optical measurement result measured during a process.

[0062] In an embodiment of the inventive concept, the display device 100 may include a flat display device, a curved display device in which a portion of the pixel unit 110 is bent, a flexible display device that can be partially folded or bent, and a stretchable display device that can be partially stretched.

[0063] In an embodiment of the present inventive concept, the display device 100 may be a device that displays a moving image or a still image, and may include portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation, and UMPCs (ultra mobile PCs). In an embodiment of the present inventive concept, the display device 100 may include electronic devices such as televisions, laptops, monitors, billboards, and Internet of Things (IoT).

[0064] Figure 2 is a diagram showing an embodiment of a stage included in a gate driver. As an example, Figure 2 A level located on the i-th horizontal line is shown.

[0065] refer to Figure 2 , the stage STi according to an embodiment of the inventive concept may include a first input terminal IN1, a second input terminal IN2, a first power input terminal VIN1, a second power input terminal VIN2, a clock input terminal CK, a first output terminal Gout, and a second output terminal Cout.

[0066] The first input terminal IN1 can receive the carry signal CRi-1 (or the start signal STP) of the previous stage (see Figure 8 ). When the carry signal CRi-1 of the previous stage is input to the first input terminal IN1, the stage STi may output the scan signal SSi to the first output terminal Gout and output the carry signal CRi to the second output terminal Cout.

[0067] The second input terminal IN2 can receive the carry signal CRi+1 (or the end signal ENP) of the next stage (see Figure 8 ). When the carry signal CRi+1 of the next stage is input to the second input terminal IN2, the stage STi may stop outputting the scan signal SSi and the carry signal CRi.

[0068] The clock input terminal CK can receive the first clock signal CLK1 (or the second clock signal CLK2) (see Figure 4 ). As an example, the clock input terminal CK included in the odd (or even) stage may receive the first clock signal CLK1, and the clock input terminal CK included in the even (or odd) stage may receive the second clock signal CLK2. That is, the first clock signal CLK1 and the second clock signal CLK2 may be alternately input to each stage of each horizontal line.

[0069] The first power input terminal VIN1 may receive a voltage of a first power supply VSS1. The second power input terminal VIN2 may receive a voltage of a second power supply VSS2. The first power supply VSS1 and the second power supply VSS2 may have a gate-off voltage. As an example, a transistor receiving a voltage of the first power supply VSS1 or the second power supply VSS2 through a gate electrode may be set to a disconnected state.

[0070] The first output terminal Gout may output a scan signal SSi. The second output terminal Cout may output a carry signal CRi. The carry signal CRi may be supplied to a previous stage and a next stage.

[0071] Figure 3 According to the embodiment Figure 2 The circuit diagram of the stage circuit is shown in .

[0072] refer to Figure 3 , the stage STi according to an embodiment of the inventive concept may include a pull-up unit 200 , a pull-down unit 202 , a controller 204 , and an output unit 206 .

[0073] The pull-up unit 200 may control a voltage of a first node Q1 (Q node) in response to an (i-1)th carry signal CRi-1. To this end, the pull-up unit 200 may include a first transistor M1.

[0074] The first electrode and the gate electrode of the first transistor M1 may be connected to the first input terminal IN1, and the second electrode of the first transistor M1 may be connected to the first node Q1. That is, the first transistor M1 may be connected in the form of a diode and may be turned on when the (i-1)th carry signal CRi-1 is supplied to the first input terminal IN1.

[0075] The output unit 206 may output the scan signal SSi through the first output terminal Gout and the carry signal CRi through the second output terminal Cout in response to the voltages of the first node Q1 and the second node Q2 based on the first clock signal CLK1 supplied to the clock input terminal CK. To this end, the output unit 206 may include second to sixth transistors M2 to M6 and a second capacitor C2.

[0076] A first electrode of the second transistor M2 may be connected to the clock input terminal CK, and a second electrode of the second transistor M2 may be connected to the second output terminal Cout. A gate electrode of the second transistor M2 may be connected to the first node Q1. The second transistor M2 may be turned on and off in response to a voltage of the first node Q1 to control the connection between the clock input terminal CK and the second output terminal Cout.

[0077] A first electrode of the third transistor M3 may be connected to the second output terminal Cout, and a second electrode of the third transistor M3 may be connected to the second power input terminal VIN2. A gate electrode of the third transistor M3 may be connected to the second node Q2. The third transistor M3 may be turned on and off in response to a voltage of the second node Q2 to control the connection between the second output terminal Cout and the second power input terminal VIN2.

[0078] A first electrode of the fourth transistor M4 may be connected to the clock input terminal CK, and a second electrode of the fourth transistor M4 may be connected to the first output terminal Gout. A gate electrode of the fourth transistor M4 may be connected to the first node Q1. The fourth transistor M4 may be turned on and off in response to a voltage of the first node Q1 to control the connection between the clock input terminal CK and the first output terminal Gout.

[0079] A first electrode of the fifth transistor M5 may be connected to the first output terminal Gout, and a second electrode of the fifth transistor M5 may be connected to the first power input terminal VIN1. A gate electrode of the fifth transistor M5 may be connected to the second node Q2. The fifth transistor M5 may be turned on and off in response to a voltage of the second node Q2 to control the connection between the first output terminal Gout and the first power input terminal VIN1.

[0080] A first electrode of the sixth transistor M6 may be connected to the first output terminal Gout, and a second electrode of the sixth transistor M6 may be connected to the first power input terminal VIN1. A gate electrode of the sixth transistor M6 may be connected to the second input terminal IN2. The sixth transistor M6 may be turned on when the (i+1)th carry signal CRi+1 is supplied to electrically connect the first output terminal Cout and the first power input terminal VIN1.

[0081] The second capacitor C2 may be connected between the first node Q1 and the first output terminal Gout. The second capacitor C2 may be used as a boost capacitor. In other words, when the fourth transistor M4 is turned on, the second capacitor C2 may increase the voltage of the first node Q1 in response to the increase in the voltage of the first output terminal Gout. Accordingly, the fourth transistor M4 may stably maintain a turned-on state.

[0082] The controller 204 may control the voltage of the second node Q2 in response to the first clock signal CLK1 supplied to the clock input terminal CK. To this end, the controller 204 may include seventh to tenth transistors M7 to M10.

[0083] A first electrode and a gate electrode of the seventh transistor M7 may be connected to the clock input terminal CK, and a second electrode of the seventh transistor M7 may be connected to a first electrode of the eighth transistor M8 and a gate electrode of the ninth transistor M9. The seventh transistor M7 may be connected in the form of a diode and may be turned on when the first clock signal CLK1 is supplied to the clock input terminal CK.

[0084] A first electrode of the eighth transistor M8 may be connected to a second electrode of the seventh transistor M7, and a second electrode of the eighth transistor M8 may be connected to the second power input terminal VIN2. A gate electrode of the eighth transistor M8 may be connected to the second output terminal Cout. The eighth transistor M8 may be turned on when the carry signal CRi is supplied to the second output terminal Cout.

[0085] A first electrode of the ninth transistor M9 may be connected to the clock input terminal CK, and a second electrode of the ninth transistor M9 may be connected to the second node Q2. A gate electrode of the ninth transistor M9 may be connected to the second electrode of the seventh transistor M7. The ninth transistor M9 may be turned on and off in response to a voltage supplied from the seventh transistor M7 to control the connection between the clock input terminal CK and the second node Q2.

[0086] A first electrode of the tenth transistor M10 may be connected to the second node Q2, and a second electrode of the tenth transistor M10 may be connected to the second power input terminal VIN2. A gate electrode of the tenth transistor M10 may be connected to the second output terminal Cout. The tenth transistor M10 may be turned on when the carry signal CRi is supplied to the second output terminal Cout.

[0087] The pull-down unit 202 may control the voltage of the first node Q1 and the second output terminal Cout in response to the voltage of the second node Q2 and the (i+1)th carry signal CRi+1 supplied to the second input terminal IN2. To this end, the pull-down unit 202 may include eleventh to fifteenth transistors M11 to M15 and a first capacitor C1.

[0088] The eleventh transistor M11 and the twelfth transistor M12 may be connected in series between the first node Q1 and the second power input terminal VIN2. The gate electrodes of the eleventh transistor M11 and the twelfth transistor M12 may be connected to the second input terminal IN2. The eleventh transistor M11 and the twelfth transistor M12 may be turned on when the (i+1)th carry signal CRi+1 is supplied to electrically connect the first node Q1 and the second power input terminal VIN2. In addition, since the transistors M11 and M12 are connected in series between the first node Q1 and the second power input terminal VIN2, the voltage between the first node Q1 and the second power input terminal VIN2 can be divided, and thus the life characteristics can be improved.

[0089] The thirteenth transistor M13 and the fourteenth transistor M14 may be connected in series between the first node Q1 and the second power input terminal VIN2. The gate electrodes of the thirteenth transistor M13 and the fourteenth transistor M14 may be connected to the second node Q2. The thirteenth transistor M13 and the fourteenth transistor M14 may be turned on and off in response to the voltage of the second node Q2 to control the electrical connection between the first node Q1 and the second power input terminal VIN2. In addition, since the transistors M13 and M14 are connected in series between the first node Q1 and the second power input terminal VIN2, the voltage between the first node Q1 and the second power input terminal VIN2 can be divided, and thus the life characteristics can be improved.

[0090] A first electrode of the fifteenth transistor M15 may be connected to the second output terminal Cout, and a second electrode of the fifteenth transistor M15 may be connected to the second power input terminal VIN2. A gate electrode of the fifteenth transistor M15 may be connected to the second input terminal IN2. The fifteenth transistor M15 may be turned on when the (i+1)th carry signal CRi+1 is supplied to electrically connect the second output terminal Cout and the second power input terminal VIN2. A first electrode of the first capacitor C1 may be connected to the first node Q1, and a second electrode of the first capacitor C1 may be connected to the second input terminal IN2.

[0091] Figure 4 Is shown driving Figure 3 The waveform diagram of the method of one stage shown in . In the following description, the expression "supplying a clock signal, a carry signal, etc." may refer to supplying a gate-on voltage. In addition, the expression "supply of a clock signal, a carry signal, etc." may refer to supplying a gate-off voltage.

[0092] refer to Figure 4 First, during the first period T1, the (i-1)th carry signal CRi-1 may be supplied to the first input terminal IN1. When the (i-1)th carry signal CRi-1 is supplied, the first transistor M1 may be turned on. When the first transistor M1 is turned on, the (i-1)th carry signal CRi-1 may be supplied to the first node Q1.

[0093] When the (i-1)th carry signal CRi-1 is supplied to the first node Q1, the second transistor M2 and the fourth transistor M4 may be turned on. When the second transistor M2 and the fourth transistor M4 are turned on, the first output terminal Gout and the second output terminal Cout may be electrically connected to the clock input terminal CK.

[0094] In the second period T2, the first clock signal CLK1 may be supplied to the clock input terminal CK. In this case, since the second transistor M2 and the fourth transistor M4 are set to be in a conducting state, the first clock signal CLK1 supplied to the clock input terminal CK may be supplied to the first output terminal Gout and the second output terminal Cout. Here, the first clock signal CLK1 supplied to the first output terminal Gout may be supplied to the scan line as the scan signal SSi. In addition, the first clock signal CLK1 supplied to the second output terminal Cout may be supplied to the previous stage and the next stage as the i-th carry signal CRi.

[0095] Meanwhile, during the second period T2, the voltage of the first node Q1 may increase to a voltage higher than that of the first clock signal CLK1 due to the boosting of the second capacitor C2. Accordingly, the second transistor M2 and the fourth transistor M4 may be stably maintained in a turned-on state.

[0096] In addition, during the second period T2, the eighth transistor M8 and the tenth transistor M10 can be turned on by the i-th carry signal CRi supplied to the second output terminal Cout. When the eighth transistor M8 is turned on, the voltage of the second power supply VSS2 can be supplied to the gate electrode of the ninth transistor M9. When the tenth transistor M10 is turned on, the voltage of the second power supply VSS2 can be supplied to the second node Q2. Accordingly, during the second period T2, the second node Q2 can be set to the voltage of the second power supply VSS2, and accordingly, the third transistor M3 can remain in a disconnected state.

[0097] Meanwhile, during the second period T2, when the first clock signal CLK1 is supplied to the clock input terminal CK, the seventh transistor M7 may be turned on. Here, the seventh transistor M7 may be connected in the form of a diode. Accordingly, when the seventh transistor M7 and the eighth transistor M8 have similar channel widths, the voltage of the gate electrode of the ninth transistor M9 may be reduced to the voltage of the second power supply VSS2. In addition, even if the ninth transistor M9 is turned on, the second node Q2 may stably maintain the voltage of the second power supply VSS2 through the tenth transistor M10.

[0098] In the third period T3, the (i+1)th carry signal CRi+1 may be supplied to the second input terminal IN2. When the (i+1)th carry signal CRi+1 is supplied to the second input terminal IN2, the sixth transistor M6, the eleventh transistor M11, the twelfth transistor M12, and the fifteenth transistor M15 may be turned on.

[0099] When the sixth transistor M6 is turned on, the voltage of the first power supply VSS1 from the first power supply input terminal VIN1 can be supplied to the first output terminal Gout. When the fifteenth transistor M15 is turned on, the voltage of the second power supply VSS2 from the second power supply input terminal VIN2 can be supplied to the second output terminal Cout.

[0100] When the eleventh transistor M11 and the twelfth transistor M12 are turned on, the voltage of the second power supply VSS2 may be supplied to the first node Q1. When the voltage of the second power supply VSS2 is supplied to the first node Q1, the second transistor M2 and the fourth transistor M4 may be turned off. In this case, the voltage of the second power supply VSS2 may be supplied to the gate electrode of the fourth transistor M4, and the voltage of the first power supply VSS1 higher than the voltage of the second power supply VSS2 may be supplied to the second electrode of the fourth transistor M4. Accordingly, during the third period T3, the fourth transistor M4 may be set to a completely disconnected state.

[0101] In the fourth period T4, the first clock signal CLK1 may be supplied to the clock input terminal CK. When the first clock signal CLK1 is supplied to the clock input terminal CK, the seventh transistor M7 and the ninth transistor M9 may be turned on. When the ninth transistor M9 is turned on, the voltage of the first clock signal CLK1 may be supplied to the second node Q2.

[0102] When the first clock signal CLK1 is supplied to the second node Q2 , the third transistor M3 , the fifth transistor M5 , the thirteenth transistor M13 , and the fourteenth transistor M14 may be turned on.

[0103] When the third transistor M3 is turned on, the voltage of the second power supply VSS2 may be supplied to the second output terminal Cout. When the fifth transistor M5 is turned on, the voltage of the first power supply VSS1 may be supplied to the first output terminal Gout. When the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, the voltage of the second power supply VSS2 may be supplied to the first node Q1. When the voltage of the second power supply VSS2 is supplied to the first node Q1, the second transistor M2 and the fourth transistor M4 may be set to a disconnected state.

[0104] Basically, each of the stages according to the inventive concept may output the scan signal SS and the carry signal CR in response to the first to fourth periods T1 to T4 described above.

[0105] at the same time, Figure 2 and Figure 4The stage circuit shown in relates to an embodiment of the inventive concept, and the inventive concept is not limited thereto. As an example, the inventive concept is intended to minimize the parasitic capacitance generated by the signal line, and can be applied to various known stages driven by receiving a carry signal of the previous stage and a carry signal of the next stage.

[0106] Figure 5 is a diagram illustrating a gate driver according to an embodiment of the inventive concept. Figure 6 is a diagram illustrating a connection relationship between signal lines and stages according to an embodiment of the inventive concept.

[0107] refer to Figure 5 and Figure 6 , the gate driver 130 according to an embodiment of the inventive concept may include a plurality of signal lines 1301 to 1306 connected to the stages ST1 , ST2 , . . . , STn- 1 , and STn.

[0108] Each of the stages ST1 to STn may be connected to one of the scan lines SL1 to SLn and may be arranged along the first direction DR1. Here, the first stage ST1 may be located above the gate driver 130 (or above the pixel unit 110), and the nth stage STn may be located below the gate driver 130 (or below the pixel unit 110). In addition, in each of the stages ST1 to STn, the first input terminal IN1 may be located above the second input terminal IN2.

[0109] The first stage ST1 may refer to a stage in which a scan signal is supplied in response to a start signal STP supplied from a start signal line 1301. The nth stage STn may refer to a stage in which supply of a scan signal is stopped by an end signal ENP supplied from an end signal line 1302.

[0110] The plurality of signal lines may include a start signal line 1301 for supplying a start signal STP, an end signal line 1302 for supplying an end signal ENP, clock signal lines 1303 and 1304 for supplying clock signals CLK1 and CLK2, and power signal lines 1305 and 1306 for supplying a predetermined power source.

[0111] The start signal line 1301 may be arranged closest to the stages ST1 to STn. As an example, the start signal line 1301 may be arranged closest to the stages ST1 to STn in the second direction DR2. The start signal line 1301 may be connected to the first input terminal IN1 of the first stage ST1. Here, the start signal line 1301 may be arranged closest to the stages ST1 to STn, and therefore may not intersect with the other signal lines 1302 to 1306.

[0112] That is, Figure 6As shown in , the starting signal line 1301 may not intersect with other signal lines 1302 to 1306, and may be formed by a single metal layer without a separate contact portion. When the starting signal line 1301 does not intersect with other signal lines 1302 to 1306, parasitic capacitance may not be generated between the starting signal line 1301 and other signal lines 1302 to 1306 or the parasitic capacitance may be minimized. Accordingly, signal delay, signal interference, etc. can be minimized.

[0113] The end signal line 1302 may be arranged farthest from the stages ST1 to STn. As an example, the end signal line 1302 may be arranged farthest from the stages ST1 to STn in the second direction DR2. The end signal line 1302 may be connected to the second input terminal IN2 of the nth stage STn. Here, the end signal line 1302 may be arranged farthest from the stages ST1 to STn, and thus may not intersect with the other signal lines 1301 and 1303 to 1306.

[0114] That is, Figure 6 As shown in , the end signal line 1302 may not intersect with other signal lines 1301 and 1303 to 1306, and may be formed by a single metal layer without a separate contact portion. When the end signal line 1302 does not intersect with other signal lines 1301 and 1303 to 1306, parasitic capacitance may not be generated between the end signal line 1302 and other signal lines 1301 and 1303 to 1306 or the parasitic capacitance may be minimized. Accordingly, signal delay, signal interference, etc. can be minimized.

[0115] The clock signal lines 1303 and 1304 and the power signal lines 1305 and 1306 may be arranged in the second direction DR2 between the start signal line 1301 and the end signal line 1302. As an example, the clock signal lines 1303 and 1304 and the power signal lines 1305 and 1306 may be arranged in the second direction DR2 between the start signal line 1301 and the end signal line 1302.

[0116] The first clock signal line 1303 may supply the first clock signal CLK1 to the stages ST1 and STn-1 located on the odd (or even) horizontal lines. As an example, the first clock signal line 1303 may be connected to the clock input terminals CK of the odd stages ST1 and STn-1. To this end, the first clock signal line 1303 may include a first sub-first clock signal line 1303a and a second sub-first clock signal line 1303b, the first sub-first clock signal line 1303a being formed by a first metal layer and extending in a first direction DR1, and the second sub-first clock signal line 1303b being formed by a second metal layer located on a layer different from the first metal layer and extending in a second direction DR2. The first sub-first clock signal line 1303a and the second sub-first clock signal line 1303b may be electrically connected to each other through a first contact portion CT1.

[0117] The second clock signal line 1304 can supply the second clock signal CLK2 to the stages ST2 and STn located on the even (or odd) horizontal lines. As an example, the second clock signal line 1304 can be connected to the clock input terminals CK of the even stages ST2 and STn. To this end, the second clock signal line 1304 can include a first sub-second clock signal line 1304a and a second sub-second clock signal line 1304b, the first sub-second clock signal line 1304a is formed by the first metal layer and extends in the first direction DR1, and the second sub-second clock signal line 1304b is formed by the second metal layer and extends in the second direction DR2. The first sub-second clock signal line 1304a and the second sub-second clock signal line 1304b can be electrically connected to each other through the second contact portion CT2.

[0118] The first power signal line 1305 may supply the voltage of the first power supply VSS1 to the stages ST1 to STn. As an example, the first power signal line 1305 may be connected to the first power input terminal VIN1 of the stages ST1 to STn. To this end, the first power signal line 1305 may include a first sub-first power signal line 1305a formed by a first metal layer and extending in a first direction DR1 and a second sub-first power signal line 1305b formed by a second metal layer and extending in a second direction DR2. The first sub-first power signal line 1305a and the second sub-first power signal line 1305b may be electrically connected to each other through a third contact portion CT3.

[0119] The second power signal line 1306 may supply the voltage of the second power supply VSS2 to the stages ST1 to STn. As an example, the second power signal line 1306 may be connected to the second power input terminal VIN2 of the stages ST1 to STn. To this end, the second power signal line 1306 may include a first sub-second power signal line 1306a and a second sub-second power signal line 1306b, the first sub-second power signal line 1306a being formed by the first metal layer and extending in the first direction DR1, and the second sub-second power signal line 1306b being formed by the second metal layer and extending in the second direction DR2. The first sub-second power signal line 1306a and the second sub-second power signal line 1306b may be electrically connected to each other through the fourth contact portion CT4.

[0120] As described above, according to an embodiment of the present invention, the start signal line 1301 may be arranged to be closest to the stages ST1 to STn in the second direction DR2, and the end signal line 1302 may be arranged to be farthest from the stages ST1 to STn in the second direction DR2. Accordingly, the start signal line 1301 and the end signal line 1302 may not intersect with other signal lines 1303 to 1306. Therefore, signal distortion of the start signal and the end signal can be prevented. In addition, the number and type of the signal lines 1303 to 1306 arranged between the start signal line 1301 and the end signal line 1302 may vary according to the type of the stage.

[0121] In an embodiment, the start signal line 1301 and the end signal line 1302 may be formed by a first metal layer. In another embodiment, the start signal line 1301 and the end signal line 1302 may be formed by a second metal layer. That is, since the start signal line 1301 and the end signal line 1302 do not intersect with other signal lines 1303 to 1306, the start signal line 1301 and the end signal line 1302 can be formed by the first metal layer and / or the second metal layer, thereby ensuring freedom in design.

[0122] Figure 7 1 is a diagram showing the connection relationship between signal lines and stages according to an embodiment of the inventive concept. Figure 7 , will omit Figure 6 The same components as shown in the figure are described repeatedly.

[0123] refer to Figure 7 , the gate driver 130 may include a plurality of signal lines 1301 to 1306 connected to the stages ST1 , ST2 , . . . , STn- 1 , and STn.

[0124] The plurality of signal lines may include a start signal line 1301 for supplying a start signal STP, an end signal line 1302 for supplying an end signal ENP, clock signal lines 1303 and 1304 for supplying clock signals CLK1 and CLK2, and power signal lines 1305 and 1306 for supplying a predetermined power source.

[0125] The start signal line 1301 may be arranged closest to the stages ST1 to STn. As an example, the start signal line 1301 may be arranged closest to the stages ST1 to STn in the second direction DR2. The start signal line 1301 may be connected to the first input terminal IN1 of the first stage ST1. Here, the start signal line 1301 may be arranged closest to the stages ST1 to STn, and thus may not intersect with the other signal lines 1302 to 1306.

[0126] In an embodiment, the start signal line 1301 may include a first sub-start signal line 1301a formed of a first metal layer and extending in a first direction DR1, and a second sub-start signal line 1301b formed of a second metal layer and extending in a second direction DR2. The first sub-start signal line 1301a and the second sub-start signal line 1301b may be electrically connected to each other through a contact portion CTS.

[0127] The end signal line 1302 may be arranged farthest from the stages ST1 to STn. As an example, the end signal line 1302 may be arranged farthest from the stages ST1 to STn in the second direction DR2. The end signal line 1302 may be connected to the second input terminal IN2 of the nth stage STn. Here, the end signal line 1302 may be arranged farthest from the stages ST1 to STn, and thus may not intersect with the other signal lines 1301 and 1303 to 1306.

[0128] In an embodiment, the end signal line 1302 may include a first sub-end signal line 1302a formed by a first metal layer and extending in a first direction DR1, and a second sub-end signal line 1302b formed by a second metal layer and extending in a second direction DR2. The first sub-end signal line 1302a and the second sub-end signal line 1302b may be electrically connected to each other through a contact portion CTE.

[0129] Figure 8 is shown to be supplied to Figure 5 Illustration of the start signal and end signal of the gate driver and the corresponding scan signal.

[0130] refer to Figure 8, when the start signal STP is supplied to the first stage ST1, the scan signals SS1, SS2, SS3, ..., SSn-1 and SSn may be supplied to the scan lines SL1 to SLn from the stages ST1 to STn in sequence. After the scan signal SSn is supplied from the last stage STn, the end signal ENP may be supplied. The end signal ENP may be supplied to the second input terminal IN2 of the last stage STn. When the end signal ENP is supplied, the supply of the scan signal from the last stage STn may be stopped.

[0131] Meanwhile, in an embodiment of the present inventive concept, the end signal ENP may be additionally supplied to the last stage STn in synchronization with the start signal STP (or at least partially overlapped with the start signal STP). In more detail, during a blank period after the scan signal SSn is supplied from the last stage STn, the gate driver 130 may be set to a disconnected state. As an example, during the blank period, the clock signals CLK1 and CLK2 may not be supplied to the gate driver 130.

[0132] Afterwards, when the gate driver 130 is driven and the end signal ENP is supplied to the last stage STn in synchronization with the start signal STP, the last stage STn may be initialized. In this case, ripples or the like may be prevented from occurring in the last stage STn.

[0133] Fig. 9 1 is a diagram showing a gate driver according to an embodiment of the inventive concept. Fig. 9 , will omit Figures 5 to 7 Duplicate description.

[0134] refer to Fig. 9 , the gate driver 130 may include a plurality of signal lines 1301 c , 1302 c , and 1303 to 1306 connected to the stages ST1 , ST2 , . . . , STn- 1 , and STn.

[0135] Each of the stages ST1 to STn may be connected to one of the scan lines SL1 to SLn and may be arranged along the first direction DR1. Here, the first stage ST1 may be located below the gate driver 130 (or below the pixel unit 110), and the nth stage STn may be located above the gate driver 130 (or above the pixel unit 110). In addition, in each of the stages ST1 to STn, the second input terminal IN2 may be located above the first input terminal IN1.

[0136] The first stage ST1 may refer to a stage in which a scan signal is supplied in response to a start signal STP supplied from a start signal line 1301c. The nth stage STn may refer to a stage in which supply of a scan signal is stopped by an end signal ENP supplied from an end signal line 1302c.

[0137] The plurality of signal lines may include a start signal line 1301c for supplying a start signal STP, an end signal line 1302c for supplying an end signal ENP, clock signal lines 1303 and 1304 for supplying clock signals CLK1 and CLK2, and power signal lines 1305 and 1306 for supplying a predetermined power source.

[0138] The starting signal line 1301c may be arranged to be the farthest from the stage ST1 to STn. As an example, the starting signal line 1301c may be arranged to be the farthest from the stage ST1 to STn in the second direction DR2. The starting signal line 1301c may be connected to the first input terminal IN1 of the first stage ST1. Here, the starting signal line 1301c may be arranged to be the farthest from the stage ST1 to STn, and thus may not intersect with other signal lines 1302c and 1303 to 1306. When the starting signal line 1301c does not intersect with other signal lines 1302c and 1303 to 1306, parasitic capacitance may not be generated between the starting signal line 1301c and other signal lines 1302c and 1303 to 1306 or the parasitic capacitance may be minimized. Accordingly, signal delay, signal interference, etc. can be minimized.

[0139] The end signal line 1302c may be arranged to be closest to the stage ST1 to STn. As an example, the end signal line 1302c may be arranged to be closest to the stage ST1 to STn in the second direction DR2. The end signal line 1302c may be connected to the second input terminal IN2 of the nth stage STn. Here, the end signal line 1302c may be arranged to be closest to the stage ST1 to STn, and thus may not intersect with other signal lines 1301c and 1303 to 1306. When the end signal line 1302c does not intersect with other signal lines 1301c and 1303 to 1306, parasitic capacitance may not be generated between the end signal line 1302c and other signal lines 1301c and 1303 to 1306 or the parasitic capacitance may be minimized. Accordingly, signal delay, signal interference, etc. can be minimized.

[0140] The clock signal lines 1303 and 1304 and the power signal lines 1305 and 1306 may be arranged between the start signal line 1301c and the end signal line 1302c. As an example, the clock signal lines 1303 and 1304 and the power signal lines 1305 and 1306 may be arranged between the start signal line 1301c and the end signal line 1302c in the second direction DR2.

[0141] According to the gate driver of the embodiment of the present invention and the display device including the gate driver, the start signal line supplying the start signal can be arranged to be closest to or farthest from the stage, and the end signal line supplying the end signal can be arranged to be farthest from or closest to the stage. Therefore, the intersection between the signal lines can be minimized, and thus signal distortion can be prevented.

[0142] However, the effects of the inventive concept are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the inventive concept.

[0143] As described above, the preferred embodiments of the inventive concept have been described with reference to the accompanying drawings. However, those skilled in the art will appreciate that various modifications and changes can be made to the inventive concept without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A gate driver, comprising: a plurality of stages arranged in a first direction to output a plurality of scan signals; a clock signal line for supplying a plurality of clock signals to the plurality of stages; a power signal line for supplying power to the plurality of stages; a start signal line for supplying a start signal to a first stage among the plurality of stages; as well as an end signal line for supplying an end signal to a last stage among the plurality of stages, Wherein, in a plan view, the start signal line does not overlap with the end signal line, the clock signal line, and the power signal line, and Wherein, in a plan view, the end signal line does not overlap with the start signal line, the clock signal line, and the power signal line.

2. The gate driver according to claim 1, wherein: When the start signal is supplied to the start signal line, the end signal is supplied to the end signal line.

3. The gate driver according to claim 2, wherein: After the scan signal is supplied to the last stage, the end signal is further supplied.

4. The gate driver according to claim 1, wherein: The clock signal line and the power signal line are arranged between the start signal line and the end signal line in a second direction different from the first direction.

5. The gate driver according to claim 4, wherein: The first direction is a direction connecting an upper side and a lower side of the gate driver, and the second direction is a direction connecting a left side and a right side of the gate driver.

6. The gate driver according to claim 4, wherein: The first stage is arranged on an upper side of the gate driver, and the last stage is arranged on a lower side of the gate driver, and The start signal line is arranged to be closest to the plurality of stages in the second direction, and the end signal line is arranged to be farthest from the plurality of stages in the second direction.

7. The gate driver according to claim 6, wherein: Each of the plurality of stages has a first input terminal connected to the start signal line or a carry signal line of a previous stage and a second input terminal connected to the end signal line or a carry signal line of a next stage, and Wherein, in each of the plurality of stages, the first input terminal is located above the second input terminal.

8. The gate driver according to claim 4, wherein: The first stage is arranged on the lower side of the gate driver, and the last stage is arranged on the upper side of the gate driver, and The start signal line is arranged to be farthest from the plurality of stages in the second direction, and the end signal line is arranged to be closest to the plurality of stages in the second direction.

9. The gate driver according to claim 8, wherein: Each of the plurality of stages has a first input terminal connected to the start signal line or a carry signal line of a previous stage and a second input terminal connected to the end signal line or a carry signal line of a next stage, and Wherein, in each of the plurality of stages, the first input terminal is located below the second input terminal.

10. The gate driver according to claim 4, wherein: Each of the clock signal line and the power signal line includes a first metal layer extending in the first direction and a second metal layer extending in the second direction, and wherein the second metal layer is located in a different layer from the first metal layer, and The start signal line and the end signal line are formed by the first metal layer, or Wherein, the start signal line and the end signal line are formed by the second metal layer.

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