Cholesteric LCD display screen image display device based on FPGA

Abstract

The invention discloses a cholesteric LCD display screen image display device based on an FPGA, and the device comprises an image updating module which is used for converting received image bitmap data into RGB pixel data and transmitting the RGB pixel data to an image processing module; the image processing module is used for receiving the RGB pixel data and storing the RGB pixel data to the BRAM; the time sequence control module is used for acquiring a resolution score, generating a field synchronization signal and a line synchronization signal of one frame of image according to the resolution score, and transmitting the field synchronization signal and the line synchronization signal to the image processing module and the source electrode control signal generation module; and the mode selection module is also used for generating a mode selection signal according to the working mode of the control system and transmitting the mode selection signal to the source control signal generation module. According to the display device, multi-gray-scale display of the cholesteric LCD display screen can be effectively controlled, the display efficiency and the response speed are improved, and meanwhile good expandability and flexibility are achieved.

Description

Technical Field

[0001] The present invention relates to the field of LCD display technology, and in particular to a cholesteric LCD display screen image display device based on FPGA. Background Art

[0002] FPGA devices have been widely used in the field of digital signal processing due to their highly flexible programmability, high-speed data processing capabilities and low power consumption. At present, the interface protocols for image display based on FPGA mainly include DP, HDMI, DVI, VGA, etc. These technologies are widely used in various display devices, including but not limited to computer monitors, televisions, projectors, etc. However, in specific applications, such as cholesteric LCD display screens, these traditional technologies have encountered challenges. In the prior art, the FPGA-based cholesteric LCD display screen image display system can only display two grayscales, which greatly limits the quality and application scope of image display. Summary of the invention

[0003] In order to solve the technical problems existing in the background technology, the present invention proposes a cholesteric LCD display screen image display device based on FPGA.

[0004] The present invention proposes a device for realizing a cholesteric LCD display screen image display based on FPGA, comprising:

[0005] An image updating module, used for converting received image bitmap data into RGB pixel data and then forwarding it to the image processing module;

[0006] An image processing module, used for receiving RGB pixel data and storing the RGB pixel data in BRAM;

[0007] A timing control module, used to obtain a resolution score, generate a field synchronization signal and a line synchronization signal of a frame of image according to the resolution score, and transmit the field synchronization signal and the line synchronization signal to the image processing module and the source control signal generation module; and also used to generate a mode selection signal according to the working mode of the control system, and transmit the mode selection signal to the source control signal generation module;

[0008] The image processing module is also used to generate a read address according to the field synchronization signal and the line synchronization signal, read out the corresponding RGB pixel data from the BRAM according to the read address and output it to the source control signal generation module;

[0009] The source control signal generation module is used to generate a source driving signal for driving a cholesteric LCD display screen according to a mode selection signal, a field synchronization signal, a line synchronization signal, RGB pixel data and a preset grayscale division strategy.

[0010] Preferably, the preset grayscale division strategy specifically includes:

[0011] Dividing each pixel of the cholesteric LCD display screen into regions so that each pixel corresponds to n display regions;

[0012] Allocating display control signals to the n display areas one by one, so that the n display areas correspond to the n display control signals;

[0013] The RGB value corresponding to the current pixel is obtained from the RGB pixel data, and n display control signals are driven and controlled according to the specific numerical value of the RGB value to realize the cholesteric LCD display screen to display N grayscales; wherein N=2 n , n is greater than or equal to 1, and n is a natural number.

[0014] Preferably, the n display areas specifically include a first area A, a second area B and a third area C; the driving and controlling of the n display control signals according to the specific numerical values ​​of the RGB values ​​to realize the cholesteric LCD display screen displaying N grayscales specifically includes:

[0015] According to the specific numerical values ​​of the RGB values, the display instructions corresponding to the first area A, the second area B and the third area C of the current pixel point are determined to realize the cholesteric LCD display screen to display 8 gray levels, and the display instructions include lighting and not lighting.

[0016] Preferably, the source driving signal includes an output control data signal DATA, a source clock output signal SCLK, an image latch enable signal LE, and a cascade control signal STL; the output control data signal DATA specifically includes n display control signals.

[0017] Preferably, the timing control module is further used to transmit the field synchronization signal and the line synchronization signal to the gate control signal generation module.

[0018] Preferably, it also includes:

[0019] The gate control signal generating module is used to generate a gate driving signal for driving the cholesteric LCD display screen according to the mode selection signal, the field synchronization signal and the line synchronization signal, wherein the gate driving signal includes a gate clock output signal GCLK and a cascade control signal STV.

[0020] Preferably, the timing control module is further used to transmit the mode selection signal, the field synchronization signal and the line synchronization signal to the PWM signal generation module.

[0021] Preferably, it also includes:

[0022] The PWM signal generation module is used to generate a PWM signal according to a mode selection signal and a field synchronization signal to control the power supply circuit in the cholesteric LCD display screen to output a voltage in a corresponding working mode.

[0023] Preferably, the working modes include an image update mode, a screen refresh mode and an image display mode.

[0024] In the present invention, the proposed FPGA-based cholesteric LCD display screen image display device divides each pixel of the cholesteric LCD display screen into regions so that each pixel corresponds to n display regions, and then controls the n display regions to display multiple grayscales on the cholesteric LCD display screen. The grayscale display of the cholesteric LCD display screen can be effectively controlled, the display efficiency and response speed are improved, and the device has good scalability and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the device architecture of the cholesteric LCD display screen image display device based on FPGA proposed by the present invention;

[0026] Figure 2 Schematic diagram of pixel area division of the cholesteric LCD display screen image display device based on FPGA proposed by the present invention Figure 1 ;

[0027] Figure 3 This is a schematic diagram of the structure of the output control data signal DATA of the cholesteric LCD display screen image display device based on FPGA proposed by the present invention;

[0028] Figure 4 Schematic diagram of pixel area division of the cholesteric LCD display screen image display device based on FPGA proposed by the present invention Figure 2 . DETAILED DESCRIPTION

[0029] Reference Figure 1-4 The present invention proposes a device for realizing a cholesteric LCD display screen image display based on FPGA, comprising:

[0030] The image updating module is used to convert the received image bitmap data into RGB pixel data and then forward it to the image processing module.

[0031] In this embodiment, the image update module receives the image bitmap data sent by the SPI.

[0032] The image processing module is used to receive RGB pixel data and store the RGB pixel data into BRAM.

[0033] The timing control module is used to obtain the resolution score, and generate the field synchronization signal and the line synchronization signal of a frame of image according to the resolution score, and transmit the field synchronization signal and the line synchronization signal to the image processing module and the source control signal generation module; it is also used to generate a mode selection signal according to the working mode of the control system, and transmit the mode selection signal to the source control signal generation module.

[0034] The timing control module is also used to transmit the field synchronization signal and the line synchronization signal to the gate control signal generation module.

[0035] The timing control module is also used to transmit the mode selection signal, the field synchronization signal and the line synchronization signal to the PWM signal generation module.

[0036] In this embodiment, the timing control module generates a field synchronization signal and a line synchronization signal of a frame of image, controls each module to generate the required signal, and then drives the cholesteric LCD display screen to realize image display. Because the system can adapt to different resolutions, the module can receive resolution parameters to generate field synchronization and line synchronization signals of different resolutions; in addition, the timing control module outputs a mode selection signal to control the working mode of the system.

[0037] The image processing module is also used to generate a read address according to the field synchronization signal and the line synchronization signal, read out the corresponding RGB pixel data from the BRAM according to the read address and output it to the source control signal generation module.

[0038] The source control signal generation module is used to generate a source driving signal for driving a cholesteric LCD display screen according to a mode selection signal, a field synchronization signal, a line synchronization signal, RGB pixel data and a preset grayscale division strategy.

[0039] In this embodiment, the source driving signal includes an output control data signal DATA, a source clock output signal SCLK, an image latch enable signal LE, and a cascade control signal STL; the output control data signal DATA specifically includes n display control signals.

[0040] In this embodiment, the preset grayscale division strategy specifically includes: dividing each pixel of the cholesteric LCD display screen into regions so that each pixel corresponds to n display regions; allocating display control signals to the n display regions one by one so that the n display regions correspond to n display control signals; obtaining the RGB value corresponding to the current pixel from the RGB pixel data, and driving and controlling the n display control signals according to the specific numerical value of the RGB value, so as to realize the cholesteric LCD display screen to display N grayscales; wherein N=2 n , n is greater than or equal to 1, and n is a natural number.

[0041] In this embodiment, the n display areas specifically include a first area A, a second area B, and a third area C; and the n display control signals are driven and controlled according to the specific numerical values ​​of the RGB values ​​to realize that the cholesteric LCD display screen displays N grayscales, specifically including:

[0042] According to the specific numerical values ​​of the RGB values, the display instructions corresponding to the first area A, the second area B and the third area C of the current pixel point are determined to realize the cholesteric LCD display screen to display 8 gray levels, and the display instructions include lighting and not lighting.

[0043] Specifically, Figure 2 As shown, different combinations of areas between the first area A, the second area B, and the third area C light up to display different grayscales, with a total of 8 grayscales. For example: when the RGB value is less than the first threshold, A, B, and C are not lit, when RGB is greater than or equal to the first threshold and less than the second threshold, A is lit, B and C are not lit, ..., when RGB is greater than or equal to the eighth threshold, ABC are all lit. Among them, the values ​​corresponding to the first threshold, the second threshold, ... the eighth threshold gradually increase. For example, the first threshold is 32, the second threshold is 64, and the eighth threshold is 224.

[0044] Since one pixel is displayed by three regions, a 3-bit wide signal source ([s3 s2 s1]) is defined in the FPGA to control the output DATA signal. Figure 3 shown.

[0045] Specifically, Figure 4 As shown, since a pixel is displayed by four areas, different combinations of areas between the first area A, the second area B, the third area C and the fourth area D will display different grayscales, with a total of 16 grayscales. If a pixel is divided into four display areas, specifically the first area A, the second area B, the third area C and the fourth area D; different combinations of areas will display different grayscales, with a total of 16 grayscales. For example, when RGB is less than 16, A, B, C, and D are not lit; when RGB is greater than or equal to 16 and less than 32, A is lit, B, C, and D are not lit, ..., when RGB is greater than or equal to 16 and less than 224, A is not lit, B, C, and D are all lit, and when RGB is greater than or equal to 240, A, B, C, and D are all lit.

[0046] In this embodiment, it also includes:

[0047] The gate control signal generating module is used to generate a gate driving signal for driving the cholesteric LCD display screen according to the mode selection signal, the field synchronization signal and the line synchronization signal. The gate driving signal includes a gate clock output signal GCLK and a cascade control signal STV.

[0048] The PWM signal generation module is used to generate a PWM signal according to a mode selection signal and a field synchronization signal to control the power supply circuit in the cholesteric LCD display screen to output a voltage in a corresponding working mode.

[0049] In this embodiment, the working modes include an image update mode, a screen refresh mode and an image display mode.

[0050] Specifically, when the working mode is the image update mode, the image update module receives the image bitmap data that needs to be updated through the SPI interface, converts the image bitmap data into RGB pixel data according to the bitmap protocol and outputs it to the image processing module. After the image processing module generates a write address, it stores the RGB image bitmap data in the BRAM, and the image update is completed.

[0051] Specifically, when the working mode is the screen refresh mode, due to the particularity of the screen, the screen refresh mode is entered first each time the image is refreshed. The PWM signal generation module first outputs the maximum positive voltage control signal to the screen, then outputs the maximum negative voltage control signal, and then outputs a 0V voltage control signal. The duration of each voltage control signal is the same as one frame of signal refresh time.

[0052] Specifically, when the working mode is the image display mode, the timing control module generates a field synchronization signal and a line synchronization signal, the image processing module generates a read address according to the field synchronization signal and the line synchronization signal, reads out the corresponding RGB pixel data from the BRAM and outputs it to the source control signal generation module; the source control signal generation module generates STL, LE, DATA, and SCLK signals for driving the cholesteric LCD display screen according to the field synchronization signal, the line synchronization signal, and the RGB pixel data; at the same time, the gate control signal generation module generates GCLK and STV signals for driving the cholesteric LCD display screen according to the field synchronization signal and the line synchronization signal; the PWM signal generation module provides the screen with a control signal for the image display voltage.

[0053] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. Implementing a cholesteric LCD display screen image display device based on FPGA, characterized in that: include: An image updating module, used for converting received image bitmap data into RGB pixel data and then forwarding it to the image processing module; An image processing module, used for receiving RGB pixel data and storing the RGB pixel data in BRAM; A timing control module, used to obtain a resolution score, generate a field synchronization signal and a line synchronization signal of a frame of image according to the resolution score, and transmit the field synchronization signal and the line synchronization signal to the image processing module and the source control signal generation module; and also used to generate a mode selection signal according to the working mode of the control system, and transmit the mode selection signal to the source control signal generation module; The image processing module is also used to generate a read address according to the field synchronization signal and the line synchronization signal, read out the corresponding RGB pixel data from the BRAM according to the read address and output it to the source control signal generation module; The source control signal generation module is used to generate a source driving signal for driving a cholesteric LCD display screen according to a mode selection signal, a field synchronization signal, a line synchronization signal, RGB pixel data and a preset grayscale division strategy.

2. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 1, characterized in that: The preset grayscale division strategy specifically includes: Dividing each pixel of the cholesteric LCD display screen into regions so that each pixel corresponds to n display regions; Allocating display control signals to the n display areas one by one, so that the n display areas correspond to the n display control signals; The RGB value corresponding to the current pixel is obtained from the RGB pixel data, and n display control signals are driven and controlled according to the specific numerical value of the RGB value to realize the cholesteric LCD display screen to display N grayscales; wherein N=2 n , n is greater than or equal to 1, and n is a natural number.

3. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 2, characterized in that: The n display areas specifically include a first area A, a second area B, and a third area C; the n display control signals are driven and controlled according to the specific numerical values ​​of the RGB values ​​to realize the cholesteric LCD display screen displaying N grayscales, specifically including: According to the specific numerical values ​​of the RGB values, the display instructions corresponding to the first area A, the second area B and the third area C of the current pixel point are determined to realize the cholesteric LCD display screen to display 8 gray levels, and the display instructions include lighting and not lighting.

4. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 2, characterized in that: The source driving signal includes an output control data signal DATA, a source clock output signal SCLK, an image latch enable signal LE, and a cascade control signal STL; the output control data signal DATA specifically includes n display control signals.

5. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 1, characterized in that: The timing control module is also used to transmit the field synchronization signal and the line synchronization signal to the gate control signal generation module.

6. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 5, characterized in that: Also includes: The gate control signal generating module is used to generate a gate driving signal for driving the cholesteric LCD display screen according to the mode selection signal, the field synchronization signal and the line synchronization signal, wherein the gate driving signal includes a gate clock output signal GCLK and a cascade control signal STV.

7. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 6, characterized in that: The timing control module is also used to transmit the mode selection signal, the field synchronization signal and the line synchronization signal to the PWM signal generation module.

8. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 7, characterized in that: Also includes: The PWM signal generation module is used to generate a PWM signal according to a mode selection signal and a field synchronization signal to control the power supply circuit in the cholesteric LCD display screen to output a voltage in a corresponding working mode.

9. The device for realizing cholesteric LCD display screen image display based on FPGA according to claim 8, characterized in that: The working modes include an image updating mode, a screen refreshing mode and an image display mode.

Images