Management of program disturb in memory devices

Abstract

Exemplary memory devices, memory systems, and methods for reducing programming interference in NAND flash memory are disclosed. An exemplary method includes: applying a first voltage to a first word line coupled to the first memory cell at a first time point and during a channel preparation period of programming operation of a first memory cell in a memory cell array; applying a second voltage to the first word line at a second time point after the first time point and during the channel preparation period, wherein the second voltage is lower than the first voltage; and applying a programming voltage to the first word line after the channel preparation period and during programming operation of the first memory cell.

Description

Technical Field

[0001] This disclosure relates to memory devices, memory systems, and methods for reducing programming interference in flash memory. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed on flash memory, such as programming (write) and erasing operations, thereby changing the threshold voltage of each memory cell to a corresponding level. For NAND flash memory, erasing operations can be performed at the block level, programming operations at the page level, and reading operations at the page level. Summary of the Invention

[0003] This disclosure relates to memory devices, memory systems, and methods for reducing programming interference in NAND flash memory. An exemplary method includes applying a first voltage to a first word line coupled to the first memory cell at a first time point and during a channel preparation period of programming operation of a first memory cell in a memory cell array. At a second time point after the first time point and during the channel preparation period, a second voltage is applied to the first word line, wherein the second voltage is lower than the first voltage. After the channel preparation period and during programming operation of the first memory cell, a programming voltage is applied to the first word line.

[0004] Although generally described as computer-implemented software embodied in tangible media for processing and transforming corresponding data, some or all of these aspects may be computer-implemented methods or further incorporated into a corresponding system or other apparatus to perform the described functions. Details of these and other aspects and embodiments of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will become apparent from these descriptions, drawings, and claims. Attached Figure Description

[0005] Figure 1 An example of a schematic diagram of a memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0006] Figure 2 An example of a side view of a cross-section of a memory cell array including NAND memory strings, according to some aspects of this disclosure, is shown.

[0007] Figure 3 Some exemplary peripheral circuits according to some aspects of this disclosure are shown.

[0008] Figure 4An exemplary memory cell stack comprising multiple decks of memory cells is shown according to some aspects of this disclosure.

[0009] Figure 5A Some aspects of this disclosure are shown. Figure 4 During the programming of memory cells in stack 2 Figure 4 An example of the voltage of components in a stack of memory cells.

[0010] Figure 5B Some aspects of this disclosure are shown. Figure 4 During the programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in a memory cell stack.

[0011] Figure 5C Some aspects of this disclosure are shown. Figure 4 During the programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in a memory cell stack.

[0012] Figure 6 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack, wherein stack 1 has memory cells selected for programming.

[0013] Figure 7A Some aspects of this disclosure are shown. Figure 6 During the programming of memory cells in stack 1 Figure 6 An example of the voltage of components in a stack of memory cells.

[0014] Figure 7B Some aspects of this disclosure are shown. Figure 6 During the programming of memory cells in stack 1 Figure 6 Another example of the voltage of components in a stack of memory cells.

[0015] Figure 7C Some aspects of this disclosure are shown. Figure 6 During the programming of memory cells in stack 1 Figure 6 Another example of the voltage of components in a stack of memory cells.

[0016] Figure 8 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack, wherein stack 0 has memory cells selected for programming.

[0017] Figure 9ASome aspects of this disclosure are shown. Figure 8 During the programming of memory cells in stack 0 Figure 8 An example of the voltage of components in a stack of memory cells.

[0018] Figure 9B Some aspects of this disclosure are shown. Figure 8 During the programming of memory cells in stack 0 Figure 8 Another example of the voltage of components in a stack of memory cells.

[0019] Figure 9C Some aspects of this disclosure are shown. Figure 8 During the programming of memory cells in stack 0 Figure 8 Another example of the voltage of components in a stack of memory cells.

[0020] Figure 10A Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 2 Figure 4 An example of the voltage of components in a stack of memory cells.

[0021] Figure 10B Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in a stack of memory cells.

[0022] Figure 10C Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in a stack of memory cells.

[0023] Figure 11A Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 1 Figure 4 An example of the voltage of components in a stack of memory cells.

[0024] Figure 11B Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 1 Figure 4 Another example of the voltage of components in a stack of memory cells.

[0025] Figure 11C Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 1 Figure 4 Another example of the voltage of components in a stack of memory cells.

[0026] Figure 12A Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 0 Figure 4 An example of the voltage of components in a stack of memory cells.

[0027] Figure 12B Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 0 Figure 4 Another example of the voltage of components in an exemplary memory cell stack.

[0028] Figure 12C Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 0 Figure 4 Another example of the voltage of components in an exemplary memory cell stack.

[0029] Figure 13 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack, wherein, during the process of programming memory cells in the memory cell stack from bottom to top, stack 0 has memory cells selected for programming.

[0030] Figure 14A The programming period of memory cells in stack 0 according to some aspects of this disclosure is shown. Figure 13 An example of the voltage of components in a stack of memory cells.

[0031] Figure 14B The programming period of memory cells in stack 0 according to some aspects of this disclosure is shown. Figure 13 Another example of the voltage of components in a stack of memory cells.

[0032] Figure 14C The programming period of memory cells in stack 0 according to some aspects of this disclosure is shown. Figure 13 Another example of the voltage of components in a stack of memory cells.

[0033] Figure 15 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack, wherein, during the process of programming the memory cells in the memory cell stack from bottom to top, stack 1 has memory cells selected for programming.

[0034] Figure 16A The programming period of memory cells in stack 1 according to some aspects of this disclosure is shown. Figure 15 An example of the voltage of components in a stack of memory cells.

[0035] Figure 16B The programming period of memory cells in stack 1 according to some aspects of this disclosure is shown. Figure 15 Another example of the voltage of components in a stack of memory cells.

[0036] Figure 16C The programming period of memory cells in stack 1 according to some aspects of this disclosure is shown. Figure 15 Another example of the voltage of components in a stack of memory cells.

[0037] Figure 17 An example flowchart of a method for reducing programming interference in a memory device according to some aspects of this disclosure is shown.

[0038] Figure 18 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0039] Figure 19A An illustration of a memory card having a memory device according to some aspects of this disclosure is shown.

[0040] Figure 19B A diagram of a solid-state drive (SSD) having a memory device is shown according to some aspects of this disclosure.

[0041] Similar reference numerals and names in the various figures denote similar elements. Detailed Implementation

[0042] This specification relates to memory devices, memory systems, methods, and media for reducing programming interference in NAND flash memory. In some cases, programming interference may be caused by hot carrier injection (HCI), in which electrons are injected into memory cells that are not selected for programming but are coupled to a word line (WLn) connected to a memory cell selected for programming. HCI may increase the threshold voltage of the unselected memory cell, thereby causing programming interference. HCI may be attributed to the large channel potential difference between the memory cell coupled to WLn and the memory cell coupled to the preceding WLn-1 in the word line programming sequence when a programming voltage is applied to WLn.

[0043] In some cases, the HCI problem described above occurs during the channel preparation period prior to the programming of memory cells, especially for NAND flash memories with a reduced gate length to gate spacing ratio (Lg / Ls) or an increased number of programming pulses. To reduce HCI-induced programming interference during the channel preparation period, a bias voltage can be applied to the specific word line during the channel preparation period without affecting the channel potential during the programming period.

[0044] Figure 1 An example of a schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically over a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and arranged vertically stacked. Each memory cell 106 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a "floating gate" type memory cell including a floating gate transistor, or a "charge trap" type memory cell including a charge trap transistor.

[0045] In some implementations, each memory cell 106 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some implementations, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC may be capable of storing two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to present a range of possible nominal memory values. In one example, if each MLC stores two bits of data, then the MLC can be programmed from an erase state to present one of three possible programming levels by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value can be used as the erase state.

[0046] like Figure 1As shown, each NAND memory string 108 may include a source select gate (SSG) 110 at its source end and a drain select gate (DSG) 112 at its drain end. SSG 110 and DSG 112 can be configured to activate the selected NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled via the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, enabling data to be read from or written to the corresponding bit line 116 via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selected voltage or deselected voltage (e.g., 0V) to the corresponding DSG 112 via one or more DSG lines 113 and / or by applying a selected voltage or deselected voltage (e.g., 0V) to the corresponding SSG 110 via one or more SSG lines 115.

[0047] like Figure 1 As shown, NAND memory strings 108 can be organized into multiple blocks 104, each of which may have a common source line 114 (e.g., coupled to the ACS). In some implementations, each block 104 is the basic data unit for an erase operation, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher), can be used to bias the source lines 114 coupled to the selected block 104 and unselected blocks 104 located in the same plane as the selected block 104. In some examples, erase operations can be performed at the half-block level, the quarter-block level, or at the level of any suitable number of blocks or suitable fractions of blocks. Memory cells 106 of adjacent NAND memory strings can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. Each word line 118 may include multiple control gates (gate electrodes) at each memory cell 106 and gate lines that couple the control gates. Figure 1 The exemplary word lines shown include pseudo WL, WL1, WL2, WL3, WL4 and WL5 located between one or more DSG lines 113 and one or more SSG lines 115.

[0048] Figure 2An example of a side view of a cross-section of a memory cell array 101 including NAND memory strings 108 is shown, according to some aspects of this disclosure. Figure 2 As shown, the NAND memory string 108 may extend vertically through the memory stack 204 above the substrate 202. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0049] The memory stack 204 may include alternating gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate, DSG 112, or SSG 110 surrounding the memory cell 106, and may extend laterally as a DSG line 113 at the top of the memory stack 204, as an SSG line 115 at the bottom of the memory stack 204, or as a word line 118 between DSG lines 113 and SSG lines 115.

[0050] Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 101 by applying voltage and / or current signals to each target memory cell in memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113, and by sensing voltage and / or current signals from each target memory cell. Peripheral circuitry 102 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some exemplary peripheral circuitry according to certain aspects of this disclosure is shown. The exemplary peripheral circuitry includes a page buffer / sensing amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface 316, and a data bus. In some examples, it may also include... Figure 3 Other peripheral circuits not shown.

[0051] Page buffer / sensor amplifier 304 can be configured to read data from memory cell array 101 and program (write) data to memory cell array 101 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store a page of programming data (write data) to be programmed into a page 120 of memory cell array 101. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal representing a data bit stored in memory cell 106 from bit line 116 during a read operation and amplify the small voltage swing to a recognizable logic level. Column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated by voltage generator 310.

[0052] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select / deselect block 104 of memory cell array 101, and to select / deselect word line 118 of block 104. The row decoder / word line driver 308 can be further configured to drive word line 118 using word line voltage generated by voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive SSG line 115 and DSG line 113. As described in detail below, the row decoder / word line driver 308 is configured to apply a read voltage to the selected word line 118 during a read operation targeting a memory cell 106 coupled to the selected word line 118.

[0053] The voltage generator 310 can be configured to be controlled by the control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages that will be provided to the memory cell array 101.

[0054] Control logic 312 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. Register 314 may be coupled to control logic 312 and includes a status register, a command register, and an address register to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. As described in detail below, the status register in register 314 may include one or more registers configured to store opening information (e.g., having an ADSV list) indicating one or more open blocks among all blocks 104 in the memory cell array 101. In some embodiments, the opening information also indicates the last programming page of each open block.

[0055] Interface 316 can be coupled to control logic 312 and act as a control buffer to buffer control commands received from the host (not shown) and forward them to control logic 312, and to buffer status information received from control logic 312 and forward it to the host. Interface 316 can also be coupled to column decoder / bit line driver 306 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and forward data to and from memory cell array 101.

[0056] Figure 4 An exemplary memory cell stack 400 comprising multiple stacks of memory cells is shown according to some aspects of this disclosure. Figure 4 The diagram illustrates three exemplary stacks of memory cells from top to bottom of stack 400: stack 2, stack 1, and stack 0. An example of stack 400 is... Figure 1 Block 104 is shown. Stack 2 (e.g., first stack) is on top of stack 1 (e.g., second stack), and stack 1 is on top of stack 0. Figure 4 Adjacent stacks are connected using inter-stack plugs (IDPs). Figure 4 In the context of stack 1, IDPDMY stack 1 represents the pseudo-word line (e.g., the fifth or sixth word line) in stack 1 and stack 2 that is adjacent to the inter-stack plug (IDP) connecting stack 1 and stack 2. Figure 4 In the IDPMY stack 0, it represents the pseudo-word line adjacent to the IDP connecting stacks 0 and 1 in stacks 0 and 1. A memory cell in stack 2 (e.g., a first memory cell) is selected for programming. Programming this memory cell is part of the process of programming the memory cell from top to bottom of the stack 400. Therefore, the memory cells above the selected memory cell in stack 2 have already been programmed. The memory cells in stack 400 can be multi-level cells, such as three-level cells (TLC). (Reference) Figure 2The programming process for memory cells in a memory cell stack proceeds from top to bottom, starting with memory cells coupled to word lines farther from the substrate 202 and moving to memory cells coupled to word lines closer to the substrate 202. Although Figure 4 Three stacks of memory cells are shown, but stack 400 may contain one or more stacks of memory cells.

[0057] Figure 5A Some aspects of this disclosure are shown. Figure 4 During the programming of memory cells in stack 2 Figure 4 An example of the voltage of components in the stack 400. In some embodiments, selected WLn represents a word line (e.g., a first word line) selected for programming operations of a memory cell (e.g., a first memory cell) in stack 2. Selected WLn can be Figure 1 Example of word line 118 in the text. WLn-1 to WLn-x represent coupling to Figure 4 Word lines (e.g., second word lines) of memory cells that have been programmed during programming from top to bottom in stack 400 in stack 2. An exemplary range of x in WLn-x can be 3 to 10. Each of WLn-1 to WLn-x can also be Figure 1 Example of word line 118. BSG (e.g., select gate line) represents one or more select gate transistors coupled to the stack body 400 (e.g., ...). Figure 1 One or more bottom select gate lines (e.g., SSG line 115) of SSG110 (e.g., source select gate transistor). BTM DMY (e.g., fourth word line) represents one or more pseudo word lines in stack 0 of stack 400 that are close to the BSG of stack 400. Other WL (e.g., third word line) represents word lines other than selected WLn, WLn-1 to WLn-x, BTM DMY, IDPDMY stack 0 and IDPDMY stack 1. ACS (e.g., source line) represents the source line connected to all memory strings in stack 400, e.g. Figure 1 Source line 114. The channel preparation period represents the time interval from t0 to t4, and is in the... Figure 4 The channel preparation period is before the programming phase in stack 2, which is coupled to the selected WLn and is selected as the memory cell to be programmed. The channel preparation period can be divided into phase 1 and phase 2, where phase 1 is from t0 to t2 and phase 2 is from t2 to t4.

[0058] In some implementations, in order to reduce Figure 4Programming interference during the programming operation of memory cells in stack 2 is mitigated by applying a voltage Vpre (e.g., a first voltage) at t1 (e.g., a first time) to selected WLn and WLn-1 to WLn-x during channel preparation phase 1. This increases the voltage of selected WLn and WLn-1 to WLn-x from Vss (e.g., a third voltage) to Vpre, thereby increasing the channel potential associated with memory cells coupled to word lines WLn-x to WLn during the channel preparation phase, and allowing memory cells coupled to word lines WLn-x to WLn to be turned on. Thus, the increased channel potential associated with memory cells coupled to word lines WLn-x to WLn can facilitate the application of programming voltage Vpgm to the selected WLn and WLn-1 to WLn-x. Figure 4 The memory cell in stack 2 is thus programmed to reduce programming interference caused by thermal current injection. An exemplary value of Vss is 0V. An exemplary range of Vpre is 0V to 3.3V. A stage 2 voltage (e.g., Vss or a value greater than 0V) is applied to selected WLn and WLn-1 to WLn-x at t2 (e.g., a second time), thereby reducing the voltage of selected WLn and WLn-1 to WLn-x from Vpre to the stage 2 voltage. An exemplary range of the stage 2 voltage from t2 to t4 can be 0V to 2V. At t4, which is the end of the channel preparation period and the beginning of the programming period for the memory cell in stack 2, a pass voltage Vpass is applied to WLn-1 to WLn-x, thereby increasing the voltage of WLn-1 to WLn-x from the stage 2 voltage (e.g., a fourth voltage) to the pass voltage Vpass. Starting at t4, the voltage of the selected WLn is first increased from the stage 2 voltage (e.g., the second voltage) to an intermediate voltage, and then increased to the programming voltage Vpgm. In some implementations, when a specific voltage is applied to a line at a specific time, it may take some time for the voltage of that line to reach that specific voltage due to the load effect associated with that line. For example, when Vpre is applied to the selected WLn at t1, it may take some time for the voltage of the selected WLn to increase from Vss to Vpre, such as... Figure 5A As shown in the diagram. In some embodiments, the voltage of the line can immediately reach the applied voltage at that specific time.

[0059] In some implementations, during the channel preparation period from t0 to t4, the voltage of the word line represented by other WLs (e.g., a fifth voltage) is maintained at Vss because memory cells coupled to the word lines represented by other WLs can remain off during the channel preparation period. During the channel preparation period, a voltage Vpre_dmy (e.g., a sixth voltage) is applied at t1 to BTM DMY, IDPDMY stack 0, and IDPDMY stack 1, thereby increasing the voltage of BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 from an initial voltage to Vpre_dmy, so that pseudo-memory cells coupled to pseudo-word lines BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 can be turned on during the channel preparation period. An exemplary value of Vpre_dmy could be 2.2V, thereby turning on the corresponding pseudo-memory cells. During phase 2 of the channel preparation period, a pseudo-line voltage is applied to BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 at time t3 (e.g., a third time), causing the voltages of BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 to decrease from Vpre-dmy to the pseudo-line voltage. t3 may be the same as t2 or t3 may be later than t2. At time t4, a through voltage Vpass is applied to BTM DMY, IDPDMY stack 0, and IDPDMY stack 1, causing the voltages of BTM DMY, IDPDMY stack 0, and IDPDMY stack 1 to increase from the pseudo-line voltage to the through voltage Vpass.

[0060] In some implementations, a turn-on voltage (e.g., a seventh voltage) is applied to the BSG at t1, thereby increasing the voltage of the BSG from Vss to the turn-on voltage to turn on the transistor coupled to the BSG, for example, Figure 1 SSG 110 in the stack 400 connects the channels of the memory strings in the stack to the ACS, for example, Figure 1 The source line 114 is in the middle. An exemplary value for the turn-on voltage is 2.2V. During phase 2 of the channel preparation period, a voltage Vss is applied to the BSG at t3, causing the voltage of the BSG to drop from the turn-on voltage to Vss.

[0061] In some implementations, during the channel preparation period from t0 to t4, the voltage of the ACS (e.g., the eighth voltage) remains at Vss, or a channel precharge voltage may be applied to the ACS at t1 to raise the voltage of the ACS from Vss to the channel precharge voltage, thereby precharging the channels of the memory strings in the stack 400. In either case, the voltage of the ACS (either Vss or the channel precharge voltage) can be used to increase the channel potential of the memory cells in the stack 400. An exemplary value for the channel precharge voltage is 2.2V.

[0062] Figure 5B Some aspects of this disclosure are shown. Figure 4 During the programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in stack 400. Except for selected WLn, the voltage conditions of most components in stack 400 (e.g., WLn-1 to WLn-x, other WLs, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to... Figure 5A The corresponding voltage conditions are equivalent. More specifically, such as Figure 5B As shown, at t2, the beginning of phase 2, which is the channel preparation period, a voltage Vpre_WLn (e.g., a second voltage) is applied to a selected WLn, causing the voltage of the selected WLn to drop from Vpre to Vpre_WLn. Figure 5A In this process, the stage 2 voltage is applied to the selected WLn at t2, causing the voltage of the selected WLn to drop from Vpre to the stage 2 voltage. Vpre_WLn can be greater than the stage 2 voltage. An exemplary range of Vpre_WLn is 0V to 3.3V.

[0063] Figure 5C Some aspects of this disclosure are shown. Figure 4 During the programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in stack 400. Except for WLn-1, the voltage conditions of most components in stack 400 (e.g., WLn-2 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to... Figure 5B The corresponding voltage conditions are equivalent. More specifically, such as Figure 5C As shown, at t2, the beginning of phase 2, which is the channel preparation period, a voltage Vpre_WLn is applied to WLn-1, causing the voltage of WLn-1 to drop from Vpre to Vpre_WLn. Figure 5B In this process, the stage 2 voltage is applied to WLn-1 at t2, causing the voltage of WLn-1 to drop from Vpre to the stage 2 voltage. In some implementations, the voltage conditions of one or more word lines from WLn-2 to WLn-x that are closer to WLn-1 can be the same as the voltage conditions of WLn-1.

[0064] Figure 6 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack 400 is shown, wherein stack 1 (but not stack 2 or stack 0) has memory cells selected for programming. The programming process of stack 400 is from top to bottom, which is consistent with... Figure 4 Same as above.

[0065] Figure 7A Some aspects of this disclosure are shown. Figure 6 During the programming of memory cells in stack 1 Figure 6 Examples of voltage conditions for components in a memory cell stack. Except for IDPDMY stack 1, the voltage conditions of most components in stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, BSG, and ACS) are similar to... Figure 5A The corresponding voltage conditions are equivalent. More specifically, given... Figure 6 In the case of the top-to-bottom programming process of the memory cells in WLn-x, when WLn-x is located Figure 6 In stack 1, since the memory cell selected for programming is located in stack 1 rather than stack 2, therefore Figure 6 The voltage condition of layer 1 of IDPDMY in the stack is determined by Figure 7A The voltage conditions for other WLs are represented as follows. When WLn-x is located in stack 2 and the selected memory cell for programming is located in stack 1, IDPDMY stack 1 is located between WLn-x and WLn, therefore the voltage conditions of IDPDMY stack 1 are equivalent to... Figure 7A The voltage conditions of BTM DMY or IDPDMY stack 0 in the stack enable the pseudo memory cells coupled to IDPDMY stack 1 to be turned on.

[0066] Figure 7B Some aspects of this disclosure are shown. Figure 6 During the programming of memory cells in stack 1 Figure 6 Another example of the voltage of components in a memory cell stack. Except for IDPDMY stack 1, the voltage conditions of most components in stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, BSG, and ACS) are similar to... Figure 5B The corresponding voltage conditions are equivalent. More specifically, given... Figure 6 In the case of the top-to-bottom programming process of the memory cells in WLn-x, when WLn-x is located Figure 6 In stack 1, since the memory cell selected for programming is located in stack 1 rather than stack 2, therefore Figure 6 The voltage condition of layer 1 of IDPDMY in the stack is determined by Figure 7BThe voltage conditions of other WLs in the stack are not represented by BTM DMY and IDPDMY stack 0. When WLn-x is located in stack 2 and the selected memory cell for programming is located in stack 1, IDPDMY stack 1 is located between WLn-x and WLn, therefore the voltage conditions of IDPDMY stack 1 are equivalent to Figure 7B The voltage conditions of the BTM DMY or IDPDMY stack 0 enable the pseudo memory cells coupled to the IDPDMY stack 1 to be turned on.

[0067] Figure 7C Some aspects of this disclosure are shown. Figure 6 During the programming of memory cells in stack 1 Figure 6 Another example of the voltage of components in a memory cell stack. Except for IDPDMY stack 1, the voltage conditions of most components in stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, BSG, and ACS) are similar to... Figure 5C The corresponding voltage conditions are equivalent. More specifically, given... Figure 6 In the case of the top-to-bottom programming process of the memory cells in WLn-x, when WLn-x is located Figure 6 In stack 1, since the memory cell selected for programming is located in stack 1 rather than stack 2, therefore Figure 6 The voltage condition of layer 1 of IDPDMY in the stack is determined by Figure 7C The voltage conditions of other WLs in the stack are not represented by BTM DMY and IDPDMY stack 0. When WLn-x is located in stack 2 and the selected memory cell for programming is located in stack 1, IDPDMY stack 1 is located between WLn-x and WLn, therefore the voltage conditions of IDPDMY stack 1 are equivalent to Figure 7C The voltage conditions of BTM DMY or IDPDMY stack 0 in the stack enable the pseudo memory cells coupled to IDPDMY stack 1 to be turned on.

[0068] Figure 8 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack 400 is shown, wherein stack 0 (but not stack 2 or stack 1) has memory cells selected for programming. The programming process of stack 400 is from top to bottom, which is consistent with... Figure 4 Same as above.

[0069] Figure 9A Some aspects of this disclosure are shown. Figure 8 During the programming of memory cells in stack 0 Figure 8Examples of voltage conditions for components in a memory cell stack. Except for IDPDMY stack 0, the voltage conditions of most components in stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 1, BSG, and ACS) are similar to... Figure 7A The corresponding voltage conditions are equivalent. More specifically, given... Figure 8 In the case of the top-to-bottom programming process of the memory cells in WLn-x, when WLn-x is located Figure 8 When in stack 0, because the memory cell selected for programming is located in stack 0 rather than stack 1, therefore Figure 8 The voltage condition of the IDPDMY stack 0 in the middle is determined by Figure 9A The voltage conditions for other WLs are represented as follows. When WLn-x is located in stack 1 and the selected memory cell for programming is located in stack 0, IDPDMY stack 0 is located between WLn-x and WLn, therefore the voltage condition of IDPDMY stack 0 is equivalent to... Figure 9A The voltage condition of BTM DMY in the middle enables the pseudo memory cell coupled to IDPDMY stack 0 to be turned on.

[0070] Figure 9B Some aspects of this disclosure are shown. Figure 8 During the programming of memory cells in stack 0 Figure 8 Another example of the voltage of components in a memory cell stack. Except for IDPDMY stack 0, the voltage conditions of most components in stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 1, BSG, and ACS) are similar to... Figure 7B The corresponding voltage conditions are equivalent. More specifically, given... Figure 8 In the case of the top-to-bottom programming process of the memory cells in WLn-x, when WLn-x is located Figure 8 When in stack 0, because the memory cell selected for programming is located in stack 0 rather than stack 1, therefore Figure 8 The voltage condition of the IDPDMY stack 0 in the middle is determined by Figure 9B The voltage conditions for other WLs are represented as follows. When WLn-x is located in stack 1 and the selected memory cell for programming is located in stack 0, IDPDMY stack 0 is located between WLn-x and WLn, therefore the voltage condition of IDPDMY stack 0 is equivalent to... Figure 9B The voltage condition of BTM DMY enables the pseudo memory cell coupled to IDPDMY stack 0 to be turned on.

[0071] Figure 9C Some aspects of this disclosure are shown. Figure 8 During the programming of memory cells in stack 0 Figure 8 Another example of the voltage of components in a memory cell stack. Except for IDPDMY stack 0, the voltage conditions of most components in stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 1, BSG, and ACS) are similar to... Figure 7C The corresponding voltage conditions are equivalent. More specifically, given... Figure 8 In the case of the top-to-bottom programming process of the memory cells in WLn-x, when WLn-x is located Figure 8 When in stack 0, because the memory cell selected for programming is located in stack 0 rather than stack 1, therefore Figure 8 The voltage condition of the IDPDMY stack 0 in the middle is determined by Figure 9C The voltage conditions for other WLs are represented as follows. When WLn-x is located in stack 1 and the selected memory cell for programming is located in stack 0, IDPDMY stack 0 is located between WLn-x and WLn, therefore the voltage condition of IDPDMY stack 0 is equivalent to... Figure 9C The voltage condition of BTM DMY in the middle enables the pseudo memory cell coupled to IDPDMY stack 0 to be turned on.

[0072] In some implementations... Figure 4 The memory cells in the stack 400 may include multi-level memory cells, such as quad-level memory cells (QTC). Programming operations on the memory cells in the stack 400 may include coarse programming and fine programming of the memory cells. Coarse programming can be used in conjunction with fine programming to achieve a strict threshold distribution without unduly slowing down the programming process of the memory cells. In the coarse programming stage, the threshold voltage used to program the memory cells can be increased in a faster manner, while in the fine programming stage, the threshold voltage can be increased in a slower manner to reach the target threshold voltage, while simultaneously achieving a stricter threshold distribution.

[0073] In some implementations... Figures 5A to 5C , Figures 7A to 7A as well as Figures 9A to 9C The voltage conditions shown and described above can be applied to the coarse programming of memory cells in the stack 400. More specifically, Figure 5A , Figure 5B or Figure 5C The voltage conditions shown can be applied to the coarse programming of memory cells in stack 2 of stack 400. Figure 7A , Figure 7B or Figure 7CThe voltage conditions shown can be applied to the coarse programming of memory cells in stack 1 of stack 400, and Figure 9A , Figure 9B or Figure 9C The voltage conditions shown can be applied to the coarse programming of memory cells in stack 0 of stack 400.

[0074] In some implementations, for fine programming of memory cells coupled to a selected WLn within the stack 400, in Figure 5A During the channel preparation period from t0 to t4, the voltage condition of word line WLn+1 (e.g., the seventh word line) can be the same as the voltage condition of a selected WLn during the channel preparation period, rather than the voltage conditions of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of the memory cell coupled to the selected WLn. WLn+1 is a word line coupled to an unprogrammed memory cell (e.g., the second memory cell) and is located immediately below the selected WLn for programming.

[0075] In some implementations... Figure 10A This illustrates the fine-tuning of memory cells in stack 2 of stack 400 according to some aspects of this disclosure. Figure 4 An example of the voltage of components in the stack 400. Figure 10A The example in [example name] refers to the fine programming of memory cells in stack 2 of stack 400 after coarse programming of memory cells in stack 2. Besides WLn+1, Figure 10A The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 5A The corresponding voltage conditions are equivalent. For example... Figure 10A As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period. This enables the memory cell coupled to WLn+1 to be turned on during the channel preparation period, thereby further reducing programming interference during fine programming of the memory cell coupled to selected WLn.

[0076] Figure 10B Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in the stack 400. Besides WLn+1, Figure 10BThe voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 5B The corresponding voltage conditions are equivalent. For example... Figure 10B As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0077] Figure 10C Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in the stack 400. Besides WLn+1, Figure 10C The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 5C The corresponding voltage conditions are equivalent. For example... Figure 10C As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0078] Figure 11A This illustrates the fine-tuning of memory cells in stack 1 of stack 400 according to some aspects of this disclosure. Figure 4 An example of the voltage of components in the stack 400. Besides WLn+1, Figure 11A The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 7A The corresponding voltage conditions are equivalent. For example... Figure 11A As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0079] Figure 11BSome aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 1 Figure 4 Another example of the voltage of components in the stack 400. Besides WLn+1, Figure 11B The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 7B The corresponding voltage conditions are equivalent. For example... Figure 11B As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0080] Figure 11C Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 1 Figure 4 Another example of the voltage of components in the stack 400. Besides WLn+1, Figure 11C The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 7C The corresponding voltage conditions are equivalent. For example... Figure 11C As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0081] Figure 12A This illustrates the fine programming of memory cells in stack 0 of stack body 400 according to some aspects of this disclosure. Figure 4 An example of the voltage of components in the stack 400. Besides WLn+1, Figure 12A The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 9A The corresponding voltage conditions are equivalent. For example... Figure 12AAs shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0082] Figure 12B Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in the stack 400. Besides WLn+1, Figure 12B The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 9B The corresponding voltage conditions are equivalent. For example... Figure 12B As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0083] Figure 12C Some aspects of this disclosure are shown. Figure 4 During fine programming of memory cells in stack 2 Figure 4 Another example of the voltage of components in the stack 400. Besides WLn+1, Figure 12C The voltage conditions of most of the components in the stack 400 shown (e.g., selected WLn, WLn-1 to WLn-x, other WL, BTM DMY, IDPDMY stack 0, IDPDMY stack 1, BSG, and ACS) are similar to those of the components in the stack 400 shown. Figure 9C The corresponding voltage conditions are equivalent. For example... Figure 12C As shown, the voltage condition of word line WLn+1 during the channel preparation period is the same as the voltage condition of selected WLn during the channel preparation period, rather than the voltage condition of other WLs during the channel preparation period, thereby further reducing programming interference during fine programming of memory cells coupled to selected WLn.

[0084] As mentioned above, Figures 5A to 5C , Figures 7A to 7C as well as Figures 9A to 12C This illustrates the process of programming memory cells in stack 400 from top to bottom. Figure 4The voltage conditions of the components in the stack 400. When programming the memory cells in the stack 400 from bottom to top, with certain exceptions, it can also be done according to... Figures 5A to 5C , Figures 7A to 7C as well as Figures 9A to 12C The voltage conditions of the components in the stack 400 are illustrated in a similar manner. (See reference...) Figure 2 The programming process of memory cells in the memory cell stack proceeds from bottom to top, starting with memory cells coupled to word lines closer to the substrate 202 and moving to memory cells coupled to word lines further away from the substrate 202.

[0085] More specifically, when programming the memory cells in the stack 400 from bottom to top, Figures 5A to 5C , Figures 7A to 7C as well as Figures 9A to 12C The voltage conditions of the BSG in each of them can be applied to the TSG in the stack 400. Figures 5A to 5C , Figures 7A to 7C as well as Figures 9A to 12C The voltage conditions of the ACS in each of them can be applied to the bit lines (BL) of the stack 400 and Figures 5A to 5C , Figures 7A to 7C as well as Figures 9A to 12C The voltage condition of the BTM DMY in each of the stacks can be applied to the TOP DMY of the stack body 400. TSG represents coupling to one or more select gate transistors (e.g., Figure 1 One or more select gate lines (e.g., DSG line 113) in DSG 112. BL represents a bit line in the stack 400, for example, Figure 1 Bit line 116 in the stack. TOP DMY represents the topmost pseudoword line in stack 2 of stack 400.

[0086] For example, Figure 13 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack 400 is provided, wherein, during the process of programming memory cells in the stack 400 from bottom to top, the stack 0 has memory cells selected for programming.

[0087] Figure 14A The programming period of memory cells in stack 0 according to some aspects of this disclosure is shown. Figure 13 Examples of voltages for components in stack 400. Besides TSG, BL, and TOP DMY, Figure 13 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, IDPDMY stack 0, and IDPDMY stack 1) are related to Figure 5A The corresponding voltage conditions are equivalent. In some implementations, WLn is selected to represent the word line selected for programming operations on memory cells in stack 0. WLn can be... Figure 1 Example of word line 118 in the text. WLn-1 to WLn-x represent coupling to Figure 13 Word lines of memory cells that have been programmed during programming from bottom to top in stack 400 in stack 0. An exemplary range of x in WLn-x can be 3 to 10. Each of WLn-1 to WLn-x can also be Figure 1 Example of word line 118 in Chinese. For Figure 13 Regarding the voltage conditions of TSG, BL, and TOP DMY of the stack 400, since the memory cells in the stack 0 are selected for programming during the process of programming the memory cells in the stack 400 from the bottom to the top of the stack 400, therefore Figure 5A The voltage conditions of BSG in the text can be applied to Figure 13 The stack of 400 TSGs in the middle, Figure 5A The voltage conditions of ACS in the data can be applied to Figure 13 The stacked volume 400 BL, and Figure 5A The voltage conditions of BTM DMY in the code can be applied to Figure 13 The TOP DMY of the stacked volume 400.

[0088] Figure 14B The programming period of memory cells in stack 0 according to some aspects of this disclosure is shown. Figure 13 Another example of the voltage of components in the stack 400. Besides TSG, BL, and TOP DMY, Figure 13 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, IDPDMY stack 0, and IDPDMY stack 1) are related to Figure 5B The corresponding voltage conditions are equivalent. More specifically, since the memory cells in stack 0 are selected for programming during the process of programming the memory cells in stack 400 from bottom to top, therefore Figure 5B The voltage conditions of BSG in the text can be applied to Figure 13 The stack of 400 TSGs in the middle, Figure 5B The voltage conditions of ACS in the data can be applied to Figure 13 The stacked volume 400 BL, and Figure 5B The voltage conditions of BTM DMY in the code can be applied to Figure 13 The TOP DMY of the stacked volume 400.

[0089] Figure 14CThe programming period of memory cells in stack 0 according to some aspects of this disclosure is shown. Figure 13 Another example of the voltage of components in the stack 400. Besides TSG, BL, and TOP DMY, Figure 13 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL, IDPDMY stack 0, and IDPDMY stack 1) are related to Figure 5C The corresponding voltage conditions are equivalent. More specifically, since the memory cells in stack 0 are selected for programming during the process of programming the memory cells in stack 400 from bottom to top, therefore Figure 5C The voltage conditions of BSG in the text can be applied to Figure 13 The stack of 400 TSGs in the middle, Figure 5C The voltage conditions of ACS in the data can be applied to Figure 13 The stacked volume 400 BL, and Figure 5C The voltage conditions of BTM DMY in the code can be applied to Figure 13 The TOP DMY of the stacked volume 400.

[0090] As another example, Figure 15 Some aspects of this disclosure are shown. Figure 4 An exemplary memory cell stack 400 is provided, wherein, during the process of programming the memory cells in the stack 400 from bottom to top, the stack 1 has memory cells selected for programming.

[0091] Figure 16A The programming period of memory cells in stack 1 according to some aspects of this disclosure is shown. Figure 15 Examples of voltages for components in stack 400. Besides TSG, BL, and TOP DMY, Figure 15 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL and IDPDMY stack 1) are related to Figure 7A The corresponding voltage conditions are equivalent. More specifically, since the memory cells in stack 1 are selected for programming during the process of programming the memory cells in stack 400 from bottom to top, therefore Figure 7A The voltage conditions of BSG in the text can be applied to Figure 15 The stack of 400 TSGs in the middle, Figure 7A The voltage conditions of ACS in the data can be applied to Figure 15 The stacked volume 400 BL, and Figure 7A The voltage conditions of BTM DMY in the code can be applied to Figure 15The stack of 400 TOPDMYs.

[0092] Figure 16B The programming period of memory cells in stack 1 according to some aspects of this disclosure is shown. Figure 15 Another example of the voltage of components in the stack 400. Besides TSG, BL, and TOP DMY, Figure 15 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL and IDPDMY stack 1) are related to Figure 7B The corresponding voltage conditions are equivalent. More specifically, since the memory cells in stack 1 are selected for programming during the process of programming the memory cells in stack 400 from bottom to top, therefore Figure 7B The voltage conditions of BSG in the text can be applied to Figure 15 The stack of 400 TSGs in the middle, Figure 7B The voltage conditions of ACS in the data can be applied to Figure 15 The stacked volume 400 BL, and Figure 7B The voltage conditions of BTM DMY in the code can be applied to Figure 15 The stack of 400 TOPDMYs.

[0093] Figure 16C The programming period of memory cells in stack 1 according to some aspects of this disclosure is shown. Figure 15 Another example of the voltage of components in the stack 400. Besides TSG, BL, and TOP DMY, Figure 15 The voltage conditions of most components of the stack 400 (e.g., selected WLn, WLn-1 to WLn-x, other WL and IDPDMY stack 1) are related to Figure 7C The corresponding voltage conditions are equivalent. More specifically, since the memory cells in stack 1 are selected for programming during the process of programming the memory cells in stack 400 from bottom to top, therefore Figure 7C The voltage conditions of BSG in the text can be applied to Figure 15 The stack of 400 TSGs in the middle, Figure 7C The voltage conditions of ACS in the data can be applied to Figure 15 The stacked volume 400 BL, and Figure 7C The voltage conditions of BTM DMY in the code can be applied to Figure 15 The stack of 400 TOPDMYs.

[0094] Figure 17An example flowchart of a method for reducing programming interference in a memory device according to some aspects of this disclosure is shown. At 1702, the peripheral circuitry of the memory device applies a first voltage to a first word line coupled to the first memory cell at a first time and during the channel preparation period of a programming operation of a first memory cell in the memory cell array.

[0095] At 1704, the peripheral circuit applies a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage.

[0096] At 1706, the peripheral circuitry applies a programming voltage to the first word line after the channel preparation period and during the programming operation of the first memory cell.

[0097] Figure 18 A block diagram of an exemplary system 1800 having a memory device according to some aspects of this disclosure is shown. System 1800 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other electronic device having storage components located therein. Figure 18 As shown, system 1800 may include a host 1808 and a memory system 1802, the memory system 1802 having one or more memory devices 1804 and a memory controller 1806. The host 1808 may be a processor of an electronic device, such as a central processing unit (CPU), or it may be a system-on-a-chip (SoC), such as an application processor (AP). The host 1808 may be configured to send or receive data to or from the memory device 1804.

[0098] Memory device 1804 can be any memory device disclosed in this disclosure. According to some embodiments, memory controller 1806 is coupled to memory device 1804 and host 1808 and is configured to control memory device 1804. Memory controller 1806 can manage data stored in memory device 1804 and communicate with host 1808. In some embodiments, memory controller 1806 is designed to operate in a low-duty environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 1806 is designed to operate in a high-duty environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablet computers, laptop computers, etc., and for enterprise storage arrays. Memory controller 1806 can be configured to control the operation of memory device 1804, such as read, erase, and program operations. The memory controller 1806 may also be configured to manage various functions relating to data stored in or to be stored in the memory device 1804, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the memory controller 1806 is further configured to process error correction codes (ECC) relating to data read from or written to the memory device 1804. The memory controller 1806 may also perform any other suitable functions, such as formatting the memory device 1804.

[0099] The memory controller 1806 can communicate with external devices (e.g., host 1808) according to a specific communication protocol. For example, the memory controller 1806 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0100] The memory controller 1806 and one or more memory devices 1804 can be integrated into various types of memory devices, for example, contained in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 1802 can be implemented and packaged into different types of end electronic products. Figure 19AIn one example shown, the memory controller 1806 and a single memory device 1804 can be integrated into a memory card 1902. The memory card 1902 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1902 may further include a connection between the memory card 1902 and a host computer (e.g., Figure 18 The memory card connector 1904 is coupled to the host (1808) in the memory card. In such a... Figure 19B In another example shown, the memory controller 1806 and multiple memory devices 1804 can be integrated into the SSD 1906. The SSD 1906 may further include interfaces between the SSD 1906 and a host (e.g., Figure 18 The SSD connector 1908 is coupled to the host 1808 in the memory card 1902. In some embodiments, the storage capacity and / or operating speed of the SSD 1906 is higher than that of the memory card 1902.

[0101] Certain aspects of the subject matter described herein can be implemented as a memory device. The memory device includes a memory cell array and peripheral circuitry. The memory cell array includes memory cells. The peripheral circuitry is coupled to the memory cell array and configured to perform operations, wherein, in order to perform these operations, the peripheral circuitry is configured to apply a first voltage to a first word line coupled to the first memory cell at a first time and during a channel preparation period of programming operation of a first memory cell in the memory cell array; apply a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage; and apply a programming voltage to the first word line after the channel preparation period and during programming operation of the first memory cell.

[0102] The memory device may include one or more of the following features.

[0103] In some implementations, the first voltage is lower than the programming voltage.

[0104] In some implementations, the peripheral circuitry is further configured to apply a third voltage to the first word line before a first time, wherein the third voltage is lower than the first voltage.

[0105] In some implementations, the third voltage is lower than or equal to the second voltage.

[0106] In some embodiments, the peripheral circuitry is further configured to: apply a first voltage to a second word line coupled to one or more memory cells in the memory cell array at a first time, wherein each of the one or more memory cells is a programmed memory cell; and apply a fourth voltage to the second word line at a second time.

[0107] In some implementations, the first voltage is lower than the pass voltage to be applied to the second word line after the second time.

[0108] In some implementations, the fourth voltage is lower than or equal to the second voltage.

[0109] In some embodiments, the peripheral circuitry is further configured to apply a fifth voltage to the third word line before applying a pass voltage to the third word line, wherein the third word line is coupled to one or more memory cells in the memory cell array, and each of the one or more memory cells is an unprogrammed memory cell.

[0110] In some implementations, the fifth voltage is lower than the pass voltage.

[0111] In some embodiments, the peripheral circuit is further configured to: apply a sixth voltage to a fourth word line coupled to a memory cell adjacent to a select gate transistor at a first time, wherein the select gate transistor is coupled to the source line of the memory cell array, the sixth voltage is higher than a third voltage and the fourth word line is a first pseudo word line; and apply a third voltage to the fourth word line at a third time after the second time.

[0112] In some embodiments, the peripheral circuitry is further configured to: apply a seventh voltage to the select gate line coupled to the select gate transistor at a first time, wherein the seventh voltage is higher than a third voltage; and apply a third voltage to the select gate line at a third time.

[0113] In some implementations, the peripheral circuitry is further configured to apply an eighth voltage to the source line of the memory cell array at a first time.

[0114] In some implementations, the eighth voltage is equal to the third voltage.

[0115] In some embodiments, the memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack being adjacent to the second stack, the first memory cell being located in the first stack, and the peripheral circuitry being further configured to apply a sixth voltage at a first time to a fifth word line of the memory cell in the first stack that is closest to the second stack, wherein the fifth word line is a second pseudo-word line.

[0116] In some implementations, the peripheral circuitry is further configured to apply the sixth voltage to the sixth word line of the memory cell closest to the first stack in the second stack at a first time, wherein the sixth word line is the third pseudo-word line.

[0117] In some implementations, the first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

[0118] In some embodiments, the first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine programming operation, and the peripheral circuitry is further configured to apply a first voltage to a seventh word line of a second memory cell coupled to the memory cell array at a first time, wherein the seventh word line is adjacent to the first word line; and to apply a second voltage to the seventh word line at a second time.

[0119] Certain aspects of the subject matter described herein can be implemented as a memory system. The memory system includes a memory device and a controller. The memory device includes a memory cell array and peripheral circuitry. The memory cell array includes memory cells. The peripheral circuitry is coupled to the memory cell array and configured to perform operations, wherein, in order to perform these operations, the peripheral circuitry is configured to apply a first voltage to a first word line coupled to the first memory cell at a first time and during a channel preparation period of programming operation of a first memory cell in the memory cell array, apply a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage, and apply a programming voltage to the first word line after the channel preparation period and during programming operation of the first memory cell.

[0120] Certain aspects of the subject matter described herein can be implemented as a method. The method includes: applying a first voltage to a first word line coupled to the first memory cell at a first time and during a channel preparation period of programming operation of a first memory cell in a memory cell array; applying a second voltage to the first word line at a second time after the first time and during the channel preparation period, wherein the second voltage is lower than the first voltage; and applying a programming voltage to the first word line after the channel preparation period and during programming operation of the first memory cell.

[0121] The method may include one or more of the following features.

[0122] In some implementations, the first voltage is lower than the programming voltage.

[0123] In some embodiments, the method further includes applying a third voltage to the first word line before a first time, wherein the third voltage is lower than the first voltage.

[0124] In some implementations, the third voltage is lower than or equal to the second voltage.

[0125] In some embodiments, the method further includes: applying a first voltage to a second word line coupled to one or more memory cells in the memory cell array at a first time, wherein each of the one or more memory cells is a programmed memory cell; and applying a fourth voltage to the second word line at a second time.

[0126] In some implementations, the first voltage is lower than the pass voltage to be applied to the second word line after the second time.

[0127] In some implementations, the fourth voltage is lower than or equal to the second voltage.

[0128] In some embodiments, the method further includes: applying a sixth voltage to a fourth word line coupled to a memory cell adjacent to a select gate transistor at a first time, wherein the select gate transistor is coupled to a source line of the memory cell array, the sixth voltage is higher than a third voltage and the fourth word line is a first pseudo-word line; and applying a third voltage to the fourth word line at a third time after a second time.

[0129] In some embodiments, the memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack being adjacent to the second stack, the first memory cell being located in the first stack, and the method further includes applying a sixth voltage at a first time to a fifth word line of the memory cell in the first stack that is closest to the second stack, wherein the fifth word line is a second pseudo-word line.

[0130] In some embodiments, the method further includes applying the sixth voltage at a first time to a sixth word line of a memory cell in the second stack that is closest to the first stack, wherein the sixth word line is a third pseudo-word line.

[0131] In some implementations, the first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

[0132] In some embodiments, the first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine programming operation, and the method further includes: applying a first voltage to a seventh word line of a second memory cell coupled to the memory cell array at a first time, wherein the seventh word line is adjacent to the first word line; and applying a second voltage to the seventh word line at a second time.

[0133] Although this specification contains many specific implementation details, these should not be construed as limiting the scope of the claimed protection, but rather as descriptions of features specific to particular embodiments. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any sub-combination in multiple embodiments. Furthermore, while the features described above may be described as functioning in certain combinations and even initially claimed accordingly, one or more features from the claimed combination may be removed from that combination in certain circumstances, and the claimed combination may involve sub-combinations or variations thereof.

[0134] As used in this disclosure, indefinite or definite articles are used to include one or more, unless the context clearly indicates otherwise. The word "or" is used to indicate a non-exclusive "or," unless otherwise specified. The expression "at least one of A and B" has the same meaning as "A, B, or A and B." Furthermore, the wording or terminology used in this disclosure unless otherwise defined is for descriptive purposes only and not for limitation. Any use of section headings is intended to aid in reading this document and should not be construed as limiting; information relating to section headings may appear within or outside of that particular section.

[0135] As used in this article, the words “approximately” or “roughly” allow for a degree of variation in the value or range, for example, within 10%, 5%, or 1% of the stated value or range limit.

[0136] As used in this disclosure, the term “basic” means the majority, the majority, or at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0137] Values ​​expressed in range format should be interpreted flexibly to include not only the values ​​explicitly referenced as range limits, but also all individual values ​​or subranges encompassed within that range, as if each value and subrange were explicitly referenced. For example, the range “0.1% to approximately 5%” or “0.1% to 5%” should be interpreted as including approximately 0.1% to approximately 5%, as well as the individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. The expression “X to Y” has the same meaning as “approximately X to approximately Y”, unless otherwise specified. Similarly, the expression “X, Y, or Z” has the same meaning as “approximately X, approximately Y, or approximately Z”, unless otherwise specified.

[0138] Specific embodiments of this subject matter have been described. Other embodiments, as well as modifications and substitutions to the described embodiments, are within the scope of the following claims and will be apparent to those skilled in the art. Although operations are depicted in a specific order in the drawings or claims, it is not required that such operations be performed in the specific order shown or in a sequential order in order to achieve the desired results, nor is it required that all illustrated operations be performed (some operations may be shown as optional). In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed where deemed appropriate.

[0139] Furthermore, not all implementations require the division or integration of the various system modules and components described in the foregoing implementations, and the described components and systems are generally integrated together or packaged into multiple products.

[0140] Accordingly, the exemplary embodiments described above do not limit or restrict this disclosure. Other changes, substitutions, and modifications are also possible without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: A memory cell array, comprising memory cells; as well as Peripheral circuitry, coupled to the memory cell array and configured to perform operations including: At a first time point and during the channel preparation period of the programming operation of the first memory cell in the memory cell array, a first voltage is applied to the first word line coupled to the first memory cell; At a second time following the first time and during the channel preparation period, a second voltage is applied to the first word line, wherein the second voltage is lower than the first voltage; and A programming voltage is applied to the first word line after the channel preparation period and during the programming operation of the first memory cell. Wherein, the voltage applied to the third word line at the first time and during the channel preparation period is the fifth voltage, wherein the third word line is coupled to one or more memory cells in the memory cell array, and each of the one or more memory cells is an unprogrammed memory cell, and wherein the fifth voltage is lower than or equal to the second voltage.

2. The memory device according to claim 1, wherein, The first voltage is lower than the programming voltage.

3. The memory device according to claim 1 or 2, wherein, The operation further includes: A third voltage is applied to the first word line before the first time, wherein the third voltage is lower than the first voltage.

4. The memory device according to claim 3, wherein, The third voltage is lower than or equal to the second voltage.

5. The memory device according to claim 1 or 2, wherein, The operation further includes: At the first time point, the first voltage is applied to a second word line coupled to one or more memory cells in the memory cell array, wherein each of the one or more memory cells is a programmed memory cell; and A fourth voltage is applied to the second word line at the second time point.

6. The memory device according to claim 5, wherein, The first voltage is lower than the pass voltage that will be applied to the second word line after the second time.

7. The memory device according to claim 5 or 6, wherein, The fourth voltage is lower than or equal to the second voltage.

8. The memory device according to claim 1 or 2, wherein, The operation further includes: The fifth voltage is applied to the third word line before the pass voltage is applied to the third word line.

9. The memory device according to claim 8, wherein, The fifth voltage is lower than the passing voltage.

10. The memory device according to claim 3, wherein, The operation further includes: At the first time point, a sixth voltage is applied to a fourth word line coupled to a memory cell adjacent to a select gate transistor, wherein the select gate transistor is coupled to the source line of the memory cell array, the sixth voltage is higher than the third voltage, and the fourth word line is a first pseudo-word line; and The third voltage is applied to the fourth word line at a third time after the second time.

11. The memory device according to claim 10, wherein, The operation further includes: At the first time point, a seventh voltage is applied to the select gate line coupled to the select gate transistor, wherein the seventh voltage is higher than the third voltage; and The third voltage is applied to the selected gate line at the third time point.

12. The memory device according to claim 10 or 11, wherein, The operation further includes: An eighth voltage is applied to the source line of the memory cell array at the first time point.

13. The memory device according to claim 12, wherein, The eighth voltage is equal to the third voltage.

14. The memory device according to claim 10 or 11, wherein, The memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack being adjacent to the second stack, the first memory cell being located within the first stack, and the operation further including: At the first time point, a sixth voltage is applied to the fifth word line of the memory cell closest to the second stack in the first stack, wherein the fifth word line is a second pseudo word line.

15. The memory device according to claim 14, wherein, The operation further includes: At the first time point, the sixth voltage is applied to the sixth word line of the memory cell closest to the first stack coupled to the second stack, wherein the sixth word line is the third pseudo word line.

16. The memory device according to claim 1 or 2, wherein, The first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

17. The memory device according to claim 1 or 2, wherein, The first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine-grained programming operation, and the operation further includes: At the first time point, the first voltage is applied to the seventh word line of the second memory cell coupled to the memory cell array, wherein the seventh word line is adjacent to the first word line; and The second voltage is applied to the seventh word line at the second time.

18. A memory system comprising: A memory device comprising: Memory cell array, comprising memory cells; and Peripheral circuitry, coupled to the memory cell array and configured to perform operations including: At a first time point and during the channel preparation period of the programming operation of the first memory cell in the memory cell array, a first voltage is applied to the first word line coupled to the first memory cell; At a second time following the first time and during the channel preparation period, a second voltage is applied to the first word line, wherein the second voltage is lower than the first voltage; and A programming voltage is applied to the first word line after the channel preparation period and during the programming operation of the first memory cell. Wherein, the voltage applied to the third word line at the first time and during the channel preparation period is a fifth voltage, wherein the third word line is coupled to one or more memory cells in the memory cell array, and each of the one or more memory cells is an unprogrammed memory cell, and wherein the fifth voltage is lower than or equal to the second voltage; and A controller, coupled to the memory device and configured to send signals to the memory device to initiate the programming operation.

19. A method comprising: At the first time point and during the channel preparation period of the programming operation of the first memory cell in the memory cell array, a first voltage is applied to the first word line coupled to the first memory cell; At a second time following the first time and during the channel preparation period, a second voltage is applied to the first word line, wherein the second voltage is lower than the first voltage; and A programming voltage is applied to the first word line after the channel preparation period and during the programming operation of the first memory cell. Wherein, the voltage applied to the third word line at the first time and during the channel preparation period is the fifth voltage, wherein the third word line is coupled to one or more memory cells in the memory cell array, and each of the one or more memory cells is an unprogrammed memory cell, and wherein the fifth voltage is lower than or equal to the second voltage.

20. The method according to claim 19, wherein, The first voltage is lower than the programming voltage.

21. The method according to claim 19 or 20, further comprising: A third voltage is applied to the first word line before the first time, wherein the third voltage is lower than the first voltage.

22. The method according to claim 21, wherein, The third voltage is lower than or equal to the second voltage.

23. The method according to claim 19 or 20, further comprising: At the first time point, the first voltage is applied to a second word line coupled to one or more memory cells in the memory cell array, wherein each of the one or more memory cells is a programmed memory cell; and A fourth voltage is applied to the second word line at the second time point.

24. The method according to claim 23, wherein, The first voltage is lower than the pass voltage that will be applied to the second word line after the second time.

25. The method according to claim 23, wherein, The fourth voltage is lower than or equal to the second voltage.

26. The method of claim 21, further comprising: At the first time point, a sixth voltage is applied to a fourth word line coupled to a memory cell adjacent to a select gate transistor, wherein the select gate transistor is coupled to the source line of the memory cell array, the sixth voltage is higher than the third voltage, and the fourth word line is a first pseudo-word line; and A third voltage is applied to the fourth word line at a third time point following the second time point.

27. The method according to claim 26, wherein, The memory cell array includes a first stack of memory cells and a second stack of memory cells, the first stack being adjacent to the second stack, the first memory cell being located within the first stack, and the method further comprising: At the first time point, the sixth voltage is applied to the fifth word line of the memory cell closest to the second stack in the first stack, wherein the fifth word line is the second pseudo word line.

28. The method of claim 27, further comprising: At the first time point, the sixth voltage is applied to the sixth word line of the memory cell closest to the first stack coupled to the second stack, wherein the sixth word line is the third pseudo word line.

29. The method according to claim 19 or 20, wherein, The first memory cell is a multi-level cell, and the programming operation of the first memory cell is a coarse programming operation.

30. The method according to claim 19 or 20, wherein, The first memory cell is a multi-level cell, the programming operation of the first memory cell is a fine-grained programming operation, and the method further includes: At the first time point, the first voltage is applied to the seventh word line of the second memory cell coupled to the memory cell array, wherein the seventh word line is adjacent to the first word line; and The second voltage is applied to the seventh word line at the second time.

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