Display device

Abstract

Embodiments of the present disclosure provide a display device including: a substrate including a display area and a peripheral area disposed on a side portion of the display area; a first alignment electrode, a second alignment electrode, and a third alignment electrode overlapping the display area, spaced apart from each other in the first direction, and extending in a second direction intersecting the first direction; a light emitting element disposed between the first alignment electrode and the second alignment electrode and between the second alignment electrode and the third alignment electrode; and a data line overlapping the second alignment electrode in a plan view and extending in the second direction. A length of a first width of the data line in the first direction is less than or equal to a length of a second width of the second alignment electrode in the first direction.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices are being continuously conducted. Summary of the invention

[0003] An aspect of the present invention is to provide a display device which can improve light emitting efficiency by fixing a light emitting element disposed between alignment electrodes.

[0004] Aspects of the present disclosure are not limited to the above-described aspects, and may be variously extended without departing from the spirit and scope of the present disclosure.

[0005] An embodiment of the present disclosure provides a display device, which may include: a substrate including a display area and a peripheral area arranged on a side of the display area; a first alignment electrode, a second alignment electrode, and a third alignment electrode, which overlap with the display area, are spaced apart from each other in a first direction, and extend in a second direction intersecting the first direction; a light emitting element, which is arranged between the first alignment electrode and the second alignment electrode and between the second alignment electrode and the third alignment electrode; and a data line, which overlaps with the second alignment electrode in a plan view and extends in the second direction, wherein a length of a first width of the data line in the first direction is less than or equal to a length of a second width of the second alignment electrode in the first direction.

[0006] The display device may further include a pattern electrode overlapping the first alignment electrode, the second alignment electrode, and the third alignment electrode in a plan view and extending in the first direction.

[0007] The light emitting element may not overlap with the pattern electrode in a plan view.

[0008] The second alignment electrode and the data line may provide a first alignment signal when aligning the light emitting element, and the first alignment electrode and the third alignment electrode may provide a second alignment signal different from the first alignment signal.

[0009] The display device may further include a passivation layer and a via layer sequentially disposed on the substrate, wherein the data line may be disposed between the passivation layer and the via layer, and the first, second, and third alignment electrodes may be disposed on the via layer.

[0010] The second alignment electrode and the data line may extend from the display region to the peripheral region, and the second alignment electrode and the data line may directly contact through a contact portion passing through the via layer in the peripheral region.

[0011] The display device may further include a dummy electrode spaced apart from the second alignment electrode in the second direction in the peripheral region.

[0012] The display area may include a display element area and a pixel circuit area spaced apart from the display element area in a second direction, a first alignment electrode, a second alignment electrode, a third alignment electrode and a light emitting element may be arranged in the display element area, and a plurality of transistors and a storage capacitor may be arranged in the pixel circuit area.

[0013] The display device may further include a buffer layer and an interlayer insulating layer disposed between the substrate and the passivation layer, wherein a lower electrode of the storage capacitor may be disposed between the substrate and the buffer layer, an upper electrode of the storage capacitor may be disposed between the interlayer insulating layer and the passivation layer, and a pattern electrode may be disposed between the buffer layer and the interlayer insulating layer.

[0014] The display device may further include: a first vertical power line receiving a voltage from a first power source and extending in a second direction; a first horizontal power line electrically connected to the first vertical power line and extending in the first direction; a second vertical power line receiving a voltage from a second power source and extending in the second direction; and a second horizontal power line electrically connected to the second vertical power line and extending in the first direction, wherein the first alignment electrode and the second alignment electrode may be disposed between the first horizontal power line and the second horizontal power line in a plan view.

[0015] The first vertical power line and the second vertical power line may be disposed on a different layer from the data line.

[0016] The storage capacitor may be spaced apart from the first horizontal power line in the second direction.

[0017] The display device may further include a scan line disposed in the pixel circuit region and extending in the first direction, wherein the storage capacitor may be disposed between the first horizontal power line and the scan line in a plan view.

[0018] A portion of the data line may overlap the first horizontal power line in a plan view.

[0019] Another embodiment of the present disclosure provides a display device, which may include: a substrate; and a display element region, which is disposed on the substrate and includes a first sub-pixel and a second sub-pixel spaced apart from each other in a first direction. The display element region may also include: a first alignment electrode, a second alignment electrode, a third alignment electrode, a fourth alignment electrode, and a fifth alignment electrode, which are spaced apart from each other in the first direction and extend in a second direction intersecting the first direction; a light emitting element, which is disposed between the first alignment electrode and the second alignment electrode, between the second alignment electrode and the third alignment electrode, between the third alignment electrode and the fourth alignment electrode, and between the fourth alignment electrode and the fifth alignment electrode; a first data line of the first sub-pixel, which overlaps with the second alignment electrode in a plan view and extends in the second direction; and a second data line of the second sub-pixel, which overlaps with the fourth alignment electrode in a plan view and extends in the second direction, and the length of the first width of the first data line and the second data line in the first direction is less than or equal to the length of the second width of the second alignment electrode and the fourth alignment electrode in the first direction.

[0020] The display device may further include a pixel circuit region spaced apart from the display element region in the second direction and including a plurality of transistors and a storage capacitor.

[0021] The display device may further include: a first pattern electrode overlapping the first alignment electrode, the second alignment electrode, and the third alignment electrode in a plan view and extending in the first direction; and a second pattern electrode spaced apart from the first pattern electrode in the first direction, overlapping the third alignment electrode, the fourth alignment electrode, and the fifth alignment electrode, and extending in the first direction.

[0022] In a plan view, the first pattern electrode and the second pattern electrode may not overlap the light emitting element.

[0023] The display device may further include: a pattern electrode overlapping the first, second, third, fourth and fifth alignment electrodes in plan view and extending in the first direction, wherein the pattern electrode may not overlap the light emitting element in plan view.

[0024] The first subpixel may include a (1-1)th light-emitting element overlapping the first alignment electrode and the second alignment electrode and a (1-2)th light-emitting element overlapping the second alignment electrode and the third alignment electrode, and the second subpixel may include a (2-1)th light-emitting element overlapping the third alignment electrode and the fourth alignment electrode and a (2-2)th light-emitting element overlapping the fourth alignment electrode and the fifth alignment electrode.

[0025] According to the display device according to the embodiment of the present disclosure, in the alignment process of the light-emitting element, through the configuration of the pixel circuit, by removing (or minimizing) the components of the pixel circuit that overlap with the area between the alignment electrodes, the distortion of the alignment signal or the limitation of the area where the light-emitting element is aligned can be minimized (or improved).

[0026] However, the effects of the present disclosure are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic plan view of a display device according to an embodiment of the present disclosure is shown.

[0028] Figure 2A Shown included in Figure 1 Schematic circuit diagram of an embodiment of a pixel in a display device.

[0029] Figure 2B Shown included in Figure 1 Schematic circuit diagram of an embodiment of a pixel in a display device.

[0030] Figure 3 A schematic perspective view of a light emitting element according to an embodiment is shown.

[0031] Figure 4 A schematic cross-sectional view of a light emitting element according to an embodiment is shown.

[0032] Figure 5 Shown included in Figure 1 Schematic top plan view of an embodiment of a sub-pixel in a display device.

[0033] Figure 6 Shown along Figure 5 A schematic cross-sectional view of an embodiment of a sub-pixel taken along line AA′ of FIG.

[0034] Figure 7 A comparative example of arrangement of the light emitting element according to the position of the conductive pattern of the pixel circuit is shown.

[0035] Figure 8 Shows Figure 1 Schematic top plan view of an embodiment of a display area.

[0036] Fig. 9 Shown along Figure 8 A schematic cross-sectional view taken along line II'.

[0037] Fig.10 Shown along Figure 8 A schematic cross-sectional view taken along line II-II'.

[0038] Fig.11 Shown along Figure 8 A schematic cross-sectional view taken along line III-III'.

[0039] Fig. 12A Shows Figure 1 Schematic cross-sectional view of an embodiment of the peripheral area of ​​.

[0040] Fig. 12B Shows Figure 1 Schematic cross-sectional view of another embodiment of the peripheral area of ​​.

[0041] Fig.13 Shows Figure 1 Schematic top plan view of another embodiment of a display area. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and repeated description of the same constituent elements may be omitted.

[0043] In the drawings, the size, thickness, ratio, and scale of elements may be exaggerated for convenience of description and clarity.

[0044] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or".

[0046] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0047] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0048] For ease of description, spatially relative terms "below," "below," "down," "above," "upper," etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, in the case where the device shown in the drawings is flipped, a device located "below" or "below" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0049] The term "overlap" or "overlapped" means that a first object can be above or below a second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" may include layering, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0050] When an element is described as “not overlapping” or “to not overlap” another element, this may include the elements being spaced apart, offset or separated from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0051] When used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including,” “has,” “have,” and / or “having,” and variations thereof, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] The phrase "in a plan view" means that an object is viewed from the top, and the phrase "in a schematic sectional view" means that a vertically cut section of an object is viewed from the side.

[0053] As used herein, "about" or "approximately" or "substantially" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0055] Figure 1 A schematic plan view of a display device according to an embodiment of the present disclosure is shown.

[0056] refer to Figure 1 The display device DD may be provided in various shapes, and as an example, may be provided in a rectangular plate shape having two pairs of sides parallel to each other, but is not limited thereto. In the case where the display device DD is provided in a rectangular plate shape, one pair of sides may be provided to be longer than the other pair of sides.

[0057] At least a portion of the display device DD may have flexibility, and the display device DD may be folded at the portion having flexibility, but is not limited thereto.

[0058] The substrate SUB may configure a basic component of the display device DD, and may be a rigid substrate or a flexible substrate or a rigid film or a flexible film. For example, the substrate SUB may be a hard substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal material, or at least one layered insulating film. The material and / or physical properties of the substrate SUB are not particularly limited.

[0059] The substrate SUB (and the display device DD) may include a display area DA for displaying an image and a peripheral area PA (or non-display area) other than the display area DA. The display area DA may configure a screen on which an image is displayed, and the peripheral area PA may be provided on at least one side of the display area DA to surround the display area DA, but is not limited thereto. The peripheral area PA may surround the periphery (or edge) of the display area DA. The peripheral area PA may be a frame area of ​​the display device DD.

[0060] The pixel PXL may be arranged in the display area DA on the substrate SUB. The peripheral area PA may be arranged around the display area DA. The peripheral area PA may have a structure for protecting the components included in the pixel PXL arranged in the display area DA, but is not limited thereto. For example, the peripheral area PA may be an area in which a driver for driving the pixel PXL and a wiring portion for connecting the pixel PXL and the driver are partially arranged. The wiring portion may electrically connect the driver and the pixel PXL. The wiring portion may provide a signal to the pixel PXL, and may include signal lines respectively connected to the pixel PXL, for example, fan-out lines connected to a scan line, a data line, a light emitting control line, etc.

[0061] The pixel PXL may include sub-pixels SPX1 to SPX3. For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged in a first direction DR1. However, they are not limited thereto, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged in a second direction DR2 intersecting the first direction DR1. In an embodiment, the third direction DR3 may be a thickness direction of the display device DD.

[0062] The first to third sub-pixels SPX1 to SPX3 may emit light of different colors. For example, the first sub-pixel SPX1 may be a red sub-pixel emitting red light, the second sub-pixel SPX2 may be a green sub-pixel emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel emitting blue light. However, the color, type, and / or number of sub-pixels constituting the pixel PXL are not particularly limited, and, for example, the color of light emitted by each of the sub-pixels SPX1 to SPX3 may be variously changed.

[0063] A plurality of pixels PXL may be arranged in a matrix form along rows extending in the first direction DR1 and columns extending in the second direction DR2. The arrangement form of the pixels PXL is not particularly limited, and in the case where a plurality of pixels PXL are provided, they may be provided to have different areas (or sizes). For example, in the case where the pixels PXL have emitted light of different colors, the pixels PXL of each color may be provided to have different areas (or sizes) or different shapes.

[0064] The driver may provide a predetermined or selected signal and a predetermined or selected power to each pixel PXL through the wiring portion, thereby controlling driving of the pixel PXL.

[0065] Figure 2A Shown included in Figure 1Schematic circuit diagram of an embodiment of a pixel in a display device. Figure 2B Shown included in Figure 1 Schematic circuit diagram of an embodiment of a pixel in a display device.

[0066] Figure 2A and Figure 2B The electrical connection relationship of the constituent elements included in each of the sub-pixels SPX1 to SPX3 applicable to the active matrix display device according to the embodiment is shown. However, the connection relationship of the constituent elements of each of the sub-pixels SPX1 to SPX3 is not limited thereto. In the following embodiments, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may each be referred to as a sub-pixel SPX.

[0067] refer to Figure 1 , Figure 2A and Figure 2B The sub-pixel SPX may include a light emitting portion EMU (or a light emitting unit) that generates light having a brightness corresponding to the data signal. The sub-pixel SPX may further selectively include a pixel circuit PXC for driving the light emitting portion EMU.

[0068] In some embodiments, the light emitting part EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2. The first power line PL1 may be connected to a first driving power source VDD to be applied with a voltage of the first driving power source VDD, and the second power line PL2 may be connected to a second driving power source VSS to be applied with a voltage of the second driving power source VSS.

[0069] For example, the light emitting portion EMU may include a first pixel electrode PE1 connected to a first driving power source VDD via a pixel circuit PXC and a first power line PL1, a second pixel electrode PE2 connected to a second driving power source VSS via a second power line PL2, and a plurality of light emitting elements LD connected in parallel between the first pixel electrode PE1 and the second pixel electrode PE2 in the same direction. In an embodiment, the first pixel electrode PE1 may be an anode (or an anode electrode), and the second pixel electrode PE2 may be a cathode (or a cathode electrode).

[0070] Each of the light emitting elements LD included in the light emitting part EMU may include a first end portion connected to a first driving power source VDD through a first pixel electrode PE1 and a second end portion connected to a second driving power source VSS through a second pixel electrode PE2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source. During the light emitting period of each sub-pixel SPX, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to be equal to or higher than the threshold voltage of the light emitting element LD.

[0071] As described above, the respective light emitting elements LD connected in parallel between the first pixel electrode PE1 and the second pixel electrode PE2 supplied with voltages of different power sources in the same direction (eg, forward direction) may form respective effective light sources.

[0072] The light emitting element LD of the light emitting part EMU may emit light having a brightness corresponding to the driving current provided by the corresponding pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may provide the light emitting part EMU with a driving current corresponding to the grayscale value of the corresponding frame data of the pixel circuit PXC. The driving current provided to the light emitting part EMU may be distributed to flow in each of the light emitting elements LD. Therefore, when each light emitting element LD emits light having a brightness corresponding to the current flowing therein, the light emitting part EMU may emit light having a brightness corresponding to the driving current.

[0073] In the above-mentioned embodiment, although the structure in which the two end portions of the light-emitting element LD are connected between the first driving power source VDD and the second driving power source VSS in the same direction has been described, the present disclosure is not limited thereto. In some embodiments, in addition to the light-emitting element LD forming the corresponding effective light source, the light-emitting portion EMU may further include at least one invalid light source, for example, a reverse light-emitting element LDr. The reverse light-emitting element LDr may be connected in parallel between the first pixel electrode PE1 and the second pixel electrode PE2 together with the light-emitting element LD forming the effective light source, but may be connected between the first pixel electrode PE1 and the second pixel electrode PE2 in the opposite direction relative to the light-emitting element LD. Even when a predetermined or selected driving voltage (for example, a driving voltage in the forward direction) is applied between the first pixel electrode PE1 and the second pixel electrode PE2, the reverse light-emitting element LDr remains in an inactive state, so that current does not substantially flow in the reverse light-emitting element LDr.

[0074] The pixel circuit PXC may be connected to the scan line SLi and the data line DLj of the sub-pixel SPX. The pixel circuit PXC may be connected to the control line CLi and the sensing line SENj of the sub-pixel SPX. For example, in the case where the sub-pixel SPX is set to the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be connected to the i-th scan line SLi, the j-th data line DLj, the i-th control line CLi, and the j-th sensing line SENj of the display area DA. In some embodiments, the control line CLi may be connected to the scan line SLi, or may be the scan line SLi.

[0075] The pixel circuit PXC may include transistors T1 to T3 and a storage capacitor Cst (or capacitor).

[0076] The first transistor T1 may be a driving transistor for controlling a driving current applied to the light-emitting part EMU, and may be connected between the first driving power supply VDD and the light-emitting part EMU. Specifically, the first terminal (or first transistor electrode) of the first transistor T1 may be electrically connected to the first driving power supply VDD through the first power line PL1, the second terminal (or second transistor electrode) of the first transistor T1 may be electrically connected to the second node N2, and the gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light-emitting part EMU from the first driving power supply VDD through the second node N2 according to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, but the present disclosure is not limited thereto. In some embodiments, its first terminal may be a source electrode, and its second terminal may be a drain electrode.

[0077] The second transistor T2 may be a switching transistor that selects the sub-pixel SPX in response to the scan signal and activates the sub-pixel SPX, and may be connected between the data line DLj and the first node N1. A first terminal of the second transistor T2 may be connected to the data line DLj, a second terminal of the second transistor T2 may be connected to the first node N1, and a gate electrode of the second transistor T2 may be connected to the scan line SLi. The first terminal and the second terminal of the second transistor T2 are different terminals, and for example, in the case where the first terminal is a drain electrode, the second terminal may be a source electrode.

[0078] In the case where a scan signal of a gate-on voltage (e.g., a high level voltage) is provided from the scan line SLi, the second transistor T2 may be turned on to electrically connect the data line DLj and the first node N1. The first node N1 may be a point at which the second terminal of the second transistor T2 is connected to the gate electrode of the first transistor T1, and the second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0079] The first terminal of the third transistor T3 may be connected to the sensing line SENj, the second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1, and the gate electrode of the third transistor T3 may be connected to the control line CLi. An initialization power supply may be applied to the sensing line SENj. The third transistor T3 may be an initialization transistor capable of initializing the second node N2, and in the case where a sensing control signal is provided from the control line CLi, the third transistor T3 may be turned on to transfer the voltage of the initialization power supply to the second node N2. Therefore, the second storage electrode of the storage capacitor Cst electrically connected to the second node N2 may be initialized. In some embodiments, the third transistor T3 connects the first transistor T1 to the sensing line SENj, so that a sensing signal may be obtained through the sensing line SENj, and the characteristics of the sub-pixel SPX including the threshold voltage of the first transistor T1 may be detected by using the sensing signal. Information about the characteristics of the sub-pixel SPX may be used to convert image data, so that characteristic deviations between the sub-pixels SPX may be compensated.

[0080] The storage capacitor Cst may be formed between the first node N1 and the second node N2, or may be electrically connected between the first node N1 and the second node N2. The storage capacitor Cst may charge a data voltage corresponding to a data signal supplied to the first node N1 during a frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0081] The light emitting part EMU may be configured to include at least one series stage including a plurality of light emitting elements LD electrically connected in parallel to each other.

[0082] In an embodiment, the light emitting part EMU may be configured as a series / parallel hybrid structure. Figure 2B As shown in , the light emitting part EMU can be configured to include a first series stage SET1, a second series stage SET2, a third series stage SET3 and a fourth series stage SET4. The number of series stages included in the light emitting part EMU can be variously changed, and for example, the light emitting part EMU can include 1, 2, 3 or 5 or more series stages.

[0083] The light emitting part EMU may include a first series stage SET1, a second series stage SET2, a third series stage SET3, and a fourth series stage SET4 sequentially connected between a first driving power source VDD and a second driving power source VSS.

[0084] The first series stage SET1 (or the first stage) may include a first pixel electrode PE1 and a first intermediate electrode CNE1, and may include at least one first light emitting element LDa connected between the first pixel electrode PE1 and the first intermediate electrode CNE1. The first series stage SET1 may also include a reverse light emitting element LDr connected to the first light emitting element LDa in an opposite direction between the first pixel electrode PE1 and the first intermediate electrode CNE1.

[0085] The second series stage SET2 (or the second stage) may include a first intermediate electrode CNE1 and a second intermediate electrode CNE2, and it may include at least one second light emitting element LDb connected between the first intermediate electrode CNE1 and the second intermediate electrode CNE2. The second series stage SET2 may also include a reverse light emitting element LDr connected to the second light emitting element LDb in an opposite direction between the first intermediate electrode CNE1 and the second intermediate electrode CNE2.

[0086] The third series stage SET3 (or the third stage) may include the second intermediate electrode CNE2 and the third intermediate electrode CNE3, and it may include at least one third light emitting element LDc connected between the second intermediate electrode CNE2 and the third intermediate electrode CNE3. The third series stage SET3 may also include a reverse light emitting element LDr connected to the third light emitting element LDc in the opposite direction between the second intermediate electrode CNE2 and the third intermediate electrode CNE3.

[0087] The fourth series stage SET4 (or the fourth stage) may include a third intermediate electrode CNE3 and a second pixel electrode PE2, and it may include at least one fourth light emitting element LDd connected between the third intermediate electrode CNE3 and the second pixel electrode PE2. The fourth series stage SET4 may further include a reverse light emitting element LDr connected to the fourth light emitting element LDd in the opposite direction between the third intermediate electrode CNE3 and the second pixel electrode PE2. The terms pixel electrode and intermediate electrode are merely expressions for distinguishing electrodes, and the corresponding configuration (e.g., electrode) is not limited by these terms.

[0088] As described above, the light emitting portion EMU of the sub-pixel SPX including the series stages SET1 to SET4 (or the light emitting element LD) connected in a series / parallel hybrid structure can easily adjust the driving current / voltage conditions according to the applied product specifications.

[0089] Specifically, compared with the light-emitting part in which the light-emitting elements LD are connected only in parallel, the light-emitting part EMU of the sub-pixel SPX including the series stages SET1 to SET4 can reduce the driving current. In other words, for the same driving current, the light-emitting part EMU of the sub-pixel SPX including the series stages SET1 to SET4 can emit light with higher brightness.

[0090] The light emitting section EMU including the sub-pixels SPX of the series stages SET1 to SET4 can reduce the driving voltage applied to both ends of the light emitting section EMU compared to a light emitting section having a structure in which the same number of light emitting elements LD are all connected in series.

[0091] exist Figure 2A and Figure 2B , the transistors T1 to T3 included in the pixel circuit PXC are all shown as n-type transistors, but the transistors are not necessarily limited thereto. For example, at least one of the transistors T1 to T3 may be changed to a p-type transistor.

[0092] The structure and driving method of the sub-pixel SPX can be changed in various ways. Figure 2A and Figure 2B In addition to the pixel circuit PXC of the embodiment shown in FIG. 1 , the pixel circuit PXC may be configured as a pixel circuit having various structures and / or driving methods.

[0093] For example, the pixel circuit PXC may not include the third transistor T3. The pixel circuit PXC may further include other circuit elements, such as a compensation transistor for compensating for the threshold voltage of the first transistor T1, an initialization transistor for initializing the voltage of the first node N1 and / or the first pixel electrode PE1, a light emitting control transistor for controlling a period of providing a driving current to the light emitting portion EMU, and / or a boost capacitor for boosting the voltage of the first node N1.

[0094] Figure 3 A schematic perspective view of a light emitting element according to an embodiment is shown. Figure 4 A schematic cross-sectional view of a light emitting element according to an embodiment is shown.

[0095] The type and / or shape of the light emitting element LD is not limited to Figure 3 and Figure 4 The embodiment shown in .

[0096] refer to Figure 3 and Figure 4, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as a stacked light emitting body (or stacked pattern) in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are stacked on each other.

[0097] The light emitting element LD may be provided to have a shape extending in one direction. In the case where the extending direction of the light emitting element LD is the length direction, the light emitting element LD may include a first end portion EP1 and a second end portion EP2 along the length direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be located on the first end portion EP1 of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be located on the second end portion EP2 of the light emitting element LD. For example, the second semiconductor layer 13 may be located on the first end portion EP1 of the light emitting element LD, and the first semiconductor layer 11 may be located on the second end portion EP2 of the corresponding light emitting element LD.

[0098] The light emitting element LD can be arranged in various shapes. For example, Figure 3 As shown in , the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape that is long in the length direction (or the aspect ratio is greater than 1). As another example, the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape that is short in the length direction (or the aspect ratio is less than 1). As another example, the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape with an aspect ratio of 1.

[0099] For example, the light emitting element LD may include a light emitting diode (LED) manufactured to have an ultra-small size having a diameter D and / or a length L of a nanometer scale (or nanometer) to a micrometer scale (or micrometer).

[0100] In the case where the light emitting element LD is long in the length direction (for example, the aspect ratio is greater than 1), the diameter D of the light emitting element LD may be about 0.5 μm to about 6 μm, and the length L thereof may be about 1 μm to about 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto, and the size of the light emitting element LD may be changed so that the light emitting element LD satisfies the requirements (or design conditions) of the lighting device or the self-luminous display device to which the light emitting element LD is applied.

[0101] For example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include a semiconductor material of at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. However, the material included in the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be made of various materials. The first semiconductor layer 11 may include an upper surface in contact with the active layer 12 along the length direction of the light emitting element LD and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may be an end portion (or lower end portion) of the light emitting element LD.

[0102] The active layer 12 may be disposed on the first semiconductor layer 11, and may be formed to have a single quantum well structure or a multi-quantum well structure. For example, in the case where the active layer 12 is formed of a multi-quantum well structure, the active layer 12 may have a structure in which a barrier layer (not shown), a strain enhancement layer, and a well layer composed of one unit are periodically and repeatedly stacked on each other. Since the strain enhancement layer has a lattice constant smaller than that of the barrier layer, it can further enhance the strain applied to the well layer, for example, compressive strain. However, the structure of the active layer 12 is not limited to the above-described embodiment.

[0103] The active layer 12 may emit light having a wavelength of about 400 nm to about 900 nm, and may have a double heterostructure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12 along the length direction of the light emitting element LD. For example, the cladding layer may be formed as an AlGaN layer or an InAlGaN layer. In some embodiments, materials such as AlGaN and InAlGaN may be used to form the active layer 12, and in addition, various materials may form the active layer 12. The active layer 12 may include a first surface contacting the first semiconductor layer 11 and a second surface contacting the second semiconductor layer 13.

[0104] When an electric field of a predetermined or selected voltage or more is applied to the corresponding end portions of the light emitting element LD, the light emitting element LD emits light while electron-hole pairs are recombined in the active layer 12. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source (or light emission source) of various light emitting devices in addition to pixels of a display device.

[0105] The second semiconductor layer 13 may be disposed on the second surface of the active layer 12, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, and Ba. However, the material included in the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various materials. The second semiconductor layer 13 may include a lower surface in contact with the second surface of the active layer 12 along the length direction of the light emitting element LD and an upper surface exposed to the outside. Here, the upper surface of the second semiconductor layer 13 may be the other end portion (or upper end portion) of the light emitting element LD.

[0106] In an embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses from each other in the length direction of the light emitting element LD. For example, along the length direction of the light emitting element LD, the first semiconductor layer 11 may have a thickness relatively thicker than that of the second semiconductor layer 13. Therefore, compared to the lower surface of the first semiconductor layer 11, the active layer 12 of the light emitting element LD may be disposed closer to the upper surface of the second semiconductor layer 13.

[0107] It is shown that each of the first semiconductor layer 11 and the second semiconductor layer 13 is formed as one layer, but the present disclosure is not limited thereto. In an embodiment, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer, for example, a cladding layer and / or a tensile strain barrier reduction (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain reduction layer disposed between semiconductor layers having different lattice structures and used as a buffer to reduce the difference in lattice constants. The TSBR layer may be formed of a p-type semiconductor layer such as p-GaInP, p-AlInP, or p-AlGaInP, but is not limited thereto.

[0108] In some embodiments, in addition to the above-mentioned first semiconductor layer 11, active layer 12 and second semiconductor layer 13, the light emitting element LD may further include a contact electrode (hereinafter, referred to as "first contact electrode") (not shown) disposed on the second semiconductor layer 13. In another embodiment, another contact electrode (not shown, hereinafter referred to as "second contact electrode") disposed on one end of the first semiconductor layer 11 may be further included.

[0109] Each of the first contact electrode and the second contact electrode may be an ohmic contact electrode, but the present disclosure is not limited thereto. In some embodiments, the first contact electrode and the second contact electrode may be Schottky contact electrodes. The first contact electrode and the second contact electrode may include a conductive material. For example, the first contact electrode and the second contact electrode may include an opaque metal, wherein chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) and oxides or alloys thereof are used alone or in combination, but are not limited thereto. In some embodiments, the first contact electrode and the second contact electrode may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO).

[0110] The materials included in the first contact electrode and the second contact electrode may be the same or different from each other. The first contact electrode and the second contact electrode may be substantially transparent or translucent. Therefore, the light generated by the light emitting element LD may be transmitted through each of the first contact electrode and the second contact electrode to be output to the outside of the light emitting element LD. In some embodiments, in the case where the light generated by the light emitting element LD is not transmitted through the first contact electrode and the second contact electrode and is discharged to the outside through an area other than the corresponding end portion of the light emitting element LD, the first contact electrode and the second contact electrode may include an opaque metal.

[0111] In an embodiment, the light emitting element LD may further include an insulating film 14. However, in some embodiments, the insulating film 14 may be omitted, or the insulating film 14 may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0112] The insulating film 14 can prevent an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 14 can minimize surface defects of the light emitting element LD to improve the life and luminous efficiency of the light emitting element LD. In the case where a plurality of light emitting elements LD are closely arranged, the insulating film 14 can prevent an undesirable short circuit that may occur between the light emitting elements LD. Whether or not the insulating film 14 is provided is not limited as long as a short circuit between the active layer 12 and an external conductive material can be prevented.

[0113] The insulating film 14 may be provided in a form that completely surrounds the outer peripheral surface of the light emitting stack structure including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

[0114] In the above embodiment, a structure in which the insulating film 14 completely surrounds the peripheral surface of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 is described, but the present disclosure is not limited thereto. In some embodiments, in the case where the light emitting element LD includes a first contact electrode, the insulating film 14 may completely surround the peripheral surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first contact electrode. In another embodiment, the insulating film 14 may not completely surround the peripheral surface of the first contact electrode, or may only surround a portion of the peripheral surface of the first contact electrode, and may not surround the remaining portion of the peripheral surface of the first contact electrode. In some embodiments, in the case where the first contact electrode is disposed at the other end portion (or upper end portion) of the light emitting element LD and the second contact electrode is disposed at one end portion (or lower end portion) of the light emitting element LD, the insulating film 14 may expose at least one region of each of the first contact electrode and the second contact electrode.

[0115] The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium oxide (TiO x ), hafnium oxide (HfO x ), strontium titanium oxide (SrTiO x ), cobalt oxide (Co x O y )、MgO、ZnO x ), ruthenium oxide (RuO x ), nickel oxide (NiO), tungsten oxide (WO x ), tantalum oxide (TaO x ), Gadolinium oxide (GdO x ), zirconium oxide (ZrO x ), gallium oxide (GaO x ), vanadium oxide (V x O y )、ZnO:Al、ZnO:B、In x O y :H, niobium oxide (Nb x O y ), magnesium fluoride (MgF x ), aluminum fluoride (AlF x ), aluminum cone polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN xAt least one of insulating materials of gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN), and vanadium nitride (VN), but the present disclosure is not limited thereto, and various materials having insulating properties may be used as the material of the insulating film 14. Here, zinc oxide (ZnO x ) can be zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0116] The insulating film 14 may be provided in the form of a single layer or in the form of a multilayer including a double layer. For example, in the case where the insulating film 14 is configured as a double layer including a first insulating layer and a second insulating layer stacked on each other, the first insulating layer and the second insulating layer may be made of different materials (or substances) and may be formed by different processes. In some embodiments, the first insulating layer and the second insulating layer may include the same material to be formed by a continuous process.

[0117] The light emitting element LD may be implemented as a light emitting pattern having a core-shell structure. The above-mentioned first semiconductor layer 11 may be located at the core (e.g., the middle (or center) of the light emitting element LD), and the active layer 12 may surround the outer peripheral surface of the first semiconductor layer 11, and the second semiconductor layer 13 may be provided and / or formed to surround the active layer 12. The light emitting element LD may further include a contact electrode (not shown) surrounding at least one side of the second semiconductor layer 13. In some embodiments, the light emitting element LD may further include an insulating film 14 provided on the outer peripheral surface of the light emitting pattern having a core-shell structure and including a transparent insulating material. The light emitting element LD implemented as a light emitting pattern having a core-shell structure may be manufactured by a growth method.

[0118] The above-mentioned light emitting element LD can be used as a light source (or light source) for various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and provided to each pixel area (for example, the light emitting area of ​​each pixel or the light emitting area of ​​each sub-pixel), each light emitting element LD can be surface treated so that the light emitting element LD can be unevenly gathered in the solution and can be uniformly sprayed.

[0119] The light-emitting unit (or light-emitting device) including the above-mentioned light-emitting element LD can be used in various types of electronic devices that require a display device and a light source. For example, in the case where a plurality of light-emitting elements LD are arranged in a pixel region of each pixel of a display panel, the light-emitting element LD can be used as a light source for each pixel. However, the application field of the light-emitting element LD is not limited to the above-mentioned example. For example, the light-emitting element LD can be used in other types of electronic devices (such as lighting equipment) that require a light source.

[0120] Figure 5 Shown included in Figure 1 Schematic top plan view of an embodiment of a sub-pixel in a display device. Figure 5 is a diagram for explaining some components included in the sub-pixel SPX.

[0121] refer to Figure 5 The subpixel SPX may include a bank BNK, first and second pixel electrodes PE1 and PE2, (1-1)th and (1-2)th intermediate electrodes CNEa and CNEb, first to third alignment electrodes ALE1 to ALE3, first to second connection electrodes CNL1 and CNL2, and a light emitting element LD.

[0122] The bank BNK may separate the sub-pixels SPX, and the emission area EMA may correspond to an opening defined by the bank BNK. In an embodiment, the bank BNK may form a space in which a fluid may be accommodated. For example, during a manufacturing process, ink including the light emitting element LD may be disposed in the space in which a fluid may be accommodated.

[0123] The non-light emitting area NEA may be a region substantially corresponding to the bank BNK. In a plan view, the bank BNK may surround the light emitting area EMA.

[0124] The sub-pixel SPX may include first to third alignment electrodes ALE1 to ALE3. In an implementation, the first to third alignment electrodes ALE1 to ALE3 may be used as electrodes for aligning the light emitting element LD and electrodes for applying a predetermined or selected voltage.

[0125] The first to third alignment electrodes ALE1 to ALE3 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0126] The first connection electrode CNL1 may be integrally formed by being disposed in the same layer as the first alignment electrode ALE1 and the third alignment electrode ALE3. The second connection electrode CNL2 may be integrally formed by being disposed in the same layer as the second alignment electrode ALE2.

[0127] The first to third alignment electrodes ALE1 to ALE3 may serve as alignment electrodes of the light emitting elements LD. For example, the light emitting elements LD may be arranged based on electrical signals supplied to the first to third alignment electrodes ALE1 to ALE3.

[0128] In an embodiment, in a process step (hereinafter, alignment process) in which the light emitting element LD is aligned, the first to third alignment electrodes ALE1 to ALE3 may be supplied (or provided) with a first alignment signal or a second alignment signal, respectively.

[0129] In an embodiment, a first alignment signal may be applied to the first alignment electrode ALE1 and the third alignment electrode ALE3. A second alignment signal may be applied to the second alignment electrode ALE2 disposed between the first alignment electrode ALE1 and the third alignment electrode ALE3. In an embodiment, the first alignment electrode ALE1 and the third alignment electrode ALE3 may be connected to the first signal line through the (1-1)th contact portion CNTa formed on the first connection electrode CNL1, and in an alignment process, the first alignment signal may be provided to the first alignment electrode ALE1 and the third alignment electrode ALE3 through the first signal line. In an embodiment, the second alignment signal may be provided to the second alignment electrode ALE2 through the (1-2)th contact portion CNTb formed on the second connection electrode CNL2.

[0130] The light emitting elements LD may be arranged in a parallel structure along the second direction DR2. The arrangement structure of the light emitting elements LD is not limited thereto.

[0131] In a plan view, the light emitting element LD may be disposed between the first to third alignment electrodes ALE1 to ALE3. In an embodiment, the light emitting element LD may include a (1-1)th light emitting element LD1 and a (1-2)th light emitting element LD2. In an embodiment, the (1-1)th light emitting element LD1 may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2 (or disposed on the first alignment electrode ALE1 and the second alignment electrode ALE2). The (1-2)th light emitting element LD2 may be disposed between the second alignment electrode ALE2 and the third alignment electrode ALE3 (or disposed on the second alignment electrode ALE2 and the third alignment electrode ALE3).

[0132] The first pixel electrode PE1 may be disposed on the first alignment electrode ALE1 in a plan view to be electrically connected to one end portion of the (1-1)th light emitting element LD1. The (1-1)th intermediate electrode CNEa may be disposed on the second alignment electrode ALE2 to be electrically connected to the other end portion of the (1-1)th light emitting element LD1. In an embodiment, the (1-1)th intermediate electrode CNEa may correspond to Figure 2BThe first pixel electrode PE1 and the (1-1)th intermediate electrode CNEa may cover an end portion of a light emitting element adjacent to the first connection electrode CNL1 among the (1-1)th light emitting element LD1 disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2, and an end portion of a light emitting element adjacent to the second connection electrode CNL2 among the (1-1)th light emitting element LD1 may be connected by a separate intermediate electrode (e.g., Figure 2B The first intermediate electrode CNE1 and the second intermediate electrode CNE2 are covered.

[0133] The second pixel electrode PE2 may be disposed on the second alignment electrode ALE2 in a plan view to be electrically connected to one end portion of the (1-2)th light emitting element LD2. The (1-2)th intermediate electrode CNEb may be disposed on the third alignment electrode ALE3 to be electrically connected to the other end portion of the (1-2)th light emitting element LD2. In an embodiment, the (1-2)th intermediate electrode CNEb may correspond to Figure 2B The second pixel electrode PE2 and the (1-2)th intermediate electrode CNEb may cover an end portion of a light emitting element adjacent to the first connection electrode CNL1 among the (1-2)th light emitting element LD2 disposed between the second alignment electrode ALE2 and the third alignment electrode ALE3, and an end portion of a light emitting element adjacent to the second connection electrode CNL2 among the (1-2)th light emitting element LD2 may be connected by a separate intermediate electrode (e.g., Figure 2B The second intermediate electrode CNE2 and the third intermediate electrode CNE3 are covered.

[0134] The first to third alignment electrodes ALE1 to ALE3 may be electrically connected to a pixel circuit (eg, Figure 2A or Figure 2B For example, the first alignment electrode ALE1 and the third alignment electrode ALE3 may be electrically connected to the pixel circuit PXC and / or the first power line (eg, Figure 2A or Figure 2B The second alignment electrode ALE2 may be electrically connected to the pixel circuit PXC and / or the second power line (eg, Figure 2A or Figure 2B The second power line PL2).

[0135] The first pixel electrode PE1 may be directly connected to the first power line PL1 through a separate contact portion (not shown) different from the (1-1)th contact portion CNTa, and the second pixel electrode PE2 may be directly connected to the second power line PL2 through a separate contact portion (not shown) different from the (1-2)th contact portion CNTb, but is not limited thereto. The first pixel electrode PE1 may be connected to the first power line PL1 through the first connection electrode CNL1, and the second pixel electrode PE2 may be connected to the second power line PL2 through the second connection electrode CNL2.

[0136] In the case where the light emitting element LD is provided in the sub-pixel SPX, the light emitting element LD may configure an effective light source in the case where the light emitting element LD is arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 or between the second alignment electrode ALE2 and the third alignment electrode ALE3 in the forward direction, and the light emitting element LD may configure an ineffective light source in the case where it is arranged in the reverse direction. In an embodiment, in order to improve the light emitting efficiency of the sub-pixel SPX, it may be desirable to ensure that sufficient light emitting elements LD are provided in the forward direction between the first alignment electrode ALE1 and the second alignment electrode ALE2 or between the second alignment electrode ALE2 and the third alignment electrode ALE3.

[0137] Figure 6 Shown along Figure 5 A schematic cross-sectional view of an embodiment of a sub-pixel taken along line AA′ of FIG.

[0138] In an embodiment, the subpixel SPX may include a substrate SUB, a display element region DPA, and a light conversion region LCA. The display element region DPA and the light conversion region LCA may be sequentially disposed and / or formed on the substrate SUB. When viewed in a cross-sectional view, the light conversion region LCA may overlap with the display element region DPA.

[0139] In an implementation, the display element area DPA may include a passivation layer PVX, a via layer VIA, a data line DL, a wall pattern WP, first and second alignment electrodes ALE1 and ALE2 , a (1-1)th light emitting element LD1 , and insulating layers INS1 to INS3 .

[0140] In an embodiment, the passivation layer PVX may be completely disposed on the substrate SUB. The passivation layer PVX may include an inorganic material. The passivation layer PVX may be provided as a single film, or may be provided as a multi-film of at least two or more films. The data line DL of the sub-pixel SPX may be provided on the passivation layer PVX. When viewed in a cross-sectional view, the data line DL may overlap with the second alignment electrode ALE2.

[0141] In an implementation, the via layer VIA may be completely disposed on the passivation layer PVX to cover the data line DL. The via layer VIA may include an organic material and may provide a flat surface at an upper portion thereof.

[0142] In an embodiment, when viewed in a cross-sectional view, the display element region DPA may not be aligned with the pixel circuit (eg, Figure 2A or Figure 2B Components of the pixel circuit PXC) in FIG. Figure 2A or Figure 2B The transistors T1 to T3 in the pixel circuit region (eg, Figure 8 The pixel circuit area PCA) overlaps.

[0143] The wall pattern WP, the first and second alignment electrodes ALE1 and ALE2 , the (1-1)th light emitting element LD1 , the first pixel electrode PE1 , the (1-1)th intermediate electrode CNEa, and the insulating layers INS1 to INS3 may be disposed on the via layer VIA.

[0144] The wall pattern WP may be disposed on the through-hole layer VIA. Each of the wall patterns WP may include a curved surface having a cross section of a semi-elliptical shape or a semi-circular shape (or a hemispherical shape), the width of which narrows from the surface of the through-hole layer VIA along the third direction DR3 toward its upper portion. However, the embodiment is not limited thereto, and each of the wall patterns WP may have a trapezoidal cross section, the width of which narrows from the surface (e.g., the upper surface) of the through-hole layer VIA along the third direction DR3 toward its upper portion. When viewed in a cross-sectional view, the shape of each of the wall patterns WP is not limited to the above-described embodiment, and the shape thereof may be variously changed within a range in which the wall pattern WP may improve the efficiency of light emitted from the (1-1)th light emitting element LD1.

[0145] The wall pattern WP may include an inorganic material and / or an organic material, and may be configured by a single film or a plurality of films. In some embodiments, the wall pattern WP may be omitted. For example, a structure corresponding to the wall pattern WP may be formed in the via layer VIA.

[0146] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed on the via layer VIA and the wall pattern WP. The first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed on the wall pattern WP. When viewed in a cross-sectional view, the first alignment electrode ALE1 and the second alignment electrode ALE2 may have surface profiles corresponding to shapes of the wall pattern WP, respectively.

[0147] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may include a conductive material having a constant reflectivity to allow light emitted from the (1-1)th light emitting element LD1 to be guided in an image display direction (e.g., third direction DR3) of the display device. The first alignment electrode ALE1 and the second alignment electrode ALE2 may be configured by a single film or a plurality of films.

[0148] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be used as alignment electrodes for aligning the (1-1)th light emitting element LD1 in a manufacturing process of the display device.

[0149] refer to Figure 5 and Figure 6 , Figure 6 Only the first alignment electrode ALE1 and the second alignment electrode ALE2 except the third alignment electrode ALE3 are shown, but the third alignment electrode ALE3 and the second alignment electrode ALE2 may be spaced apart from each other in the first direction DR1, and the (1-2)th light emitting element LD2 may be disposed between the second alignment electrode ALE2 and the third alignment electrode ALE3.

[0150] The first insulating layer INS1 may be disposed on the via layer VIA to cover at least a portion of the first alignment electrode ALE1 and the second alignment electrode ALE2. The first insulating layer INS1 may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2 and may prevent a short circuit between the first alignment electrode ALE1 and the second alignment electrode ALE2. The first insulating layer INS1 may include an organic material or an inorganic material.

[0151] The (1-1)th light emitting element LD1 may be disposed on the first insulating layer INS1. In an embodiment, a first end portion (eg, Figure 3 The first end portion EP1 in the (1-1) light emitting element LD1 is directed toward the first alignment electrode ALE1, and the second end portion (eg, Figure 3 The second end portion EP2 in the embodiment is directed toward the second alignment electrode ALE2, so that the (1-1)th light emitting element LD1 can be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0152] The second insulating layer INS2 (or the second insulating pattern) may be disposed on the (1-1)th light emitting element LD1. The second insulating layer INS2 may be disposed on a portion of the upper surface of the (1-1)th light emitting element LD1 so that the first end portion and the second end portion of the (1-1)th light emitting element LD1 are exposed to the outside. In some embodiments, the second insulating layer INS2 may also be disposed on the first insulating layer INS1.

[0153] According to the design conditions of the display device including the (1-1)th light emitting element LD1, the second insulating layer INS2 may include an inorganic material or an organic material. After completing the alignment of the (1-1)th light emitting element LD1 on the first insulating layer INS1, the second insulating layer INS2 may be disposed on the (1-1)th light emitting element LD1, thereby preventing the (1-1)th light emitting element LD1 from being separated from the aligned position. Before forming the second insulating layer INS2, in the case where there is a gap (or space) between the first insulating layer INS1 and the (1-1)th light emitting element LD1, in the process of forming the second insulating layer INS2, the gap may be filled with the second insulating layer INS2.

[0154] In an implementation, the first pixel electrode PE1 may be disposed on the second insulating layer INS2. The first pixel electrode PE1 may directly contact a first end portion of the (1-1)th light emitting element LD1. The first pixel electrode PE1 may be disposed on the first alignment electrode ALE1.

[0155] In an embodiment, the third insulating layer INS3 may be disposed on the second insulating layer INS2 and the first pixel electrode PE1 to cover the second insulating layer INS2 and the first pixel electrode PE1. The third insulating layer INS3 may be disposed so that an end of the third insulating layer INS3 and an edge of the second insulating layer INS2 contact each other so that the second end portion of the (1-1)th light emitting element LD1 is exposed. The third insulating layer INS3 may include an inorganic material.

[0156] In an embodiment, the (1-1)th intermediate electrode CNEa may be disposed on the third insulating layer INS3. The (1-1)th intermediate electrode CNEa may directly contact the second end portion of the (1-1)th light emitting element LD1. The (1-1)th intermediate electrode CNEa may be disposed on the second alignment electrode ALE2.

[0157] Figure 6 It is shown that the first pixel electrode PE1 and the (1-1)th intermediate electrode CNEa are disposed on different layers, and the third insulating layer INS3 may be between the first pixel electrode PE1 and the (1-1)th intermediate electrode CNEa, but the present disclosure is not limited thereto. For example, the first pixel electrode PE1 and the (1-1)th intermediate electrode CNEa may be disposed on the same layer (e.g., the second insulating layer INS2) by the same process.

[0158] The light conversion area LCA may be disposed and / or formed on the display element area DPA. The light conversion area LCA may include a color conversion layer CCL and a color filter CF.

[0159] dike (e.g. Figure 5A bank BNK (not shown) may be disposed on the third insulating layer INS3. The bank may have a trapezoidal cross-section in which a width of the bank decreases from a surface (eg, upper surface) of the third insulating layer INS3 toward an upper portion along a third direction DR3.

[0160] The color conversion layer CCL may be disposed on the display element area DPA (or the (1-1)th light emitting element LD1 ) in a region surrounded by the bank.

[0161] The color conversion layer CCL may include color conversion particles QD (or wavelength conversion particles) corresponding to a specific color. As an example, the color conversion layer CCL may include color conversion particles QD that convert light of a first color (or a first wavelength band) incident from the light emitting element LD into light of a second color (or a specific color or a second wavelength band) and emit the light.

[0162] In the case where the subpixel SPX is a red pixel (or a red subpixel), the subpixel SPX may include color conversion particles of red quantum dots that convert first color light emitted from the (1-1)th light emitting element LD1 into second color light (eg, red light).

[0163] In the case where the subpixel SPX is a green pixel (or green subpixel), the subpixel SPX may include color conversion particles of green quantum dots that convert the first color light emitted from the (1-1)th light emitting element LD1 into second color light (eg, green light).

[0164] In the case where the sub-pixel SPX is a blue pixel (or a blue sub-pixel), the sub-pixel SPX may include color conversion particles of blue quantum dots that convert light of a first color emitted from the (1-1)th light-emitting element LD1 into light of a second color (e.g., blue light). In the case where the sub-pixel SPX is a blue pixel and the (1-1)th light-emitting element LD1 emits blue-based light, the sub-pixel SPX may include a light scattering layer including light scattering particles SCT. According to an embodiment, the above-mentioned light scattering layer may be omitted. According to another embodiment, in the case where the sub-pixel SPX is a blue pixel, a transparent polymer may be provided instead of the color conversion layer CCL.

[0165] The first capping layer CAP1 may seal (or cover) the color conversion layer CCL. The first capping layer CAP1 may be disposed between the low refractive index layer LRL and the color conversion layer CCL. The first capping layer CAP1 may prevent impurities such as moisture or air from penetrating from the outside. For example, the first capping layer CAP1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlOx ) at least one of.

[0166] The low refractive index layer LRL may be disposed between the first capping layer CAP1 and the second capping layer CAP2. The low refractive index layer LRL may improve light efficiency by recycling light provided from the color conversion layer CCL. To this end, the low refractive index layer LRL may have a lower refractive index than the color conversion layer CCL. In an embodiment, the low refractive index layer LRL may include a base resin and hollow particles dispersed in the base resin. The hollow particles may include hollow silica particles. The hollow particles may be pores formed by a porogen, but are not necessarily limited thereto. The low refractive index layer LRL may include zinc oxide (ZnO x ), titanium oxide (TiO x ) and at least one of nano-silicate particles, but not necessarily limited thereto.

[0167] In an embodiment, the second capping layer CAP2 may be disposed on the low refractive index layer LRL. The second capping layer CAP2 may prevent impurities such as moisture or air from penetrating from the outside. The second capping layer CAP2 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0168] In an embodiment, a color filter CF may be disposed on the second capping layer CAP2. The color filter CF may include a color filter material that selectively transmits light of a specific color converted by the color conversion layer CCL. In an embodiment, when the sub-pixel SPX is a red pixel, the color filter CF disposed on the color conversion layer CCL may be a red color filter. When the sub-pixel SPX is a green pixel, the color filter CF disposed on the color conversion layer CCL may be a green color filter. When the sub-pixel SPX is a blue pixel, the color filter CF disposed on the color conversion layer CCL may be a blue color filter.

[0169] The overcoat layer OC may be disposed on the color filter CF. The overcoat layer OC may include an inorganic material or an organic material. The overcoat layer OC may completely cover the components disposed thereunder to prevent moisture or water from flowing from the outside into the color filter CF and the display element area DPA. In an embodiment, the overcoat layer OC may be formed of a plurality of layers. For example, the overcoat layer OC may include at least two layers of an inorganic film and at least one layer of an organic film interposed between the at least two layers of the inorganic film. However, the material and / or structure of the overcoat layer OC may be variously changed.

[0170] In the above embodiments, it has been described that the color conversion layer CCL is directly formed on the display element area DPA, but the present disclosure is not limited thereto. In some embodiments, the color conversion layer CCL may be formed on a separate substrate to be coupled to the display element area DPA through an adhesive material. For example, the adhesive material may be an optically transparent adhesive layer, but is not limited thereto.

[0171] Figure 7 A comparative example of arrangement of the light emitting element according to the position of the conductive pattern of the pixel circuit is shown.

[0172] refer to Figure 7 , the display device may include alignment electrodes ALE1 to ALE7 and light emitting elements LD for configuring pixels.

[0173] The alignment electrodes ALE1 to ALE7 may be spaced apart from each other in the first direction DR1.

[0174] The first pixel PXL1 and the second pixel PXL2 may be spaced apart from each other in the second direction DR2. The first to third subpixels SPX1 to SPX3 included in each of the first pixel PXL1 to the second pixel PXL2 may be spaced apart from each other in the first direction DR1.

[0175] The first pixel PXL1 and the second pixel PXL2 may share alignment electrodes ALE1 to ALE7 with each other. The first subpixel SPX1 of the first pixel PXL1 may share first to third alignment electrodes ALE1 to ALE3 with the first subpixel SPX1 of the second pixel PXL2.

[0176] The alignment electrodes ALE1 to ALE7 may be electrodes for aligning the light emitting element LD. For example, an electric field is formed between (or on) the alignment electrodes ALE1 to ALE7, and the light emitting element LD may be aligned on the alignment electrodes ALE1 to ALE7 based on the electric field. For example, the light emitting element LD may be moved (or rotated) by a force according to the electric field (e.g., a dielectrophoresis (DEP) force) to align (or set) on the alignment electrodes ALE1 to ALE7.

[0177] A pixel circuit including a plurality of transistors and capacitors may be disposed under the alignment electrodes ALE1 to ALE7 where the light emitting elements LD are disposed. Since the pixel circuit may be disposed under the alignment electrodes ALE1 to ALE7, the conductive pattern CP may overlap a region between the alignment electrodes ALE1 to ALE7.

[0178] In the case where the conductive pattern CP is disposed in the lower region between the alignment electrodes ALE1 to ALE7, the signal of the electric field formed between the alignment electrodes ALE1 to ALE7 may be distorted due to the conductive pattern CP during the alignment process. Therefore, in the alignment process of the light emitting element LD, even if the electric field is applied to the alignment electrodes ALE1 to ALE7, the light emitting element LD may not be disposed on the alignment electrodes ALE1 to ALE7 overlapping the conductive pattern CP. For example, in the case where the conductive pattern CP is disposed in the lower region between the alignment electrodes ALE1 to ALE7, it may be difficult to ensure the light emitting efficiency because the light emitting element does not match the display region.

[0179] In the alignment process, in order to fix the light emitting element LD set on the alignment electrodes ALE1 to ALE7 and configure an effective light source, the distortion of the signal of the electric field formed between the alignment electrodes ALE1 to ALE7 should be minimized. To this end, the lower area of ​​the alignment electrodes ALE1 to ALE7 and the components of the pixel circuit may not overlap. Specifically, when the conductive pattern CP does not overlap with the lower area between the alignment electrodes ALE1 to ALE7 (which is most likely to affect the electric field formed between the alignment electrodes ALE1 to ALE7), the distortion of the signal of the electric field formed between the alignment electrodes ALE1 to ALE7 can be minimized.

[0180] The conductive pattern CP may be an electrode of a storage capacitor configuring the pixel circuit, but is not limited thereto. For example, the conductive pattern CP may include a first terminal (source electrode) or a second terminal (drain electrode) of a transistor.

[0181] Figure 8 Shows Figure 1 Schematic top plan view of an embodiment of a display area.

[0182] Figure 8 A layout diagram showing an embodiment of a pixel that may be included in a display device is shown. Figure 8 The pixel PXL may include first to third sub-pixels SPX1 to SPX3 spaced apart from each other in the first direction DR1, and a pixel circuit (eg, Figure 2A or Figure 2B The pixel circuit PXC) may have a structure symmetrical with the pixel circuit of the second sub-pixel SPX2 in the first direction DR1, and the third sub-pixel SPX3 may have a structure substantially the same as or similar to that of the first sub-pixel SPX1. Therefore, the configurations of the first to third sub-pixels SPX1 to SPX3 will be described based on the first sub-pixel SPX1, and redundant descriptions will not be repeated.

[0183] In an embodiment, the first sub-pixel SPX1 to the third sub-pixel SPX3 may include a display element area DPA and a pixel circuit area PCA. In an embodiment, the display element area DPA may be a region in which a light-emitting element LD emitting light is disposed. In an embodiment, the pixel circuit area PCA may include a plurality of transistors and signal wirings connected to the transistors. In each of the transistors, a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode may be stacked on each other. An insulating layer may be disposed between one or more of the semiconductor pattern, the gate electrode, the source electrode, and the drain electrode. In an embodiment, the pixel circuit area PCA may not overlap with the display element area DPA in a plan view. In an embodiment, the pixel circuit area PCA may be spaced apart from the display element area DPA in the second direction DR2.

[0184] In an embodiment, the first vertical power line PL1a, the first data line DL1, the first sensing line SEN1, the second data line DL2, the second vertical power line PL2a, the third data line DL3, and the second sensing line SEN2 may extend in the second direction DR2, respectively, and may be arranged along the first direction DR1. In an embodiment, the first vertical power line PL1a and the second vertical power line PL2a and the first sensing line SEN1 and the second sensing line SEN2 may be disposed on a first conductive layer (e.g., Fig.11 The first to third data lines DL1 to DL3 may be disposed on an interlayer insulating layer ILD in the embodiment of the present invention, and the first to third data lines DL1 to DL3 may be disposed on a second conductive layer (eg, a second conductive layer) that may be different from the first conductive layer. Fig.11 However, the present disclosure is not limited thereto, and the first to third data lines DL1 to DL3 may be disposed on the first conductive layer.

[0185] In an embodiment, the second horizontal power line PL2b, the first horizontal power line PL1b, and the scan line SL may extend in the first direction DR1, respectively, and may be arranged along the second direction DR2. In an embodiment, the first horizontal power line PL1b, the second horizontal power line PL2b, and the scan line SL may be disposed on the third conductive layer (e.g., Fig.11 On the buffer layer BFL).

[0186] In an implementation, the first power line PL1 may receive a voltage of a first driving power source VDD. The first vertical power line PL1a and the first horizontal power line PL1b may be electrically connected to each other through the first contact hole CNT1.

[0187] In an implementation, the second power line PL2 may receive a voltage of a second driving power source VSS. The second vertical power line PL2a and the second horizontal power line PL2b may be electrically connected to each other through the second contact hole CNT2.

[0188] In an embodiment, the first vertical power line PL1a and the second vertical power line PL2a may extend from the display element area DPA to the pixel circuit area PCA. In an embodiment, the first vertical power line PL1a may be disposed on one side of the first subpixel SPX1. In an embodiment, the first vertical power line PL1a may overlap with the first alignment electrode ALE1 disposed in the display element area DPA. The second vertical power line PL2a may be disposed between the second subpixel SPX2 and the third subpixel SPX3. The second vertical power line PL2a may overlap with the fifth alignment electrode ALE5 disposed in the display element area DPA.

[0189] In an embodiment, the first sensing line SEN1 and the second sensing line SEN2 may extend from the display element area DPA to the pixel circuit area PCA. The first sensing line SEN1 and the second sensing line SEN2 may receive a voltage of an initialization power supply. The first sensing line SEN1 may be electrically connected to a third transistor T3 of each of the first sub-pixel SPX1 and the second sub-pixel SPX2. The second sensing line SEN2 may be electrically connected to a third transistor T3 of the third sub-pixel SPX3 and a third transistor T3 of the first sub-pixel SPX1 of a pixel adjacent to the pixel PXL in the first direction DR1.

[0190] In an embodiment, the first to third data lines DL1 to DL3 may extend from the display element area DPA to the pixel circuit area PCA. The first data line DL1 may overlap with the second alignment electrode ALE2 of the first sub-pixel SPX1. The first data line DL1 may overlap with the eighth alignment electrode ALE8 of the first sub-pixel SPX1 adjacent to the third sub-pixel SPX3. The second data line DL2 may overlap with the fourth alignment electrode ALE4 of the second sub-pixel SPX2. The third data line DL3 may overlap with the sixth alignment electrode ALE6 of the third sub-pixel SPX3. Each of the first to third data lines DL1 to DL3 may receive a data signal. The first data line DL1 may be electrically connected to the second transistor T2 of the first sub-pixel SPX1. The second data line DL2 may be electrically connected to the second transistor T2 of the second sub-pixel SPX2. The third data line DL3 may be electrically connected to the second transistor T2 of the third sub-pixel SPX3.

[0191] In an embodiment, in a process step (hereinafter referred to as an alignment process) in which the light emitting element LD is aligned on the alignment electrodes ALE1 to ALE7, the same alignment signal as the alignment signal applied to the second alignment electrode ALE2, the fourth alignment electrode ALE4, and the sixth alignment electrode ALE6 may be applied to the first data line DL1, the second data line DL2, and the third data line DL3. For example, when the same alignment signal as the alignment signal applied to the alignment electrodes ALE2, ALE4, and ALE6 overlapping the first data lines DL1 to DL3 is applied to the first data lines DL1 to DL3, in the alignment process, distortion of the alignment signal caused by the first data lines DL1 to DL3 may be reduced.

[0192] In an embodiment, in a plan view, the first sensing line SEN1 may be disposed between the first data line DL1 and the second data line DL2. The second sensing line SEN2 may be disposed between the third data line DL3 and the first data line DL1 of the first subpixel SPX1 of the pixel adjacent to the pixel PXL in the first direction DR1. In an embodiment, the first sensing line SEN1 may overlap the third alignment electrode ALE3. The second sensing line SEN2 may overlap the seventh alignment electrode ALE7.

[0193] In an embodiment, in the display element area DPA of the first sub-pixel SPX1, the first to third alignment electrodes ALE1 to ALE3 may extend in the second direction DR2 and may be sequentially arranged in the first direction DR1. In an embodiment, in the display element area DPA of the second sub-pixel SPX2, the third to fifth alignment electrodes ALE3 to ALE5 may extend in the second direction DR2 and may be sequentially arranged in the first direction DR1. In an embodiment, in the display element area DPA of the third sub-pixel SPX3, the fifth to seventh alignment electrodes ALE5 to ALE7 may extend in the second direction DR2 and may be sequentially arranged in the first direction DR1.

[0194] In an embodiment, the first sub-pixel SPX1 and the second sub-pixel SPX2 may share the third alignment electrode ALE3 , and the second sub-pixel SPX2 and the third sub-pixel SPX3 may share the fifth alignment electrode ALE5 .

[0195] In an embodiment, the light emitting element LD may be disposed on (or between) the first to seventh alignment electrodes ALE1 to ALE7 .

[0196] In an embodiment, the pattern electrode CPE may be disposed in the display element area DPA of the first sub-pixel SPX1 to the third sub-pixel SPX3. In an embodiment, the pattern electrode CPE may include the first pattern electrode CPE1 to the third pattern electrode CPE3. The first pattern electrode CPE1 to the third pattern electrode CPE3 may extend in the first direction DR1 and may be spaced apart from each other along the first direction DR1. In an embodiment, the first pattern electrode CPE1 may extend in the first direction DR1 in the display element area DPA of the first sub-pixel SPX1, and in a plan view, they may overlap with the first alignment electrode ALE1 to the third alignment electrode ALE3. In an embodiment, the second pattern electrode CPE2 may extend in the first direction DR1 in the display element area DPA of the second sub-pixel SPX2, and in a plan view, they may overlap with the third alignment electrode ALE3 to the fifth alignment electrode ALE5. In an embodiment, the third pattern electrode CPE3 may extend in the first direction DR1 in the display element area DPA of the third sub-pixel SPX3, and in a plan view, they may overlap with the fifth alignment electrode ALE5 to the seventh alignment electrode ALE7.

[0197] In an embodiment, the light emitting element LD may not be disposed on the alignment electrodes ALE1 to ALE7 overlapping the pattern electrode CPE. In an embodiment, in a plan view, the first pattern electrode CPE1 of the first subpixel SPX1 may overlap an area between the first alignment electrode ALE1 and the second alignment electrode ALE2 and an area between the second alignment electrode ALE2 and the third alignment electrode ALE3. In an embodiment, the light emitting element LD may not be disposed on the first alignment electrodes ALE1 to the third alignment electrodes ALE3 overlapping the first pattern electrode CPE1.

[0198] In an embodiment, the light emitting element LD may include a (1-1)th light emitting element LD1 and a (1-2)th light emitting element LD2. The (1-1)th light emitting element LD1 may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2. The (1-2)th light emitting element LD2 may be disposed between the second alignment electrode ALE2 and the third alignment electrode ALE3.

[0199] In an embodiment, the (1-1)th light emitting element LD1 may include the (1-1a)th light emitting element LD1a disposed in the second direction DR2 (or at the upper side) relative to the first pattern electrode CPE1 and the (1-1b)th light emitting element LD1b disposed in the direction opposite to the second direction DR2 (or at the lower side). In an embodiment, the (1-2)th light emitting element LD2 may include the (1-2a)th light emitting element LD2a disposed in the second direction DR2 (or at the upper side) relative to the first pattern electrode CPE1 and the (1-2b)th light emitting element LD2b disposed in the direction opposite to the second direction DR2 (or at the lower side). In an embodiment, in the case where the first sub-pixel SPX1 has 4 consecutive series stages, the (1-1a)th light emitting element LD1a may correspond to the first light emitting element (for example, Figure 2B The (1-1b)th light emitting element LD1b may correspond to the second light emitting element (eg, Figure 2B The (1-2a)th light emitting element LD2a may correspond to the fourth light emitting element (eg, Figure 2B The (1-2b)th light emitting element LD2b may correspond to the third light emitting element (eg, Figure 2B The third light emitting element LDc in the embodiment.

[0200] In another embodiment, the pattern electrode CPE may be omitted. The light emitting elements LD may be uniformly disposed between the alignment electrodes ALE1 to ALE7 in the region between the alignment electrodes ALE1 to ALE7 without a region in which the light emitting elements LD are not disposed.

[0201] In an embodiment, the pixel circuit area PCA of the first to third subpixels SPX1 to SPX3 may include first to third connection patterns CP1 to CP3 and a capacitor Cst.

[0202] In an embodiment, the first data line DL1 may extend from the display element area DPA to the pixel circuit area PCA to be disposed adjacent to one side of the capacitor Cst. A portion of the first data line DL1 may overlap the first horizontal power line PL1b.

[0203] In an embodiment, the capacitor Cst may be spaced apart from the first horizontal power line PL1b in the second direction DR2.

[0204] In an embodiment, the first connection pattern CP1 may configure the first transistor T1. The first connection pattern CP1 may correspond to a semiconductor pattern of the first transistor T1. In an embodiment, one end of the first connection pattern CP1 may be electrically connected to the first horizontal power line PL1b through the (3-1)th contact hole CNT3a of the third contact hole CNT3. The other end of the first connection pattern CP1 may be electrically connected to the pixel electrode through the (3-2)th contact hole CNT3b of the third contact hole CNT3.

[0205] In an embodiment, the second connection pattern CP2 may configure the second transistor T2. The second connection pattern CP2 may correspond to a semiconductor pattern of the second transistor T2. The second connection pattern CP2 may be spaced apart from the first connection pattern CP1 in a diagonal direction (e.g., a direction between the first direction DR1 and the second direction DR2), and may extend in the first direction DR1. In an embodiment, one end of the second connection pattern CP2 may be electrically connected to the first data line DL1 through the first bridging electrode BRE1 and the fourth contact portion CNT4. The other end of the second connection pattern CP2 may be electrically connected to the upper electrode UE of the capacitor Cst through the second bridging electrode BRE2 and the fifth contact portion CNT5.

[0206] In an embodiment, the third connection pattern CP3 may configure the third transistor T3. The third connection pattern CP3 may correspond to a semiconductor pattern of the third transistor T3. In an embodiment, one end of the third connection pattern CP3 may be electrically connected to the first sensing line SEN1 through the fourth bridging electrode BRE4 and the seventh contact portion CNT7. The third connection pattern CP3 may be spaced apart from the second connection pattern CP2 in the first direction DR1 and may extend in the first direction DR1. In an embodiment, one end of the third connection pattern CP3 may be electrically connected to the lower electrode LE of the capacitor Cst through the third bridging electrode BRE3 and the sixth contact portion CNT6.

[0207] In an embodiment, the scan line SL may be spaced apart from the capacitor Cst in a direction opposite to the second direction DR2 and may extend in the first direction DR1. The first to third subpixels SPX1 to SPX3 may configure gate electrodes of the second and third transistors T2 and T3, respectively.

[0208] The data lines DL1 to DL3 of the display device according to the embodiment of the present disclosure may overlap with the alignment electrodes, so that the data lines DL1 to DL3 of each of the first to third sub-pixels SPX1 to SPX3 may not be exposed through the space between the alignment electrodes ALE1 to ALE7, thereby minimizing the distortion of the electric field formed between the alignment electrodes ALE1 to ALE7 in the alignment process. Therefore, since the light emitting elements LD may be uniformly disposed between the alignment electrodes ALE1 to ALE7, the display device may improve light emitting efficiency.

[0209] In the display device according to the embodiment, by preventing the display element region DPA in which the light emitting element LD is disposed and the pixel circuit region PCA in which the transistors T1 to T3 and the capacitor Cst are disposed from overlapping, the distortion of the electric field formed between the alignment electrodes ALE1 to ALE7 caused by the transistors T1 to T3 and the capacitor Cst configuring the pixel circuit can be minimized (or improved) in the alignment process. Therefore, the display device can ensure light emission efficiency.

[0210] The display device according to the embodiment may dispose the pattern electrode CPE to cross the alignment electrodes ALE1 to ALE7 in the display element area DPA to more efficiently form a series stage of the light emitting element LD including the first to third sub-pixels SPX1 to SPX3 .

[0211] Fig. 9 Shown along Figure 8 A schematic cross-sectional view taken along line II'.

[0212] refer to Figure 8 and Fig. 9 , the substrate SUB, the buffer layer BFL, the interlayer insulating layer ILD, the passivation layer PVX and the via layer VIA may be included in the display element area DPA of each of the first to third subpixels SPX1 to SPX3. The buffer layer BFL, the interlayer insulating layer ILD, the passivation layer PVX and the via layer VIA may be sequentially disposed on the substrate SUB.

[0213] In an implementation, the first data line DL1 may be disposed on the passivation layer PVX. A via layer VIA may be disposed on the passivation layer PVX to cover the first data line DL1.

[0214] In an implementation, the first to third alignment electrodes ALE1 to ALE3 may be spaced apart from each other in the first direction DR1 on the via layer VIA.

[0215] In an embodiment, the (1-1)th light emitting element LD1 may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2. The (1-2)th light emitting element LD2 may be disposed between the second alignment electrode ALE2 and the third alignment electrode ALE3.

[0216] In an embodiment, the first data line DL1 may overlap the second alignment electrode ALE2 when viewed in a cross-sectional view. In an embodiment, the first data line DL1 may not overlap an area between the first alignment electrode ALE1 and the second alignment electrode ALE2 and an area between the second alignment electrode ALE2 and the third alignment electrode ALE3. In an embodiment, a length of a first width L1 of the first data line DL1 in the first direction DR1 may be equal to or less than a length of a second width L2 of the second alignment electrode ALE2 in the first direction DR1. Since the first width L1 of the first data line DL1 is equal to or less than the second width L2 of the second alignment electrode ALE2, the influence of an electric field formed between the first to third alignment electrodes ALE1 to ALE3 in an alignment process may be minimized.

[0217] In an embodiment, in a process of aligning the light emitting element LD, a first alignment signal or a second alignment signal different from the first alignment signal may be supplied (provided) to the first to third alignment electrodes ALE1 to ALE3 and the first data line DL1 , respectively.

[0218] In an embodiment, the first alignment signal and the second alignment signal may have different waveforms, potentials and / or phases. The first alignment signal may be a ground signal, and the second alignment signal may be an AC signal. However, the present disclosure is not necessarily limited to the above examples. For example, the first alignment signal may be an AC signal, and the second alignment signal may be a ground signal.

[0219] In an embodiment, a first alignment signal may be applied to the first alignment electrode ALE1 and the third alignment electrode ALE3 . A second alignment signal may be applied to the second alignment electrode ALE2 and the first data line DL1 .

[0220] In an embodiment, a first end portion EP1 of the (1-1)th light emitting element LD1 may be adjacent to the first alignment electrode ALE1. A second end portion EP2 of the (1-1)th light emitting element LD1 may be adjacent to the second alignment electrode ALE2.

[0221] In an embodiment, the first end portion EP1 of the (1-2)th light emitting element LD2 may be adjacent to the third alignment electrode ALE3. The second end portion EP2 of the (1-2)th light emitting element LD2 may be adjacent to the second alignment electrode ALE2.

[0222] Fig.10Shown along Figure 8 A schematic cross-sectional view taken along line II-II'.

[0223] refer to Figure 8 and Fig.10 , the first pattern electrode CPE1 may be disposed on the buffer layer BFL. However, the present disclosure is not limited thereto, and the first pattern electrode CPE1 may be disposed on the interlayer insulating layer ILD. In an embodiment, the first pattern electrode CPE1 may configure the bottom metal layer of the first transistor T1, but is not limited thereto, and may form a gate electrode, a source electrode, or a drain electrode of the first transistor T1.

[0224] The first pattern electrode CPE1 may overlap the first to third alignment electrodes ALE1 to ALE3. In an embodiment, the first pattern electrode CPE1 may overlap a lower area between the first to third alignment electrodes ALE1 to ALE3. When viewed on the first to third alignment electrodes ALE1 to ALE3, the first pattern electrode CPE1 may be visually recognized by the area between the first to third alignment electrodes ALE1 to ALE3.

[0225] In an embodiment, the light emitting element LD may not be disposed on the first to third alignment electrodes ALE1 to ALE3 overlapping the first pattern electrode CPE1. In an alignment process of the light emitting element LD, the first pattern electrode CPE1 may affect an electric field formed on the first to third alignment electrodes ALE1 to ALE3 disposed on the first pattern electrode CPE1.

[0226] Fig.11 Shown along Figure 8 A schematic cross-sectional view taken along line III-III'.

[0227] refer to Fig.11 , the lower electrode LE may be disposed on the substrate SUB. A buffer layer BFL may be disposed on the substrate SUB to cover the lower electrode LE.

[0228] In an embodiment, the first connection pattern CP1 may be disposed on the buffer layer BFL. When viewed in a cross-sectional view, the first connection pattern CP1 may overlap the lower electrode LE. In an embodiment, an interlayer insulating layer ILD may be disposed on the buffer layer BFL to cover the first connection pattern CP1.

[0229] In an embodiment, the first vertical power line PL1a may be disposed on the interlayer insulating layer ILD. A passivation layer PVX may be disposed on the interlayer insulating layer ILD to cover the first vertical power line PL1a.

[0230] In an embodiment, the first data line DL1 and the upper electrode UE may be disposed on the passivation layer PVX. The first data line DL1 and the upper electrode UE may be spaced apart from each other in the first direction DR1. The upper electrode UE may overlap the lower electrode LE. The via layer VIA may cover the first data line DL1 and the upper electrode UE.

[0231] In an embodiment, the second pixel electrode PE2 and the bank BNK may be sequentially disposed on the via layer VIA. The second pixel electrode PE2 may be electrically connected to the first connection pattern CP1 through the (3-2)th contact hole CNT3b. The (3-2)th contact hole CNT3b may pass through the via layer VIA, the passivation layer PVX, and the interlayer insulating layer ILD.

[0232] Fig. 12A Shows Figure 1 Schematic cross-sectional view of an embodiment of the peripheral area of ​​. Fig. 12B Shows Figure 1 Schematic cross-sectional view of another embodiment of the peripheral area of ​​.

[0233] Fig. 12A An embodiment of a peripheral area PA of a display device before an alignment process during a manufacturing process of the display device is shown, and Fig. 12B An embodiment of a peripheral area PA of a display device after completing an alignment process during a manufacturing process of the display device is shown.

[0234] refer to Figure 5 , Figure 8 and Fig. 12A , in the alignment process of the light emitting element LD during the manufacturing process of the display device, the second connection electrode CNL2 may directly contact the data lines DL1 and DL2 through the first contact portion CH1. For example, the second connection electrode CNL2 may be electrically connected to the first data line DL1 and the second data line DL2 through the first contact portion CH1. In an embodiment, in the case where the first alignment signal is applied to the second alignment electrode ALE2, the fourth alignment electrode ALE4, and the sixth alignment electrode ALE6 connected to the second connection electrode CNL2, the same first alignment signal may be applied to the first data line DL1 and the second data line DL2. In an embodiment, in the alignment process of the light emitting element LD, the alignment signal applied to the second alignment electrode ALE2 overlapping the first data line DL1 and the fourth alignment electrode ALE4 overlapping the second data line DL2 may be equally applied to the first data line DL1 and the second data line DL2.

[0235] refer to Figure 5 , Figure 8 and Fig. 12BAfter the alignment process of the light emitting element LD is completed, the second connection electrode CNL2 may be divided into a (2-1)th partial connection electrode CNL2a, a (2-2)th partial connection electrode CNL2b, and a dummy electrode DME.

[0236] In an embodiment, regions corresponding to a portion from which the second connection electrode CNL2 is removed may be referred to as a first floating area FLA1 and a second floating area FLA2 .

[0237] In an embodiment, the first floating area FLA1 of the second link electrode CNL2 may be removed to be separated into the (2-1)th partial connection electrode CNL2a and the dummy electrode DME. The second floating area FLA2 of the second link electrode CNL2 may be removed to be separated into the (2-2)th partial connection electrode CNL2b and the dummy electrode DME.

[0238] In an embodiment, the process of removing a region of the second connection electrode CNL2 to separate it into the (2-1) partial connection electrode CNL2a, the (2-2) partial connection electrode CNL2b, and the dummy electrode DME may form a floating hole by emitting a laser to the second connection electrode CNL2 to remove a portion of the second connection electrode CNL2.

[0239] refer to Fig. 12B The floating area of ​​the second link electrode CNL2 is shown as the first floating area FLA1 and the second floating area FLA2, but is not limited thereto. For example, the floating area of ​​the second link electrode CNL2 may be one or more.

[0240] In an embodiment, the dummy electrode DME may be disposed between the first data line DL1 and the second data line DL2 extending to the peripheral area PA. In an embodiment, the dummy electrode DME may be in a floating state. For example, the dummy electrode DME may have an island shape that is not connected to other conductive layers (or conductive patterns).

[0241] Fig.13 Shows Figure 1 Schematic top plan view of another embodiment of a display area.

[0242] In components other than the pattern electrode CPE', Figure 8 Components that are identical or correspond to those shown in are not described redundantly.

[0243] In an implementation, the pattern electrode CPE' may extend in the first direction DR1 and may be integrally disposed across the first to third subpixels SPX1 to SPX3. In a plan view, the pattern electrode CPE' may overlap the first to seventh alignment electrodes ALE1 to ALE7.

[0244] In an implementation, the light emitting element LD may not be disposed on the alignment electrodes ALE1 to ALE7 overlapping the pattern electrode CPE′.

[0245] In an embodiment, the pattern electrode CPE' may be disposed on a conductive layer different from the conductive layer on which the first sensing line SEN1 and the second sensing line SEN2 are disposed. For example, the pattern electrode CPE' may be disposed on a substrate (eg, Fig.10 The substrate SUB) in the embodiment of the present invention may be formed on the substrate SUB, and a bottom metal layer of the first transistor T1 may be formed, but is not limited thereto.

[0246] In another embodiment, the pattern electrode CPE′ may be omitted. The light emitting elements LD may be uniformly disposed between the alignment electrodes ALE1 to ALE7 in the region between the alignment electrodes ALE1 to ALE7 without a region in which the light emitting elements LD are not disposed.

[0247] According to the display device according to the embodiment of the present disclosure, in the alignment process of the light-emitting element, through the configuration of the pixel circuit, by removing (or minimizing) the components of the pixel circuit that overlap with the area between the alignment electrodes, the distortion of the alignment signal or the limitation of the area where the light-emitting element is aligned can be minimized (or improved).

[0248] While the disclosure has been described in connection with what are considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the disclosure.

Claims

1. Display equipment, including: Substrate, comprising: display area; and a peripheral area, arranged on a side of the display area; a first alignment electrode, a second alignment electrode, and a third alignment electrode, overlapping the display area, being spaced apart from each other in a first direction, and extending in a second direction intersecting the first direction; a light emitting element disposed between the first alignment electrode and the second alignment electrode and between the second alignment electrode and the third alignment electrode; and a data line overlapping the second alignment electrode in a plan view and extending in the second direction, Wherein, a length of a first width of the data line in the first direction is less than or equal to a length of a second width of the second alignment electrode in the first direction.

2. The display device according to claim 1, further comprising: a pattern electrode overlapping the first alignment electrode, the second alignment electrode, and the third alignment electrode in a plan view and extending in the first direction, and The light emitting element does not overlap with the pattern electrode in a plan view.

3. The display device according to claim 2, wherein: The second alignment electrode and the data line provide a first alignment signal when aligning the light emitting element, and The first alignment electrode and the third alignment electrode provide a second alignment signal different from the first alignment signal.

4. The display device according to claim 2, further comprising: A passivation layer and a via layer are sequentially arranged on the substrate, wherein: The data line is disposed between the passivation layer and the via layer, and The first alignment electrode, the second alignment electrode, and the third alignment electrode are disposed on the via layer.

5. The display device according to claim 4, further comprising: a dummy electrode spaced apart from the second alignment electrode in the second direction in the peripheral region, and wherein, The second alignment electrode and the data line extend from the display area to the peripheral area, and The second alignment electrode and the data line are in direct contact in the peripheral region through a contact portion passing through the via layer.

6. The display device according to claim 4, wherein: The display area includes a display element area and a pixel circuit area spaced apart from the display element area in the second direction; The first alignment electrode, the second alignment electrode, the third alignment electrode and the light emitting element are arranged in the display element region; as well as A plurality of transistors and a storage capacitor are disposed in the pixel circuit region.

7. The display device according to claim 6, further comprising: A buffer layer and an interlayer insulating layer are arranged between the substrate and the passivation layer, wherein: The lower electrode of the storage capacitor is disposed between the substrate and the buffer layer, The upper electrode of the storage capacitor is disposed between the via layer and the passivation layer, and The pattern electrode is disposed between the buffer layer and the interlayer insulating layer.

8. The display device according to claim 6, further comprising: a first vertical power line receiving a voltage from a first power source and extending in the second direction; a first horizontal power line electrically connected to the first vertical power line and extending in the first direction; a second vertical power line receiving a voltage from a second power source and extending in the second direction; as well as a second horizontal power line electrically connected to the second vertical power line and extending in the first direction, The first alignment electrode and the second alignment electrode are arranged between the first horizontal force line and the second horizontal force line in a plan view.

9. The display device according to claim 8, wherein: The first vertical power line and the second vertical power line are disposed on a different layer from the data line, and wherein, The storage capacitor is spaced apart from the first horizontal power line in the second direction.

10. The display device according to claim 8, further comprising: a scan line disposed in the pixel circuit region and extending in the first direction, The storage capacitor is disposed between the first horizontal power line and the scan line in a plan view.

11. Display equipment, including: substrate; as well as A display element region is provided on the substrate and includes a first sub-pixel and a second sub-pixel spaced apart from each other in a first direction, Wherein, the display element area also includes: a first alignment electrode, a second alignment electrode, a third alignment electrode, a fourth alignment electrode, and a fifth alignment electrode, which are spaced apart from each other in the first direction and extend in a second direction intersecting the first direction; a light emitting element disposed between the first alignment electrode and the second alignment electrode, between the second alignment electrode and the third alignment electrode, between the third alignment electrode and the fourth alignment electrode, and between the fourth alignment electrode and the fifth alignment electrode; a first data line of the first subpixel overlapping the second alignment electrode in a plan view and extending in the second direction; and a second data line of the second sub-pixel overlapping the fourth alignment electrode in a plan view and extending in the second direction, and The length of the first width of the first data line and the second data line in the first direction is less than or equal to the length of the second width of the second alignment electrode and the fourth alignment electrode in the first direction.

12. The display device according to claim 11, further comprising: a pattern electrode overlapping the first alignment electrode, the second alignment electrode, the third alignment electrode, the fourth alignment electrode, and the fifth alignment electrode in a plan view and extending in the first direction, Wherein, in a plan view, the pattern electrode does not overlap with the light emitting element.

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