A method, apparatus and system for bidirectional high-speed conversion between RDMA and CXL protocols

Abstract

This invention belongs to the field of FPGA application design and provides a method for bidirectional high-speed conversion between RDMA and CXL protocols. The technical solution adopts a brand-new "FPGA heterogeneous bidirectional protocol conversion" concept as the core design idea; uses the massive resources of FPGA chips as the architecture carrier, and implements a functional core pipeline design to perform bidirectional concurrent protocol conversion; it realizes centralized management and overall coordination of multiple different RDMA and CXL devices to efficiently complete the communication protocol conversion task in parallel, thereby realizing real-time communication between different devices.

Description

Technical Field

[0001] This invention belongs to the field of FPGA application design, and in particular relates to a bidirectional high-speed conversion method, device and system for RDMA and CXL protocols. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Currently, RDMA (Remote Direct Memory Access) and CXL (Compute Express Link) technologies have been widely used in many fields. However, due to technical barriers and protocol incompatibility, devices that only support the RDMA protocol and devices that only support the CXL protocol cannot directly communicate and exchange data, significantly limiting efficient interaction between devices. To solve these problems, purchasing or upgrading equipment can achieve a certain degree of compatibility, but the cost is high; software protocol conversion heavily relies on CPU collaboration, resulting in low protocol conversion efficiency and significant consumption of device CPU computing resources, affecting overall system performance. Summary of the Invention

[0004] To address at least one of the technical problems mentioned above, this invention provides a method, apparatus, and system for bidirectional high-speed conversion between RDMA and CXL protocols, which is used to meet the high-efficiency conversion needs of RDMA and CXL protocols in the context of the big data era, so as to fundamentally solve the problem of incompatibility between RDMA and CXL devices.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] The first aspect of the present invention provides a bidirectional high-speed conversion method between RDMA and CXL protocols, comprising the following steps:

[0007] Receive access requests from multiple source devices;

[0008] Determine whether the target device address is directly connected to the switch corresponding to the current request source device. If so, the request source device directly accesses the storage of the target device address through the corresponding switch to receive the target data.

[0009] Otherwise, determine the type of the target device. If the target device is an RDMA device, identify the device type and supported CXL protocols of the CXL request source device, and package the detailed request information for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals.

[0010] If the target device is a CXL device, identify the device type and supported CXL protocols of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals;

[0011] The protocol-converted data is sent to the requesting source device.

[0012] Furthermore, the protocol conversion from CXL protocol signals to RDMA protocol signals includes:

[0013] Receives raw access request messages using various CXL protocols;

[0014] Decode the original access request messages of various CXL protocols and decompose them to obtain the CXL source address, RDMA destination address, data length, CXL protocol version sequence number and corresponding transmission data information in the original message;

[0015] The transmitted data is grouped according to the CXL protocol version sequence number, the grouped data is decoded according to the corresponding CXL protocol, the current signal obtained from the decomposition is re-encoded, the re-encoding result is verified, and the converted data is obtained.

[0016] Furthermore, multiple CXL protocols include CXL1.0, CXL1.1, CXL2.0, CXL3.0, and CXL3.1 protocols.

[0017] Furthermore, the protocol conversion from RDMA protocol signals to CXL protocol signals includes:

[0018] Receive raw messages conforming to the RDMA protocol;

[0019] Decode the original message conforming to the RDMA protocol to obtain the RDMA source address, CXL destination address, data length, conversion requirement CXL protocol version sequence number, and corresponding transmission data information in the original message;

[0020] Based on the CXL protocol version serial number for conversion requirements, read the storage partition corresponding to different versions, package the decoded data and the data from different storage partitions, and encode them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

[0021] Furthermore, the original access request messages of various CXL protocols are decoded and the original messages conforming to the RDMA protocol are decoded sequentially according to the IPC / IP signal format.

[0022] A second aspect of the present invention provides a high-speed bidirectional conversion device for RDMA and CXL protocols, including a CXL-RDMA protocol conversion module, an RDMA-CXL protocol conversion module, a first conversion interface, and a second conversion interface; one end of the first conversion interface is connected to the input terminal of the CXL-RDMA protocol conversion module, and the other end is connected to the output terminal of the RDMA-CXL protocol conversion module; one end of the second conversion interface is connected to the output terminal of the CXL-RDMA protocol conversion module, and the other end is connected to the input terminal of the RDMA-CXL protocol conversion module.

[0023] The CXL-RDMA protocol conversion module is configured to: identify the device type and supported CXL protocols of the CXL request source device, and package the request details for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals;

[0024] The RDMA-CXL protocol conversion module is configured to: identify the device type and supported CXL protocols of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals.

[0025] Furthermore, the CXL-RDMA protocol conversion module includes a first TCP / IP signal decoding module, a CXL sub-protocol identification module, multiple sub-protocol decoding modules, and an RDMA signal recoding module;

[0026] The TCP / IP signal decoding module is used to decode the original access request messages of various CXL protocols and decompose them to obtain the CXL source address, RDMA destination address, data length, CXL protocol version sequence number and corresponding transmission data information in the original message;

[0027] The CXL sub-protocol identification module is used to group transmitted data according to the CXL protocol version serial number;

[0028] The multiple sub-protocol decoding modules are used to decode the packet data according to the corresponding CXL protocol;

[0029] The RDMA signal encoding module is used to re-encode the decomposed current signal to obtain re-encoded data.

[0030] Furthermore, the RDMA-CXL protocol conversion module includes a second TCP / IP signal decoding module and multiple sub-protocol encoding modules;

[0031] The second TCP / IP signal decoding module is used to decode the original message conforming to the RDMA protocol to obtain the RDMA source address, CXL destination address, data length, conversion requirement CXL protocol version sequence number and corresponding transmission data information in the original message;

[0032] The multiple sub-protocol encoding modules are used to read the storage partitions corresponding to different versions according to the CXL protocol version serial number of the conversion requirements, package the decoded data and the data of different storage partitions, and encode them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

[0033] Furthermore, the device also includes an RDMAX signal transmission verification module and a CXL signal transmission verification module;

[0034] The RDMAX signal transmission verification module is used to verify the RDMA protocol and TPC / IP format of the input data respectively. After the verification is successful, the input data is sent to the RDMA switch in sequence.

[0035] The CXL signal transmission verification module is used to verify the CXL protocol and TPC / IP format of the input data. After the verification is successful, the input data is sent to the CXL switch in sequence.

[0036] A third aspect of the present invention provides a bidirectional conversion system for RDMA and CXL protocols, including a CXL device cluster, an RDMA device cluster, a CXL switch, an RDMA switch, and the apparatus described in the second aspect;

[0037] The CXL device cluster is connected to one end of the CXL switch, the other end of the CXL switch is connected to one end of the device, the other end of the device is connected to one end of the RDMA switch, and the other end of the RDMA switch is connected to the RDMA device cluster. Each CXL device cluster includes several CXL devices of different types, and each RDMA device cluster includes several RDMA hosts containing CPU, buffer, and RDMA engine.

[0038] Compared with the prior art, the beneficial effects of the present invention are:

[0039] This invention adopts a novel "FPGA heterogeneous bidirectional protocol conversion" concept as its core design philosophy; it uses the massive resources of FPGA chips as its architectural carrier, with a functional core pipeline design and bidirectional concurrent execution of protocol conversion; it achieves centralized management and overall coordination of multiple different RDMA and CXL devices to efficiently complete communication protocol conversion tasks in parallel, thereby realizing real-time communication between different devices; and fundamentally solves the problem of incompatibility between RDMA and CXL devices.

[0040] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0041] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0042] Figure 1 This is a system architecture diagram of a bidirectional conversion system between RDMA and CXL protocols provided in an embodiment of the present invention;

[0043] Figure 2 This is an architecture diagram of an FPGA-based high-speed RDMA-CXL protocol conversion device provided in an embodiment of the present invention;

[0044] Figure 3 This is a flowchart of the application method for access requests of CXL devices provided in this embodiment of the invention;

[0045] Figure 4 This is a flowchart of the application method for access requests of RDMA devices provided in an embodiment of the present invention;

[0046] Figure 5 This is the FPGA core architecture design of the RDMA-CXL protocol high-speed conversion device provided in the embodiments of the present invention. Detailed Implementation

[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0048] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0049] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0050] RDMA (Remote Direct Memory Access) was developed to address latency in terminal data processing during network transmission. RDMA allows user-mode applications to directly read from or write to remote memory without kernel intervention or memory copying. Initially used only in high-performance computing, it has recently gained increasing attention due to the growing prominence of network bottlenecks in large-scale distributed systems and data centers.

[0051] CXL (Compute Express Link) is a new device interconnection technology standard that has become a breakthrough in data exchange efficiency. It is used not only for memory capacity / bandwidth expansion but also for heterogeneous interconnection and decoupling of data center resource pools. In data centers, CXL technology can interconnect different computing and storage resources to complete data transmission and exchange tasks with higher system performance and efficiency.

[0052] To address the incompatibility issue between RDMA and CXL devices, this invention presents an FPGA-based high-speed RDMA-CXL protocol conversion device. It adopts a novel "FPGA heterogeneous bidirectional protocol conversion" concept as its core design principle. Utilizing the vast resources of FPGA chips as its architectural carrier, it employs a functional core pipeline design and enables bidirectional concurrent execution of protocol conversion. This allows for centralized management and coordinated efficient parallel completion of communication protocol conversion tasks for multiple different RDMA and CXL devices, thereby achieving real-time communication between the different devices.

[0053] This invention presents an FPGA-based high-speed RDMA-CXL protocol conversion device that is compatible with multiple versions of the CXL protocol, including CXL 1.0, 1.1, 2.0, 3.0, and 3.1, and supports all types of CXL devices, such as CXL Type 1, CXL Type 2, and CXL Type 3, thus having a wide range of applications. Furthermore, the designed protocol conversion device can support any number of CXL and RDMA device clusters, allowing for flexible access. In addition, the FPGA-based high-speed RDMA-CXL protocol conversion device uses the FPGA's functional core for protocol conversion, employing a pipelined design that supports bidirectional concurrent conversion in a single time period, significantly improving the system's protocol conversion and signal transmission efficiency. Moreover, this invention eliminates the need for the access device's CPU to perform auxiliary operations, greatly reducing the device's computational load. Simultaneously, this design provides detailed application methods for the FPGA-based high-speed RDMA-CXL protocol conversion device, enabling better unified scheduling and control, and significantly improving the application performance of the CXL-RDMA hybrid system.

[0054] Figure 1The architecture is an FPGA-based high-speed RDMA-CXL protocol conversion device, including a CXL device cluster, an RDMA device cluster, a CXL switch, and an RDMA switch.

[0055] Each CXL device cluster includes several CXL Type1-NIC data acceleration card devices, CXL Type2-data acceleration card devices with storage, CXL Type3-CXL memory pools, and other devices;

[0056] Each RDMA device cluster consists of several RDMA hosts, each containing a CPU, buffer, and RDMA engine.

[0057] The CXL device cluster deploys several CXL application devices that can support any of the protocols in CXL1.0, CXL1.1, CXL2.0, CXL3.0, and CXL3.1. These devices are connected to the CXL switch via the network, and different CXL devices can directly exchange information through the CXL switch.

[0058] The RDMA device cluster deploys several RDMA hosts that support the RDMA transmission protocol. These devices are connected to the RDMA switch via a network, and different RDMA hosts can directly exchange information through the RDMA switch.

[0059] The CXL switch and the RDMA switch are connected to an FPGA-based RDMA-CXL protocol high-speed conversion device via network cables. This protocol conversion device completes the high-speed conversion between the CXL protocol and the RDMA protocol, thereby enabling real-time communication between the CXL device cluster and the RDMA device cluster.

[0060] Figure 2 The architecture of the RDMA-CXL protocol high-speed conversion device based on FPGA consists of two parts: core board hardware design and FPGA chip module design. The RDMA-CXL protocol high-speed conversion device hardware board includes FPGA chip, peripheral electronic devices, DDR4 memory, peripheral interfaces and PCB board.

[0061] The FPGA internally encompasses the application engineering module structure and specific information processing methods necessary for the normal operation of the RDMA-CXL protocol bidirectional high-speed conversion (the specific FPGA module composition and working mechanism are given in Part 3 of the instruction manual); peripheral electronic components include power interfaces, power chips, clock chips, and necessary resistors and capacitors; peripheral interfaces include a JTAG debug interface, a PCIe interface, and two Gigabit Ethernet ports. The PCB board provides the carrier for the FPGA chip and peripheral electronic components.

[0062] The board is responsible for the collection, processing and transmission of information in the industrial wireless sensor network. It is also responsible for the power supply, clock input and various forms of IO communication of the FPGA core chip, as well as information interaction with peripheral interfaces.

[0063] Gigabit Ethernet port 1 is connected to the CXL switch and is responsible for sending and receiving CXL protocol related signals; Gigabit Ethernet port 2 is connected to the RDMA switch and is responsible for sending and receiving RDMA protocol related signals.

[0064] For example, if it is necessary to convert the CXL protocol to the RDMA protocol, the FPGA receives the CXL signal sent by the CXL switch through Gigabit Ethernet port 1, and after completing the protocol conversion, sends the conversion result RDMA signal to the RDMA switch through Gigabit Ethernet port 2.

[0065] The application method of the FPGA-based RDMA-CXL protocol high-speed conversion device is divided into two parts: access request for CXL device and access request for RDMA.

[0066] Figure 3 The flowchart illustrates the application method for access requests to CXL devices, which includes the following steps:

[0067] Step 1: The CXL device sends a data read access request, target device address, target data storage address, and other information to the CXL switch;

[0068] Step 2: The CXL switch receives the request and verifies the validity of the source device address that sent the request;

[0069] Step 3: After the legality verification is passed, the CXL switch determines whether the target device address has been directly connected to the current CXL switch. If so, proceed to step 4; otherwise, proceed to step 6.

[0070] Step 4: The target device is a CXL device. The CXL request source device directly accesses the target device's address storage through the CXL switch;

[0071] Step 5: The CXL source device directly receives the target data through the CXL switch and then proceeds to step 10;

[0072] Step 6: If the target device is an RDMA device, the CXL switch identifies the device type and supported CXL protocol of the source device, and packages it together with the request details for the target device and sends it through Gigabit Ethernet port 1 to the FPGA-based RDMA-CXL protocol high-speed conversion device.

[0073] Step 7: The RDMA-CXL protocol high-speed conversion device performs IPC / IP signal decoding, CXL protocol decoding, RDMA signal recoding and other processes to complete the CXL to RDMA protocol conversion, and sends the converted request to the RDMA switch through Gigabit Ethernet port 2;

[0074] Step 8: The RDMA switch receives the request, directly extracts the corresponding target data from the target RDMA device, and sends it back to the RDMA-CXL protocol high-speed converter via Gigabit Ethernet port 2 in RDMA protocol format;

[0075] Step 9: The RDMA-CXL protocol high-speed conversion device converts the received RDMA protocol format data into the CXL protocol format of the target device, and then sends the access result to the source CXL device through the CXL switch;

[0076] Step 10: Complete the data read access request.

[0077] Figure 4 The flowchart illustrates the application method for access requests to RDMA devices, including the following steps:

[0078] Step 1: The RDMA device sends a data read access request, target device address, target data storage address, and other information to the RDMA switch;

[0079] Step 2: The RDMA switch receives the request and verifies the validity of the source device address that sent the request;

[0080] Step 3: After the legality verification is passed, the RDMA switch determines whether the target device address has been directly connected to the current RDMA switch. If so, proceed to step 4; otherwise, proceed to step 6.

[0081] Step 4: The target device is an RDMA device. The RDMA request source device directly accesses the target device's address storage through the CXL switch.

[0082] Step 5: The RDMA engine of the RDMA source device directly receives the target data through the RDMA switch and jumps to step 10;

[0083] Step 6: If the target device is a CXL device, the RDMA switch identifies the device type and supported CXL protocol of the target CXL device, and packages it together with the request details for the target device and sends it through Gigabit Ethernet port 2 to the FPGA-based RDMA-CXL protocol high-speed conversion device.

[0084] Step 7: The RDMA-CXL protocol high-speed conversion device performs processes such as IPC / IP signal decoding, RDMA protocol decoding, and CXL signal recoding to complete the RDMA to CXL protocol conversion, and sends the converted request to the CXL switch through Gigabit Ethernet port 1;

[0085] Step 8: The CXL switch receives the request to convert to the target device's CXL protocol, directly extracts the corresponding target data from the target CXL device, and sends it back to the RDMA-CXL protocol high-speed converter in CXL protocol format through Gigabit Ethernet port 1;

[0086] Step 9: The RDMA-CXL protocol high-speed conversion device converts the received CXL protocol format data into the RDMA protocol format of the target device, and then sends the access result to the requesting RDMA device through the RDMA switch;

[0087] Step 10: Complete the data read access request.

[0088] Figure 5 The FPGA core architecture for the high-speed RDMA-CXL protocol conversion device includes a CXL-RDMA protocol conversion partition and an RDMA-CXL protocol conversion partition;

[0089] Specifically, it includes a CXL input data buffer module, a TPC / IP signal decoding module, a CXL sub-protocol identification module, a CXL1.0 / 1.1 protocol decoding module, a CXL2.0 protocol decoding module, a CXL3.0 / 3.1 protocol decoding module, an RDMA signal recoding module, a TPC / IP signal encoding module, an RDMA signal transmission verification module, an RDMA input data buffer module, a TPC / IP signal decoding module, a MIG, a CXL protocol encoding information acquisition FSM state machine, a CXL1.0 / 1.1 protocol encoding module, a CXL2.0 protocol encoding module, a CXL3.0 / 3.1 protocol encoding module, a CXL data aggregation and collection module, a TPC / IP signal encoding module, and a CXL signal transmission verification module.

[0090] The FPGA core architecture of the RDMA-CXL protocol high-speed converter can be divided into two relatively independent stages:

[0091] 1. Convert CXL protocol signals to RDMA protocol signals;

[0092] This phase is performed by the FPGA's CXL-RDMA protocol conversion partition.

[0093] When Gigabit Ethernet port 1 receives the raw message from the CXL switch that conforms to the CXL1.0 / CXL1.1 / CXL2.0 / CXL3.0 / CXL3.1 protocol, the CXL input data buffer module buffers the raw data and sends it to the TPC / IP signal decoding module in sequence according to the IPC / IP signal format;

[0094] The TPC / IP signal decoding module decodes the received information, decomposes the CXL source address, RDMA destination address, data length, CXL protocol version sequence number and corresponding transmission data information in the original data, and sends it to the CXL sub-protocol identification module.

[0095] The CXL sub-protocol identification module identifies the CXL protocol version serial number (only one CXL sub-protocol is allowed in a single CXL-RDMA protocol conversion). Based on the sub-protocol version, it categorizes the protocols into CXL1.0 / CXL1.1, CXL2.0, and CXL3.0 / CXL3.1 groups. Then, according to the category, it sends the module input data in 64-bit AHB bus format to the CXL1.0 / CXL1.1, CXL2.0, and CXL3.0 / CXL3.1 protocol decoding modules. These modules then perform CXL protocol decoding as specified by the corresponding sub-protocol, decomposing the entire original data of the current signal and packaging it for transmission to the RDMA signal re-encoding module.

[0096] The RDMA signal recoding module performs encoding operations on the input data according to the RDMA protocol requirements and sends the recoded information to the TPC / IP signal encoding module; the TPC / IP signal encoding module performs the encoding operations necessary for TPC / IP transmission on the input signal and sends the result to the RDMA signal transmission verification module.

[0097] The RDMA signal transmission verification module buffers the received data and verifies the RDMA protocol and TPC / IP format of the input data respectively. After successful verification, the input data is sent to the RDMA switch sequentially via Gigabit Ethernet port 2.

[0098] 2. Convert RDMA protocol signals to CXL protocol signals;

[0099] This phase is performed by the FPGA's RDMA-CXL protocol conversion partition.

[0100] When Gigabit Ethernet port 2 receives the raw message conforming to the RDMA protocol from the RDMA switch, the RDMA input data buffer module buffers the raw data and sends it to the TPC / IP signal decoding module in sequence according to the IPC / IP signal format;

[0101] The TPC / IP signal decoding module decodes the received information, decomposes the RDMA source address, CXL destination address, data length, conversion requirement CXL protocol version sequence number and corresponding transmission data information in the original data, and sends it to the CXL protocol encoding information to obtain the FSM state machine.

[0102] After receiving the TPC / IP signal decoding result, the FSM state machine, based on the conversion requirement and the CXL protocol version sequence number (CXL1.0 / CXL1.1 / CXL2.0 / CXL3.0 / CXL3.1 protocol), controls the MIG storage read module to read the corresponding DDR4 storage partition. It then reads the corresponding CXL protocol conversion mode requirement information (including header signals, frame information, transmission step size signals, etc.) and packages this information with the data to be converted received from the TPC / IP signal decoding module, distributing it to the corresponding CXL1.0 version. The module includes CXL1.1, CXL2.0, and CXL3.0 / CXL3.1 protocol encoding modules (each RDMA-CXL protocol conversion only allows conversion of the same CXL sub-protocol); these modules execute the CXL protocol encoding specified by the corresponding sub-protocol on the input data, obtain the CXL protocol conversion result of the original input data, and send the corresponding results sequentially to the CXL data aggregation and collection module.

[0103] After receiving CXL data of the target length, the CXL data aggregation and collection module aggregates and caches all input data, packages all CXL protocol conversion results and sends them to the TPC / IP signal encoding module.

[0104] The TPC / IP signal encoding module performs the necessary encoding operations for TPC / IP transmission on the input signal and sends the result to the CXL signal transmission verification module. The CXL signal transmission verification module buffers the received data and verifies the CXL protocol and TPC / IP format of the input data respectively. After the verification is successful, the input data is sent to the CXL switch sequentially through Gigabit Ethernet port 1.

[0105] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for bidirectional high-speed conversion between RDMA and CXL protocols, comprising the following steps: Receive access requests from multiple source devices; Determine whether the target device address is directly connected to the switch corresponding to the current request source device. If so, the request source device directly accesses the storage of the target device address through the corresponding switch to receive the target data. Otherwise, determine the type of the target device. If the target device is an RDMA device, identify the device type and supported CXL protocols of the CXL request source device, and package the detailed request information for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals. If the target device is a CXL device, identify the device type and supported CXL protocols of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals; The protocol-converted data is sent to the requesting source device.

2. The bidirectional high-speed conversion method between RDMA and CXL protocols as described in claim 1, characterized in that, The protocol conversion from CXL protocol signals to RDMA protocol signals includes: Receives raw access request messages using various CXL protocols; Decode the original access request messages of various CXL protocols and decompose them to obtain the CXL source address, RDMA destination address, data length, CXL protocol version sequence number and corresponding transmission data information in the original message; The transmitted data is grouped according to the CXL protocol version sequence number, the grouped data is decoded according to the corresponding CXL protocol, the current signal obtained from the decomposition is re-encoded, the re-encoding result is verified, and the converted data is obtained.

3. The bidirectional high-speed conversion method between RDMA and CXL protocols as described in claim 1, characterized in that, Multiple CXL protocols include CXL1.0, CXL1.1, CXL2.0, CXL3.0, and CXL3.

1.

4. The bidirectional high-speed conversion method between RDMA and CXL protocols as described in claim 1, characterized in that, The protocol conversion from RDMA protocol signals to CXL protocol signals includes: Receive raw messages conforming to the RDMA protocol; Decode the original message conforming to the RDMA protocol to obtain the RDMA source address, CXL destination address, data length, conversion requirement CXL protocol version sequence number, and corresponding transmission data information in the original message; Based on the CXL protocol version serial number for conversion requirements, read the storage partition corresponding to different versions, package the decoded data and the data from different storage partitions, and encode them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

5. A bidirectional high-speed conversion method for RDMA and CXL protocols as described in claim 2 or 4, characterized in that, Decode the raw access request messages of various CXL protocols and decode the raw messages conforming to the RDMA protocol in sequence according to the IPC / IP signal format.

6. A bidirectional high-speed conversion device for RDMA and CXL protocols, comprising a CXL-RDMA protocol conversion module, an RDMA-CXL protocol conversion module, a first conversion interface, and a second conversion interface; one end of the first conversion interface is connected to the input terminal of the CXL-RDMA protocol conversion module, and the other end is connected to the output terminal of the RDMA-CXL protocol conversion module; one end of the second conversion interface is connected to the output terminal of the CXL-RDMA protocol conversion module, and the other end is connected to the input terminal of the RDMA-CXL protocol conversion module. The CXL-RDMA protocol conversion module is configured to: identify the device type and supported CXL protocols of the CXL request source device, and package the request details for the target device to perform protocol conversion from CXL protocol signals to RDMA protocol signals; The RDMA-CXL protocol conversion module is configured to: identify the device type and supported CXL protocols of the target CXL device, and package the request details for the target device to perform protocol conversion from RDMA protocol signals to CXL protocol signals.

7. The bidirectional high-speed conversion device for RDMA and CXL protocols as described in claim 6, characterized in that, The CXL-RDMA protocol conversion module includes a first TCP / IP signal decoding module, a CXL sub-protocol identification module, multiple sub-protocol decoding modules, and an RDMA signal recoding module; The TCP / IP signal decoding module is used to decode the original access request messages of various CXL protocols and decompose them to obtain the CXL source address, RDMA destination address, data length, CXL protocol version sequence number and corresponding transmission data information in the original message; The CXL sub-protocol identification module is used to group transmitted data according to the CXL protocol version serial number; The multiple sub-protocol decoding modules are used to decode the packet data according to the corresponding CXL protocol; The RDMA signal encoding module is used to re-encode the decomposed current signal to obtain re-encoded data.

8. The bidirectional high-speed conversion device for RDMA and CXL protocols as described in claim 6, characterized in that, The RDMA-CXL protocol conversion module includes a second TCP / IP signal decoding module and multiple sub-protocol encoding modules; The second TCP / IP signal decoding module is used to decode the original message conforming to the RDMA protocol to obtain the RDMA source address, CXL destination address, data length, conversion requirement CXL protocol version sequence number and corresponding transmission data information in the original message; The multiple sub-protocol encoding modules are used to read the storage partitions corresponding to different versions according to the CXL protocol version serial number of the conversion requirements, package the decoded data and the data of different storage partitions, and encode them according to the corresponding CXL protocol to obtain the CXL protocol conversion result of the original message.

9. The bidirectional high-speed conversion device for RDMA and CXL protocols as described in claim 6, characterized in that, The device also includes an RDMAX signal transmission verification module and a CXL signal transmission verification module; The RDMAX signal transmission verification module is used to verify the RDMA protocol and TPC / IP format of the input data respectively. After the verification is successful, the input data is sent to the RDMA switch in sequence. The CXL signal transmission verification module is used to verify the CXL protocol and TPC / IP format of the input data. After the verification is successful, the input data is sent to the CXL switch in sequence.

10. A bidirectional high-speed conversion system for RDMA and CXL protocols, characterized in that, Includes CXL device clusters, RDMA device clusters, CXL switches, RDMA switches, and the apparatus according to any one of claims 6-9; The CXL device cluster is connected to one end of the CXL switch, the other end of the CXL switch is connected to one end of the device, the other end of the device is connected to one end of the RDMA switch, and the other end of the RDMA switch is connected to the RDMA device cluster. Each CXL device cluster includes several CXL devices of different types, and each RDMA device cluster includes several RDMA hosts containing CPU, buffer, and RDMA engine.

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