Integrated circuit structure and method of forming and operating same

Abstract

The invention provides an integrated circuit structure and a forming and operating method thereof. The integrated circuit structure includes a substrate and a memory cell on the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a ferroelectric material layer and a gate layer. The first doped region is located on the first side of the channel layer, the first doped region has a first dopant, and the first dopant belongs to the first conductivity type. The second doped region is located on a second side opposite to the channel layer, the second side and the first side are located on opposite sides of the channel layer, the second doped region has a second dopant, and the second dopant belongs to a second conductivity type different from the first conductivity type. The ferroelectric material layer is located on the channel layer and located between the first doped region and the second doped region. The gate layer is located on the ferroelectric material layer.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit structure, and more particularly to a method for forming the integrated circuit structure and a method for operating the integrated circuit structure. Background Art

[0002] The present disclosure relates generally to semiconductor devices, and more particularly to three-dimensional (3D) memory devices and methods of forming such semiconductor devices.

[0003] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, the increase in integration density comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0004] The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate and a memory cell located on the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric material layer and a first gate layer. The first doped region is located on a first side of the channel layer and is doped with a first dopant, the first dopant being of a first conductivity type. The second doped region is located on a second side of the channel layer, and the second side is located on an opposite side of the channel layer to the first side), the second doped region has a second dopant, the second dopant being of a second conductivity type different from the first conductivity type. The first ferroelectric material layer is located on the channel layer and between the first doped region and the second doped region. The first gate layer is located on the first ferroelectric material layer.

[0005] In some embodiments, the doping concentration of the channel layer is less than 1E11 cm -3 .

[0006] In some embodiments, the channel layer extends from the first doped region to the second doped region in a direction parallel to the top surface of the substrate.

[0007] In some embodiments, the channel layer extends from the first doped region to the second doped region in a direction perpendicular to the top surface of the substrate.

[0008] In some embodiments, the first dopant is a p-type dopant and the second dopant is an n-type dopant.

[0009] In some embodiments, the first ferroelectric material layer is made of silicon-doped aluminum oxide (HfO2), aluminum-doped aluminum oxide (HfO2), aluminum oxide aluminum oxide (HFZrO x ), aluminum oxide (HfO2) or aluminum oxide (ZrO2), or any combination of the foregoing materials.

[0010] In some embodiments, the integrated circuit structure further includes a word line connected to the first gate layer.

[0011] In some embodiments, the integrated circuit structure further comprises a second ferroelectric material layer and a second gate layer. The second ferroelectric material layer is located on the channel layer and is separated from the first ferroelectric material layer by a non-zero distance. The second gate layer is located on the second ferroelectric material layer.

[0012] The present disclosure provides a method for manufacturing an integrated circuit structure. The manufacturing method includes: forming a first doped semiconductor layer on a substrate, the first doped semiconductor layer comprising a first dopant, the first dopant having a first conductivity type; forming a multilayer stacking structure on the first doped semiconductor layer, the multilayer stacking structure comprising a plurality of insulating layers stacked in a vertical direction and separated from each other; forming a channel layer, the channel layer vertically extending through the first multilayer stacking structure and located on the first doped semiconductor layer; forming a second doped semiconductor layer on the channel layer, the second doped semiconductor layer comprising a second dopant, the second dopant having a second conductivity type different from the first conductivity type; forming a plurality of ferroelectric material layers alternately stacked with a plurality of insulating layers, the plurality of ferroelectric material layers being located on the channel layer; and forming a plurality of gate layers on the plurality of ferroelectric material layers.

[0013] In some embodiments, the channel layer is formed by fabricating undoped silicon.

[0014] In some embodiments, the first dopant is a p-type dopant and the second dopant is an n-type dopant.

[0015] In some embodiments, the material of the gate layer includes tungsten.

[0016] In some embodiments, the method for manufacturing an integrated circuit structure further comprises: before forming a plurality of ferroelectric material layers, forming a plurality of interface layers alternately stacked with a plurality of insulating layers, wherein the plurality of interface layers are located on the channel layer.

[0017] In some embodiments, the method for manufacturing an integrated circuit structure further comprises: before forming the plurality of gate layers, forming a plurality of barrier layers on the plurality of ferroelectric material layers.

[0018] In some embodiments, the material of the barrier layer includes titanium nitride.

[0019] The present disclosure provides an operation method of an integrated circuit structure. The operation method of the integrated circuit structure includes a memory cell array structure. The memory cell array structure includes a plurality of ferroelectric tunneling field effect transistors. The plurality of ferroelectric tunneling field effect transistors are configured as a plurality of memory cells in a grid-like structure. The grid-like structure is defined by a plurality of lateral gate layers and a plurality of vertical channel layers. The plurality of lateral gate layers are arranged in a vertical direction and are respectively connected to different word lines (WLs). The plurality of vertical channel layers are arranged in a horizontal direction, and the top ends thereof are connected to a plurality of bit lines (BLs) in sequence through a plurality of first doped regions, and the bottom ends thereof are connected to a sensing circuit in sequence through a plurality of second doped regions. The conductivity type of the second doped region is different from the conductivity type of the first doped region. The method includes performing a programming operation on the memory cell array structure; performing an erasing operation on the memory cell array structure; and performing a reading operation on the memory cell array structure.

[0020] In some embodiments, the programming operation includes: providing a voltage to one of the word lines to generate an electric field that causes the polarization of a ferroelectric material layer within one of the ferroelectric tunneling field effect transistors to shift; maintaining other word lines among the multiple word lines at zero voltage; grounding one of the multiple bit lines; and providing the voltage to other bit lines among the bit lines.

[0021] In some embodiments, the erase operation includes: providing a voltage to the word lines to induce polarization reversal in a ferroelectric material layer within one of the ferroelectric tunneling field effect transistors; and grounding the bit lines.

[0022] In some embodiments, the read operation includes: providing a first voltage to (one of) a plurality of word lines; adjusting the first voltage to be between a programming threshold voltage and an erasure threshold voltage; providing a second voltage to other word lines among the word lines, the second voltage causing the sensing circuit to detect a storage state of a corresponding one of the memory cells; providing a third voltage to one of the bit lines; and grounding the other bit lines among the plurality of bit lines.

[0023] In some embodiments, the third voltage is 0.7V. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0025] Figure 1A as well as Figure 1BSchematic diagrams of a ferroelectric-tunnel field effect transistor (FeTFET) of a storage device in a program operation and an erase operation in some embodiments of the present disclosure are schematically shown.

[0026] Figure 1C The characteristics of the drain current (Drain current, ID) and the gate voltage of a ferroelectric tunneling field effect transistor according to some embodiments of the present disclosure are schematically shown.

[0027] FIG. 2A to FIG. 3B A schematic diagram of a ferroelectric tunneling field effect transistor of a memory device in some embodiments of the present disclosure is schematically shown.

[0028] Figure 4A The structure of a memory cell array including a ferroelectric tunneling field effect transistor of a memory device in some embodiments of the present disclosure is schematically shown.

[0029] FIG. 4B to FIG. 4D The schematic diagram shows the operation Figure 4A An equivalent circuit diagram of the storage device method in FIG.

[0030] Figures 5 to 14A by Figures 15 to 17 Schematically illustrates cross-sectional views at various stages of a method for forming a ferroelectric tunneling field effect transistor for a memory device according to some embodiments of the present disclosure.

[0031] Fig. 14B Schematically shows Fig.14A A partial enlarged view of the middle area C1.

[0032] Description of Reference Numerals

[0033] 100, 500: Storage cell array structure

[0034] 101: Substrate

[0035] 102: Dielectric layer

[0036] 102t, 104t: Top surface

[0037] 103, 106: Doped semiconductor layer

[0038] 104: Multi-layer stacking structure

[0039] 104a: Sacrificial layer

[0040] 104b: Insulation layer

[0041] 105, 205, 305, 405, 505: channel layer

[0042] 107: Interface layer

[0043] 108, 208, 308, 408: ferroelectric material layer

[0044] 109: Barrier layer

[0045] 110, 210, 310, 410, 510: Gate layer

[0046] 111: Dielectric Materials

[0047] 120, 220, 320, 420, 520: Ferroelectric tunneling field effect transistor

[0048] 203, 206, 303, 306, 403, 406, 503, 506: Source / drain regions

[0049] BL1, BL2, BL3, BL4: bit lines

[0050] C1: Area

[0051] GSL: Ground Select Line

[0052] O1: Opening

[0053] O2, O3, O4: through hole openings

[0054] P1, P2, P4: Etching process

[0055] P3: Polishing process

[0056] S1: Space

[0057] SA: Sensing Circuit

[0058] SSL: string selection line

[0059] V D 、V G1 、V G2 ,…V Gn 、V S :Voltage

[0060] V DD : Supply voltage

[0061] -V DD : Negative voltage

[0062] V t，program : Programming threshold voltage

[0063] V t，erase : Erase threshold voltage

[0064] WL1, WL2, WL3: word lines DETAILED DESCRIPTION

[0065] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is directly contacted with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present disclosure may repeatedly refer to numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0066] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature of the illustrations in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0067] As used herein, "approximately", "about", "roughly", or "substantially" shall generally mean within 20%, or within 10%, or within 5% of a given value or range. However, those skilled in the art will recognize that the values ​​or ranges cited throughout the description are merely examples and may decrease as the scale of integrated circuits decreases. The quantities given herein are approximate, meaning that the terms "approximately", "about", "roughly", or "substantially" may be inferred where not explicitly stated.

[0068] In typical n-type ferroelectric field-effect transistors (FeFETs), both the source and drain regions are doped with the same conductivity type dopant (e.g., n-type dopant), and program and erase operations rely on electrons and positively ionized donors. This poses a challenge when dealing with n-type FETs with p-type or undoped bodies, as the erase process becomes particularly difficult. The problem stems from the interaction of different charge carriers required for the proper operation of these devices, which affects the performance and reliability of FETs in memory cell array structures.

[0069] Therefore, the present disclosure of various embodiments provides a ferroelectric tunneling field effect transistor. The source region and drain region of the ferroelectric tunneling field effect transistor of the present disclosure adopt dopants with different conductivity (i.e., n-type dopants and p-type dopants). This configuration can provide enhanced control over the movement of charge carriers, thereby improving the overall function of the transistor on the memory cell array structure. In addition, the ferroelectric tunneling field effect transistor can eliminate the need for channel doping, so the floating body of the ferroelectric tunneling field effect transistor can effectively perform programming operations and erase operations, and the complexity of manufacturing can be reduced accordingly.

[0070] See also Figures 1A to 1C . Figure 1A as well as Figure 1B FIG. 1 schematically shows a schematic diagram of a ferroelectric tunnel field effect transistor 220 in a memory device during a program operation and an erase operation according to some embodiments of the present disclosure. Figure 1C The characteristics of the drain current (Drain current, ID) and the gate voltage of the ferroelectric tunneling field effect transistor 220 according to some embodiments of the present disclosure are schematically shown. Figure 1A as well as Figure 1B As shown, the ferroelectric tunneling field effect transistor 220 may include a source / drain region 203 , a source / drain region 206 , a ferroelectric material layer 208 , a gate layer 210 and a channel layer 205 .

[0071] The source / drain region 203 and the source / drain region 206 are heavily doped with impurities to create excess electrons (e.g., n-type doping) or excess holes (e.g., p-type doping). The source / drain region 203 and the source / drain region 206 serve as the starting point and end point of the flow of charge through the channel layer 205. The conductivity of the source / drain region 203 is different from that of the source / drain region 206. In some embodiments, the source / drain region 203 may be a p-type source / drain region, and the source / drain region 206 may be an n-type source / drain region. For example, but not limited to, the source / drain region 203 may be heavily doped with a p-type dopant (e.g., boron), and the source / drain region 206 may be heavily doped with an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, the source / drain region 203 may be an n-type source / drain region, and the source / drain region 206 may be a p-type source / drain region. For example, but the present disclosure is not limited thereto, the source / drain region 203 may be heavily doped with an n-type dopant, and the source / drain region 206 may be heavily doped with a p-type dopant. In some embodiments, the source / drain region 203 and the source / drain region 206 may be made of a doped semiconductor material, such as silicon (Si), germanium (Ge), a III-V compound semiconductor (e.g., indium gallium arsenic (InGaAs), any combination of the foregoing materials, or other suitable materials. Therefore, the source / drain region 203 may be interchangeably referred to as a first doped region, and the source / drain region 206 may be interchangeably referred to as a second doped region. In some embodiments, the source / drain region 203 is a source region, and the source / drain region 206 is a drain region, but the present disclosure is not limited thereto.

[0072] The ferroelectric material layer 208 may be made of a ferroelectric material, such as silicon-doped aluminum oxide (HfO2), aluminum-doped aluminum oxide (HfO2), aluminum oxide aluminum oxide (HfZrO x ), aluminum oxide (HfO2) or aluminum oxide (ZrO2), any combination of the foregoing materials, or other suitable materials. Such materials can exhibit spontaneous electric polarization, which can be reversed by applying an external electric field and enable the ferroelectric tunneling field effect transistor 220 to have a non-volatile memory function.

[0073] The gate layer 210 can control the terminal of the ferroelectric tunneling field effect transistor 220, apply an electric field to the ferroelectric material layer 208, and thus control the polarization state of the ferroelectric material and the conductivity of the channel layer 205. In some embodiments, the gate layer 210 can be made of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), any combination of the foregoing materials, or other suitable materials.

[0074] The channel layer 205 can connect the source / drain region 203 to the source / drain region 206. In the ferroelectric tunneling field effect transistor 220, when the ferroelectric tunneling field effect transistor 220 is in the "on" state, the channel layer 205 can flow through a thin layer of semiconductor material. Figure 1A as well as Figure 1B As shown, the channel layer 205 can be formed on a substrate (not shown) and extend laterally in a direction parallel to the top surface of the substrate. In the ferroelectric tunneling field effect transistor 220, the channel layer 205 can be lightly or undoped. This allows the state of the ferroelectric material layer 208 (i.e., its polarization) to control the flow of charge carriers (electrons or holes) through the channel layer 205, thereby switching the ferroelectric tunneling field effect transistor 220 "on" or "off". In some embodiments, the channel layer 205 can be made of a semiconductor material, such as silicon (Si), germanium (Ge), a III-V compound semiconductor (e.g., indium gallium arsenide (InGaAs), any combination of the foregoing materials, or other suitable materials. In some embodiments, the doping concentration of the channel layer 205 is less than 1E11cm -3 In some embodiments, the doping concentration of the channel layer 205 is lower than the doping concentration of the source / drain region 203, and lower than the doping concentration of the source / drain region 206. In some embodiments, the channel layer 205 may be free of dopants.

[0075] like Figures 1A to 1C As shown, the ferroelectric tunneling field effect transistor 220 can use the ferroelectric material layer 208 to control the state of the transistor, rather than relying on a doped channel. This simplifies the manufacturing process and improves the reliability of the device by reducing variability. In addition, the programming and erasing of the device state in the ferroelectric tunneling field effect transistor 220 can be achieved more efficiently. During programming and erasing operations, the voltage V connected to the source / drain regions 203 and 206 is S and V D The same means that no bias is applied to these areas. This configuration helps simplify the control process and reduce power consumption during these operations.

[0076] Specifically, during a programming operation (see Figure 1A as well as Figure 1C ), the power supply voltage (V program =+V DD ) promotes, electrons from n + The side (for example, one of the source / drain regions 203 and 206) is injected into the channel layer 205. When the voltage (level) V connected to the source / drain regions 203 and 206 is S and voltage (level) V DWhen the voltage is the same (for example, V S and V D The gate voltage can independently control the injection of electrons, so that the ferroelectric tunneling field effect transistor 220 is switched to a specific storage state. In some embodiments, during a programming operation, a floating or grounding method can be used on the source / drain regions 203 and 206 to make the voltage levels on the source / drain regions 203 and 206 the same, but the present disclosure is not limited thereto. During an erase operation (see Figure 1B as well as Figure 1C ), a negative voltage (V erase =-V DD ) promotes, holes from p + The other side (eg, the source / drain region 203 and 206) is injected into the channel layer 205. When the voltage (level) V connected to the source / drain region 203 and 206 is S and voltage (level) V D When the voltage is the same (for example, V S and V D The gate voltage can control the injection of holes independently, so that the ferroelectric tunneling field effect transistor 220 is switched to another specific storage state. In some embodiments, during the erase operation, the source / drain regions 203 and 206 can be floated or grounded to make the voltage levels on the source / drain regions 203 and 206 the same, but the present disclosure is not limited thereto. On the other hand, the read operation (see Figure 1C ) involves + The voltage V on the source / drain region 206 is D will be greater than or slightly greater than the voltage V on the source / drain region 203 S , and its gate voltage (V read ) between the threshold voltages for programming and erasing operations (V t，program <V read <V t，erase ). This method allows the ferroelectric tunneling field effect transistor 220 to switch between different memory states efficiently and stably, and the polarization state of the ferroelectric tunneling field effect transistor 220 can be non-volatile. That is, even if the power is removed from the ferroelectric tunneling field effect transistor 220, it can maintain the memory state.

[0077] See also Figure 2A as well as Figure 2B . Figure 2A as well as Figure 2BThe schematic diagram of the ferroelectric tunneling field effect transistor 320 in the memory device in programming operation and erasing operation according to some embodiments of the present disclosure is schematically shown. The description provided refers to another embodiment of the memory device, specifically, Figure 1A as well as Figure 1B Compared with the embodiment schematically shown in FIG. , this embodiment is different in structural layout. Figure 2A as well as Figure 2B In this embodiment schematically shown in FIG. 1 , the source / drain regions 303 and 306, the ferroelectric material layer 308, the gate layer 310, and the channel layer 305 are made of the same materials and fabricated in the same manner as in FIG. Figure 1A as well as Figure 1B In other words, the source / drain regions 303 and 306 may correspond to the source / drain regions 303 and 306, the ferroelectric material layer 308 may correspond to the ferroelectric material layer 208, the gate layer 310 may correspond to the gate layer 210, and the channel layer 305 may correspond to the channel layer 205. In some embodiments, the source / drain region 303 is a source region, and the source / drain region 306 is a drain region, but the present disclosure is not limited thereto. In some embodiments, the source / drain region 303 may be interchangeably referred to as a first doped region, and the source / drain region 306 may be interchangeably referred to as a second doped region.

[0078] The difference of this embodiment lies in the structural layout of the ferroelectric tunneling field effect transistor 320. Figure 2A as well as Figure 2B The channel layer 305 extending laterally on the substrate (not shown) is different. Figure 2A as well as Figure 2B The embodiment includes a channel layer 305 extending in a direction perpendicular to the top surface of the substrate (not shown) so that the gate layer 210 can laterally surround the channel layer 305, and the source / drain regions 303 and 306 are respectively located at two opposite vertical ends of the channel layer 305. This vertical arrangement can save space. Instead of arranging components in a two-dimensional plane, this vertical arrangement effectively utilizes the third dimension (vertical direction) to arrange components. Therefore, for a given area on the substrate, more ferroelectric tunneling field effect transistors 320 can be arranged, resulting in a higher storage density, and therefore, the overall footprint of a given storage capacity is smaller.

[0079] Ferroelectric tunneling field effect transistor 320 can use ferroelectric material layer 308 to control the state of the transistor, rather than relying on a doped channel. This simplifies the manufacturing process and improves the reliability of the device by reducing variability. In addition, programming and erasing of the device state in ferroelectric tunneling field effect transistor 320 can be achieved more efficiently. Specifically, during a programming operation (see Figure 2A ), the power supply voltage (V program =+V DD ) promotes, electrons from n + The side (one of the source / drain regions 303 and 306) is injected into the channel layer 305. When the voltage (level) connected to the source / drain regions 303 and 306 is V S and voltage (level) V D When the voltage is the same (for example, V S and V D The gate voltage can independently control the injection of electrons, so that the ferroelectric tunneling field effect transistor 320 is switched to a specific storage state. In some embodiments, during a programming operation, a floating or grounding method can be used on the source / drain regions 303 and 306 to make the voltage levels on the source / drain regions 303 and 306 the same, but the present disclosure is not limited thereto. During an erase operation (see Figure 2B ), a negative voltage (V erase =-V DD ) promotes, holes from p + The other side (eg, the source / drain region 303 and 306) is injected into the channel layer 305. When the voltage (level) V connected to the source / drain region 303 and 306 is S and voltage (level) V D When the voltage is the same (for example, V S and V D The gate voltage can independently control the injection of holes, so that the ferroelectric tunneling field effect transistor 320 switches to another specific storage state. In some embodiments, during the erase operation, the source / drain regions 303 and 306 can be floated or grounded to make the voltage levels on the source / drain regions 303 and 306 the same, but the present disclosure is not limited thereto. On the other hand, the read operation involves reading from n + The voltage V on the source / drain region 306 is D will be greater than or slightly greater than the voltage V on the source / drain region 303 S , and its gate voltage (V read ) between the threshold voltages for programming and erasing operations (V t，program <V read <V t，erase). This method allows the ferroelectric tunneling field effect transistor 320 to switch between different memory states efficiently and stably, and the polarization state of the ferroelectric tunneling field effect transistor 320 can be non-volatile. That is, even if the power is removed from the ferroelectric tunneling field effect transistor 320, it can maintain the memory state.

[0080] Reference Figure 3A as well as Figure 3B . Figure 3A as well as Figure 3B The schematic diagram of multiple ferroelectric tunneling field effect transistors 420 in a memory device in programming and erasing operations according to some embodiments of the present disclosure is shown. The description provided refers to another embodiment of a memory device, specifically, it has Figure 2A as well as Figure 2B The embodiment shown in FIG. 4 shows a different gate layer configuration and a different ferroelectric material layer configuration compared to the embodiment shown in FIG. Figure 3A as well as Figure 3B In this variation shown in FIG. 1 , the source / drain regions 403, the source / drain regions 406, the plurality of ferroelectric material layers 408, the plurality of gate layers 410, and the channel layer 405 are substantially the same in terms of materials and manufacturing methods. Figure 2A as well as Figure 2B . This means that the source / drain regions 403 and 406 can correspond to the source / drain regions 303 and 306, the ferroelectric material layer 408 can correspond to the ferroelectric material layer 308, the gate layer 410 can correspond to the gate layer 310, and the channel layer 405 can correspond to the channel layer 305. In some embodiments, the source / drain region 403 is a source region, and the source / drain region 406 is a drain region, but the present disclosure is not limited to this. In some embodiments, the source / drain region 403 can be interchangeably referred to as a first doped region, and the source / drain region 406 can be interchangeably referred to as a second doped region.

[0081] This embodiment differs in the structural configuration of the gate layer and the structural configuration of the ferroelectric material layer. Figure 2A as well as Figure 2B The single gate layer 310 and the single ferroelectric material layer 308 are different. Figure 3A as well as Figure 3B The embodiment in the embodiment includes multiple gate layers 410 and multiple ferroelectric material layers 408. These gate layers 410 and ferroelectric material layers 408 are formed to be arranged laterally around the channel layer 405, and are separated by a non-zero distance G1. In some embodiments, the distance G1 ranges from 5 to 10 nm, but the present disclosure is not limited thereto. In this embodiment, the multiple gate layers 410 and multiple ferroelectric material layers 408 can more accurately and variably control the channel current by adjusting the voltage V G1 、VG2 ,…V Gn Applied to the gate layer 310 .

[0082] Reference 4A to 4D . Figure 4A A memory cell array structure 500 including a plurality of ferroelectric tunneling field effect transistors 520 in a memory device according to some embodiments of the present disclosure is schematically shown. FIG. 4B to FIG. 4D Schematic diagram of an operation Figure 4A An equivalent circuit diagram of a method for storing a storage device in the embodiment of the present invention includes a programming operation, an erasing operation and a reading operation. 4A to 4D In the variation shown in FIG. 5 , the various components of the plurality of ferroelectric tunneling field effect transistors 520 are substantially the same in terms of materials and manufacturing methods. Figure 3A This means that the ferroelectric tunneling field effect transistor 520 can correspond to the ferroelectric tunneling field effect transistor 420 in the previous figure.

[0083] like Figure 4A As shown, five gate layers 510 are arranged in parallel in the vertical direction, and the gate layers 510 are integrated with four channel layers 505, and the aforementioned channel layers 505 are arranged vertically in sequence along the horizontal direction. Other embodiments may include more or fewer gate layers and correspondingly more or fewer channel layers. The integration of the gate layer 510 and the channel layer 505 forms a grid-like structure, which defines a single cell of the memory cell array structure 500. The bottommost gate layer 510 can be connected to the ground select line GSL as the ground reference level of the memory cell array structure 500. The topmost gate layer 510 can be connected to the string select line SSL, providing an interface for selecting a specific memory cell string for operation. The three middle gate layers 510 can be connected to word lines WL1, WL2 and WL3, each of which can be controlled separately. These word lines WL1, WL2 and WL3 can interface with the gate layer 510 and control access to a single memory cell. Multiple ferroelectric material layers 508 are formed respectively and sandwiched between the middle three gate layers 510 and the channel layer 505. In some embodiments, the middle three gate layers 510 can be interchangeably referred to as word line conductors, and the bottommost gate layer 510 connected to the ground selection line GSL can be interchangeably referred to as a selection gate conductor.

[0084] The vertically arranged channel layer 505 can form a connection between the memory cell array structure 500 and an external circuit. The top end of the channel layer 505 is sequentially connected to the bit lines BL1, BL2, BL3 and BL4 through the source / drain region 506. These bit lines BL1, BL2, BL3 and BL4 allow data to be transferred to and from the memory cell. The bottom end of the channel layer 505 can be sequentially connected to the sensing circuit SA through the source / drain region 503. The sensing circuit SA can read the state of the memory cell by detecting the change of the current through the string selection line SSL. This memory cell array structure 500 including multiple ferroelectric tunneling field effect transistors 520 can provide a clear path for data input and output, allowing precise access and operation of a single memory cell. In some embodiments, the source / drain region 503 is a source region, and the source / drain region 506 is a drain region, but the present disclosure is not limited to this. In some embodiments, the source / drain region 503 may be interchangeably referred to as a first doped region, and the source / drain region 506 may be interchangeably referred to as a second doped region.

[0085] like Figure 4B As shown, during the programming operation, the top word line WL1 is charged to the power supply voltage V DD In other words, the power supply voltage V DD is provided to the topmost word line WL1. This bias provides an electric field to induce a polarization transition of the ferroelectric material within the ferroelectric tunneling field effect transistor 520, effectively programming the selected memory cell. At the same time, the other word lines WL2 and WL3 are maintained at zero voltage to prevent undesired programming of unselected cells. Bit line BL1 is grounded (e.g., substantially 0V), while the other bit lines BL2, BL3, and BL4 are charged to the power supply voltage V DD , isolating the selected memory cell in the bit line architecture to prevent interference with adjacent cells. The string select line SSL is charged to the power supply voltage V DD , establishes an effective path to the selected storage string, and the ground selection line GSL is grounded to provide a stable reference voltage. In other words, the power supply voltage V DD is provided to other bit lines BL2, BL3 and BL4 and a string selection line SSL.

[0086] like Figure 4C As shown, during the erase operation, all word lines WL1, WL2 and WL3 are charged to a negative voltage -V DD , which facilitates polarization reversal in the ferroelectric material layer, effectively erasing the stored data. All bit lines BL1, BL2, BL3, and BL4 are grounded (e.g., substantially 0V), ensuring isolation of activated memory cells. The string select line SSL is charged to the positive supply voltage VDD , to establish an effective path to the selected memory cell string, the ground select line GSL is grounded to provide a stable reference voltage. In other words, the negative voltage -V DD is supplied to all word lines WL1, WL2 and WL3, while the power supply voltage V DD Provided to the string select line SSL.

[0087] like Figure 4D As shown, in the read operation, the voltage applied to the word line WL1 is adjusted to be at the programming threshold voltage (V t，program ) and the erase threshold voltage (V t，erase ) to facilitate reading the state of the selected memory cell without causing a program or erase operation. The other word lines WL2 and WL3 are biased to the erase threshold voltage (V t，erase ) and the power supply voltage V DD The bit line BL1 is charged to a voltage of 0.7V to enable the sensing circuit SA to detect the storage state. At the same time, the other bit lines BL2, BL3 and BL4 are grounded. The string selection line SSL and the ground selection line GSL are both charged to the power supply voltage V DD , to establish the electrical conditions required for the read operation. In other words, the 0.7V power supply voltage V DD is supplied to the bit line BL1, and the power supply voltage V DD is provided to the string selection line SSL and the ground selection line GSL. Therefore, through the voltage control mechanism at different levels of the plurality of ferroelectric tunneling field effect transistors 520, the memory cell array structure 500 realizes accurate control of different memory operations.

[0088] See also Figures 5 to 17 . Figures 5 to 14A as well as Figures 15 to 17 Schematically illustrates a method for forming a ferroelectric tunneling field effect transistor 120 (see Fig.14A ) are cross-sectional views of a method for manufacturing a memory cell array structure 100 at various stages. Fig. 14B Schematically shows Fig.14A A partial enlarged view of area C1 in FIG. Figure 5As shown, a dielectric layer 102 is formed on a substrate 101. The substrate 101 may be a semiconductor substrate, such as a monocrystalline silicon bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and the aforementioned substrate may be doped (e.g., doped with p-type or n-type impurities) or undoped. An insulator-on-semiconductor substrate may be a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates may also be used. In some embodiments, the substrate 101 may be a carrier chip, such as a low-cost chip or a recycled chip. The substrate 101 may have a circular top view shape or a rectangular top view shape. In some embodiments, the substrate 101 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; the like; or any combination of the foregoing materials.

[0089] In some embodiments, the dielectric layer 102 can be made of a dielectric material, such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), silicate, any combination of the foregoing materials, or other suitable materials. In some embodiments, the dielectric layer 102 can be formed by a chemical vapor deposition (CVD) process.

[0090] See also Figure 6A plurality of openings O1 are formed through the dielectric layer 102 to expose portions of the substrate 101 . In some embodiments, the openings O1 are formed to extend downward through the dielectric layer 102 and terminate before reaching the substrate 101 .

[0091] Reference Figure 7 Subsequently, a doped semiconductor layer 103 is formed in the opening O1 and on the substrate 101 to form an electrical contact with the channel layer 105, as shown in FIG. Fig.10 In some embodiments, the doped semiconductor layer 103 is formed by depositing polysilicon (Si), germanium, and a p-type dopant (p + ), such as boron. In some embodiments, the doped semiconductor layer 103 may be formed by selective silicon epitaxial growth, for example, using silicon on the substrate 101 as a seed. Subsequently, a planarization process is performed to remove excess semiconductor material on the top surface 102t of the dielectric layer 102. Thus, the above method may form a semiconductor layer such as Figure 6 The doped semiconductor layer 103 is shown. In some embodiments, the doped semiconductor layer 103 may be p + In some embodiments, the doped semiconductor layer 103 may be referred to interchangeably as a source / drain region corresponding to the ferroelectric tunneling field effect transistor 120, such as Fig.14A shown.

[0092] Reference Figure 8 . The multilayer stack structure 104 is formed on the dielectric layer 102. The multilayer stack structure 104 may include a plurality of sacrificial layers 104a and a plurality of insulating layers 104b that are parallel and alternately superimposed on the substrate 101. Other embodiments may include a greater or lesser number of sacrificial layers 104a and a corresponding greater or lesser number of insulating layers 104b. In some embodiments, the multilayer stack structure 104 may be alternately referred to as a thin film stack or a stack of oxide-nitride pairs (ON pairs). However, it should be understood that in embodiments of the present disclosure, the sacrificial layer 104a and the insulating layer 104 are made of different materials. For example, the sacrificial layer 104a may be made of silicon nitride and the insulating layer 104b may be made of silicon oxide. In some embodiments, the topmost layer of the insulating layer 104b may be alternately referred to as a hard mask oxide layer (Hard Mask Oxide). In some embodiments, the sacrificial layer 104a and the insulating layer 104b may be formed by a low pressure chemical vapor deposition (LPCVD) process.

[0093] Reference Fig. 9. An etching process P1, such as a hole etch process, is performed on the multilayer stacked structure 104 to form a plurality of through-hole openings O2 that pass through the multilayer stacked structure 104 and expose the doped semiconductor layer 103. In some embodiments, the etching process P1 may be an anisotropic etching process, such as a reactive ion etching (RIE) process formed on the multilayer stacked structure 104 using a patterned hard mask layer (not shown) as an etching mask. In some embodiments, the through-hole openings O2 may be a plurality of circular through holes that pass through the multilayer stacked structure 104 in a direction Z and terminate at the doped semiconductor layer 103. The through-hole openings O2 expose portions of the sacrificial layer 104a and the insulating layer 104b as their sidewalls. In some embodiments, the through-hole openings O2 may be referred to interchangeably as vertical channel openings.

[0094] Reference Fig.10 . A channel layer 105 is formed in the through hole opening O2. In some embodiments, the channel layer 105 may be made of a semiconductor material, such as polysilicon (Si), germanium (Ge), or other doped / undoped semiconductor materials. For example, the channel layer 105 may be made of doped polysilicon. In some embodiments, the channel layer 105 may be formed by selective silicon epitaxial growth, for example, using the silicon on the multilayer stack structure 104 as a seed. Subsequently, a polishing process is performed to remove excess semiconductor material on the top surface 104t of the multilayer stack structure 104. Thus, the foregoing method may form a structure such as Fig.10 The channel layer 105 is shown, and thus the integrated circuit structure may include a vertical channel memory structure.

[0095] Reference Fig.11 A doped semiconductor layer 106 is formed on the upper portion of the through hole opening O2 and on the etched channel layer 105 to form an electrical contact with the channel layer 105. In some embodiments, the doped semiconductor layer 106 is formed by depositing polysilicon (Si), germanium (Ge), and generally n-type dopants (N + ), such as phosphorus or arsenic. Subsequently, a polishing process is performed to remove excess semiconductor material on the top surface 104t of the multilayer stack structure 104. Therefore, the above method can form Fig.11 The doped semiconductor layer 106 is shown. In some embodiments, the doped semiconductor layer 106 may be n + In some embodiments, the doped semiconductor layer 106 may be referred to interchangeably as a source / drain region corresponding to the ferroelectric tunneling field effect transistor 120, such as Fig.14A shown.

[0096] Reference Fig.12 The etching process P2 is performed to form a through hole opening O3 that passes through the multilayer stack structure 104 along the direction Z and terminates at the top surface 102t of the dielectric layer 102, so as to partially expose the sacrificial layer 104a and the insulating layer 104b. In some embodiments, the etching process P2 can be an anisotropic etching process, such as a reactive ion etching (RIE) process using a patterned hard mask layer (not shown) as an etching mask on the multilayer stack structure 104.

[0097] Reference Fig.13 The sacrificial layer 104a is removed through the via opening O3 using an etchant (eg, hot phosphoric acid (H3PO4) solution) to expose a portion of the channel layer 105. Thus, a space S1 is formed to inherit the sacrificial layer 104a (see Fig.12 ) shape.

[0098] Please refer to Fig.14A as well as Fig. 14B . An interface layer 107, a ferroelectric material layer 108, a barrier layer 109 and a gate layer 110 are sequentially formed in the space S1 through the through hole opening O3. Specifically, the interface layer 107 can be formed on the multilayer stacked structure 104. In some embodiments, the interface layer 107 may include silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicate, a combination thereof or other suitable materials. The interface layer 107 can serve as a buffer layer or interface between the multilayer stacked structure 104 and the ferroelectric material layer 108. The interface layer 107 can help reduce potential unnecessary chemical reactions or diffusion between layers, thereby improving the overall performance of the memory cell array structure 100.

[0099] The ferroelectric material layer 108 may be formed on the interface layer 107. In some embodiments, the ferroelectric material layer 108 may include a ferroelectric material such as silicon-doped bonded oxide (HfO2), aluminum-doped (HfO2), bonded zirconium oxide (HfZrO x ), bonding oxide (HfO2) or zirconium oxide (ZrO2), a combination thereof or other suitable materials. The ferroelectric material layer 108 can exhibit ferroelectric properties in the memory cell array structure 100. Even if the electric field is removed, the ferroelectric material layer 108 can retain polarization (electric dipole direction). Therefore, data storage in the memory cell array structure 100 can be represented by two possible polarization states of the ferroelectric material layer 108, corresponding to binary "0" and "1".

[0100] The barrier layer 109 may be formed on the ferroelectric material layer 108. In some embodiments, the barrier layer 109 may include tantalum nitride (TaN), titanium, titanium nitride (TiN), a combination thereof, or other suitable materials. The barrier layer 109 may protect the ferroelectric material layer 108 and prevent unnecessary chemical interactions or material diffusion between the ferroelectric material layer 108 and the gate layer 110.

[0101] Subsequently, the ferroelectric material layer 108 may be subjected to an annealing process to crystallize the deposited ferroelectric material layer 108. Specifically, the ferroelectric properties of the ferroelectric material layer 108 come from the alignment of electric dipoles in the lattice structure of the material. When an electric field is applied, these dipoles can align in a specific direction, establishing a polarization state that persists even after the electric field is removed. This provides the non-volatile memory characteristics of the ferroelectric tunneling field effect transistor 120. However, ferroelectric materials tend to be amorphous when initially deposited, meaning that the atoms are randomly distributed rather than orderly arranged in a lattice. Therefore, the annealing process can heat the ferroelectric material layer 108 to a specific temperature for a certain period of time and then slowly cool it down. This annealing process allows the atoms in the ferroelectric material layer 108 to rearrange into a crystal structure and promotes the formation of a crystalline phase with the desired ferroelectric properties.

[0102] Subsequently, a gate layer 110 may be deposited on the barrier layer 109 and filled into the through hole opening O3. In some embodiments, the gate layer 110 may include polysilicon, metal, or other suitable conductive materials. In some embodiments, the gate layer 110 may include tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), combinations thereof, or other suitable materials. The gate layer 110 may serve as a control terminal of the ferroelectric tunneling field effect transistor 120. By applying different voltages to the gate layer 110, the polarization state of the ferroelectric material layer 108 may be affected to effectively program (or program), erase, or read the state of the memory cells in the memory cell array structure 100 (see Fig.14A to Figure 14D).

[0103] Therefore, the ferroelectric tunneling field effect transistor 120 can be defined at the intersection of the interface layer 107, the ferroelectric material layer 108, the barrier layer 109, the gate layer 110 and the channel layer 105, thereby forming the memory cell array structure 100. In some embodiments, the ferroelectric tunneling field effect transistor 120 and the Figure 1A 3D. That is, the ferroelectric tunneling field effect transistor 120 may correspond to the ferroelectric tunneling field effect transistor in the previous figures. In some embodiments, the ferroelectric tunneling field effect transistor 120 may be interchangeably referred to as a memory cell.

[0104] Please refer to Fig.15 A polishing process P3 (eg, chemical mechanical polishing) is performed to remove the excess interface layer 107 , the ferroelectric material layer 108 , the barrier layer 109 , and the gate layer 110 located above the top surface 104 t of the multi-layer stack structure 104 .

[0105] Please refer to Fig.16 The etching process P4 is performed to form a through hole opening O4 through the multilayer stack structure 104 along the direction Z and terminated at the top surface 102t of the dielectric layer 102. In some embodiments, the etching process P4 can be an anisotropic etching process, such as a reactive ion etching (RIE) process, performed on the multilayer stack structure 104 using a pattern hard mask layer (not shown) as an etching mask.

[0106] Please refer to Fig.17 . A dielectric material 111 is deposited on the multilayer stacked structure 104 and fills the through-hole opening O4. In some embodiments, the dielectric material 111 may be made of a material such as silicon dioxide (SiO2). In some embodiments, the dielectric material 111 may be made of the same material as the insulating layer 104b. In some embodiments, the dielectric material 111 may be made of a material different from the insulating layer 104b. Subsequently, a polishing process is performed to remove excess dielectric material 111 located above the top surface 104t of the multilayer stacked structure 104.

[0107] In some embodiments, a gate layer (not shown) connected to a ground selection line (not shown) may be formed below the bottommost gate layer 110, and this gate layer may be used as a reference level or ground level to ensure that the memory cell array structure has a stable standard voltage. On top of the topmost gate layer 110, a gate layer (not shown) connected to a string selection line (not shown) may be formed, and this gate layer may be used as a control terminal for the topmost memory cell in each memory string to facilitate selection in read, program (or program) and erase operations. Bit lines and other related structures may be formed on top of this entire structure, and the bit lines may be used as data paths to transfer information to and from the memory cell array structure 100.

[0108] Although the present invention has described some of its embodiments in detail, other embodiments are still possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. The present invention provides, in various embodiments, a ferroelectric tunneling field effect transistor in which the source region and the drain region use dopants with different conductivities (i.e., n-type dopants and p-type dopants). This configuration can provide enhanced control over the movement of charge carriers, thereby improving the overall functionality of the transistor on the memory cell array structure. In addition, the ferroelectric tunneling field effect transistor can eliminate the need for channel doping, so that the floating body of the ferroelectric tunneling field effect transistor can effectively perform programming operations and erase operations, and the complexity of manufacturing can be reduced accordingly.

[0109] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit structure, comprising: a substrate; as well as A memory cell, located on the substrate, comprising: A channel layer; a first doped region located on a first side of the channel layer, the first doped region having a first dopant, the first dopant being of a first conductivity type; a second doped region located on a second side relative to the channel layer, the second side and the first side being located on opposite sides of the channel layer, the second doped region having a second dopant, the second dopant being of a second conductivity type different from the first conductivity type; a first ferroelectric material layer, located on the channel layer and between the first doped region and the second doped region; and A first gate layer is located on the first ferroelectric material layer.

2. The integrated circuit structure according to claim 1, wherein the doping concentration of the channel layer is lower than 1E11cm -3 . 3 . The integrated circuit structure according to claim 1 , wherein in a direction parallel to a top surface of the substrate, the channel layer extends from the first doped region to the second doped region. 4 . The integrated circuit structure according to claim 1 , wherein in a direction perpendicular to a top surface of the substrate, the channel layer extends from the first doped region to the second doped region. 5 . The integrated circuit structure according to claim 1 , wherein the first dopant is a p-type dopant, and the second dopant is an n-type dopant.

6. The integrated circuit structure according to claim 1, wherein the first ferroelectric material layer is made of silicon-doped aluminum oxide (HfO2), aluminum-doped aluminum oxide (HfO2), aluminum oxide aluminum oxide (HFZrO x ), aluminum oxide (HfO2) or aluminum oxide (ZrO2), or any combination of the foregoing materials.

7. The integrated circuit structure according to claim 1, further comprising: A word line is connected to the first gate layer.

8. The integrated circuit structure of claim 1, further comprising: a second ferroelectric material layer located on the channel layer and separated from the first ferroelectric material layer by a non-zero distance; and A second gate layer is located on the second ferroelectric material layer.

9. A method for manufacturing an integrated circuit structure, comprising: Forming a first doped semiconductor layer on a substrate, wherein the first doped semiconductor layer comprises a first dopant having a first conductivity type; forming a multi-layer stacking structure on the first doped semiconductor layer, wherein the multi-layer stacking structure comprises a plurality of insulating layers stacked in a vertical direction and separated from each other; forming a channel layer, the channel layer vertically extending through the first multi-layer stack structure and located on the first doped semiconductor layer; forming a second doped semiconductor layer on the channel layer, wherein the second doped semiconductor layer comprises a second dopant having a second conductivity type different from the first conductivity type; forming a plurality of ferroelectric material layers alternately stacked with the insulating layers, the ferroelectric material layers being located on the channel layer; as well as A plurality of gate layers are formed on the ferroelectric material layers. 10 . The manufacturing method according to claim 9 , wherein the channel layer is formed by manufacturing undoped silicon. 11 . The manufacturing method according to claim 9 , wherein the first dopant is a p-type dopant, and the second dopant is an n-type dopant. 12 . The manufacturing method according to claim 9 , wherein a material of the gate layers comprises tungsten.

13. The manufacturing method according to claim 9, further comprising: Before forming the ferroelectric material layers, a plurality of interface layers alternately stacked with the insulating layers are formed, and the interface layers are located on the channel layer.

14. The manufacturing method according to claim 9, further comprising: Before forming the gate layers, a plurality of barrier layers are formed on the ferroelectric material layers. The manufacturing method according to claim 14 , wherein a material of the barrier layers comprises titanium nitride.

16. An operating method of an integrated circuit structure, the integrated circuit structure comprising a memory cell array structure, the memory cell array structure comprising a plurality of ferroelectric tunneling field effect transistors, the ferroelectric tunneling field effect transistors being configured as a plurality of memory cells in a grid structure, the grid structure being defined by the integration of a plurality of lateral gate layers and a plurality of vertical channel layers, the lateral gate layers being arranged in a vertical direction and respectively connected to a plurality of different word lines, the vertical channel layers being arranged in a horizontal direction, the top ends of which are sequentially connected to a plurality of bit lines through a plurality of first doped regions, and the bottom ends of which are sequentially connected to a sensing circuit through a plurality of second doped regions, the conductivity type of the second doped regions being different from the conductivity type of the first doped regions, the method comprising: Performing a programming operation on the memory cell array structure; Performing an erase operation on the memory cell array structure; as well as A read operation is performed on the memory cell array structure.

17. The operating method according to claim 16, wherein the programming operation comprises: providing a voltage to one of the word lines to generate an electric field that causes a polarization shift in a ferroelectric material layer within one of the ferroelectric tunneling field effect transistors; maintaining other of the word lines at zero voltage; grounding one of the bit lines; and This voltage is provided to other of the bit lines.

18. The operating method according to claim 16, wherein the erasing operation comprises: providing a voltage to the word lines to induce polarization reversal in a ferroelectric material layer within one of the ferroelectric tunneling field effect transistors; as well as The bit lines are connected to ground.

19. The operating method according to claim 16, wherein the reading operation comprises: providing a first voltage to one of the word lines; The first voltage is adjusted to be between a programming threshold voltage and an erasing threshold voltage; providing a second voltage to other word lines among the word lines, the second voltage enabling the sensing circuit to detect a storage state of a corresponding one of the memory cells; providing a third voltage to one of the bit lines; as well as Others of the bit lines are grounded. 20 . The operating method according to claim 19 , wherein the third voltage is 0.7V.

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