A semiconductor device structure and a method of fabricating the same

Abstract

The application provides a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a back layer of a first conductive type which is composed of a buffer layer of the first conductive type and a freewheeling heavy doped region of the first conductive type under the deep trench field plate, a trench gate and a deep trench field plate which penetrate a body region of a second conductive type and extend into a substrate layer of the first conductive type; and the trench gate which also penetrates the heavy doped region of the first conductive type has a depth smaller than that of the deep trench field plate. The deep trench field plate which is short-circuited with the emitter and arranged on both sides of the trench gate can accumulate a large number of holes when the deep trench field plate is turned on, so that the on-state voltage drop is reduced. Meanwhile, the deep trench field plate optimizes the compromise relationship between the FRD breakdown voltage and the on-state voltage in the RC-IGBT with a vertical electric field distribution, so that the working loss of the RC-IGBT in the freewheeling state is reduced. In addition, the deep trench field plate can quickly extract the carriers in the depletion layer in the freewheeling state, so that the current released in the reverse recovery is reduced, and the peak current in the reverse recovery is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a semiconductor device structure and its fabrication method. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) is an advanced power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device technology that has wide applications in high-voltage fields.

[0003] like Figure 1 The diagram shows a cross-sectional structure of an IGBT cell region, including a TGFS (Trench Gate Field Stop) in the prior art. On the back side of the IGBT cell, a heavily P-type doped region (P+) is formed through implantation. When the IGBT is turned on, holes are injected into the N-type substrate to modulate conductivity, thereby significantly reducing the on-state voltage drop. An N-type buffer layer is also provided on the back side of the IGBT cell to rapidly reduce the electric field during reverse breakdown, achieving low resistivity and high breakdown voltage in the N-type substrate region.

[0004] However, during the switching process, IGBTs repeatedly inject and extract holes. While these non-equilibrium carriers reduce the resistivity of the N-type substrate and thus lower the on-state voltage drop by injecting holes through conductivity modulation when the IGBT is on, they also increase losses during IGBT off-state due to the tailing current of non-equilibrium holes, thereby increasing turn-off losses. Therefore, the inverse correlation between on-state voltage drop and turn-off losses necessitates a trade-off between these two factors in IGBT design, thus limiting the efficiency performance of IGBTs in electronic power systems.

[0005] Furthermore, in RC-IGBTs (Reverse Conducting IGBTs), the integration of the FRD (Fast Recovery Diode) within the IGBT causes the resistivity of the shared substrate to affect not only the IGBT's on-state voltage drop and turn-off losses, but also the BV (Breakdown Voltage) and VF (Forward Voltage) of the integrated FRD. This limits the dual optimization of BV and VF of the FRD in the RC-IGBT, resulting in higher operating losses in freewheeling mode. Simultaneously, the FRD in the RC-IGBT generates a spike current during reverse recovery, leading to greater switching losses, lower reliability, and increased susceptibility to electromagnetic interference.

[0006] Therefore, there is an urgent need for a structure or method that can significantly improve the trade-off relationship between IGBT on-state voltage drop and turn-off loss, the relationship between FRD breakdown voltage and on-state voltage drop, and reduce reverse recovery spike current in RC-IGBTs, so as to improve the device performance and reliability of RC-IGBTs.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0008] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor device structure and its fabrication method to solve the problems of the difficulty in simultaneously optimizing the on-state voltage drop and breakdown voltage of RC-IGBT and the large reverse recovery peak current in the prior art.

[0009] To achieve the above objectives, the present invention provides a semiconductor device structure, the semiconductor device structure comprising: a collector, a heavily doped layer of a second conductivity type, a back layer of a first conductivity type, a substrate layer of a first conductivity type, a trench gate, a deep trench field plate, a body region of a second conductivity type, a heavily doped region of a first conductivity type, a gate, and an emitter;

[0010] The first conductivity type back surface layer includes a first conductivity type buffer layer and a first conductivity type heavy doped region that are alternately distributed along the direction of the trench gate and the deep trench field plate. The first conductivity type heavy doped region is distributed at a corresponding position below the deep trench field plate.

[0011] The first conductivity type substrate layer includes a first surface and a second surface disposed opposite to each other. The first conductivity type back surface layer, the second conductivity type heavily doped layer and the collector are located on the second surface of the first conductivity type substrate layer from top to bottom. The second conductivity type body region and the first conductivity type heavily doped region are located on the first surface of the first conductivity type substrate layer from bottom to top.

[0012] Both the trench gate and the deep trench field plate are filling layers that penetrate the second conductivity type body region and extend into the trench of the first conductivity type substrate layer. The depth of the trench gate is less than the depth of the deep trench field plate. The trench gate also penetrates the first conductivity type heavily doped region.

[0013] The emitter is effectively electrically connected to the deep trench field plate, the second conductivity type body region, and the second conductivity type heavily doped layer, and the gate is effectively electrically connected to the trench gate.

[0014] Optionally, the depth of the deep trench field plate is greater than or equal to 20 micrometers.

[0015] Optionally, the depth of the deep trench field plate is 2-3 times the depth of the trench grid.

[0016] Optionally, the trench gate includes a gate oxide layer and a gate polysilicon layer, the gate oxide layer covering the inner wall of the trench where the trench gate is located, and the gate polysilicon filling the surface of the gate oxide layer within the trench where the trench gate is located; the deep trench field plate includes a field plate oxide layer and a field plate polysilicon layer, the field plate oxide layer covering the inner wall of the trench where the deep trench field plate is located, and the field plate polysilicon filling the surface of the field plate oxide layer within the trench where the deep trench field plate is located.

[0017] Optionally, the semiconductor device structure further includes a passivation layer and a protective layer, wherein the passivation layer is located on all surfaces of the gate and the emitter that are not electrically led out, and the protective layer is located on the surface of the passivation layer.

[0018] Optionally, the semiconductor device structure further includes an interlayer dielectric layer; the interlayer dielectric layer is located on the surface of the first conductivity type heavily doped region exposed between adjacent gates and / or emitters to provide insulation between adjacent gates and / or emitters.

[0019] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0020] The present invention also provides a method for fabricating a semiconductor device structure, the method being used to fabricate any one of the semiconductor device structures described above, the method comprising:

[0021] A first conductivity type substrate is provided, the first conductivity type substrate including a first surface and a second surface disposed opposite to each other;

[0022] A first trench and a second trench are formed on a first surface of the first conductive type substrate, wherein the depth of the second trench is greater than the depth of the first trench;

[0023] A trench grid is provided in the first trench, and a deep trench field plate is provided in the second trench;

[0024] Doping is performed on the first surface of the first conductivity type substrate at a location where the trench gate and the deep trench field plate are not provided, to obtain a second conductivity type body region and a first conductivity type heavily doped region. The second conductivity type body region and the first conductivity type heavily doped region are located from bottom to top in the first conductivity type substrate near the first surface.

[0025] Patterned trenches are formed in the first conductivity type heavily doped region and the second conductivity type body region. The patterned trenches penetrate the first conductivity type heavily doped region and extend into the second conductivity type body region to expose the surface of the trench gate, the deep trench field plate and the second conductivity type body region.

[0026] A patterned conductive layer is provided to cover the surface exposed by the patterned trench. The conductive layer electrically connected to the trench gate is the gate electrode, and the conductive layer electrically connected to the deep trench field plate is the emitter electrode.

[0027] The second surface of the first conductivity type substrate is doped to obtain a first conductivity type back surface layer and a second conductivity type heavily doped layer. The first conductivity type back surface layer includes a first conductivity type buffer layer and a first conductivity type freewheeling heavily doped region that are alternately distributed along the distribution direction of the trench gate and the deep trench field plate. The first conductivity type freewheeling heavily doped region is distributed at a corresponding position below the deep trench field plate. The first conductivity type back surface layer and the second conductivity type heavily doped layer are located from top to bottom in the first conductivity type substrate near the second surface. The first conductivity type substrate between the first conductivity type back surface layer and the second conductivity type body region is the first conductivity type substrate layer.

[0028] A collector electrode is disposed on the surface of the heavily doped layer of the second conductivity type.

[0029] Optionally, the method of forming the first trench and the second trench on the first surface of the first conductivity type substrate includes:

[0030] A hard mask layer is disposed on the first surface of the first conductivity type substrate, and the hard mask layer comprises, from bottom to top, a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer;

[0031] The hard mask layer is patterned to expose a first surface of the first conductivity type substrate at a predetermined location for setting the first trench;

[0032] The first surface of the first conductivity type substrate is etched using the patterned hard mask layer as a mask to obtain the first trench;

[0033] The hard mask layer is patterned again to simultaneously expose the first surface of the first conductivity type substrate for setting the preset positions of the first trench and the second trench;

[0034] Using the patterned hard mask layer as a mask, the first surface of the first conductive type substrate is etched to obtain a second trench; at the same time, the first trench is further etched to obtain a second trench with a depth greater than the depth of the first trench.

[0035] Remove the remaining hard mask layer.

[0036] Optionally, the method of setting the trench grid and the deep trench field plate includes:

[0037] The inner surfaces of the first trench and the second trench are thermally oxidized by furnace tube growth to obtain a gate oxide layer on the inner surface of the first trench and a field plate oxide layer on the inner surface of the second trench.

[0038] Polycrystalline silicon is grown in a furnace tube to fill the first and second trenches, so that the gate oxide layer surface in the first trench is filled with gate polycrystalline silicon and the field oxide layer surface in the second trench is filled with field polycrystalline silicon.

[0039] The first surface of the first conductive type substrate is planarized to expose the trench gate in the first trench and the deep trench field plate in the second trench.

[0040] As described above, the semiconductor device structure and its fabrication method of the present invention have the following beneficial effects:

[0041] The present invention provides a deep trench field plate that is shorted to the emitter on both sides of the trench gate, so that when the semiconductor device structure is turned on, the deep trench field plate accumulates a large number of holes, thereby reducing the on-state voltage drop;

[0042] This invention utilizes the vertical electric field distribution added by the deep trench field plate to optimize the trade-off between the FRD breakdown voltage and the turn-on voltage in the RC-IGBT, thereby reducing the operating loss of the RC-IGBT in the freewheeling state.

[0043] This invention, in conjunction with a deep trench field plate, enables the carriers in the depletion layer to be rapidly extracted during freewheeling, thereby reducing the current released during reverse recovery and lowering the peak current during reverse recovery. Attached Figure Description

[0044] Figure 1 The diagram shows a schematic of the structure of an RC-IGBT in the prior art.

[0045] Figure 2 The diagram shown is a schematic representation of the semiconductor device structure in this invention.

[0046] Figure 3 The diagram shown is a schematic representation of the structure presented in step 2 of the method for fabricating the semiconductor device structure of the present invention, where a hard mask layer is set.

[0047] Figure 4 The diagram shown is a schematic representation of the structure presented by the patterned hard mask layer in step 2 of the method for fabricating the semiconductor device structure of the present invention.

[0048] Figure 5 The diagram shown is a schematic representation of the structure of the first trench obtained in step 2 of the method for fabricating the semiconductor device structure of the present invention.

[0049] Figure 6 The diagram shown is a schematic representation of the structure presented by the hard mask layer in step 2 of the method for fabricating the semiconductor device structure of the present invention.

[0050] Figure 7 The diagram shown is a schematic representation of the structure of the first trench and the second trench obtained in step 2 of the method for fabricating the semiconductor device structure of the present invention.

[0051] Figure 8 The diagram shows the structure of the trench gate and deep trench field plate in step 3 of the method for fabricating the semiconductor device structure of the present invention.

[0052] Figure 9 The diagram shows the structure of the second conductivity type bulk region and the first conductivity type heavily doped region obtained in step 4 of the semiconductor device structure fabrication method of the present invention.

[0053] Figure 10 The diagram shown is a schematic representation of the structure presented in step 4 of the method for fabricating the semiconductor device structure of the present invention, where an interlayer dielectric layer is set.

[0054] Figure 11 The diagram shows the structure of the semiconductor device structure fabrication method of the present invention, specifically step 5, which involves setting patterned trenches.

[0055] Figure 12 The diagram shown is a schematic representation of the structure of the semiconductor device structure fabrication method of the present invention, step 6, which involves setting a conductive layer.

[0056] Figure 13The diagram shown is a schematic representation of the patterned conductive layer in step 6 of the method for fabricating the semiconductor device structure of the present invention.

[0057] Figure 14 The diagram shown is a schematic representation of the structure formed by setting a passivation layer and a protective layer in step 6 of the method for fabricating the semiconductor device structure of the present invention.

[0058] Figure 15 The diagram shows the structure of the first conductivity type back surface layer and the second conductivity type heavily doped layer obtained in step 7 of the method for fabricating the semiconductor device structure of the present invention.

[0059] Figure 16 The diagram shows the structure of the semiconductor device structure fabrication method of the present invention, specifically step 8, which involves setting the collector electrode.

[0060] Explanation of icon numbers

[0061] 10. First conductivity type substrate; 11. First conductivity type substrate layer; 12. Second conductivity type body region; 13. First conductivity type heavily doped region; 14. First conductivity type back surface layer; 141. First conductivity type buffer layer; 142. First conductivity type freewheeling heavily doped region; 15. Second conductivity type heavily doped layer; 16. Interlayer dielectric layer; 17. Passivation layer; 18. Protective layer; 19. Patterned trench;

[0062] 20. Conductive layer; 21. Collector; 22. Emitter; 23. Gate;

[0063] 30. Trench gate; 31. Gate oxide layer; 32. Gate polysilicon; 33. First trench;

[0064] 40. Deep trench field plate; 41. Field plate oxide layer; 42. Field plate polysilicon; 43. Second trench;

[0065] 50. Hard mask layer; 51. Silicon dioxide layer; 52. Silicon nitride layer. Detailed Implementation

[0066] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0068] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0069] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0070] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] like Figure 1 As shown, in existing RC-IGBTs (Reverse Conducting IGBTs) that integrate IGBTs (Insulated Gate Bipolar Transistors) and FRDs (Fast Recovery Diodes), the inverse correlation between the on-state voltage drop and turn-off loss of the IGBT section necessitates a trade-off between these two factors in the IGBT design, thus limiting the efficiency performance of IGBTs in electronic power systems. Furthermore, the integration of the FRD into the IGBT causes the resistivity of their shared substrate to affect the breakdown voltage (BV) of the FRD. The voltage (breakdown voltage) and VF (forward voltage drop) limit the dual optimization of BV and VF of the FRD in the RC-IGBT, resulting in greater operating losses when it is in freewheeling mode. At the same time, the FRD in the RC-IGBT will generate a spike current during reverse recovery, resulting in greater switching losses, poor reliability, and easy generation of large electromagnetic interference in the RC-IGBT.

[0072] This invention provides a semiconductor device structure, such as... Figure 2 As shown, the semiconductor device structure includes: collector 21, second conductivity type heavily doped layer 15, first conductivity type back layer 14, first conductivity type substrate layer 11, trench gate 30, deep trench field plate 40, second conductivity type body region 12, first conductivity type heavily doped region 13, gate 23, and emitter 22.

[0073] The first conductivity type back surface layer 14 includes a first conductivity type buffer layer 141 and a first conductivity type freewheeling heavily doped region 142 that are alternately distributed along the direction of the trench gate 30 and the deep trench field plate 40. The first conductivity type freewheeling heavily doped region 142 is distributed at a corresponding position below the deep trench field plate 40.

[0074] The first conductivity type substrate layer 11 includes a first surface and a second surface disposed opposite to each other. The first conductivity type back surface layer 14, the second conductivity type heavily doped layer 15 and the collector electrode 21 are located on the second surface of the first conductivity type substrate layer 11 from top to bottom. The second conductivity type body region 12 and the first conductivity type heavily doped region 13 are located on the first surface of the first conductivity type substrate layer 11 from bottom to top.

[0075] The trench gate 30 and the deep trench field plate 40 are both filling layers that penetrate the second conductivity type body region 12 and extend into the trench of the first conductivity type substrate layer 11. The depth of the trench gate 30 is less than the depth of the deep trench field plate 40. The trench gate 30 also penetrates the first conductivity type heavily doped region 13.

[0076] The emitter 22 is effectively electrically connected to the deep trench field plate 40, the second conductivity type body region 12, and the second conductivity type heavily doped layer 15, and the gate 23 is effectively electrically connected to the trench gate 30.

[0077] This invention provides a deep trench field plate 40 shorted to the emitter 22 on both sides of the trench gate 30 of the RC-IGBT. When the semiconductor device structure is turned on, the deep trench field plate 40 accumulates a large number of holes, resulting in a stronger conductivity modulation effect during partial IGBT conduction. This leads to a higher carrier concentration near the emitter region, thereby reducing the resistivity of the first conductivity type substrate layer 11 (drift region) and thus lowering the on-state voltage drop V. CESimultaneously, the vertical electric field distribution added by the deep trench field plate 40 can make the electric field distribution in the RC-IGBT more uniform. This allows for an increase in the BV (breakdown voltage) of the FRD portion under the condition that the VF (on-state voltage drop) is the same (i.e., the doping concentration of the first conductivity type substrate 11 remains unchanged). Thus, while keeping the BV constant, a higher doping concentration of the first conductivity type substrate 11 can be used to reduce the VF of the RC-IGBT, reducing the operating state loss of the RC-IGBT when it is running in the circuit. This optimizes the trade-off between the breakdown voltage and the on-state voltage of the FRD in the RC-IGBT. In addition, the deep trench field plate 40 allows the carriers stored in the depletion layer to be quickly extracted during the freewheeling state, thereby reducing the current released during reverse recovery and lowering the peak current during reverse recovery.

[0078] Specifically, the doping concentration of the first conductivity type freewheeling heavy doping region 142 is greater than that of the first conductivity type buffer layer 141, thereby achieving the heavy doping effect of the first conductivity type freewheeling heavy doping region 142 to meet its freewheeling function in the FRD.

[0079] In one embodiment, the depth of the deep trench plate 40 is greater than or equal to 20 micrometers.

[0080] This invention, by setting the depth of the deep trench field plate 40 to be greater than or equal to 20 micrometers, can further increase the number of holes accumulated by the deep trench field plate 40 when the IGBT portion of the RC-IGBT is turned on, thereby further reducing the resistivity of the drift region, and thus further reducing the on-state voltage drop of the IGBT portion and the operating loss in the FRD freewheeling state. In addition, the deep trench field plate 40 with a depth greater than or equal to 20 micrometers can also further increase the speed at which carriers in the depletion layer are extracted in the freewheeling state, thereby further reducing the peak current of the reverse recovery. At the same time, as the depth of the deep trench field plate 40 is greater than or equal to 20 micrometers, its width will also be correspondingly increased due to the process technology, thereby reducing the number of conductive channels formed per unit area of ​​the RC-IGBT, reducing the density of conductive channels, and thus improving the operating efficiency and thermal management efficiency of the RC-IGBT.

[0081] In one embodiment, the depth of the deep trench field plate 40 is 2-3 times the depth of the trench grid 30.

[0082] By setting the relationship between the depth of the deep trench field plate 40 and the trench grid 30, this invention can ensure that the deep trench field plate 40 plays its role in RC-IGBT while meeting the feasibility of the trench manufacturing process, which is conducive to its promotion and application in actual production.

[0083] In one embodiment, the trench gate 30 includes a gate oxide layer 31 and a gate polysilicon layer 32. The gate oxide layer 31 covers the inner wall of the trench where the trench gate 30 is located, and the gate polysilicon layer 32 fills the surface of the gate oxide layer 31 within the trench where the trench gate 30 is located. The deep trench field plate 40 includes a field plate oxide layer 41 and a field plate polysilicon layer 42. The field plate oxide layer 41 covers the inner wall of the trench where the deep trench field plate 40 is located, and the field plate polysilicon layer 42 fills the surface of the field plate oxide layer 41 within the trench where the deep trench field plate 40 is located.

[0084] Specifically, the gate polysilicon 32 and the field polysilicon 42 can be replaced with other gate materials, but polysilicon is preferred to ensure close contact with the underlying oxide layer and thus ensure device reliability.

[0085] Specifically, the depth of the deep trench field plate 40 mentioned in this application mainly refers to the depth of the field plate polysilicon 42, and the depth of the trench gate 30 mainly refers to the depth of the gate polysilicon 32. Especially in the deep trench structure, since the gate oxide layer 31 and the field plate oxide layer 41 are usually thin films, they can be ignored compared with the thickness of the gate polysilicon 32 and the field plate polysilicon 42.

[0086] In one embodiment, the thickness of both the gate oxide layer 31 and the field plate oxide layer 41 is 1000 angstroms to 1500 angstroms.

[0087] In one embodiment, such as Figure 2 As shown, the semiconductor device structure also includes a passivation layer 17 and a protective layer 18. The passivation layer 17 is located on all surfaces of the gate 23 and the emitter 22 that are not conductively led out, and the protective layer 18 is located on the surface of the passivation layer 17.

[0088] The present invention protects the electrodes exposed on the surface of the semiconductor device structure by setting a passivation layer 17 and a protective layer 18, thereby reducing the risks of oxidation, damage or short circuit, and improving the product yield and reliability of the semiconductor device structure.

[0089] In one embodiment, such as Figure 2 As shown, the semiconductor device structure further includes an interlayer dielectric layer 16; the interlayer dielectric layer 16 is located on the surface of the first conductivity type heavily doped region 13 exposed between adjacent gates 23 and / or emitters 22, so as to provide insulation between adjacent gates 23 and / or emitters 22.

[0090] By providing an interlayer dielectric layer 16, this invention can further improve the insulation isolation between adjacent gates 23 and / or emitters 22, avoid short circuits between electrodes, and improve product yield.

[0091] Specifically, "between adjacent gates 23 and / or emitters 22" refers to the general term for three situations: "between adjacent gates 23", "between adjacent emitters 22", or "between adjacent gates 23 and emitters 22".

[0092] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0093] By employing N-type as the first conductivity type, this invention can achieve lower resistivity, thereby further reducing conduction losses and improving the switching speed of RC-IGBT.

[0094] In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

[0095] The present invention also provides a method for fabricating a semiconductor device structure, the method being used to fabricate any one of the semiconductor device structures described above, the method comprising:

[0096] Step 1: Provide a first conductivity type substrate 10, the first conductivity type substrate 10 including a first surface and a second surface disposed opposite to each other;

[0097] Step 2: A first trench 33 and a second trench 43 are formed on the first surface of the first conductive substrate 10, wherein the depth of the second trench 43 is greater than the depth of the first trench 33;

[0098] Step 3: A trench grid 30 is provided in the first trench 33, and a deep trench plate 40 is provided in the second trench 43;

[0099] Step 4: Doping is performed on the first surface of the first conductive type substrate 10 at a location where the trench gate 30 and the deep trench field plate 40 are not provided, to obtain a second conductive type body region 12 and a first conductive type heavily doped region 13. The second conductive type body region 12 and the first conductive type heavily doped region 13 are located from bottom to top in the first conductive type substrate 10 near the first surface.

[0100] Step 5: A patterned trench 19 is formed in the first conductivity type heavily doped region 13 and the second conductivity type body region 12. The patterned trench 19 penetrates the first conductivity type heavily doped region 13 and extends into the second conductivity type body region 12 to expose the surface of the trench gate 30, the deep trench field plate 40 and the second conductivity type body region 12.

[0101] Step 6: Set a patterned conductive layer 20 to cover the exposed surface of the patterned trench 19. The conductive layer 20 electrically connected to the trench gate 30 is the gate 23, and the conductive layer 20 electrically connected to the deep trench field plate 40 is the emitter 22.

[0102] Step 7: Doping the second surface of the first conductivity type substrate 10 to obtain a first conductivity type back surface layer 14 and a second conductivity type heavily doped layer 15. The first conductivity type back surface layer 14 includes a first conductivity type buffer layer 141 and a first conductivity type freewheeling heavily doped region 142 alternately distributed along the distribution direction of the trench gate 30 and the deep trench field plate 40. The first conductivity type freewheeling heavily doped region 142 is distributed at a corresponding position below the deep trench field plate 40. The first conductivity type back surface layer 14 and the second conductivity type heavily doped layer 15 are located from top to bottom in the first conductivity type substrate 10 near the second surface. The first conductivity type substrate 10 between the first conductivity type back surface layer 14 and the second conductivity type body region 12 is the first conductivity type substrate layer 11.

[0103] Step 8: A collector electrode 21 is disposed on the surface of the heavily doped layer 15 of the second conductivity type.

[0104] The method for fabricating the semiconductor device structure of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the fabrication method of the semiconductor device structure protected by the present invention, and those skilled in the art can make changes according to the actual fabrication steps.

[0105] First, step 1 is performed, providing a first conductive type substrate 10, the first conductive type substrate 10 including a first surface and a second surface disposed opposite to each other.

[0106] Then, in step 2, a first trench 33 and a second trench 43 are formed on the first surface of the first conductive substrate 10, wherein the depth of the second trench 43 is greater than the depth of the first trench 33.

[0107] In one embodiment, a method for forming the first trench 33 and the second trench 43 on a first surface of the first conductivity type substrate 10 includes:

[0108] like Figure 3 As shown, a hard mask layer 50 is provided on the first surface of the first conductivity type substrate 10. The hard mask layer 50 includes a silicon dioxide layer 51, a silicon nitride layer 52 and a silicon dioxide layer 51 from bottom to top.

[0109] like Figure 4As shown, the hard mask layer 50 is patterned to expose the first surface of the first conductivity type substrate 10 at a predetermined position for setting the first trench 33.

[0110] like Figure 5 As shown, the first surface of the first conductive type substrate 10 is etched using the patterned hard mask layer 50 as a mask to obtain the first trench 33;

[0111] like Figure 6 As shown, the hard mask layer 50 is patterned again to simultaneously expose the first surface of the first conductive type substrate 10 for setting the preset positions of the first trench 33 and the second trench 43.

[0112] like Figure 7 As shown, the first surface of the first conductive type substrate 10 is etched using the patterned hard mask layer 50 as a mask to obtain the second trench 43; at the same time, the first trench 33 is further etched to obtain the second trench 43 with a depth greater than the depth of the first trench 33.

[0113] Remove the remaining hard mask layer 50.

[0114] In one embodiment, the method of setting the hard mask layer 50 includes: firstly, epitaxially growing a thin silicon dioxide layer 51 of a certain thickness on a first surface of a first conductivity type substrate 10; then depositing a silicon nitride layer 52 of a certain thickness on the silicon dioxide layer 51; and finally depositing another silicon dioxide layer 51 on the silicon nitride layer 52 to form a hard mask layer 50 composed of silicon dioxide-silicon nitride-silicon dioxide.

[0115] In one embodiment, the hard mask layer 50 may also be other suitable hard mask layers 50, but it is preferred to use the hard mask layer 50 composed of silicon dioxide-silicon nitride-silicon dioxide in this embodiment.

[0116] In one embodiment, the method of patterning the hard mask layer 50 includes: depositing photoresist on the hard mask layer 50; exposing and developing the photoresist to obtain patterned photoresist to expose the patterned area of ​​the hard mask layer 50; etching the patterned photoresist to expose the hard mask layer 50; removing the remaining photoresist and cleaning.

[0117] In one embodiment, the remaining hard mask layer 50 is removed by wet etching.

[0118] Next, proceed to step 3, as follows: Figure 8 As shown, a groove grid 30 is provided in the first groove 33, and a deep groove field plate 40 is provided in the second groove 43.

[0119] In one embodiment, the method of setting the trench grid 30 and the deep trench field plate 40 includes:

[0120] The inner surfaces of the first trench 33 and the second trench 43 are thermally oxidized by furnace tube growth to obtain a gate oxide layer 31 on the inner surface of the first trench 33 and a field plate oxide layer 41 on the inner surface of the second trench 43.

[0121] Polycrystalline silicon is grown in a furnace tube to fill the first trench 33 and the second trench 43, so that gate polycrystalline silicon 32 is filled on the surface of the gate oxide layer 31 in the first trench 33, and field plate polycrystalline silicon 42 is filled on the surface of the field plate oxide layer 41 in the second trench 43.

[0122] The first surface of the first conductive type substrate 10 is planarized to expose the trench gate 30 in the first trench 33 and the deep trench field plate 40 in the second trench 43.

[0123] In one embodiment, the method for planarizing the first surface of the first conductive type substrate 10 is to etch away excess polysilicon and oxide layers from the first surface of the first conductive type substrate layer 11.

[0124] Then, proceed to step 4, as follows: Figure 9 As shown, doping is performed on the first surface of the first conductivity type substrate 10 at a location where the trench gate 30 and the deep trench field plate 40 are not provided, to obtain a second conductivity type body region 12 and a first conductivity type heavily doped region 13. The second conductivity type body region 12 and the first conductivity type heavily doped region 13 are located from bottom to top in the first conductivity type substrate 10 near the first surface.

[0125] In one embodiment, the method for obtaining the second conductivity type body region 12 and the first conductivity type heavily doped region 13 includes: using photoresist exposure and development to define the position of the second conductivity type body region 12 on the first surface of the first conductivity type substrate 10, injecting P-type impurities to form the second conductivity type body region 12, and removing the remaining photoresist; using photoresist exposure and development to define the position of the first conductivity type heavily doped region 13 on the first surface of the first conductivity type substrate 10, injecting N-type impurities to form the first conductivity type heavily doped region 13, and removing the remaining photoresist; and pushing the obtained product into the furnace tube at high temperature to obtain the second conductivity type body region 12 and the first conductivity type heavily doped region 13 located from bottom to top within the first conductivity type substrate 10 near the first surface.

[0126] In one embodiment, such as Figure 10As shown, after setting the second conductivity type body region 12 and the first conductivity type heavily doped region 13, an interlayer dielectric layer 16 is set on their surfaces. The interlayer dielectric layer 16 covers the exposed surfaces of the first conductivity type heavily doped region 13, the trench gate 30, and the deep trench field plate 40.

[0127] In one embodiment, the method of setting the interlayer dielectric layer 16 includes: first forming a layer of silicon dioxide, and then depositing a certain thickness of silicon borophosphate glass to form the interlayer dielectric layer 16.

[0128] Next, proceed to step 5, as follows: Figure 11 As shown, patterned trenches 19 are provided in the first conductivity type heavily doped region 13 and the second conductivity type body region 12. The patterned trenches 19 penetrate the first conductivity type heavily doped region 13 and extend into the second conductivity type body region 12 to expose the surfaces of the trench gate 30, the deep trench field plate 40 and the second conductivity type body region 12.

[0129] In one embodiment, such as Figure 11 As shown, when an interlayer dielectric layer 16 is provided, and a patterned trench 19 is provided, the patterned trench 19 also penetrates the interlayer dielectric layer 16.

[0130] Then, in step 6, a patterned conductive layer 20 is set to cover the exposed surface of the patterned trench 19. The conductive layer 20 electrically connected to the trench gate 30 is the gate electrode 23, and the conductive layer 20 electrically connected to the deep trench field plate 40 is the emitter electrode 22.

[0131] In one embodiment, a method for setting the patterned conductive layer 20 includes: as follows Figure 12 As shown, the surface of the patterned trench 19 and the exposed interlayer dielectric layer 16 is covered with a conductive layer 20; as Figure 13 As shown, the conductive layer 20 covering and filling is patterned to obtain the gate 23 electrically connected to the trench gate 30 and the emitter 22 electrically connected to the deep trench field plate 40.

[0132] In one embodiment, such as Figure 14 As shown, a passivation layer 17 and a protective layer 18 are sequentially disposed on the surface of the patterned conductive layer 20 where no conductive leads are made.

[0133] In one embodiment, the method of setting the passivation layer 17 includes: depositing a layer of silicon nitride, using photoresist to expose, develop and etch to obtain patterned silicon nitride as the passivation layer 17; and removing the remaining photoresist for cleaning.

[0134] In one embodiment, the method for setting the protective layer 18 includes: spin-coating a layer of PI (Polyimide), using photoresist for exposure, development and etching to obtain a patterned PI, curing the PI to obtain the protective layer 18, and removing the remaining photoresist for cleaning.

[0135] Next, proceed to step 7, as follows: Figure 15 As shown, the second surface of the first conductivity type substrate 10 is doped to obtain a first conductivity type back surface layer 14 and a second conductivity type heavily doped layer 15. The first conductivity type back surface layer 14 includes a first conductivity type buffer layer 141 and a first conductivity type freewheeling heavily doped region 142, which are alternately distributed along the distribution direction of the trench gate 30 and the deep trench field plate 40. The first conductivity type freewheeling heavily doped region 142 is distributed at a corresponding position below the deep trench field plate 40. The first conductivity type back surface layer 14 and the second conductivity type heavily doped layer 15 are located from top to bottom in the first conductivity type substrate 10 near the second surface. The first conductivity type substrate 10 between the first conductivity type back surface layer 14 and the second conductivity type body region 12 is the first conductivity type substrate layer 11.

[0136] In one embodiment, the second surface of the first conductivity type substrate 10 is thinned before doping. Specifically, the thickness of the first conductivity type substrate 10 after thinning is set according to the voltage requirements of the device.

[0137] In one embodiment, the thickness of the first conductivity type substrate 10 after thinning is 60 micrometers to 100 micrometers.

[0138] In one embodiment, an N-type impurity is implanted into the second surface of the first conductivity type substrate 10 using an ion implantation machine to obtain a first conductivity type back surface layer 14 composed of an alternating distribution of a first conductivity type buffer layer 141 and a first conductivity type freewheeling heavily doped region 142; a P-type impurity is implanted into the second surface of the first conductivity type substrate 10 to obtain a second conductivity type heavily doped layer 15.

[0139] Finally, proceed to step 8, as follows: Figure 16 As shown, a collector electrode 21 is disposed on the surface of the heavily doped layer 15 of the second conductivity type.

[0140] In one embodiment, the method of setting the collector 21 includes: depositing a metal layer on the surface of the second conductivity type heavily doped layer 15, and then setting a metal alloy on the metal as a protective layer 18 for the collector 21.

[0141] In summary, the semiconductor device structure and its fabrication method of the present invention can reduce the on-state voltage drop by accumulating a large number of holes in the deep trench field plates shorted to the emitter on both sides of the trench gate when the semiconductor device structure is turned on. At the same time, the vertical electric field distribution added by the deep trench field plates optimizes the trade-off between the FRD breakdown voltage and the on-state voltage in the RC-IGBT, thereby reducing the operating loss of the RC-IGBT in the freewheeling state. In addition, the deep trench field plates enable the carriers in the depletion layer to be rapidly extracted in the freewheeling state, thereby reducing the current released during reverse recovery and reducing the peak current during reverse recovery.

[0142] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0143] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device structure, characterized in that, The semiconductor device structure is an RC-IGBT; the semiconductor device structure includes: a collector, a heavily doped layer of the second conductivity type, a back layer of the first conductivity type, a substrate layer of the first conductivity type, a trench gate, a deep trench field plate, a body region of the second conductivity type, a heavily doped region of the first conductivity type, a gate, and an emitter; The first conductivity type back surface layer includes a first conductivity type buffer layer and a first conductivity type heavy doped region that are alternately distributed along the direction of the trench gate and the deep trench field plate. The first conductivity type heavy doped region is distributed at a corresponding position below the deep trench field plate. The first conductivity type substrate layer includes a first surface and a second surface disposed opposite to each other. The first conductivity type back surface layer, the second conductivity type heavily doped layer and the collector are located on the second surface of the first conductivity type substrate layer from top to bottom. The second conductivity type body region and the first conductivity type heavily doped region are located on the first surface of the first conductivity type substrate layer from bottom to top. Both the trench gate and the deep trench field plate are filling layers that penetrate the second conductivity type body region and extend into the trench of the first conductivity type substrate layer. The depth of the trench gate is less than the depth of the deep trench field plate. The trench gate also penetrates the first conductivity type heavily doped region. The emitter is effectively electrically connected to the deep trench field plate, the second conductivity type body region, and the second conductivity type heavily doped layer, and the gate is effectively electrically connected to the trench gate.

2. The semiconductor device structure according to claim 1, characterized in that, The depth of the deep trench plate is greater than or equal to 20 micrometers.

3. The semiconductor device structure according to claim 1, characterized in that, The depth of the deep trench field plate is 2-3 times the depth of the trench grid.

4. The semiconductor device structure according to claim 1, characterized in that, The trench gate includes a gate oxide layer and a gate polysilicon layer. The gate oxide layer covers the inner wall of the trench where the trench gate is located, and the gate polysilicon layer fills the surface of the gate oxide layer within the trench where the trench gate is located. The deep trench field plate includes a field plate oxide layer and a field plate polysilicon layer. The field plate oxide layer covers the inner wall of the trench where the deep trench field plate is located, and the field plate polysilicon layer fills the surface of the field plate oxide layer within the trench where the deep trench field plate is located.

5. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure further includes a passivation layer and a protective layer. The passivation layer is located on all surfaces of the gate and the emitter that are not electrically conductive, and the protective layer is located on the surface of the passivation layer.

6. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure further includes an interlayer dielectric layer; the interlayer dielectric layer is located on the surface of the first conductivity type heavily doped region exposed between adjacent gates and / or emitters to provide insulation between adjacent gates and / or emitters.

7. The semiconductor device structure according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

8. A method for fabricating a semiconductor device structure, characterized in that, The preparation method is used to prepare the semiconductor device structure according to any one of claims 1-7, and the preparation method includes: A first conductivity type substrate is provided, the first conductivity type substrate including a first surface and a second surface disposed opposite to each other; A first trench and a second trench are formed on a first surface of the first conductive type substrate, wherein the depth of the second trench is greater than the depth of the first trench; A trench grid is provided in the first trench, and a deep trench field plate is provided in the second trench; Doping is performed on the first surface of the first conductivity type substrate at a location where the trench gate and the deep trench field plate are not provided, to obtain a second conductivity type body region and a first conductivity type heavily doped region. The second conductivity type body region and the first conductivity type heavily doped region are located from bottom to top in the first conductivity type substrate near the first surface. Patterned trenches are formed in the first conductivity type heavily doped region and the second conductivity type body region. The patterned trenches penetrate the first conductivity type heavily doped region and extend into the second conductivity type body region to expose the surface of the trench gate, the deep trench field plate and the second conductivity type body region. A patterned conductive layer is provided to cover the surface exposed by the patterned trench. The conductive layer electrically connected to the trench gate is the gate electrode, and the conductive layer electrically connected to the deep trench field plate is the emitter electrode. The second surface of the first conductivity type substrate is doped to obtain a first conductivity type back surface layer and a second conductivity type heavily doped layer. The first conductivity type back surface layer includes a first conductivity type buffer layer and a first conductivity type freewheeling heavily doped region that are alternately distributed along the distribution direction of the trench gate and the deep trench field plate. The first conductivity type freewheeling heavily doped region is distributed at a corresponding position below the deep trench field plate. The first conductivity type back surface layer and the second conductivity type heavily doped layer are located from top to bottom in the first conductivity type substrate near the second surface. The first conductivity type substrate between the first conductivity type back surface layer and the second conductivity type body region is the first conductivity type substrate layer. A collector electrode is disposed on the surface of the heavily doped layer of the second conductivity type.

9. The method for fabricating a semiconductor device structure according to claim 8, characterized in that, The method of forming the first trench and the second trench on the first surface of the first conductivity type substrate includes: A hard mask layer is disposed on the first surface of the first conductivity type substrate, and the hard mask layer comprises, from bottom to top, a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer; The hard mask layer is patterned to expose a first surface of the first conductivity type substrate at a predetermined location for setting the first trench; The first surface of the first conductivity type substrate is etched using the patterned hard mask layer as a mask to obtain the first trench; The hard mask layer is patterned again to simultaneously expose the first surface of the first conductivity type substrate for setting the preset positions of the first trench and the second trench; Using the patterned hard mask layer as a mask, the first surface of the first conductive type substrate is etched to obtain a second trench; at the same time, the first trench is further etched to obtain a second trench with a depth greater than the depth of the first trench. Remove the remaining hard mask layer.

10. The method for fabricating a semiconductor device structure according to claim 8, characterized in that, The method for setting the trench grid and the deep trench field plate includes: The inner surfaces of the first trench and the second trench are thermally oxidized by furnace tube growth to obtain a gate oxide layer on the inner surface of the first trench and a field plate oxide layer on the inner surface of the second trench. Polycrystalline silicon is grown in a furnace tube to fill the first and second trenches, so that the gate oxide layer surface in the first trench is filled with gate polycrystalline silicon and the field oxide layer surface in the second trench is filled with field polycrystalline silicon. The first surface of the first conductive type substrate is planarized to expose the trench gate in the first trench and the deep trench field plate in the second trench.

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