Semiconductor device and method of manufacturing the same, chip, electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, a chip and an electronic device, and relates to the technical field of semiconductors, and aims to solve the problem of reverse bias and / or dynamic resistance caused by body electron traps or interface state traps. The semiconductor device comprises a substrate, an epitaxial layer, a barrier layer, a gate, a cap layer, a source, a drain and a functional layer. The epitaxial layer and the barrier layer are stacked on the substrate, and the barrier layer is farther away from the substrate than the epitaxial layer. The gate is located on the side of the barrier layer away from the substrate. The cap layer is located between the barrier layer and the gate. The source and the drain are located on the side of the barrier layer away from the substrate, and are respectively located on the opposite sides of the gate. The functional layer is located on the side of the barrier layer away from the substrate. The functional layer and the drain are located on the same side of the gate, and the functional layer and the drain are connected. The thickness of the functional layer is less than the thickness of the cap layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, specifically to the field of gallium nitride HEMT devices, and more particularly to a semiconductor device and a preparation method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride (GaN), a third-generation semiconductor material, is widely used in various fields due to its wide bandgap, high power density, and stable chemical properties. GaN high-electron-mobility transistors (HEMTs), as semiconductor devices, offer advantages such as small chip area, low switching losses, fast operation, high conversion efficiency, and high power density. In the field of power electronics, they can further improve the efficiency of power electronics systems, reduce their size, and lower manufacturing costs.

[0003] However, due to manufacturing processes and other reasons, semiconductor devices contain some defects, such as bulk defects caused by lattice mismatch and thermal expansion coefficient during the growth of the GaN epitaxial structure on the silicon substrate, and / or interface state defects caused by defects induced by non-periodic lattice arrangement or unpassivated dangling bonds at the contact interface between the passivation layer and the GaN heterojunction. If the semiconductor device is in the off state, the high electric field between the drain and the substrate, and between the drain and the gate, will cause the above defects to charge and discharge with free electrons, which will cause the threshold voltage or on-resistance to change when the device is turned back on, that is, a reverse bias problem. If the device is in the hard switching process, hot electrons formed after being accelerated by the high electric field will also be captured by the above defects. The electrons captured in the defects act as negative fixed charges, repelling the two-dimensional electron gas in the channel layer, resulting in an increase in dynamic resistance and a reduction in the dynamic performance of the semiconductor device, that is, a dynamic resistance problem.

[0004] Therefore, an improved semiconductor device and a method for manufacturing the same are desired, which can solve at least one of the above problems. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to solve reverse bias problems and / or dynamic resistance problems caused by bulk electron traps or interface state traps.

[0006] In one aspect, a semiconductor device is provided, comprising a substrate, an epitaxial layer, a barrier layer, a gate, a cap layer, a source electrode, a drain electrode, and a functional layer. The epitaxial layer and the barrier layer are stacked on the substrate, with the barrier layer being further away from the substrate than the epitaxial layer. The gate electrode is located on a side of the barrier layer away from the substrate. The cap layer is located between the barrier layer and the gate electrode. The source electrode and the drain electrode are located on a side of the barrier layer away from the substrate, and are respectively located on opposite sides of the gate electrode. The functional layer is located on a side of the barrier layer away from the substrate. The functional layer and the drain electrode are located on the same side of the gate electrode, and the functional layer and the drain electrode are connected. The thickness of the functional layer is less than the thickness of the cap layer.

[0007] In a semiconductor device, the functional layer is connected to the drain, and the functional layer is used to inject holes into the passivation interface formed by the barrier layer and the passivation layer, the barrier layer, and the buffer layer, which can significantly enhance the dynamic resistance stability of the semiconductor device.

[0008] Because the functional layer is thinner than the cap layer, the two-dimensional electron gas (2DEG) still exists beneath the functional layer, reducing the forward voltage drop of the PIN junction at this location. This allows for effective hole injection in both soft-switching mode and off-state stress, improving the device's dynamic characteristics. Furthermore, the functional layer improves the injection efficiency of the PIN junction, thereby enhancing the device's dynamic reliability.

[0009] In a feasible embodiment, the thickness of the functional layer is greater than or equal to 5 nanometers.

[0010] In a feasible embodiment, the thickness of the functional layer is less than or equal to the difference between the thickness of the cap layer and a preset thickness, and the preset thickness is 1 nanometer to 6 nanometers.

[0011] In a feasible embodiment, the material of the functional layer includes P-type gallium nitride.

[0012] In a feasible embodiment, the functional layer and the cap layer are made of the same material and are provided in the same layer.

[0013] In a feasible embodiment, the semiconductor device further comprises a conductive portion disposed on a side of the functional layer away from the substrate, with a gap between the functional layer and the conductive portion and the drain; and the conductive portion is connected to the drain.

[0014] In a feasible embodiment, the conductive portion is made of the same material as the gate.

[0015] The conductive part is made of the same material as the gate and is provided in the same layer, which is beneficial to reducing the number of steps and improving production efficiency, while also effectively reducing production costs.

[0016] In a feasible embodiment, the material of the conductive part includes metal, and the work function of the metal is greater than or equal to 4.8 electron volts.

[0017] Using a metal with a work function greater than or equal to 4.8 electron volts as the conductive portion can enable the conductive portion to form a near-ohmic contact with the functional layer, effectively improving the hole injection efficiency of the functional layer.

[0018] In a feasible embodiment, the material of the conductive part includes at least one of palladium, nickel, aluminum, gold, platinum, titanium and titanium nitride.

[0019] In a feasible embodiment, the drain electrode at least covers a side of the functional layer away from the gate.

[0020] In a feasible embodiment, the drain electrode further covers at least a portion of the surface of the functional layer away from the substrate.

[0021] In a feasible embodiment, the drain electrode also covers the side surface of the functional layer close to the gate.

[0022] In a feasible embodiment, the functional layer includes at least two sub-functional layers spaced apart from each other, and the at least two sub-functional layers are arranged along a first direction; the first direction is parallel to the substrate and perpendicular to the arrangement direction of the source, the gate and the drain.

[0023] In a feasible embodiment, in an orthographic projection onto the substrate, the shape of the sub-functional layer is selected from any one of a rectangle, a circle, a triangle, a diamond, or a star.

[0024] In a feasible embodiment, it further includes: a passivation layer, the passivation layer is located on the side of the barrier layer away from the substrate; the source, the cap layer, the functional layer and the drain respectively penetrate the passivation layer and contact the barrier layer.

[0025] On the other hand, a chip is provided, comprising a packaging substrate and the above-mentioned semiconductor device, wherein the packaging substrate is coupled to the semiconductor device.

[0026] On the other hand, an electronic device is provided, comprising a circuit board and the above chip, wherein the chip is arranged on the circuit board.

[0027] On the other hand, a method for preparing a semiconductor device is provided, comprising: sequentially forming an epitaxial layer, a barrier layer, and an initial cap layer on a substrate; etching the initial cap layer to form a cap layer and an initial functional layer; thinning the initial functional layer to form a functional layer; forming a source and a drain on a side of the barrier layer away from the substrate; the source and the drain are respectively located on opposite sides of the cap layer, and the drain and the functional layer are located on the same side of the cap layer; and forming a gate on a side of the cap layer away from the substrate.

[0028] In a feasible embodiment, thinning the initial functional layer to form a functional layer includes: forming a mask layer, the mask layer exposing the initial functional layer and the source contact area and the drain contact area of ​​the barrier layer; and etching the initial functional layer and the barrier layer through the mask layer.

[0029] The initial functional layer 230 , the source contact region 240 , and the drain contact region 250 are etched simultaneously, which can simplify the process and reduce production costs.

[0030] In a feasible embodiment, the thinning of the initial functional layer to form a functional layer includes: forming a first mask layer, the first mask layer exposing the initial functional layer; etching the initial functional layer through the first mask layer; before forming the source and drain, the preparation method also includes: forming a second mask layer, the second mask layer exposing the source contact area and the drain contact area of ​​the barrier layer; etching the barrier layer through the second mask layer.

[0031] It can be understood that the beneficial effects achieved by the semiconductor device manufacturing method, chip, and electronic device provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure.

[0033] Figure 1 A structural diagram of an electronic device according to some embodiments;

[0034] Figure 2 A structural diagram of a semiconductor device provided according to some embodiments;

[0035] Figure 3 is a structural diagram of another semiconductor device provided according to some embodiments;

[0036] Figure 4 A flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0037] Figure 5 A partial flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0038] Figures 6 to 8 for Figure 4 A structural diagram of a semiconductor device in the provided preparation method;

[0039] Figure 9 A partial flow chart of another method for manufacturing a semiconductor device according to some embodiments;

[0040] Figure 10 for Figure 3 A magnesium doping concentration-depth curve of the semiconductor device shown;

[0041] Figure 11 The source-drain voltage-drain current curve of the semiconductor device with different magnesium equivalent doping concentrations in the functional layer;

[0042] Figure 12 The voltage-hole injection current curve of semiconductor devices with functional layers of different thicknesses;

[0043] Figure 13 is a structural diagram of another semiconductor device provided according to some embodiments;

[0044] Figure 14 for Figure 13 A top view of a semiconductor device;

[0045] Figure 15 for Figure 13 Another top view of the semiconductor device;

[0046] Figure 16 FIG. 1 is a structural diagram of yet another semiconductor device provided according to some embodiments. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0049] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0050] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0051] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0052] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and are not intended to be as actual views of individual layers and regions of devices and structures. As such, the actual structure can include more, less, and / or different layers and regions than illustrated in the figures. Thus, the drawings and discussion provided herein are meant to be illustrative only and not meant to be limiting. Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and are not intended to be as actual views of individual layers and regions of devices and structures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0055] As used herein, the term "substrate" refers to a material on which a subsequent layer of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0056] It should be noted that in this application, the word "comprising" is used in the citation of examples of features, integers, steps or components of the examples and embodiments of the application. This is to be construed, as specifying the presence of those features, integers, steps or components, but not giving any indication of exclusivity of features, integers, steps or components or any limitation as to their meaning or construction. It is also to be understood that, unless clearly required otherwise by standard dictionary meanings of terms used, words initially used herein in the singular will be read to include the plural and vice versa in appropriate instances.

[0057] The technical solutions of the present application can be applied to electronic devices, which are different types of user devices or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices; the electronic devices can also be network devices such as base stations. The electronic devices can also be devices such as power amplifiers used in the above electronic devices. The embodiments of the present application do not specially limit the specific form of the above electronic devices.

[0058] As Figure 1 As Figure 1A structural diagram of an electronic device according to some embodiments is provided. Embodiments of the present disclosure provide an electronic device 1, which can be a product or component with a power conversion function, such as a power conversion system of an electric vehicle, a charging device of a mobile phone, a power supply adaptation device of a notebook computer, etc. The electronic device 1 can also be a different type of user device or terminal device, such as a notebook computer, a tablet computer, a mobile phone, a wearable device, and a vehicle-mounted device, or a power amplification device applied in the above electronic devices. It should be understood that the electronic device 1 can also be a device or component with a signal receiving / transmitting function in an amplifier, a modulator, a base station, a radar, etc. The specific form of the electronic device 1 is not specially limited in the embodiments of the present application.

[0059] In the following, some embodiments of the present disclosure are schematically described by taking the electronic device 1 as an electronic device with a power conversion function as an example, but the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0060] In Figure 1 , the electronic device 1 includes, for example, a chip 10 and a circuit board 20, the chip 10 is disposed on the circuit board 20, and the circuit board 20 is configured to supply power and transmit signals to the chip 10. The chip 10 includes, for example, a semiconductor device and a packaging substrate, and the semiconductor device is coupled to the packaging substrate.

[0061] In a feasible embodiment, before the semiconductor device is coupled to the packaging substrate, a step of thinning the substrate of the semiconductor device is further included.

[0062] Figure 2 A structural diagram of a semiconductor device according to some embodiments is provided. The semiconductor device 101 includes a substrate 111, a nucleation layer 112, a buffer layer 113, a channel layer 114, a barrier layer 115, a source 120, a gate 131, a cap layer 132, and a drain 140.

[0063] The substrate 111, the nucleation layer 112, the buffer layer 113, the channel layer 114, and the barrier layer 115 are sequentially stacked. The source 120 and the drain 140 are respectively located on a side of the barrier layer 115 away from the channel layer 114, and the gate 131 is located between the source 120 and the drain 140. The epitaxial layer includes the buffer layer 113 and the channel layer 114.

[0064] In some feasible embodiments, the substrate 111 can be selected from at least one of silicon, silicon carbide, gallium nitride, sapphire, and diamond.

[0065] The nucleation layer 112 is located on one side of the substrate 111. For example, the nucleation layer 112 can be selected from at least one of aluminum nitride, gallium nitride, and aluminum gallium nitride. For example, the nucleation layer 112 can be a nitride thin film.

[0066] The buffer layer 113 is located on the side of the nucleation layer 112 away from the substrate 111. For example, the buffer layer 113 can be selected from carbon-doped gallium nitride, wherein the carbon concentration can be 10 -19 to 10 -20 The buffer layer 113 may also be a superlattice structure composed of at least one of aluminum nitride, gallium nitride and aluminum gallium nitride.

[0067] The channel layer 114 is located on a side of the buffer layer 113 away from the nucleation layer 112 . Exemplarily, the channel layer 114 is selected from a non-intentionally doped gallium nitride layer.

[0068] The barrier layer 115 is located on a side of the channel layer 114 away from the buffer layer 113. Exemplarily, the barrier layer 115 is selected from at least one of aluminum nitride and aluminum gallium nitride. It should be understood that the barrier layer 115 can also be selected from other binary, ternary, or quaternary nitrides.

[0069] The channel layer 114 and the barrier layer 115 contact to form a heterojunction interface. Due to the spontaneous polarization effect and piezoelectric polarization effect of the heterojunction, a large potential well exists at the heterojunction interface. In this structure, electrons are confined at the interface between the channel layer 114 and the barrier layer 115, thereby inducing the generation of a high-density two-dimensional electron gas 301 (2DEG) on the side of the channel layer 114 close to the barrier layer 115.

[0070] In some feasible embodiments, the semiconductor device 101 further includes an insertion layer, located between the channel layer 114 and the barrier layer 115. The insertion layer may be made of aluminum nitride. The insertion layer can improve the heterojunction interface quality, reduce scattering, and increase electron mobility. It can also improve conduction band discontinuity, thereby increasing the density of the two-dimensional electron gas 301 and improving the performance of the semiconductor device.

[0071] In some feasible embodiments, the material of the gate 131 includes at least one of palladium, nickel, aluminum, gold, platinum, titanium, and titanium nitride.

[0072] In some feasible embodiments, the material of the source 120 and the drain 140 includes at least one of titanium, aluminum, titanium nitride, silicon, and gold.

[0073] In some feasible embodiments, the semiconductor device 101 further includes a cap layer 132 . The cap layer 132 is located on a side of the barrier layer 115 away from the substrate 111 . The gate 131 is located on a side of the cap layer 132 away from the substrate 111 . As can be seen, Figure 2The two-dimensional electron gas 301 below the middle cap layer 132 is depleted. Exemplarily, the material of the cap layer 132 includes p-type gallium nitride.

[0074] In some feasible embodiments, the semiconductor device 101 further includes a passivation layer 116 , which is located on a side of the barrier layer 115 away from the substrate 111 . The source 120 , the cap layer 132 , and the drain 140 penetrate the passivation layer 116 and contact the barrier layer 115 .

[0075] Bulk electron traps 211 and interface state traps 212 also exist in semiconductor device 101. Due to the inherent cost sensitivity of semiconductor device 101, it is typically fabricated via heteroepitaxial growth on a silicon substrate. Even though current epitaxial growth technology has undergone numerous iterations, the lattice mismatch and thermal expansion coefficient difference between gallium nitride and silicon materials persist, leading to various defects in the epitaxial structure, resulting in the presence of bulk electron traps 211 in semiconductor device 101. Passivation layer 116 is used to balance the surface electric field of semiconductor device 101 and increase its withstand voltage. Insulating materials are typically used for passivation layer 116. However, no highly compatible oxide has been found in the gallium nitride material system. Materials for passivation layer 116 include silicon nitride, aluminum nitride, silicon oxide, and the like. Interface state traps 212 are introduced at the interface where passivation layer 116 and gallium nitride heterojunctions meet. Interface state traps 212 can be, for example, lattice-induced defects in a non-periodic arrangement at the interface or unpassivated dangling bonds.

[0076] Depend on Figure 2 It can be seen that if the semiconductor device 101 is in a hard switching process, hot electrons formed after being accelerated by a high electric field are captured by the bulk electron traps 211 or the interface state traps 212. The bulk electron traps 211 or the interface state traps 212 that capture the electrons act as negative fixed charges, repelling 301 in the channel layer, that is, 301 between the gate 131 and the drain 140 is weaker than 301 between the source 120 and the gate 131. This will cause the dynamic resistance to increase, reducing the dynamic performance of the semiconductor device 101, thereby causing a dynamic resistance problem. In addition, if the semiconductor device 101 is in the off state, the high electric field between the drain 140 and the substrate 111 and between the drain 140 and the gate 131 will cause the above-mentioned defects to charge and discharge with the free electrons. This will cause the threshold voltage or on-resistance to change when the semiconductor device 101 is turned on again, that is, a reverse bias problem will occur.

[0077] Figure 3 FIG1 is a structural diagram of another semiconductor device according to some embodiments. The semiconductor device 102 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 , a barrier layer 115 , a source 120 , a gate 131 , a cap layer 132 , a functional layer 150 , a conductive portion 160 , and a drain 140 .

[0078] The substrate 111, nucleation layer 112, buffer layer 113, channel layer 114 and barrier layer 115 are stacked in sequence. The source 120, gate 131 and drain 140 are respectively located on the side of the barrier layer 115 away from the substrate 111, and the gate 131 is located between the source 120 and drain 140.

[0079] The cap layer 132 is located on a side of the barrier layer 115 away from the substrate 111, and the gate 131 is located on a side of the cap layer 132 away from the substrate 111. Exemplarily, the material of the cap layer 132 includes P-type gallium nitride.

[0080] In some feasible embodiments, the material of the cap layer 132 includes magnesium-doped P-type gallium nitride, and the magnesium doping concentration is greater than 10 19 cm -3 .

[0081] In some feasible embodiments, the thickness of the cap layer 132 is greater than or equal to 30 nm and less than or equal to 200 nm. For example, the thickness of the cap layer 132 can be 30 nm, 50 nm, 70 nm, 90 nm, 110 nm, 130 nm, 150 nm, 170 nm, 190 nm, or 200 nm.

[0082] The functional layer 150 is located on the side of the barrier layer 115 away from the substrate 111 and between the gate 131 and the drain 140. The thickness of the functional layer 150 is less than that of the cap layer 132. Exemplarily, the material of the functional layer 150 includes P-type gallium nitride.

[0083] In some feasible embodiments, the material of the functional layer 150 includes magnesium-doped P-type gallium nitride, and the magnesium doping concentration is greater than 10 19 cm -3 .

[0084] In some feasible embodiments, the thickness of the functional layer 150 is greater than or equal to 5 nm.

[0085] In some feasible embodiments, the thickness of the functional layer 150 is thinner than the cap layer 132, and the thickness of the functional layer 150 is less than or equal to the difference between the thickness of the cap layer 132 and a predetermined thickness. For example, the predetermined thickness is 1 nm to 6 nm, that is, the predetermined thickness can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or 6 nm.

[0086] For example, if the thickness of the cap layer 132 is 30 nm, the thickness of the functional layer 150 is greater than or equal to 5 nm and less than or equal to 25 nm. For example, the thickness of the functional layer 150 is 5 nm, 10 nm, 15 nm, 20 nm, or 25 nm. If the thickness of the cap layer 132 is 200 nm, the thickness of the functional layer 150 is greater than or equal to 5 nm and less than or equal to 195 nm. For example, the thickness of the functional layer 150 is 5 nm, 20 nm, 30 nm, 40 nm, 50 nm, 100 nm, 150 nm, or 195 nm.

[0087] In the semiconductor device 102 , the functional layer 150 is connected to the drain 140 . The functional layer 150 is used to inject holes into the passivation interface formed by the barrier layer 115 and the passivation layer 116 , the barrier layer 115 , and the buffer layer 113 , which can significantly enhance the dynamic resistance stability of the semiconductor device 102 .

[0088] The conductive portion 160 is located on a side of the functional layer 150 away from the substrate 111 , and is connected to the drain electrode 140 . A gap exists between the conductive portion 160 and the functional layer 150 and the drain electrode 140 .

[0089] In some feasible embodiments, the conductive portion 160 and the gate 131 are made of the same material and are disposed in the same layer.

[0090] In some feasible embodiments, the material of the conductive portion 160 includes a metal having a work function greater than or equal to 4.8 electron volts. The material of the conductive portion 160 includes, for example, at least one of palladium, nickel, aluminum, gold, platinum, titanium, and titanium nitride. Here, "at least one" refers to a combination of one or more. Exemplarily, the material of the conductive portion 160 is palladium, nickel, aluminum, gold, platinum, titanium, titanium nitride, a combination of palladium and nickel, a combination of gold and platinum, a combination of palladium, nickel, and gold, etc.

[0091] Using a metal with a work function greater than or equal to 4.8 electron volts as the conductive portion 160 can enable the conductive portion 160 to form a near-ohmic contact with the functional layer 150 , effectively improving the hole injection efficiency of the functional layer 150 .

[0092] In some feasible embodiments, the semiconductor device 101 further includes a passivation layer 116 , which is located on a side of the barrier layer 115 away from the substrate 111 , and the source 120 , the cap layer 132 , the functional layer 150 and the drain 140 penetrate the passivation layer 116 and contact the barrier layer 115 .

[0093] Because functional layer 150 is thinner than cap layer 132, the two-dimensional electron gas (2DEG) is still present beneath functional layer 150, thereby reducing the forward voltage drop of the PIN junction at that location. This allows semiconductor device 102 to effectively inject holes in both soft-switching mode and off-state stress, thereby improving the dynamic characteristics of semiconductor device 102. Furthermore, functional layer 150 helps increase the injection efficiency of the PIN junction, thereby enhancing the dynamic reliability of the device.

[0094] In some feasible embodiments, the functional layer 150 and the two-dimensional electron gas 301 in the channel layer 114 form a PN junction.

[0095] In some feasible embodiments, the functional layer 150 , the barrier layer 115 , and the two-dimensional electron gas 301 in the channel layer 114 form a PIN junction.

[0096] When the semiconductor device 102 is in the off mode, the high electric field on the drain 140 side causes the body electron traps 211 and the interface state traps 212 to be occupied by electrons. At the same time, in the semiconductor device 102 provided in the embodiment of the present application, the PIN junction formed by the functional layer 150, the barrier layer 115 and the two-dimensional electron gas 301 is forward biased, and holes are injected into the passivation interface formed by the barrier layer 115 and the passivation layer 116, the barrier layer 115, the buffer layer 113 and other regions. The injected holes recombine with the electrons captured by the body electron traps 211 and / or recombine with the electrons captured by the interface state traps 212, thereby reducing the changes in the threshold voltage and on-resistance when the semiconductor device 102 is reopened.

[0097] When the semiconductor device 102 is in an operating mode, for example, a hard switching operating mode, channel hot electrons are emitted and captured by the body electron traps 211 and the interface state traps 212. In the semiconductor device 102 of the embodiment of the present application, the PIN junction formed by the functional layer 150, the barrier layer 115 and the two-dimensional electron gas 301 is forward biased, and holes are injected into the passivation interface formed by the barrier layer 115 and the passivation layer 116, the barrier layer 115, the buffer layer 113 and other regions. The injected holes recombine with the electrons captured by the body electron traps 211 and / or recombine with the electrons captured by the interface state traps 212, thereby reducing the amount of negative fixed charge and thus reducing the on-resistance of the semiconductor device 102.

[0098] Figure 4 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments. Figure 5 is a partial flow chart of a method for manufacturing a semiconductor device according to some embodiments. Figures 6 to 8 for Figure 4 A structural diagram of a semiconductor device in the provided preparation method.

[0099] The method for manufacturing a semiconductor device includes steps S10 to S50.

[0100] In step S10, an epitaxial layer, a barrier layer 115 and an initial cap layer 220 are sequentially formed on the substrate 111. For example, the epitaxial layer includes a buffer layer 113 and a channel layer 114, and the following is obtained: Figure 6 The semiconductor structure shown.

[0101] In some feasible embodiments, step S10 includes sequentially forming a nucleation layer 112 , an epitaxial layer, a barrier layer 115 and an initial cap layer 220 on the substrate, wherein the epitaxial layer includes a buffer layer 113 and a channel layer 114 .

[0102] In step S20, the initial cap layer 220 is etched to form a cap layer 132 and an initial functional layer 230, as shown in FIG. Figure 7 The semiconductor structure shown.

[0103] In step S30 , the initial functional layer 230 is thinned to form the functional layer 150 .

[0104] In some feasible embodiments, step S30 includes step S31 and step S32, such as Figure 5 shown.

[0105] In step S31, a mask layer is formed, which exposes the initial functional layer 230, as well as the source contact region 240 and the drain contact region 350 of the barrier layer 115. Exemplarily, a mask layer is formed on a side of the cap layer 132 away from the substrate 111, which exposes the initial functional layer 230, the source contact region 240, and the drain contact region 250.

[0106] In step S32, the initial functional layer 230 is etched through the mask layer to obtain the functional layer 150, and the barrier layer 115 is etched through the mask layer to obtain the source contact region 240 and the drain contact region 250. Figure 8 The semiconductor structure shown.

[0107] In this embodiment, the etching of the initial functional layer 230 , the source contact region 240 , and the drain contact region 250 is performed simultaneously, which can simplify the process and reduce production costs.

[0108] In step S40 , a source 120 and a drain 140 are formed on a side of the barrier layer 115 away from the substrate 111 . The source 120 and the drain 140 are located on opposite sides of the cap layer 132 , respectively. The drain 140 and the functional layer 150 are located on the same side of the cap layer 132 .

[0109] In some feasible embodiments, the conductive portion 160 is formed on a side of the functional layer 150 away from the substrate 111 .

[0110] In some feasible embodiments, the conductive portion 160 and the drain electrode 140 are made of the same material and are disposed in the same layer.

[0111] In some feasible embodiments, the conductive portion 160 and the gate 131 are made of the same material and are disposed in the same layer.

[0112] In step S50 , a gate 131 is formed on a side of the cap layer 132 away from the substrate 111 .

[0113] In some feasible embodiments, after step S50, the conductive portion and the drain electrode 140 are connected to obtain the following Figure 3 A semiconductor device 102 is shown.

[0114] This application also provides another method for preparing a semiconductor device, see Figure 4 and Figure 9 , Figure 9 This is a partial flow chart of another method for fabricating a semiconductor device according to some embodiments. The method provided in this embodiment further includes step S60, which is performed, for example, after step S20 and before step S30. Steps S10, S20, S40, and S50 are substantially the same as those in the previous embodiment and are therefore not further described.

[0115] Step S60 includes step S61 and step S62, and step S30 includes step S31 and step S32, see Figure 9 .

[0116] In step S61 , a second mask layer is formed, where the second mask layer exposes the source contact region 240 and the drain contact region 250 of the barrier layer 115 .

[0117] In step S62 , the barrier layer 115 is etched through the second mask layer.

[0118] In step S31 , a first mask layer is formed, where the first mask layer exposes the initial functional layer 230 .

[0119] In step S32 , the initial functional layer 230 is etched through the first mask layer. Exemplarily, the initial functional layer 230 is etched through the first mask layer to form the functional layer 150 .

[0120] In this embodiment, the source contact region 240 and the drain contact region 250 can be first defined by photolithography, and then the barrier layer 115 can be etched. After completion, the region of the initial functional layer 230 that needs to be thinned can be further defined by photolithography, and the initial functional layer 230 can be thinned to form the functional layer 150. The etching of the source contact region 240 and the drain contact region 250 is performed in steps with the etching of the functional layer 150, which can more accurately control the thickness of the functional layer 150 and improve the hole injection efficiency of the functional layer 150, thereby enabling the semiconductor device 102 to have a lower turn-on voltage and on-resistance.

[0121] In some feasible embodiments, the material of the conductive portion 160 is different from that of the gate 131 and the drain 140. That is, the source contact region 240 and the drain contact region 250 are first defined by photolithography, and then the barrier layer 115 is etched. After completion, the region of the initial functional layer 230 that needs to be thinned is defined by photolithography, and the initial functional layer 230 is thinned to form the functional layer 150. After the functional layer 150 is formed, the conductive portion 160 is formed on the side of the functional layer 150 away from the substrate 111.

[0122] In this embodiment, a process is added to form the conductive portion 160 , and different types of metals and different manufacturing processes can be selected according to actual needs, so that the contact of the functional layer 150 is an ohmic contact, thereby improving the hole injection efficiency of the functional layer 150 , thereby making the semiconductor device 102 have a lower turn-on voltage and on-resistance.

[0123] Figure 10 for Figure 3 The magnesium doping concentration-depth curve of the semiconductor device shown. Figure 10 In the figure, the horizontal axis is the depth in nanometers, with the surface of the cap layer 132 away from the substrate 111 as the starting point of 0 nm, and the vertical axis is the magnesium doping concentration in cm -3 The dotted line is the doping curve of the cap layer 132, and the dotted line is the doping curve of the functional layer 150. Figure 3 、 Figure 6 and Figure 7 The semiconductor device provided by this application is described. Due to the memory effect of magnesium and the diffusion problem during the activation process, Figure 6 The magnesium distribution of the initial cap layer 220 is non-uniform from the surface of the initial cap layer 220 away from the substrate 111 to the surface of the initial cap layer 220 close to the substrate 111, for example, approximately Gaussian distribution. Therefore, by thinning the thickness of the initial functional layer 230 to form the functional layer 150, the hole concentration in the functional layer 150 can be equivalently reduced, thereby shrinking the depletion region. The equivalent hole concentration can be Figure 10 The curve is integrated. Figure 3 As shown, since the thickness of the functional layer 150 is thinner than that of the cap layer 132 , the equivalent hole concentration of the functional layer 150 is also lower than that of the cap layer 132 , and the two-dimensional electron gas below the functional layer 150 is restored, thereby reducing the turn-on voltage of the semiconductor device 102 and increasing its hole injection current.

[0124] In some feasible embodiments, the magnesium distribution of the initial cap layer 220 may also be uniform.

[0125] Figure 11 The graph is a source-drain voltage-drain current curve of a semiconductor device with different magnesium equivalent doping concentrations in the functional layer. Figure 11 The horizontal axis is the source-drain voltage VDS , in volts, the vertical axis is the drain current I D , where the drain current ID is normalized and the unit is au (Arbitrary unit). Since the thickness of the functional layer 150 is correlated with its magnesium equivalent doping concentration, Figure 11 The magnesium equivalent doping concentration of the functional layer 150 is tested to obtain the source-drain voltage and drain current curves under different magnesium equivalent doping concentrations. The square dotted line is the voltage-current curve when the magnesium equivalent doping concentration of the functional layer 150 is equal to that of the cap layer 132, and the smooth curves are respectively when the magnesium equivalent doping concentration of the functional layer 150 is 5*10 18 cm -3 , 4*10 18 cm -3 、3*10 18 cm -3 and 2*10 18 cm -3 Voltage-current curve when .

[0126] Depend on Figure 11 It can be seen that when the thickness of the functional layer 150 is the same as that of the cap layer 132, the semiconductor device 102 has an obvious turn-on voltage. As the functional layer 150 gradually becomes thinner, the depletion effect of the functional layer 150 on the two-dimensional electron gas thereunder is weakened, and the turn-on voltage of the semiconductor device 102 decreases accordingly.

[0127] Figure 12 The voltage-hole injection current curve of semiconductor devices with functional layers of different thicknesses. Figure 12 The horizontal axis is the injected voltage V PD , that is, the voltage drop between the functional layer 150 and the two-dimensional electron gas 301, where the injection voltage V PD Normalized, the unit is au. The vertical axis is the hole injection current I PD , where the hole injection current I PD The normalized values ​​are in au. The dotted dashed line represents the voltage-hole injection current curve when the thickness of the functional layer 150 is equal to 1323 nm, and the smooth curves represent the voltage-hole injection current curves when the thickness of the functional layer 150 is 5 nm, 20 nm, 30 nm, and 40 nm, respectively.

[0128] Depend on Figure 10 As can be seen, after thinning the functional layer 150, the two-dimensional electron gas beneath it recovers, and the forward turn-on voltage of the PN junction decreases as the thickness of the functional layer 150 decreases. Furthermore, thinning the functional layer 150 reduces the intrinsic series resistance of P-type gallium nitride, meaning that the PN junction distributes more voltage drop, making it easier to turn on.

[0129] In some possible embodiments, when the thickness of the functional layer 150 is 5 nm, the hole injection current of the semiconductor device 102 is 31 times that of the semiconductor device 101 when the injection voltage V PD = 4 V. Figure 2

[0130] In some possible embodiments, when the injection voltage V PD > 5 V, the hole injection current of the semiconductor device 102 is 6 times that of the semiconductor device 101. Figure 2

[0131] Figure 13 A structure diagram of yet another semiconductor device provided according to some embodiments. Figure 14 A top view of a semiconductor device. Figure 13 The semiconductor device 103 includes a substrate 111, a nucleation layer 112, a buffer layer 113, a channel layer 114, a barrier layer 115, a source 120, a gate 131, a cap layer 132, a functional layer 150, and a drain 140.

[0132] The substrate 111, the nucleation layer 112, the buffer layer 113, the channel layer 114, and the barrier layer 115 are sequentially stacked. The source 120, the gate 131, and the drain 140 are located on a side of the barrier layer 115 away from the substrate 111, and the gate 131 is located between the source 120 and the drain 140.

[0133] The cap layer 132 is located on a side of the barrier layer 115 away from the substrate 111, and the gate 131 is located on a side of the cap layer 132 away from the substrate 111.

[0134] The functional layer 150 is located on a side of the barrier layer 115 away from the substrate 111, and between the gate 131 and the drain 140. The thickness of the functional layer 150 is less than the thickness of the cap layer 132.

[0135] In some possible embodiments, the thickness of the functional layer 150 is greater than or equal to 5 nm.

[0136] In some possible embodiments, the thickness of the functional layer 150 is less than the thickness of the cap layer 132, and the thickness of the functional layer 150 is less than or equal to the difference between the thickness of the cap layer 132 and a preset thickness. For example, the preset thickness is 4 nm to 6 nm, i.e., the preset thickness can be 4 nm, 5 nm, or 6 nm, etc.

[0137] In this embodiment, the drain 140 covers at least a side of the functional layer 150 away from the gate 131.

[0138] In some possible embodiments, the drain 140 also covers at least part of a surface of the functional layer 150 away from the substrate 111.

[0139] Referring to​​ Figure 14 , it can be seen that the functional layer 150 is in the shape of a continuous strip.

[0140] In some possible embodiments, such as Figure 15 As shown, Figure 15 for Figure 13 Another top view of the semiconductor device in FIG. The functional layer 150 includes a plurality of sub-functional layers 151. For example, the number of sub-functional layers 151 is four. In some feasible embodiments, the number of sub-functional layers 151 may be two, three, five, or six.

[0141] The sub-functional layers 151 are arranged at intervals along a first direction x. The first direction x is parallel to the substrate 111 and perpendicular to the arrangement direction of the source 120 , the gate 131 and the drain 140 .

[0142] In some feasible embodiments, in an orthographic projection onto the substrate 111 , the shape of the sub-functional layer 151 is selected from any one of a rectangle, a circle, a triangle, a diamond, and a star.

[0143] Figure 16 FIG1 is a structural diagram of another semiconductor device according to some embodiments. The semiconductor device 104 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 , a barrier layer 115 , a source 120 , a gate 131 , a cap layer 132 , a functional layer 150 , and a drain 140 .

[0144] The substrate 111, nucleation layer 112, buffer layer 113, channel layer 114 and barrier layer 115 are stacked in sequence. The source 120, gate 131 and drain 140 are respectively located on the side of the barrier layer 115 away from the substrate 111, and the gate 131 is located between the source 120 and drain 140.

[0145] The cap layer 132 is located on a side of the barrier layer 115 away from the substrate 111 , and the gate 131 is located on a side of the cap layer 132 away from the substrate 111 .

[0146] The functional layer 150 is located on a side of the barrier layer 115 away from the substrate 111 and between the gate 131 and the drain 140 . The thickness of the functional layer 150 is smaller than that of the cap layer 132 .

[0147] In some feasible embodiments, the thickness of the functional layer 150 is greater than or equal to 5 nm.

[0148] In some feasible embodiments, the thickness of the functional layer 150 is thinner than the cap layer 132, and the thickness of the functional layer 150 is less than or equal to the difference between the thickness of the cap layer 132 and a predetermined thickness. For example, the predetermined thickness is 4 nm to 6 nm, that is, the predetermined thickness can be 4 nm, 5 nm, or 6 nm.

[0149] In this embodiment, the drain electrode 140 at least covers the side surface of the functional layer 150 away from the gate 131 , the surface of the functional layer 150 away from the substrate 111 , and the side surface of the functional layer 150 close to the gate 131 .

[0150] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; an epitaxial layer and a barrier layer stacked on the substrate, wherein the barrier layer is farther away from the substrate than the epitaxial layer; a gate, located on a side of the barrier layer away from the substrate; a cap layer, located between the barrier layer and the gate; a source electrode and a drain electrode, located on a side of the barrier layer away from the substrate and respectively located on two opposite sides of the gate; A functional layer is located on a side of the barrier layer away from the substrate; the functional layer and the drain are located on the same side of the gate, and the functional layer and the drain are connected; the thickness of the functional layer is less than the thickness of the cap layer; the thickness of the functional layer is less than or equal to the difference between the thickness of the cap layer and a preset thickness, and the preset thickness is 1 nanometer to 6 nanometers.

2. The semiconductor device according to claim 1, wherein , the thickness of the functional layer is greater than or equal to 5 nanometers.

3. The semiconductor device according to claim 1, wherein The material of the functional layer includes P-type gallium nitride.

4. The semiconductor device according to claim 1, wherein The functional layer and the cap layer are made of the same material and are arranged on the same layer.

5. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a conductive portion disposed on a side of the functional layer away from the substrate, wherein both the functional layer and the conductive portion are spaced apart from the drain electrode; The conductive portion is connected to the drain electrode.

6. The semiconductor device according to claim 5, wherein The conductive portion is made of the same material as the gate.

7. The semiconductor device according to claim 5, wherein The conductive portion is made of a metal having a work function greater than or equal to 4.8 electron volts.

8. The semiconductor device according to claim 7, wherein: The material of the conductive portion includes at least one of palladium, nickel, aluminum, gold, platinum, titanium, and titanium nitride.

9. The semiconductor device according to claim 1, wherein The drain electrode at least covers a side surface of the functional layer away from the gate.

10. The semiconductor device according to claim 9, wherein The drain electrode also covers at least a portion of the surface of the functional layer away from the substrate.

11. The semiconductor device according to claim 10, wherein: The drain electrode also covers a side surface of the functional layer close to the gate.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that The functional layer includes at least two sub-functional layers spaced apart from each other, and the at least two sub-functional layers are arranged along a first direction; The first direction is parallel to the substrate and perpendicular to an arrangement direction of the source, the gate, and the drain.

13. The semiconductor device according to claim 12, wherein: In an orthographic projection onto the substrate, the sub-functional layer has a shape selected from any one of a rectangle, a circle, a triangle, a diamond, and a star.

14. The semiconductor device according to any one of claims 1 to 11, characterized in that Also includes: a passivation layer, the passivation layer being located on a side of the barrier layer away from the substrate; The source electrode, the cap layer, the functional layer, and the drain electrode respectively penetrate the passivation layer and contact the barrier layer.

15. A chip, characterized in that: The invention comprises a package substrate and the semiconductor device according to any one of claims 1 to 14, wherein the package substrate is coupled to the semiconductor device.

16. An electronic device, characterized in that: The device comprises a circuit board and the chip as claimed in claim 15, wherein the chip is arranged on the circuit board.

17. A method for preparing a semiconductor device, characterized in that: include: forming an epitaxial layer, a barrier layer and an initial cap layer on the substrate in sequence; etching the initial cap layer to form a cap layer and an initial functional layer; Thinning the initial functional layer to form a functional layer; the thickness of the functional layer is less than or equal to the difference between the thickness of the cap layer and a preset thickness, and the preset thickness is 1 nanometer to 6 nanometers; forming a source electrode and a drain electrode on a side of the barrier layer away from the substrate; the source electrode and the drain electrode are respectively located on opposite sides of the cap layer, and the drain electrode and the functional layer are located on the same side of the cap layer; A gate is formed on a side of the cap layer away from the substrate.

18. The preparation method according to claim 17, characterized in that: The thinning of the initial functional layer to form a functional layer comprises: forming a mask layer, wherein the mask layer exposes the initial functional layer, and the source contact region and the drain contact region of the barrier layer; The initial functional layer and the barrier layer are etched through the mask layer.

19. The preparation method according to claim 17, characterized in that The thinning of the initial functional layer to form a functional layer comprises: forming a first mask layer, wherein the first mask layer exposes the initial functional layer; etching the initial functional layer through the first mask layer; Before forming the source and drain, the preparation method further includes: forming a second mask layer, wherein the second mask layer exposes the source contact region and the drain contact region of the barrier layer; The barrier layer is etched through the second mask layer.

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