Semiconductor device

Abstract

Provided is a semiconductor device capable of suppressing electric field concentration of an FP electrode. The semiconductor device includes first to fourth electrodes, first to third semiconductor regions, and first and second insulating portions. The first semiconductor region is arranged on the first electrode. The second semiconductor region is arranged on the first semiconductor region. The third semiconductor region is selectively disposed on the second semiconductor region. The second electrode is arranged on the third semiconductor region. The third electrode and the second semiconductor region are arranged. The first insulating portion is provided between the second semiconductor region and the third electrode. The fourth electrode is arranged with the first and second semiconductor regions. The second insulating portion is provided between the first and second semiconductor regions and the fourth electrode. The second insulating portion has first and second insulating regions. The first insulating region surrounds the fourth electrode and is in contact with the fourth electrode. The second insulating region surrounds the first insulating region and is in contact with the first insulating region. The dielectric constant of the second insulating region is lower than that of the first insulating region.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] In order to improve the withstand voltage or reduce the on-resistance, there is known a semiconductor device including a dot-shaped field plate electrode (hereinafter referred to as "FP electrode") This semiconductor device is required to suppress the concentration of the electric field in the FP electrode.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent No. 9722036 Summary of the invention

[0006] Technical problem that the invention will solve

[0007] The technical problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the concentration of the electric field in the FP electrode.

[0008] Means for solving technical problems

[0009] A semiconductor device of an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a second electrode, a third electrode, a first insulating portion, a fourth electrode, and a second insulating portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is selectively provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode is arranged with the second semiconductor region in a second direction and a third direction. The second direction is perpendicular to the first direction from the first semiconductor region toward the second semiconductor region. The third direction is perpendicular to the first direction and intersects with the second direction. The first insulating portion is provided between the second semiconductor region and the third electrode in the second direction and the third direction. The fourth electrode is arranged with the first semiconductor region and the second semiconductor region in the second direction and the third direction. The second insulating portion is provided between the first semiconductor region and the fourth electrode and between the second semiconductor region and the fourth electrode in the second direction and the third direction. The second insulating portion has a first insulating region and a second insulating region. The first insulating region surrounds the fourth electrode and is in contact with the fourth electrode. The second insulating region surrounds the first insulating region and is in contact with the first insulating region. The dielectric constant of the first insulating region is lower than the dielectric constant of the second insulating region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a top view showing a semiconductor device according to an embodiment.

[0011] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0012] Figure 3 is a graph illustrating the characteristics of a semiconductor device according to a reference example. DETAILED DESCRIPTION

[0013] Hereinafter, each embodiment will be described with reference to the accompanying drawings. In addition, the accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. In addition, even when representing the same part, there are cases where the mutual dimensions and ratios are represented differently according to the accompanying drawings. Moreover, in this specification and each figure, the same reference numerals are marked for the same elements as those described in the figures that have appeared, and the detailed description is appropriately omitted.

[0014] In addition, for the sake of ease of explanation, the following describes the configuration and structure of each part using an XYZ orthogonal coordinate system. The X-axis, Y-axis, and Z-axis are orthogonal to each other. In addition, the direction in which the X-axis extends is referred to as the "X direction", the direction in which the Y-axis extends is referred to as the "Y direction", and the direction in which the Z-axis extends is referred to as the "Z direction". In addition, for the sake of ease of explanation, the direction of the arrow in the Z direction is referred to as upward, and the opposite direction thereof is referred to as downward, but these directions have nothing to do with the direction of gravity. Observation from above is referred to as "looking down".

[0015] In addition, the following expressions of + and - indicate the relative high and low of the impurity concentration in each conductivity type. Specifically, the expression marked with "+" indicates that the impurity concentration is higher than the expression without "+" and "-". The expression marked with "-" indicates that the impurity concentration is lower than the expression without "+" and "-". Here, in the case where each region contains both impurities that serve as donors and impurities that serve as acceptors, "impurity concentration" indicates the net impurity concentration after these impurities are offset.

[0016] Figure 1 It is a top view showing a semiconductor device according to an embodiment.

[0017] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0018] Figure 2 yes Figure 1 The cross-sectional view along line II-II is shown.

[0019] like Figure 1 as well as Figure 2 As shown, the semiconductor device 100 of the embodiment is, for example, a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 100 is a MOSFET having dot-shaped FP electrodes and a trench-shaped gate electrode between the FP electrodes.

[0020] The semiconductor device 100 includes a drain electrode 11 (first electrode), a source electrode 12 (second electrode), a gate electrode 13 (third electrode), an FP electrode 14 (fourth electrode), a gate pad 15, and a gate electrode 16. － type drift region 21 (first semiconductor region), p-type base region 22 (second semiconductor region), n + type source region 23 (third semiconductor region), n + The first conductivity type is the n-type and the second conductivity type is the p-type.

[0021] Hereinafter, the direction from the first electrode 11 toward the second electrode 12 is referred to as the first direction. In addition, the direction perpendicular to the first direction is referred to as the second direction. In addition, the direction perpendicular to the first direction and intersecting the second direction is referred to as the third direction. The first direction is, for example, the Z direction. The second direction is, for example, the X direction. The third direction is, for example, the Y direction.

[0022] A drain electrode 11 is provided at the bottom of the semiconductor device 100. + The type drain region 24 has an n － Type drift region 21. － The drift region 21 is connected to n + The type drain region 24 is electrically connected to the drain electrode 11. － A p-type base region 22 is provided on the p-type drift region 21. An n-type base region 22 is selectively provided on the p-type base region 22. + In this example, an n-type source region 23 is provided on a portion of the p-type base region 22. + The p-type source region 23 is not provided on the other part of the p-type base region 22. + Type source region 23. + The p-type source region 23 is aligned with the p-type base region 22 in the X direction and the Y direction. + The source electrode 12 is disposed on the p-type source region 23. The source electrode 12 and the p-type base region 22 and the n-type base region 23 are connected to each other. + The type source region 23 is electrically connected. Figure 1 , a top view is shown in a state where the source electrode 12 is removed.

[0023] The gate electrode 13 is aligned with the p-type base region 22 in the X direction and the Y direction. In this example, a portion of the gate electrode 13 is aligned with the n-type base region 22 in the X direction and the Y direction. － In this example, a portion of the gate electrode 13 is aligned with the n type drift region 21 in the X direction and the Y direction. + A portion of the type source region 23 is arranged.

[0024] The gate insulating portion 31 is provided between the gate electrode 13 and the p-type base region 22 in the X direction and the Y direction. In this example, a portion of the gate insulating portion 31 is provided between the gate electrode 13 and the p-type base region 22 in the X direction and the Y direction. － In this example, a portion of the gate insulating portion 31 is provided between the gate electrode 13 and the n-type drift region 21 in the X direction and the Y direction. + In this example, a portion of the gate insulating portion 31 is provided between the gate electrode 13 and the n-type source region 23 in the Z direction. －In this example, a portion of the gate insulating portion 31 is provided between the gate electrode 13 and the source electrode 12 in the Z direction. In this way, the gate electrode 13 is surrounded by the gate insulating portion 31. The gate electrode 13 is provided inside the gate insulating portion 31.

[0025] The gate electrode 13 is electrically connected to the gate pad 15. The gate pad 15 is electrically isolated from the source electrode 12. The gate electrode 13 may be electrically connected to the gate pad 15 via a gate wiring layer (not shown).

[0026] The FP electrode 14 is connected to the n electrode in the X direction and the Y direction. － The p-type drift region 21 and the p-type base region 22 are arranged. In this example, a portion of the FP electrode 14 is aligned with the n-type base region 22 in the X direction and the Y direction. + A portion of the type source region 23 is arranged.

[0027] The FP insulating portion 32 is provided between the FP electrode 14 and the n-type electrode 14 in the X direction and the Y direction. － The FP insulating portion 32 is provided between the FP electrode 14 and the p-type drift region 21 and between the FP electrode 14 and the p-type base region 22. In this example, a portion of the FP insulating portion 32 is provided between the FP electrode 14 and the n-type drift region 21 in the Z direction. － The FP electrode 14 is surrounded by the FP insulating portion 32. The FP electrode 14 is provided inside the FP insulating portion 32. The FP electrode 14 is electrically connected to the source electrode 12.

[0028] The FP insulating portion 32 includes a first insulating region 32a and a second insulating region 32b. The first insulating region 32a surrounds the FP electrode 14 on the XY plane. The first insulating region 32a is in contact with the FP electrode 14. The second insulating region 32b surrounds the first insulating region 32a on the XY plane. The second insulating region 32b is in contact with the first insulating region 32a. The first insulating region 32a is provided between the FP electrode 14 and the second insulating region 32b. The first insulating region 32a is provided inside the second insulating region 32b, and the FP electrode 14 is provided inside the first insulating region 32a.

[0029] The dielectric constant of the second insulating region 32b is lower than the dielectric constant of the first insulating region 32a. The dielectric constant of the second insulating region 32b relative to the dielectric constant of the first insulating region 32a is 1 / 2 or more and 4 / 5 or less. The dielectric constant of the first insulating region 32a is constant, for example, inside the first insulating region 32a. The dielectric constant of the second insulating region 32b is constant, for example, inside the second insulating region 32b. That is, the dielectric constant of the FP insulating portion 32 increases, for example, as the dielectric constant increases from the FP electrode 14 toward the n － The p-type drift region 21 or the p-type base region 22 becomes lower intermittently.

[0030] The thickness of the first insulating region 32a and the thickness of the second insulating region 32b are, for example, thicker than the thickness of the natural oxide film (eg, about 1 nm). The thickness of the second insulating region 32b is, for example, 0.1 to 10 times the thickness of the first insulating region 32a.

[0031] The thickness of the first insulating region 32a is represented by, for example, the average value of the length of the first insulating region 32a in the X direction, the length of the first insulating region 32a in the Y direction, and the length of the first insulating region 32a in the Z direction. The length of the first insulating region 32a in the X direction, the length of the first insulating region 32a in the Y direction, and the length of the first insulating region 32a in the Z direction are, for example, the same. That is, the thickness of the first insulating region 32a is, for example, uniform.

[0032] The thickness of the second insulating region 32b is represented by, for example, the average value of the length of the second insulating region 32b in the X direction, the length of the second insulating region 32b in the Y direction, and the length of the second insulating region 32b in the Z direction. The length of the second insulating region 32b in the X direction, the length of the second insulating region 32b in the Y direction, and the length of the second insulating region 32b in the Z direction are, for example, the same. That is, the thickness of the second insulating region 32b is, for example, uniform.

[0033] The FP insulating portion 32 may also include another insulating region surrounding the second insulating region 32b and connected to the second insulating region 32b. In this case, the dielectric constant of the other insulating region is preferably lower than the dielectric constant of the second insulating region 32b. The other insulating region may also include a plurality of layers having different dielectric constants. In this case, the dielectric constants of the plurality of layers preferably increase as the dielectric constant increases from the second insulating region 32b toward the n － The p-type drift region 21 or the p-type base region 22 becomes lower.

[0034] The dielectric constant of the FP insulating portion 32 may also be increased as the distance from the FP electrode 14 toward the n － When the dielectric constant is continuously reduced, the inner region of the FP insulating portion 32 that is in contact with the FP electrode 14 can be regarded as the first insulating region 32a, and the inner region of the FP insulating portion 32 that is in contact with the n-type drift region 21 or the p-type base region 22 can be regarded as the first insulating region 32a. －The outer area where the FP insulating portion 32 is connected to the p-type drift region 21 or the p-type base region 22 is regarded as the second insulating region 32b. The thickness of the first insulating region 32a is the same as the thickness of the second insulating region 32b. The dielectric constant at the center of the thickness direction of the first insulating region 32a can be regarded as the dielectric constant of the first insulating region 32a. The dielectric constant at the center of the thickness direction of the second insulating region 32b can be regarded as the dielectric constant of the second insulating region 32b. The dielectric constant of the FP insulating portion 32 is preferably, for example, reduced in inverse proportion to the distance from the FP electrode 14. In addition, the rate of change of the dielectric constant in the FP insulating portion 32 is preferably, for example, such that the intensity of the electric field in the FP insulating portion 32 is constant.

[0035] For example, the FP insulating portion 32 includes a first material and a second material with a lower dielectric constant than the first material. The ratio of the second material to the first material increases as the distance from the FP electrode 14 toward the n － The p-type drift region 21 or the p-type base region 22 increases, so that the dielectric constant of the FP insulating portion 32 can be increased as it moves from the FP electrode 14 toward the n-type drift region 21 or the p-type base region 22. － The first material is, for example, the same as the material of the first insulating region 32a described later. The second material is, for example, the same as the material of the second insulating region 32b described later.

[0036] The FP electrode 14 is surrounded by the first insulating region 32a in a plan view. The first insulating region 32a is surrounded by the second insulating region 32b in a plan view. The second insulating region 32b is surrounded by the p-type base region 22 in a plan view. + The type source region 23 is surrounded. + The type source region 23 is surrounded by the gate insulating portion 31 in a plan view. The gate electrode 13 is provided along between the gate insulating portions 31 in a plan view.

[0037] A plurality of FP electrodes 14 are provided in a plan view. In this example, the FP electrodes 14 are arranged in an equilateral triangle shape in a plan view. The FP electrodes 14 may be arranged in a quadrilateral shape in a plan view, for example.

[0038] In this example, the shapes of the FP electrode 14 and the FP insulating portion 32 when viewed from above are circular. The shapes of the FP electrode 14 and the FP insulating portion 32 when viewed from above are not limited thereto, and may be polygonal shapes such as triangles, quadrilaterals, or hexagons. + The shape of the n-type source region 23 is a hexagon. The gate insulating portion 31 and the n-type source region 23 are hexagonal in plan view. + The shape of the source region 23 is not limited thereto, and may be, for example, a polygon such as a triangle or a quadrilateral, or may be a circle.

[0039] An example of the material of each component of the semiconductor device 100 is described.

[0040] The drain electrode 11, the source electrode 12 and the gate pad 15 are made of metal such as aluminum or copper. The gate electrode 13 and the FP electrode 14 are made of a conductive material such as polysilicon. Impurities may be added to the conductive material.

[0041] n － type drift region 21, p-type base region 22, n + type source region 23 and n + The type drain region 24 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an impurity that serves as a donor, and boron can be used as an impurity that serves as an acceptor.

[0042] The gate insulating portion 31 and the FP insulating portion 32 include insulating materials. The gate insulating portion 31 includes, for example, silicon oxide (SiO). The first insulating region 32a of the FP insulating portion 32 includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and at least one of hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), and lanthanum oxide (LaO). The second insulating region 32b of the FP insulating portion 32 includes, for example, at least one of carbon-containing silicon oxide (SiOC) and silicon oxide (SiO). The silicon oxide (SiO) contained in the second insulating region 32b is preferably porous. The "porous" mentioned here refers to a state in which the original density and dielectric constant are reduced due to the material adopting a structure with multiple fine pores. In the case where the first insulating region 32a includes silicon nitride (SiN) or silicon oxynitride (SiON), the second insulating region 32b preferably includes silicon oxide (SiO). When the first insulating region 32 a includes silicon oxide (SiO), the second insulating region 32 b preferably includes, for example, silicon oxide containing carbon (SiOC).

[0043] The operation of the semiconductor device 100 will be described.

[0044] In a state where a positive voltage is applied to the drain electrode 11 relative to the source electrode 12, a voltage above the threshold is applied to the gate electrode 13. As a result, a channel (inversion layer) is formed in the p-type base region 22, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 12 to the drain electrode 11 through the channel. Thereafter, if the voltage applied to the gate electrode 13 becomes lower than the threshold, the channel in the p-type base region 22 disappears, and the semiconductor device 100 is turned off.

[0045] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 relative to the source electrode 12 increases. － The potential difference between the drift region 21 and the FP electrode 14 increases. Due to the increase in the potential difference, the depletion layer is formed from the FP insulating portion 32 and the n － The interface of the drift region 21 is oriented toward n － The type drift region 21 is expanded. Due to the expansion of the depletion layer, the withstand voltage of the semiconductor device 100 can be improved. Alternatively, the n type drift region 21 can be expanded while maintaining the withstand voltage of the semiconductor device 100. － The concentration of the impurities that serve as donors in the drift region 21 is reduced, thereby reducing the on-resistance of the semiconductor device 100 .

[0046] If the FP electrode 14 is provided, the electric field may be concentrated on the FP electrode 14, and the leakage current may increase. In addition, the reliability of the FP insulating portion 32 may be reduced by this.

[0047] In contrast, in the semiconductor device 100 of the embodiment, the FP insulating portion 32 surrounding the FP electrode 14 is configured as a multilayer structure including a first insulating region 32a and a second insulating region 32b, and the dielectric constant of the second insulating region 32b located on the outside is lower than the dielectric constant of the first insulating region 32a located on the inside. Thus, the intensity of the electric field in the first insulating region 32a can be reduced, and the concentration of the electric field in the FP electrode 14 can be suppressed. Therefore, it is possible to suppress the increase of the leakage current and improve the reliability of the FP insulating portion 32.

[0048] Figure 3 is a graph illustrating the characteristics of a semiconductor device according to a reference example.

[0049] Figure 3 The horizontal axis represents the position on the X-Y plane. Figure 3 The vertical axis represents the intensity of the electric field.

[0050] exist Figure 3 In the figure, the solid line represents the intensity of the electric field of the semiconductor device of reference example 1, the single-point chain line represents the intensity of the electric field of the semiconductor device of reference example 2, and the dotted line represents the intensity of the electric field of the semiconductor device of reference example 3.

[0051] The semiconductor device of Reference Example 1 Figure 3 The insulating region A has a first insulating region 32a at a position where Figure 3The second insulating region 32b is provided at the position of the insulating region B. The dielectric constant of the second insulating region 32b is lower than the dielectric constant of the first insulating region 32a. The relative dielectric constant of the first insulating region 32a of the semiconductor device of Reference Example 1 is 7.5. This is equivalent to the relative dielectric constant when the first insulating region 32a includes silicon nitride (SiN). The relative dielectric constant of the second insulating region 32b of the semiconductor device of Reference Example 1 is 3.9. This is equivalent to the relative dielectric constant when the second insulating region 32b includes silicon oxide (SiO).

[0052] When the charge density of the semiconductor region is denoted as ρ and the boundary position of the insulating region of the semiconductor region in the polar coordinate system is denoted as R Si , set the boundary position between the insulating region and the FP electrode in the polar coordinate system to R ox , set the dielectric constant of the insulating region to ε ox , set the dielectric constant of the semiconductor region to ε Si , when any position in the polar coordinate system is set to r, the electric field strength E of the insulating region at position r is ox and the electric field strength E in the semiconductor region Si It is represented by the following formula: The electric field intensity of Reference Example 1 complies with this formula.

[0053]

Mathematical formula 1

[0054]

[0055] The semiconductor device of Reference Example 2 Figure 3 The insulating region A has a first insulating region 32a at a position where Figure 3 The second insulating region 32b is provided at the position of the insulating region B. The dielectric constants of the insulating region A and the insulating region B decrease as the distance from the FP electrode 14 toward the semiconductor region (n － type drift region 21) and continuously decreases.

[0056] The semiconductor device of Reference Example 3 Figure 3 The first insulating region 32a is provided at the position of the insulating region A and the position of the insulating region B. That is, the semiconductor device of Reference Example 3 does not have the second insulating region 32b. The dielectric constant of the FP insulating portion 32 (first insulating region 32a) of the semiconductor device of Reference Example 3 is the same as the dielectric constant of the first insulating region 32a of the semiconductor device of Reference Example 1. In addition, the thickness of the FP insulating portion 32 of the semiconductor device of Reference Example 3 (the thickness of the first insulating region 32a) is the same as the thickness of the FP insulating portion 32 of the semiconductor devices of Reference Examples 1 and 2 (the sum of the thickness of the first insulating region 32a and the thickness of the second insulating region 32b).

[0057] like Figure 3As shown, in the semiconductor devices of reference examples 1 and 2 having the second insulating region 32b, the intensity of the electric field at the position of the insulating region B (i.e., the position where the second insulating region 32b is provided) becomes larger than that of the semiconductor device of reference example 3 not having the second insulating region 32b, and the intensity of the electric field at the position of the insulating region A (i.e., the position where the first insulating region 32a is provided) and the semiconductor region (n － The intensity of the electric field at the position of the type drift region 21) becomes smaller. Therefore, it is suggested that by providing the second insulating region 32b, the concentration of the electric field in the FP electrode 14 can be suppressed. In addition, in the semiconductor device of Reference Example 2, the change in the intensity of the electric field at the position of the insulating region A and the position of the insulating region B becomes smaller (for example, becomes constant) compared with the semiconductor device of Reference Example 1. Therefore, it is suggested that by making the dielectric constant of the second insulating portion 32 increase as it moves from the FP electrode 14 toward the semiconductor region (n － The type drift region 21) is continuously lowered, so that the concentration of the electric field in the FP electrode 14 can be further suppressed.

[0058] When the thickness of the first insulating region 32a is set to d1, the thickness of the second insulating region 32b is set to d2, and the semiconductor region (n － The thickness of the drift region 21 is set to d3, the relative dielectric constant of the first insulating region 32a is set to ε1, the relative dielectric constant of the second insulating region 32b is set to ε2, and the semiconductor region (n － When the relative dielectric constant of the drift region 21 is set to ε3, the intensity E1 of the electric field in the first insulating region 32a, the intensity E2 of the electric field in the second insulating region 32b, and the semiconductor region (n － The intensity E3 of the electric field in the type drift region 21) is expressed by the following formulas.

[0059]

Mathematical formula 2

[0060]

[0061]

[0062]

[0063] Thus, the above formula suggests that by setting the FP insulating portion 32 surrounding the FP electrode 14 to a multilayer structure including the first insulating region 32a and the second insulating region 32b, the dielectric constant of the second insulating region 32b located on the outside is lower than the dielectric constant of the first insulating region 32a located on the inside, thereby increasing the intensity of the electric field in the second insulating region 32b and reducing the first insulating region 32a and the semiconductor region (n － The strength of the electric field in the drift region 21).

[0064] The FP insulating portion 32 and the FP electrode 14 of the semiconductor device 100 of the embodiment can be formed, for example, in the following order. － A hole (through hole) is formed in the p-type drift region 21 and the p-type base region 22. Next, a second insulating region 32b is formed inside the hole by CVD (chemical vapor growth), coating, ALD (atomic layer deposition), thermal oxidation, etc. Next, a first insulating region 32a is formed inside the second insulating region 32b by CVD, coating, ALD, thermal oxidation, etc. Next, a FP electrode 14 is formed inside the first insulating region 32a by CVD, coating, ALD, thermal oxidation, etc. Thus, a FP insulating portion 32 having a first insulating region 32a and a second insulating region 32b can be formed.

[0065] The embodiment may include the following configurations.

[0066] (Composition 1)

[0067] A semiconductor device comprising:

[0068] a first electrode;

[0069] A first semiconductor region of a first conductivity type, disposed on the first electrode;

[0070] A second semiconductor region of a second conductivity type, disposed on the first semiconductor region;

[0071] The third semiconductor region of the first conductivity type is selectively disposed on the second semiconductor region;

[0072] A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region;

[0073] a third electrode arranged with the second semiconductor region in a second direction perpendicular to the first direction from the first electrode toward the second electrode and in a third direction perpendicular to the first direction and intersecting the second direction;

[0074] A first insulating portion is provided between the second semiconductor region and the third electrode in the second direction and the third direction;

[0075] a fourth electrode arranged with the first semiconductor region and the second semiconductor region in the second direction and the third direction; and

[0076] The second insulating portion is provided between the first semiconductor region and the fourth electrode and between the second semiconductor region and the fourth electrode in the second direction and the third direction.

[0077] The second insulating portion includes a first insulating region and a second insulating region, the first insulating region surrounds the fourth electrode and is in contact with the fourth electrode, the second insulating region surrounds the first insulating region and is in contact with the first insulating region,

[0078] The second insulating region has a lower dielectric constant than the first insulating region.

[0079] (Composition 2)

[0080] According to the semiconductor device of configuration 1, the first insulating region includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, and lanthanum oxide.

[0081] (Composition 3)

[0082] According to the semiconductor device according to configuration 1 or 2, the second insulating region includes at least one of carbon-containing silicon oxide and silicon oxide.

[0083] (Composition 4)

[0084] According to the semiconductor device of any one of Configurations 1 to 3, a thickness of the second insulating region is not less than 0.1 times and not more than 10 times a thickness of the first insulating region.

[0085] As described above, according to the embodiment, a semiconductor device capable of suppressing the concentration of the electric field in the FP electrode can be provided.

[0086] Several embodiments of the present invention are illustrated above, but these embodiments are proposed as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents. In addition, the aforementioned embodiments can be implemented in combination with each other.

[0087] Description of Reference Numerals

[0088] 11: Drain electrode (first electrode)

[0089] 12: Source electrode (second electrode)

[0090] 13: Gate electrode (third electrode)

[0091] 14: FP electrode (fourth electrode)

[0092] 15: Gate pad

[0093] 21:n －Type drift region (first semiconductor region)

[0094] 22: p-type base region (second semiconductor region)

[0095] 23:n + Type source region (third semiconductor region)

[0096] 24:n + Type drain region (fourth semiconductor region)

[0097] 31: Gate insulating portion (first insulating portion)

[0098] 32: FP insulating part (second insulating part)

[0099] 32a: First insulation area

[0100] 32b: Second insulation area

[0101] 100: Semiconductor devices

Claims

1. A semiconductor device, wherein: have: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode; A second semiconductor region of a second conductivity type, disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is selectively disposed on the second semiconductor region; A second electrode, disposed on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode arranged with the second semiconductor region in a second direction and a third direction, wherein the second direction is a direction perpendicular to the first direction from the first electrode toward the second electrode, and the third direction is a direction perpendicular to the first direction and intersecting the second direction; A first insulating portion is provided between the second semiconductor region and the third electrode in the second direction and the third direction; a fourth electrode, arranged with the first semiconductor region and the second semiconductor region in the second direction and the third direction; as well as The second insulating portion is provided between the first semiconductor region and the fourth electrode and between the second semiconductor region and the fourth electrode in the second direction and the third direction. The second insulating portion includes a first insulating region and a second insulating region, the first insulating region surrounds the fourth electrode and is in contact with the fourth electrode, the second insulating region surrounds the first insulating region and is in contact with the first insulating region, The second insulating region has a lower dielectric constant than the first insulating region.

2. The semiconductor device according to claim 1, wherein The first insulating region includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, zirconium oxide, and lanthanum oxide.

3. The semiconductor device according to claim 1 or 2, wherein: The second insulating region includes at least one of carbon-containing silicon oxide and silicon oxide.

4. The semiconductor device according to claim 1 or 2, wherein: The thickness of the second insulating region is greater than or equal to 0.1 times and less than or equal to 10 times the thickness of the first insulating region.

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